| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// |
| // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: |
| // util/topgen.py -t hw/top_earlgrey/doc/top_earlgrey.hjson --hjson-only -o hw/top_earlgrey/ |
| { |
| name: earlgrey |
| type: top |
| datawidth: "32" |
| clocks: |
| [ |
| { |
| name: main |
| freq: "100000000" |
| } |
| ] |
| num_cores: "1" |
| module: |
| [ |
| { |
| name: uart |
| type: uart |
| clock: main |
| base_addr: 0x40000000 |
| size: 0x1000 |
| ip_clock: main |
| bus_device: tlul |
| bus_host: none |
| available_input_list: |
| [ |
| { |
| name: rx |
| width: 1 |
| } |
| ] |
| available_output_list: |
| [ |
| { |
| name: tx |
| width: 1 |
| } |
| ] |
| available_inout_list: [] |
| interrupt_list: |
| [ |
| { |
| name: tx_watermark |
| width: 1 |
| } |
| { |
| name: rx_watermark |
| width: 1 |
| } |
| { |
| name: tx_overflow |
| width: 1 |
| } |
| { |
| name: rx_overflow |
| width: 1 |
| } |
| { |
| name: rx_frame_err |
| width: 1 |
| } |
| { |
| name: rx_break_err |
| width: 1 |
| } |
| { |
| name: rx_timeout |
| width: 1 |
| } |
| { |
| name: rx_parity_err |
| width: 1 |
| } |
| ] |
| } |
| { |
| name: gpio |
| type: gpio |
| clock: main |
| base_addr: 0x40010000 |
| size: 0x1000 |
| ip_clock: main |
| bus_device: tlul |
| bus_host: none |
| available_input_list: [] |
| available_output_list: [] |
| available_inout_list: |
| [ |
| { |
| name: gpio |
| width: 32 |
| } |
| ] |
| interrupt_list: |
| [ |
| { |
| name: gpio |
| width: 32 |
| } |
| ] |
| } |
| { |
| name: spi_device |
| type: spi_device |
| clock: main |
| base_addr: 0x40020000 |
| size: 0x1000 |
| ip_clock: main |
| bus_device: tlul |
| bus_host: none |
| available_input_list: |
| [ |
| { |
| name: sck |
| width: 1 |
| } |
| { |
| name: csb |
| width: 1 |
| } |
| { |
| name: mosi |
| width: 1 |
| } |
| ] |
| available_output_list: |
| [ |
| { |
| name: miso |
| width: 1 |
| } |
| ] |
| available_inout_list: [] |
| interrupt_list: |
| [ |
| { |
| name: rxf |
| width: 1 |
| } |
| { |
| name: rxlvl |
| width: 1 |
| } |
| { |
| name: txlvl |
| width: 1 |
| } |
| { |
| name: rxerr |
| width: 1 |
| } |
| ] |
| } |
| { |
| name: flash_ctrl |
| type: flash_ctrl |
| clock: main |
| base_addr: 0x40030000 |
| size: 0x1000 |
| ip_clock: main |
| bus_device: tlul |
| bus_host: none |
| available_input_list: [] |
| available_output_list: [] |
| available_inout_list: [] |
| interrupt_list: |
| [ |
| { |
| name: prog_empty |
| width: 1 |
| } |
| { |
| name: prog_lvl |
| width: 1 |
| } |
| { |
| name: rd_full |
| width: 1 |
| } |
| { |
| name: rd_lvl |
| width: 1 |
| } |
| { |
| name: op_done |
| width: 1 |
| } |
| { |
| name: op_error |
| width: 1 |
| } |
| ] |
| } |
| { |
| name: rv_timer |
| type: rv_timer |
| clock: main |
| base_addr: 0x40080000 |
| size: 0x1000 |
| ip_clock: main |
| bus_device: tlul |
| bus_host: none |
| available_input_list: [] |
| available_output_list: [] |
| available_inout_list: [] |
| interrupt_list: |
| [ |
| { |
| name: timer_expired_0_0 |
| width: 1 |
| } |
| ] |
| } |
| { |
| name: hmac |
| type: hmac |
| clock: main |
| base_addr: 0x40120000 |
| size: 0x1000 |
| ip_clock: main |
| bus_device: tlul |
| bus_host: none |
| available_input_list: [] |
| available_output_list: [] |
| available_inout_list: [] |
| interrupt_list: |
| [ |
| { |
| name: hmac_done |
| width: 1 |
| } |
| { |
| name: fifo_full |
| width: 1 |
| } |
| ] |
| } |
| { |
| name: rv_plic |
| type: rv_plic |
| clock: main |
| base_addr: 0x40090000 |
| generated: "true" |
| parameter: |
| { |
| FIND_MAX: MATRIX |
| } |
| size: 0x1000 |
| ip_clock: main |
| bus_device: tlul |
| bus_host: none |
| available_input_list: [] |
| available_output_list: [] |
| available_inout_list: [] |
| interrupt_list: [] |
| } |
| ] |
| memory: |
| [ |
| { |
| name: rom |
| type: ram_1p |
| base_addr: 0x00008000 |
| size: 0x2000 |
| } |
| { |
| name: ram_main |
| type: ram_1p |
| base_addr: 0x10000000 |
| size: 0x10000 |
| } |
| { |
| name: eflash |
| type: eflash |
| base_addr: 0x20000000 |
| size: 0x80000 |
| } |
| ] |
| xbar: |
| [ |
| { |
| name: main |
| clock: main |
| connections: |
| { |
| corei: |
| [ |
| rom |
| debug_mem |
| ram_main |
| eflash |
| ] |
| cored: |
| [ |
| rom |
| debug_mem |
| ram_main |
| eflash |
| uart |
| gpio |
| spi_device |
| flash_ctrl |
| rv_timer |
| hmac |
| rv_plic |
| ] |
| dm_sba: |
| [ |
| rom |
| ram_main |
| eflash |
| uart |
| gpio |
| spi_device |
| flash_ctrl |
| rv_timer |
| hmac |
| rv_plic |
| ] |
| } |
| nodes: |
| [ |
| { |
| name: corei |
| type: host |
| clock: main |
| pipeline: "true" |
| inst_type: rv_core_ibex |
| } |
| { |
| name: cored |
| type: host |
| clock: main |
| pipeline: "true" |
| inst_type: rv_core_ibex |
| } |
| { |
| name: dm_sba |
| type: host |
| clock: main |
| pipeline: "true" |
| inst_type: rv_dm |
| } |
| { |
| name: rom |
| type: device |
| clock: main |
| inst_type: ram_1p |
| base_addr: 0x00008000 |
| size_byte: 0x2000 |
| } |
| { |
| name: debug_mem |
| type: device |
| clock: main |
| inst_type: rv_dm |
| base_addr: 0x1A110000 |
| size_byte: 0x1000 |
| } |
| { |
| name: ram_main |
| type: device |
| clock: main |
| inst_type: ram_1p |
| base_addr: 0x10000000 |
| size_byte: 0x10000 |
| } |
| { |
| name: eflash |
| type: device |
| clock: main |
| inst_type: eflash |
| base_addr: 0x20000000 |
| size_byte: 0x80000 |
| } |
| { |
| name: uart |
| type: device |
| clock: main |
| inst_type: uart |
| base_addr: 0x40000000 |
| size_byte: 0x1000 |
| } |
| { |
| name: gpio |
| type: device |
| clock: main |
| inst_type: gpio |
| base_addr: 0x40010000 |
| size_byte: 0x1000 |
| } |
| { |
| name: spi_device |
| type: device |
| clock: main |
| inst_type: spi_device |
| base_addr: 0x40020000 |
| size_byte: 0x1000 |
| } |
| { |
| name: flash_ctrl |
| type: device |
| clock: main |
| inst_type: flash_ctrl |
| base_addr: 0x40030000 |
| size_byte: 0x1000 |
| } |
| { |
| name: rv_timer |
| type: device |
| clock: main |
| inst_type: rv_timer |
| base_addr: 0x40080000 |
| size_byte: 0x1000 |
| } |
| { |
| name: hmac |
| type: device |
| clock: main |
| inst_type: hmac |
| base_addr: 0x40120000 |
| size_byte: 0x1000 |
| } |
| { |
| name: rv_plic |
| type: device |
| clock: main |
| inst_type: rv_plic |
| base_addr: 0x40090000 |
| size_byte: 0x1000 |
| } |
| ] |
| } |
| ] |
| interrupt_module: |
| [ |
| gpio |
| uart |
| spi_device |
| flash_ctrl |
| hmac |
| ] |
| interrupt: |
| [ |
| { |
| name: gpio_gpio |
| width: 32 |
| } |
| { |
| name: uart_tx_watermark |
| width: 1 |
| } |
| { |
| name: uart_rx_watermark |
| width: 1 |
| } |
| { |
| name: uart_tx_overflow |
| width: 1 |
| } |
| { |
| name: uart_rx_overflow |
| width: 1 |
| } |
| { |
| name: uart_rx_frame_err |
| width: 1 |
| } |
| { |
| name: uart_rx_break_err |
| width: 1 |
| } |
| { |
| name: uart_rx_timeout |
| width: 1 |
| } |
| { |
| name: uart_rx_parity_err |
| width: 1 |
| } |
| { |
| name: spi_device_rxf |
| width: 1 |
| } |
| { |
| name: spi_device_rxlvl |
| width: 1 |
| } |
| { |
| name: spi_device_txlvl |
| width: 1 |
| } |
| { |
| name: spi_device_rxerr |
| width: 1 |
| } |
| { |
| name: flash_ctrl_prog_empty |
| width: 1 |
| } |
| { |
| name: flash_ctrl_prog_lvl |
| width: 1 |
| } |
| { |
| name: flash_ctrl_rd_full |
| width: 1 |
| } |
| { |
| name: flash_ctrl_rd_lvl |
| width: 1 |
| } |
| { |
| name: flash_ctrl_op_done |
| width: 1 |
| } |
| { |
| name: flash_ctrl_op_error |
| width: 1 |
| } |
| { |
| name: hmac_hmac_done |
| width: 1 |
| } |
| { |
| name: hmac_fifo_full |
| width: 1 |
| } |
| ] |
| } |
