| // Generated register defines for usbuart |
| |
| // Copyright information found in source file: |
| // Copyright lowRISC contributors. |
| |
| // Licensing information found in source file: |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| |
| #ifndef _USBUART_REG_DEFS_ |
| #define _USBUART_REG_DEFS_ |
| |
| // Interrupt State Register |
| #define USBUART_INTR_STATE(id) (USBUART##id##_BASE_ADDR + 0x0) |
| #define USBUART_INTR_STATE_TX_WATERMARK 0 |
| #define USBUART_INTR_STATE_RX_WATERMARK 1 |
| #define USBUART_INTR_STATE_TX_OVERFLOW 2 |
| #define USBUART_INTR_STATE_RX_OVERFLOW 3 |
| #define USBUART_INTR_STATE_RX_FRAME_ERR 4 |
| #define USBUART_INTR_STATE_RX_BREAK_ERR 5 |
| #define USBUART_INTR_STATE_RX_TIMEOUT 6 |
| #define USBUART_INTR_STATE_RX_PARITY_ERR 7 |
| |
| // Interrupt Enable Register |
| #define USBUART_INTR_ENABLE(id) (USBUART##id##_BASE_ADDR + 0x4) |
| #define USBUART_INTR_ENABLE_TX_WATERMARK 0 |
| #define USBUART_INTR_ENABLE_RX_WATERMARK 1 |
| #define USBUART_INTR_ENABLE_TX_OVERFLOW 2 |
| #define USBUART_INTR_ENABLE_RX_OVERFLOW 3 |
| #define USBUART_INTR_ENABLE_RX_FRAME_ERR 4 |
| #define USBUART_INTR_ENABLE_RX_BREAK_ERR 5 |
| #define USBUART_INTR_ENABLE_RX_TIMEOUT 6 |
| #define USBUART_INTR_ENABLE_RX_PARITY_ERR 7 |
| |
| // Interrupt Test Register |
| #define USBUART_INTR_TEST(id) (USBUART##id##_BASE_ADDR + 0x8) |
| #define USBUART_INTR_TEST_TX_WATERMARK 0 |
| #define USBUART_INTR_TEST_RX_WATERMARK 1 |
| #define USBUART_INTR_TEST_TX_OVERFLOW 2 |
| #define USBUART_INTR_TEST_RX_OVERFLOW 3 |
| #define USBUART_INTR_TEST_RX_FRAME_ERR 4 |
| #define USBUART_INTR_TEST_RX_BREAK_ERR 5 |
| #define USBUART_INTR_TEST_RX_TIMEOUT 6 |
| #define USBUART_INTR_TEST_RX_PARITY_ERR 7 |
| |
| // UART control register |
| #define USBUART_CTRL(id) (USBUART##id##_BASE_ADDR + 0xc) |
| #define USBUART_CTRL_TX 0 |
| #define USBUART_CTRL_RX 1 |
| #define USBUART_CTRL_NF 2 |
| #define USBUART_CTRL_SLPBK 4 |
| #define USBUART_CTRL_LLPBK 5 |
| #define USBUART_CTRL_PARITY_EN 6 |
| #define USBUART_CTRL_PARITY_ODD 7 |
| #define USBUART_CTRL_RXBLVL_MASK 0x3 |
| #define USBUART_CTRL_RXBLVL_OFFSET 8 |
| #define USBUART_CTRL_NCO_MASK 0xffff |
| #define USBUART_CTRL_NCO_OFFSET 16 |
| |
| // UART live status register |
| #define USBUART_STATUS(id) (USBUART##id##_BASE_ADDR + 0x10) |
| #define USBUART_STATUS_TXFULL 0 |
| #define USBUART_STATUS_RXFULL 1 |
| #define USBUART_STATUS_TXEMPTY 2 |
| #define USBUART_STATUS_TXIDLE 3 |
| #define USBUART_STATUS_RXIDLE 4 |
| #define USBUART_STATUS_RXEMPTY 5 |
| |
| // UART read data |
| #define USBUART_RDATA(id) (USBUART##id##_BASE_ADDR + 0x14) |
| #define USBUART_RDATA_MASK 0xff |
| #define USBUART_RDATA_OFFSET 0 |
| |
| // UART write data |
| #define USBUART_WDATA(id) (USBUART##id##_BASE_ADDR + 0x18) |
| #define USBUART_WDATA_MASK 0xff |
| #define USBUART_WDATA_OFFSET 0 |
| |
| // UART FIFO control register |
| #define USBUART_FIFO_CTRL(id) (USBUART##id##_BASE_ADDR + 0x1c) |
| #define USBUART_FIFO_CTRL_RXRST 0 |
| #define USBUART_FIFO_CTRL_TXRST 1 |
| #define USBUART_FIFO_CTRL_RXILVL_MASK 0x7 |
| #define USBUART_FIFO_CTRL_RXILVL_OFFSET 2 |
| #define USBUART_FIFO_CTRL_RXILVL_RXLVL1 0 |
| #define USBUART_FIFO_CTRL_RXILVL_RXLVL4 1 |
| #define USBUART_FIFO_CTRL_RXILVL_RXLVL8 2 |
| #define USBUART_FIFO_CTRL_RXILVL_RXLVL16 3 |
| #define USBUART_FIFO_CTRL_RXILVL_RXLVL30 4 |
| #define USBUART_FIFO_CTRL_TXILVL_MASK 0x3 |
| #define USBUART_FIFO_CTRL_TXILVL_OFFSET 5 |
| #define USBUART_FIFO_CTRL_TXILVL_TXLVL1 0 |
| #define USBUART_FIFO_CTRL_TXILVL_TXLVL4 1 |
| #define USBUART_FIFO_CTRL_TXILVL_TXLVL8 2 |
| #define USBUART_FIFO_CTRL_TXILVL_TXLVL16 3 |
| |
| // UART FIFO status register |
| #define USBUART_FIFO_STATUS(id) (USBUART##id##_BASE_ADDR + 0x20) |
| #define USBUART_FIFO_STATUS_TXLVL_MASK 0x3f |
| #define USBUART_FIFO_STATUS_TXLVL_OFFSET 0 |
| #define USBUART_FIFO_STATUS_RXLVL_MASK 0x3f |
| #define USBUART_FIFO_STATUS_RXLVL_OFFSET 16 |
| |
| // UART override control register |
| #define USBUART_OVRD(id) (USBUART##id##_BASE_ADDR + 0x24) |
| #define USBUART_OVRD_TXEN 0 |
| #define USBUART_OVRD_TXVAL 1 |
| |
| // UART oversampled values |
| #define USBUART_VAL(id) (USBUART##id##_BASE_ADDR + 0x28) |
| #define USBUART_VAL_RX_MASK 0xffff |
| #define USBUART_VAL_RX_OFFSET 0 |
| |
| // UART RX timeout control |
| #define USBUART_TIMEOUT_CTRL(id) (USBUART##id##_BASE_ADDR + 0x2c) |
| #define USBUART_TIMEOUT_CTRL_VAL_MASK 0xffffff |
| #define USBUART_TIMEOUT_CTRL_VAL_OFFSET 0 |
| #define USBUART_TIMEOUT_CTRL_EN 31 |
| |
| // USB Status |
| #define USBUART_USBSTAT(id) (USBUART##id##_BASE_ADDR + 0x30) |
| #define USBUART_USBSTAT_FRAME_MASK 0x7ff |
| #define USBUART_USBSTAT_FRAME_OFFSET 0 |
| #define USBUART_USBSTAT_HOST_TIMEOUT 14 |
| #define USBUART_USBSTAT_HOST_LOST 15 |
| #define USBUART_USBSTAT_DEVICE_ADDRESS_MASK 0x7f |
| #define USBUART_USBSTAT_DEVICE_ADDRESS_OFFSET 16 |
| |
| // USB Parmeters |
| #define USBUART_USBPARAM(id) (USBUART##id##_BASE_ADDR + 0x34) |
| #define USBUART_USBPARAM_BAUD_REQ_MASK 0xffff |
| #define USBUART_USBPARAM_BAUD_REQ_OFFSET 0 |
| #define USBUART_USBPARAM_PARITY_REQ_MASK 0x3 |
| #define USBUART_USBPARAM_PARITY_REQ_OFFSET 16 |
| #define USBUART_USBPARAM_PARITY_REQ_NONE 0 |
| #define USBUART_USBPARAM_PARITY_REQ_ODD 1 |
| #define USBUART_USBPARAM_PARITY_REQ_EVEN 2 |
| |
| #endif // _USBUART_REG_DEFS_ |
| // End generated register defines for usbuart |
