Update riscv_compliance to riscv/riscv-compliance@5a978cf Update code from upstream repository https://github.com/riscv/riscv- compliance.git to revision 5a978cfd444d5e640150d46703deda99057b2bbb * Restructure (riscv/riscv-compliance#101) (Neel Gala) * Update ChangeLog (Neel Gala) * updated ChangeLog (Neel Gala) * fixes issue riscv/riscv-compliance#95 (Neel Gala) * riscv-test-suite/rv64im/Makefrag: remove duplicate REMUW in value of variable rv64im_sc_tests (Daniel S. Wilkerson) * riscv-test-suite/rv64i/Makefrag: remove duplicate SRAIW in value of variable rv64i_sc_tests (Daniel S. Wilkerson) * removed the .pdf with version number (Allen Baum) * minor typographical corrections (Allen Baum) * Adding the jpg of the diagram included in the testformatspec doc (Allen Baum) * Adding a prebuilt version of the testspecformat (Allen Baum) * * typo grammatical, and consistency fixes (Allen Baum) * * typos fixed * added RVTEST_BASEUPD macro * added explanations for each macro * clarified restrictions on #ifdefs * added comment that test cases with identical conditions should be combined into a single case * documented that test case first parameter should match the #ifdef parameter that precedes it (Allen Baum) * added missing parameters to BASEUPD macro (Allen Baum) * * modified macro names to conformn to riscof naming convention of model specific vs. pre-defined * add more complete list of macros, their uses, parameters, and whether they are required or optional * minor structural changes (moving sentences, renumbering) and typo fixes * clarified impact of debug macros * clarified how SIGUPD and BASEUPD must be used * remove section about test taxonomy, binary tests, emulated ops * clarify/fix boundary between test target and framework responsibilities (split test target into test target and test shell) * remove To Be discussed items that have been discussed * remove default case condition; if conditions are unchanged, part of same case * minor grammatical changes related to the above (Allen Baum) * fixed some references that should have been changed, added IO_WRITE to list of macros (Allen Baum) * updated history with all the changes (Allen Baum) * fixed the appendix so it appears in the TOC (Allen Baum) * removed references to address in signature, moved note about multiple test cases in a test closer to definition fixed cut/paste error in example of test pool changed case of test subdirectoies to be all caos for primar extensions and architectures, camel-case for Z-extensions changed test example to match new macros, including ifdefs (Allen Baum) * Minor formatting fixes (Allen Baum) * More grammar, spelling corrections and clarifications, minor formatting changes. (Allen Baum) * yet more grammatical fixes and clarifications add ToBeDiscussed items for emulated ops and binary tests (Allen Baum) * minor grammer updates (Allen Baum) * Update spec/TestFormatSpec.adoc (Allen Baum) * removed ambiguity of framework functionality: it will insert test part names and version numbers and conmpare signatures. (Allen Baum) * Changed signature format to fixed maxsize physical addr:32b data in COMPLIANCE_DATA_BEGIN/END range. (Allen Baum) * minor spelling, wording corrections (Allen Baum) * Changes to match riscof implementation of macros (Allen Baum) * spelling fixes and To Be Discussed additions and clarifications (Allen Baum) * gitignore now ignores Macintosh invisible .DS_STore files ChangeLog lists all the changes made TestPsecFormat updated to v1.2 with numerous granmmer/spelling corrections, updates to changes that have been decided, new directory structure, new test macros, updated signature format, added clarifications, examples, future work, and notes that this is still a work in progress and does not reflect the current state of the test repository. (Allen Baum) * Fix Ibex target following parallel changes (Tom Roberts) * Ignore case when comparing signature outputs (Xiretza) * Support F extension on RV32 sail-riscv-c. (Prashanth Mundkur) * Correct a typo in README (Felix Yan) * Document the usage of Parallel execution (eroom1966) * Add Parallel make for supported targets (eroom1966) * Fix issues riscv/riscv-compliance#84 riscv/riscv-compliance#76 (eroom1966) * Update to riscvOVPsim (eroom1966) * Update of riscv-ovpsim (eroom1966) * fix IO behavior for verbose logging (eroom1966) * source code files for improved coverage (eroom1966) * Added coverage report information (eroom1966) * HVB update on jalr (eroom1966) * Add HVB new enhanced coverage tests (eroom1966) * Fix for issue riscv/riscv-compliance#67 (eroom1966) * Restructured RV32I to move Zicsr and Zifencei into their own suites (eroom1966) Signed-off-by: Greg Chadwick <gac@lowrisc.org>
diff --git a/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch new file mode 100644 index 0000000..72cd93c --- /dev/null +++ b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
@@ -0,0 +1,99 @@ +From 5fb77a9e75207f4a35d0b1c4ad9f0ce7faba3814 Mon Sep 17 00:00:00 2001 +From: Greg Chadwick <gac@lowrisc.org> +Date: Wed, 15 Apr 2020 15:45:31 +0100 +Subject: [PATCH 1/3] Add configurable trap alignment and entry point to p + test-env + +--- + riscv-test-env/p/riscv_test.h | 20 ++++++++++++++------ + riscv-test-suite/rv32i/src/I-EBREAK-01.S | 1 + + riscv-test-suite/rv32i/src/I-ECALL-01.S | 1 + + 3 files changed, 16 insertions(+), 6 deletions(-) + +diff --git a/riscv-test-env/p/riscv_test.h b/riscv-test-env/p/riscv_test.h +index eaa6758..9423523 100644 +--- a/riscv-test-env/p/riscv_test.h ++++ b/riscv-test-env/p/riscv_test.h +@@ -60,14 +60,14 @@ + csrw pmpaddr0, t0; \ + li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ + csrw pmpcfg0, t0; \ +- .align 2; \ ++ .align TRAPALIGN; \ + 1: + + #define INIT_SPTBR \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi sptbr, 0; \ +- .align 2; \ ++ .align TRAPALIGN; \ + 1: + + #define DELEGATE_NO_TRAPS \ +@@ -76,7 +76,7 @@ + csrwi medeleg, 0; \ + csrwi mideleg, 0; \ + csrwi mie, 0; \ +- .align 2; \ ++ .align TRAPALIGN; \ + 1: + + #define RVTEST_ENABLE_SUPERVISOR \ +@@ -125,6 +125,14 @@ + #if defined(TRAPHANDLER) + #include TRAPHANDLER + #endif ++#if !defined(TRAPALIGN) ++#define TRAPALIGN 2 ++#endif ++ ++#if !defined(RVTEST_ENTRY) ++#define RVTEST_ENTRY _start ++#endif ++ + + #define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ + +@@ -133,11 +141,11 @@ + .align 6; \ + .weak stvec_handler; \ + .weak mtvec_handler; \ +- .globl _start; \ +-_start: \ ++ .globl RVTEST_ENTRY; \ ++RVTEST_ENTRY: \ + /* reset vector */ \ + j reset_vector; \ +- .align 2; \ ++ .align TRAPALIGN; \ + trap_vector: \ + /* test whether the test came from pass/fail */ \ + csrr t5, mcause; \ +diff --git a/riscv-test-suite/rv32i/src/I-EBREAK-01.S b/riscv-test-suite/rv32i/src/I-EBREAK-01.S +index 958eebc..32c074c 100644 +--- a/riscv-test-suite/rv32i/src/I-EBREAK-01.S ++++ b/riscv-test-suite/rv32i/src/I-EBREAK-01.S +@@ -71,6 +71,7 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++.align TRAPALIGN + _trap_handler: + # increment return address + csrr x30, mepc +diff --git a/riscv-test-suite/rv32i/src/I-ECALL-01.S b/riscv-test-suite/rv32i/src/I-ECALL-01.S +index 5278207..0bdee2a 100644 +--- a/riscv-test-suite/rv32i/src/I-ECALL-01.S ++++ b/riscv-test-suite/rv32i/src/I-ECALL-01.S +@@ -73,6 +73,7 @@ RV_COMPLIANCE_CODE_BEGIN + + # --------------------------------------------------------------------------------------------- + # Exception handler ++.align TRAPALIGN + _trap_handler: + # increment return address + csrr x30, mepc +-- +2.17.1 +
diff --git a/sw/vendor/patches/riscv_compliance/0001-test-Add-OpenTitan-target-to-riscv-compliance-testin.patch b/sw/vendor/patches/riscv_compliance/0001-test-Add-OpenTitan-target-to-riscv-compliance-testin.patch deleted file mode 100644 index 865644d..0000000 --- a/sw/vendor/patches/riscv_compliance/0001-test-Add-OpenTitan-target-to-riscv-compliance-testin.patch +++ /dev/null
@@ -1,530 +0,0 @@ -From 3a53f89ce864553700a1cb33ed3ee1429e953bae Mon Sep 17 00:00:00 2001 -From: Timothy Chen <timothytim@google.com> -Date: Thu, 7 Nov 2019 14:27:59 -0800 -Subject: [PATCH 1/2] [test] Add OpenTitan target to riscv-compliance testing - -Signed-off-by: Timothy Chen <timothytim@google.com> ---- - riscv-target/opentitan/README.md | 135 ++++++++++++++++++ - riscv-target/opentitan/compliance_io.h | 22 +++ - riscv-target/opentitan/compliance_test.h | 39 +++++ - .../opentitan/device/rv32imc/Makefile.include | 76 ++++++++++ - .../opentitan/device/rv32imc/handler.S | 22 +++ - .../opentitan/device/rv32imc/isa.yaml | 49 +++++++ - riscv-target/opentitan/device/rv32imc/link.ld | 55 +++++++ - .../opentitan/device/rv32imc/platform.yaml | 10 ++ - riscv-target/opentitan/device/rv32imc/wrap.c | 38 +++++ - 9 files changed, 446 insertions(+) - create mode 100644 riscv-target/opentitan/README.md - create mode 100644 riscv-target/opentitan/compliance_io.h - create mode 100644 riscv-target/opentitan/compliance_test.h - create mode 100644 riscv-target/opentitan/device/rv32imc/Makefile.include - create mode 100644 riscv-target/opentitan/device/rv32imc/handler.S - create mode 100644 riscv-target/opentitan/device/rv32imc/isa.yaml - create mode 100644 riscv-target/opentitan/device/rv32imc/link.ld - create mode 100644 riscv-target/opentitan/device/rv32imc/platform.yaml - create mode 100644 riscv-target/opentitan/device/rv32imc/wrap.c - -diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md -new file mode 100644 -index 0000000..7fceaae ---- /dev/null -+++ b/riscv-target/opentitan/README.md -@@ -0,0 +1,135 @@ -+--- -+title: "OpenTitan RISC-V Compliance Testing" -+--- -+ -+# Overview -+The RISC-V compliance test can be run on either FPGA or Verilator. -+To run on Verilator, set the variables below -+ -+```console -+$ export RISCV_TARGET=opentitan -+$ export RISCV_DEVICE=rv32imc -+$ export TARGET=verilator -+``` -+ -+To run on FPGA, set the variables below. -+The `FPGA_UART` variable must be set to wherever a valid device is connected. -+ -+```console -+$ export RISCV_TARGET=opentitan -+$ export RISCV_DEVICE=rv32imc -+$ export TARGET=fpga -+$ export FPGA_UART=/dev/tty* -+``` -+ -+By default, the test assumes there exists a valid Verilator build at `${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`. -+If your Verilator build is at a different location, please set that as well when running with Verilator. -+For instructions on how to create a Verilator build, please refer to the [Verilator guide]({{< relref "doc/ug/getting_started_verilator" >}}). -+ -+```console -+$ export TARGET_SIM=${PATH_TO_VERILATOR_BUILD} -+``` -+ -+When running against FPGA, the test assumes the FPGA is already programmed and ready to go. -+To find out how to properly build and flash FPGA, please refer to the [FPGA manual]({{< relref "doc/rm/ref_manual_fpga" >}}) -+ -+ -+Now, run the tests. -+The following output will be seen (software build steps are truncated). -+The example below uses Verilator as an example, but the FPGA output is nearly identical. -+ -+```console -+$ cd $REPO_TOP -+$ make -C sw/vendor/riscv_compliance RISCV_ISA=rv32i \ -+ && make -C sw/vendor/riscv_compliance RISCV_ISA=rv32im \ -+ && make -C sw/vendor/riscv_compliance RISCV_ISA=rv32imc -+ -+ -+Rom initialized with program at $REPO_TOP/sw/vendor/riscv_compliance/../../boot_rom/rom.vmem -+ -+Flash initialized with program at $REPO_TOP/sw/vendor/riscv_compliance/work/rv32i/I-ENDIANESS-01.elf.vmem -+ -+JTAG: Virtual JTAG interface jtag0 is listening on port 44853. Use -+OpenOCD and the following configuration to connect: -+ interface remote_bitbang -+ remote_bitbang_host localhost -+ remote_bitbang_port 44853 -+ -+SPI: Created /dev/pts/21 for spi0. Connect to it with any terminal program, e.g. -+$ screen /dev/pts/21 -+NOTE: a SPI transaction is run for every 4 characters entered. -+SPI: Monitor output file created at $REPO_TOP/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/spi0.log. Works well with tail: -+$ tail -f $REPO_TOP/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/spi0.log -+ -+UART: Created /dev/pts/22 for uart0. Connect to it with any terminal program, e.g. -+$ screen /dev/pts/22 -+ -+Simulation running, end by pressing CTRL-c. -+TOP.top_earlgrey_verilator.top_earlgrey.core.ibex_tracer_i: Writing execution trace to trace_core_00000000.log -+Verilator sim termination requested -+Your simulation wrote to 0x10008000 -+ -+... -+ -+Compare to reference files ... -+ -+Check I-ADD-01 ... OK -+Check I-ADDI-01 ... OK -+Check I-AND-01 ... OK -+Check I-ANDI-01 ... OK -+Check I-AUIPC-01 ... OK -+Check I-BEQ-01 ... OK -+Check I-BGE-01 ... OK -+Check I-BGEU-01 ... OK -+Check I-BLT-01 ... OK -+Check I-BLTU-01 ... OK -+Check I-BNE-01 ... OK -+Check I-CSRRC-01 ... OK -+Check I-CSRRCI-01 ... OK -+Check I-CSRRS-01 ... OK -+Check I-CSRRSI-01 ... OK -+Check I-CSRRW-01 ... OK -+Check I-CSRRWI-01 ... OK -+Check I-DELAY_SLOTS-01 ... OK -+Check I-EBREAK-01 ... OK -+Check I-ECALL-01 ... OK -+Check I-ENDIANESS-01 ... OK -+Check I-FENCE.I-01 ... OK -+Check I-IO ... OK -+Check I-JAL-01 ... OK -+Check I-JALR-01 ... OK -+Check I-LB-01 ... OK -+Check I-LBU-01 ... OK -+Check I-LH-01 ... OK -+Check I-LHU-01 ... OK -+Check I-LUI-01 ... OK -+Check I-LW-01 ... OK -+Check I-MISALIGN_JMP-01 ... OK -+Check I-MISALIGN_LDST-01 ... OK -+Check I-NOP-01 ... OK -+Check I-OR-01 ... OK -+Check I-ORI-01 ... OK -+Check I-RF_size-01 ... OK -+Check I-RF_width-01 ... OK -+Check I-RF_x0-01 ... OK -+Check I-SB-01 ... OK -+Check I-SH-01 ... OK -+Check I-SLL-01 ... OK -+Check I-SLLI-01 ... OK -+Check I-SLT-01 ... OK -+Check I-SLTI-01 ... OK -+Check I-SLTIU-01 ... OK -+Check I-SLTU-01 ... OK -+Check I-SRA-01 ... OK -+Check I-SRAI-01 ... OK -+Check I-SRL-01 ... OK -+Check I-SRLI-01 ... OK -+Check I-SUB-01 ... OK -+Check I-SW-01 ... OK -+Check I-XOR-01 ... OK -+Check I-XORI-01 ... OK -+-------------------------------- -+OK: 55/55 -+ -+ -+``` -diff --git a/riscv-target/opentitan/compliance_io.h b/riscv-target/opentitan/compliance_io.h -new file mode 100644 -index 0000000..2774158 ---- /dev/null -+++ b/riscv-target/opentitan/compliance_io.h -@@ -0,0 +1,22 @@ -+// Copyright lowRISC contributors. -+// Licensed under the Apache License, Version 2.0, see LICENSE for details. -+// SPDX-License-Identifier: Apache-2.0 -+ -+// RISC-V Compliance IO Test Header File -+ -+ -+#ifndef _COMPLIANCE_IO_H -+#define _COMPLIANCE_IO_H -+ -+//----------------------------------------------------------------------- -+// RV IO Macros (Non functional) -+//----------------------------------------------------------------------- -+ -+#define RVTEST_IO_INIT -+#define RVTEST_IO_WRITE_STR(_SP, _STR) -+#define RVTEST_IO_CHECK() -+#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) -+#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) -+#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) -+ -+#endif // _COMPLIANCE_IO_H -diff --git a/riscv-target/opentitan/compliance_test.h b/riscv-target/opentitan/compliance_test.h -new file mode 100644 -index 0000000..7f1bdd3 ---- /dev/null -+++ b/riscv-target/opentitan/compliance_test.h -@@ -0,0 +1,39 @@ -+// Copyright lowRISC contributors. -+// Licensed under the Apache License, Version 2.0, see LICENSE for details. -+// SPDX-License-Identifier: Apache-2.0 -+ -+// RISC-V Compliance Test Header File -+ -+#ifndef _COMPLIANCE_TEST_H -+#define _COMPLIANCE_TEST_H -+ -+#include "sw/vendor/riscv_compliance/riscv-test-env/p/riscv_test.h" -+ -+//----------------------------------------------------------------------- -+// RV Compliance Macros -+//----------------------------------------------------------------------- -+#define RV_COMPLIANCE_HALT \ -+ la sp, _stack_start; \ -+ j dump_signature; \ -+ loop_forever: \ -+ wfi; \ -+ j loop_forever; \ -+ -+#define RV_COMPLIANCE_RV32M \ -+ RVTEST_RV32M \ -+ -+ -+#define RV_COMPLIANCE_CODE_BEGIN \ -+ RVTEST_CODE_BEGIN \ -+ -+#define RV_COMPLIANCE_CODE_END \ -+ RVTEST_CODE_END \ -+ -+#define RV_COMPLIANCE_DATA_BEGIN \ -+ .section .test.output; \ -+ RVTEST_DATA_BEGIN \ -+ -+#define RV_COMPLIANCE_DATA_END \ -+ RVTEST_DATA_END \ -+ -+#endif -diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include -new file mode 100644 -index 0000000..c18820f ---- /dev/null -+++ b/riscv-target/opentitan/device/rv32imc/Makefile.include -@@ -0,0 +1,76 @@ -+## Copyright lowRISC contributors. -+## Licensed under the Apache License, Version 2.0, see LICENSE for details. -+## SPDX-License-Identifier: Apache-2.0 -+ -+ -+OT = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc -+OTSW = $(ROOTDIR)/../../device -+OTROOT = $(OTSW)/../../ -+LDSCRIPT = $(OT)/link.ld -+TRAPHANDLER = $(OT)/handler.S -+DEFINES = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DTRAPHANDLER="\"$(TRAPHANDLER)\"" -+RV_TOOLS ?= /tools/riscv/bin -+FPGA_UART ?= -+TARGET_SIM ?= $(OTROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator -+TARGET ?= fpga -+ -+ifeq ($(TARGET),fpga) -+ CARG = -+ MAKEARG = -+ PYTEST_OPT = --fpga_uart $(FPGA_UART) --spiflash $(OTROOT)/sw/host/spiflash/spiflash \ -+ --test_bin $(work_dir_isa)/$<.bin -+else -+ CARG = -DSIMULATION=1 -+ MAKEARG = SIM=1 -+ PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(work_dir_isa)/$<.vmem \ -+ --rom_bin $(OTSW)/boot_rom/rom.vmem -+endif -+ -+ -+# The run target recipe does the following things: -+# Invoke pytest to run the test -+# Parse the resulting log for the output signatures -+# Convert all signatures to lower case since the reference is in all lower case -+RUN_TARGET=\ -+ pytest -s -v $(OTROOT)/test/systemtest/functional_$(TARGET)_test.py \ -+ $(PYTEST_OPT) \ -+ --log $(work_dir_isa)/$<.uart.log; \ -+ grep -o 'SIG: [a-zA-Z0-9_]*' $(work_dir_isa)/$<.uart.log | sed 's/SIG: //' \ -+ > $(work_dir_isa)/$(*).signature.temp.output; \ -+ tr '[:upper:]' '[:lower:]' < $(work_dir_isa)/$(*).signature.temp.output > $(work_dir_isa)/$(*).signature.output; -+ -+ -+RISCV_PREFIX ?= ${RV_TOOLS}/riscv32-unknown-elf- -+RISCV_GCC ?= ${RV_TOOLS}/riscv32-unknown-elf-gcc -+RISCV_OBJDUMP ?= ${RV_TOOLS}/riscv32-unknown-elf-objdump -+RISCV_OBJCOPY ?= ${RV_TOOLS}/riscv32-unknown-elf-objcopy -+RISCV_NM ?= ${RV_TOOLS}/riscv32-unknown-elf-nm -+RISCV_READELF ?= ${RV_TOOLS}/riscv32-unknown-elf-readelf -+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g -+ -+ -+# The compile target recipe re-uses the boot rom library. -+# This will be changed in the future when the compliance tests directly build -+# their own libraries -+# After the libraries are built, the necessary collateral (vmem for verilator, bin -+# for fpga) are created -+COMPILE_TARGET=\ -+ make -C $$(OTSW) SW_DIR=boot_rom $(MAKEARG) clean all; \ -+ $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ -+ -I$(ROOTDIR)/riscv-test-env/ \ -+ -I$(ROOTDIR)/riscv-test-env/p/ \ -+ -I$(OTSW)/boot_rom/lib \ -+ -I$(OTSW)/lib \ -+ -I$(OTROOT) \ -+ -I$(TARGETDIR)/$(RISCV_TARGET)/ \ -+ -I$(TARGETDIR)/$(RISCV_TARGET)/ \ -+ $(DEFINES) -T$(LDSCRIPT) $$< \ -+ $(OT)/wrap.c \ -+ -L$(OTSW)/boot_rom/lib \ -+ -lot \ -+ -o $(work_dir_isa)/$$@; \ -+ $$(RISCV_OBJDUMP) -SD $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \ -+ $$(RISCV_READELF) -a $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.readelf; \ -+ $$(RISCV_NM) $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.nm; \ -+ $$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@ $(work_dir_isa)/$$@.bin; \ -+ srec_cat $(work_dir_isa)/$$@.bin -binary -offset 0x0000 -byte-swap 4 -o $(work_dir_isa)/$$@.vmem -vmem -diff --git a/riscv-target/opentitan/device/rv32imc/handler.S b/riscv-target/opentitan/device/rv32imc/handler.S -new file mode 100644 -index 0000000..75dbb95 ---- /dev/null -+++ b/riscv-target/opentitan/device/rv32imc/handler.S -@@ -0,0 +1,22 @@ -+// Copyright lowRISC contributors. -+// Licensed under the Apache License, Version 2.0, see LICENSE for details. -+// SPDX-License-Identifier: Apache-2.0 -+ -+.section .text.trap; -+.align 4; -+ -+_trap_start: -+ j _trap_exception -+ -+// This could be exception or user interrupt -+// 0xb is the environment call to indicate the end -+_trap_exception: -+ csrr a0, mcause -+ addi a1, zero, 0xb -+ beq a0, a1, _int_exc -+ la a1, begin_signature -+ // write to value pointed by begin_signature and uses a1 as address scratch -+ sw a0, begin_signature, a1 -+_int_exc: -+ la a0, write_tohost -+ jr a0 -diff --git a/riscv-target/opentitan/device/rv32imc/isa.yaml b/riscv-target/opentitan/device/rv32imc/isa.yaml -new file mode 100644 -index 0000000..c526fec ---- /dev/null -+++ b/riscv-target/opentitan/device/rv32imc/isa.yaml -@@ -0,0 +1,49 @@ -+## Copyright lowRISC contributors. -+## Licensed under the Apache License, Version 2.0, see LICENSE for details. -+## SPDX-License-Identifier: Apache-2.0 -+ -+Device: rv32imc -+Vendor: opentitan -+ -+ISA: RV32IMC -+misa: -+ implemented: True -+ MXL: -+ range: -+ rangelist: [[1]] -+ mode: Unchanged -+ Extensions: -+ bitmask: -+ mask: 0x0 -+ default: 0x1104 -+hw_data_misaligned_support: True -+mtvec: -+ MODE: -+ range: -+ rangelist: [[1]] -+ BASE: -+ range: -+ rangelist: [[0x20000020]] -+ -+mstatus: -+ MPP: -+ range: -+ rangelist: [[3]] -+ -+User_Spec_Version: "2.3" -+Privilege_Spec_Version: "1.11" -+ -+mvendorid: -+ implemented: false -+marchid: -+ implemented: false -+mimpid: -+ implemented: false -+mhartid: 0 -+ -+mcycle: -+ is_hardwired: true -+ implemented: true -+minstret: -+ is_hardwired: true -+ implemented: true -diff --git a/riscv-target/opentitan/device/rv32imc/link.ld b/riscv-target/opentitan/device/rv32imc/link.ld -new file mode 100644 -index 0000000..9259121 ---- /dev/null -+++ b/riscv-target/opentitan/device/rv32imc/link.ld -@@ -0,0 +1,55 @@ -+/* Copyright lowRISC contributors. -+ Licensed under the Apache License, Version 2.0, see LICENSE for details. -+ SPDX-License-Identifier: Apache-2.0 -+*/ -+ -+OUTPUT_ARCH( "riscv" ) -+ENTRY(_start) -+ -+/* required to correctly link newlib */ -+GROUP( -lc -lgloss -lgcc -lsupc++ ) -+ -+SEARCH_DIR(.) -+__DYNAMIC = 0; -+ -+MEMORY -+{ -+ flash (rx) : ORIGIN = 0x20000000, LENGTH = 0x100000 -+ ram (wx) : ORIGIN = 0x10000000, LENGTH = 0x10000 -+} -+ -+_stack_start = ORIGIN(ram) + LENGTH(ram); -+ -+/* need to move signature data to modifiable memory */ -+SECTIONS -+{ -+ .text.init ORIGIN(flash) : { -+ *(.text.init) -+ } > flash -+ -+ .text.trap : { -+ . = ALIGN(0x100); -+ *(.text.trap) -+ } > flash -+ -+ .text : { -+ . = ALIGN(0x100); -+ *(.text) -+ } > flash -+ -+ .data : { -+ . = ALIGN(0x100); -+ *(.data.*) -+ } > flash -+ -+ .tohost ORIGIN(ram) (NOLOAD) : { -+ *(.tohost) -+ *(.test.output) -+ } > ram -+ -+ .bss : { -+ . = ALIGN(0x100); -+ *(.bss) -+ } > ram -+ _end = .; -+} -diff --git a/riscv-target/opentitan/device/rv32imc/platform.yaml b/riscv-target/opentitan/device/rv32imc/platform.yaml -new file mode 100644 -index 0000000..e834efb ---- /dev/null -+++ b/riscv-target/opentitan/device/rv32imc/platform.yaml -@@ -0,0 +1,10 @@ -+## Copyright lowRISC contributors. -+## Licensed under the Apache License, Version 2.0, see LICENSE for details. -+## SPDX-License-Identifier: Apache-2.0 -+ -+mtime: -+ implemented: False -+nmi: -+ address: 0x800000FC # trap vec (mtvec base) + 0x7C -+reset: -+ address: 0x80000080 # boot address + 0x80 -diff --git a/riscv-target/opentitan/device/rv32imc/wrap.c b/riscv-target/opentitan/device/rv32imc/wrap.c -new file mode 100644 -index 0000000..5834199 ---- /dev/null -+++ b/riscv-target/opentitan/device/rv32imc/wrap.c -@@ -0,0 +1,38 @@ -+// Copyright lowRISC contributors. -+// Licensed under the Apache License, Version 2.0, see LICENSE for details. -+// SPDX-License-Identifier: Apache-2.0 -+ -+#include <string.h> -+ -+#include "common.h" -+#include "uart.h" -+ -+#define SIM_TERM_ADDR 0x10008000 -+ -+void dump_signature(void) { -+ extern uint32_t begin_signature[]; -+ extern uint32_t end_signature[]; -+ -+ uint32_t size = end_signature - begin_signature; -+ uart_init(UART_BAUD_RATE); -+ for (uint32_t i = 0; i < size; ++i) { -+ uart_send_str("SIG: "); -+ uart_send_uint(REG32(begin_signature + i), 32); -+ uart_send_str("\r\n"); -+ } -+ -+ uart_send_str("PASS!\r\n"); -+ -+ // The "End" string here is a workaround to pytest console parsing. -+ // Without additional characters, the "\n" from above is not always -+ // detected, and this causes pytest to register the test as a false failure. -+ // This needs to be debugged further to see if it's a setup or hw issue. -+ uart_send_str("End"); -+ -+ // wait for all uart outputs to complete -+ while (!uart_tx_empty() || !uart_tx_idle()) { -+ } -+ -+ // terminate simulation -+ REG32(SIM_TERM_ADDR) = 0; -+} --- -2.24.0.rc1.363.gb1bccd3e3d-goog -
diff --git a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch new file mode 100644 index 0000000..7e3de3a --- /dev/null +++ b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
@@ -0,0 +1,591 @@ +From b9340dec1bcfadfa02b7b74a5b5a8d168de6e627 Mon Sep 17 00:00:00 2001 +From: Greg Chadwick <gac@lowrisc.org> +Date: Wed, 15 Apr 2020 15:44:54 +0100 +Subject: [PATCH 2/3] Add OpenTitan target + +--- + riscv-target/opentitan/README.md | 126 ++++++++++++++++++ + riscv-target/opentitan/compliance_io.h | 22 +++ + riscv-target/opentitan/compliance_test.h | 35 +++++ + .../opentitan/device/rv32imc/Makefile.include | 86 ++++++++++++ + .../opentitan/device/rv32imc/isa.yaml | 49 +++++++ + riscv-target/opentitan/device/rv32imc/link.ld | 56 ++++++++ + riscv-target/opentitan/device/rv32imc/main.c | 39 ++++++ + .../opentitan/device/rv32imc/platform.yaml | 10 ++ + .../opentitan/device/rv32imc/run_rvc_test.S | 85 ++++++++++++ + 9 files changed, 508 insertions(+) + create mode 100644 riscv-target/opentitan/README.md + create mode 100644 riscv-target/opentitan/compliance_io.h + create mode 100644 riscv-target/opentitan/compliance_test.h + create mode 100644 riscv-target/opentitan/device/rv32imc/Makefile.include + create mode 100644 riscv-target/opentitan/device/rv32imc/isa.yaml + create mode 100644 riscv-target/opentitan/device/rv32imc/link.ld + create mode 100644 riscv-target/opentitan/device/rv32imc/main.c + create mode 100644 riscv-target/opentitan/device/rv32imc/platform.yaml + create mode 100644 riscv-target/opentitan/device/rv32imc/run_rvc_test.S + +diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md +new file mode 100644 +index 0000000..301e9ad +--- /dev/null ++++ b/riscv-target/opentitan/README.md +@@ -0,0 +1,126 @@ ++ ++# Overview ++The RISC-V compliance test can be run on either OpenTitan FPGA or Verilator. ++OpenTitan is an open source project to build transparent, high-quality reference designs for silicon root of trust chips. ++Please see the [OpenTitan website](https://opentitan.org) for more details. ++ ++To run on Verilator, set the variables below ++ ++```console ++$ export RISCV_TARGET=opentitan ++$ export RISCV_DEVICE=rv32imc ++$ export OT_TARGET=verilator ++``` ++ ++To run on FPGA, set the variables below. ++The `FPGA_UART` variable must be set to wherever a valid device is connected. ++ ++```console ++$ export RISCV_TARGET=opentitan ++$ export RISCV_DEVICE=rv32imc ++$ export OT_TARGET=fpga ++$ export OT_FPGA_UART=/dev/tty* ++``` ++ ++In addition the UART device must be appropriately configured. ++ ++```console ++$ stty -F $OT_FPGA_UART 230400 raw ++``` ++ ++By default, the test assumes there exists a valid Verilator build at `${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`. ++If your Verilator build is at a different location, please set that as well when running with Verilator. ++ ++```console ++$ export TARGET_SIM=${PATH_TO_VERILATOR_BUILD} ++``` ++ ++When running against FPGA, the test assumes the FPGA is already programmed and ready to go with spiflash available at `${REPO_TOP}/build-bin/sw/host/spiflash/spiflash_export` ++To quickly get started with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/). ++ ++The meson build environment must be setup before running the compliance test. ++ ++```console ++$ cd $REPO_TOP ++$ ./meson_init.sh ++``` ++ ++Now, run the tests from the riscv_compliance directory. ++The following output will be seen (software build steps are truncated). ++The example below uses Verilator as an example, but the FPGA output is nearly identical. ++ ++```console ++$ cd $RISCV_COMPLIANCE_REPO_BASE ++$ make RISCV_ISA=rv32i ++ ++... verbose test output ... ++ ++Compare to reference files ... ++ ++Check I-ADD-01 ... OK ++Check I-ADDI-01 ... OK ++Check I-AND-01 ... OK ++Check I-ANDI-01 ... OK ++Check I-AUIPC-01 ... OK ++Check I-BEQ-01 ... OK ++Check I-BGE-01 ... OK ++Check I-BGEU-01 ... OK ++Check I-BLT-01 ... OK ++Check I-BLTU-01 ... OK ++Check I-BNE-01 ... OK ++Check I-DELAY_SLOTS-01 ... OK ++Check I-EBREAK-01 ... OK ++Check I-ECALL-01 ... OK ++Check I-ENDIANESS-01 ... OK ++Check I-IO-01 ... OK ++Check I-JAL-01 ... OK ++Check I-JALR-01 ... OK ++Check I-LB-01 ... OK ++Check I-LBU-01 ... OK ++Check I-LH-01 ... OK ++Check I-LHU-01 ... OK ++Check I-LUI-01 ... OK ++Check I-LW-01 ... OK ++Check I-MISALIGN_JMP-01 ... IGNORE ++Check I-MISALIGN_LDST-01 ... IGNORE ++Check I-NOP-01 ... OK ++Check I-OR-01 ... OK ++Check I-ORI-01 ... OK ++Check I-RF_size-01 ... OK ++Check I-RF_width-01 ... OK ++Check I-RF_x0-01 ... OK ++Check I-SB-01 ... OK ++Check I-SH-01 ... OK ++Check I-SLL-01 ... OK ++Check I-SLLI-01 ... OK ++Check I-SLT-01 ... OK ++Check I-SLTI-01 ... OK ++Check I-SLTIU-01 ... OK ++Check I-SLTU-01 ... OK ++Check I-SRA-01 ... OK ++Check I-SRAI-01 ... OK ++Check I-SRL-01 ... OK ++Check I-SRLI-01 ... OK ++Check I-SUB-01 ... OK ++Check I-SW-01 ... OK ++Check I-XOR-01 ... OK ++Check I-XORI-01 ... OK ++-------------------------------- ++OK: 48/48 ++``` ++ ++There are several test suites that can be run `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr`. ++Change the `RISCV_ISA` argument passed to `make` to choose between them. ++ ++ ++## Removed/Broken Tests ++A small number of tests are not run for OpenTitan riscv_compliance as they fail ++due to flaws in the compliance test suite rather than Ibex/OpenTitan itself (see ++https://github.com/lowRISC/ibex/issues/100). The I-FENCE.I-01 test attempts to ++write instruction memory which fails in the OT system as this writes to flash ++which can't be done. ++ ++* I-MISALIGN_JMP-01 ++* I-MISALIGN_LDST-01 ++* I-FENCE.I-01 ++ +diff --git a/riscv-target/opentitan/compliance_io.h b/riscv-target/opentitan/compliance_io.h +new file mode 100644 +index 0000000..2774158 +--- /dev/null ++++ b/riscv-target/opentitan/compliance_io.h +@@ -0,0 +1,22 @@ ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// RISC-V Compliance IO Test Header File ++ ++ ++#ifndef _COMPLIANCE_IO_H ++#define _COMPLIANCE_IO_H ++ ++//----------------------------------------------------------------------- ++// RV IO Macros (Non functional) ++//----------------------------------------------------------------------- ++ ++#define RVTEST_IO_INIT ++#define RVTEST_IO_WRITE_STR(_SP, _STR) ++#define RVTEST_IO_CHECK() ++#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) ++#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) ++#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) ++ ++#endif // _COMPLIANCE_IO_H +diff --git a/riscv-target/opentitan/compliance_test.h b/riscv-target/opentitan/compliance_test.h +new file mode 100644 +index 0000000..978d578 +--- /dev/null ++++ b/riscv-target/opentitan/compliance_test.h +@@ -0,0 +1,35 @@ ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// RISC-V Compliance Test Header File ++ ++#ifndef _COMPLIANCE_TEST_H ++#define _COMPLIANCE_TEST_H ++ ++#include "riscv_test.h" ++ ++//----------------------------------------------------------------------- ++// RV Compliance Macros ++//----------------------------------------------------------------------- ++#define RV_COMPLIANCE_HALT \ ++ j end_rvc_test; \ ++ ++#define RV_COMPLIANCE_RV32M \ ++ RVTEST_RV32M \ ++ ++ ++#define RV_COMPLIANCE_CODE_BEGIN \ ++ RVTEST_CODE_BEGIN \ ++ ++#define RV_COMPLIANCE_CODE_END \ ++ RVTEST_CODE_END \ ++ ++#define RV_COMPLIANCE_DATA_BEGIN \ ++ .section .data; \ ++ RVTEST_DATA_BEGIN \ ++ ++#define RV_COMPLIANCE_DATA_END \ ++ RVTEST_DATA_END \ ++ ++#endif +diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include +new file mode 100644 +index 0000000..1bfece7 +--- /dev/null ++++ b/riscv-target/opentitan/device/rv32imc/Makefile.include +@@ -0,0 +1,86 @@ ++# Copyright lowRISC contributors. ++# Licensed under the Apache License, Version 2.0, see LICENSE for details. ++# SPDX-License-Identifier: Apache-2.0 ++ ++OPENTITAN = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc ++OT_SW = $(ROOTDIR)/../../device ++OT_ROOT = $(OT_SW)/../../ ++OT_BIN ?= $(OT_ROOT)/build-bin ++OT_BUILD = $(OT_ROOT)/build-out ++OT_TOOLS ?= /tools/riscv/bin ++OT_FPGA_UART ?= ++OT_TARGET ?= fpga ++LDSCRIPT = $(OT_ROOT)/sw/device/exts/common/flash_link.ld ++DEFINES = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DRVTEST_ENTRY=_rvc_start -DTRAPALIGN=8 ++TARGET_SIM ?= $(OT_ROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator ++ ++ifeq ($(OT_TARGET),fpga) ++ CARG = ++ MAKEARG = ++ PYTEST_OPT = --fpga_uart $(OT_FPGA_UART) --spiflash $(OT_BIN)/sw/host/spiflash/spiflash \ ++ --test_bin $(<).bin ++ OT_SW_TARGET = fpga_nexysvideo ++else ++ CARG = -DSIMULATION=1 ++ MAKEARG = SIM=1 ++ PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).vmem \ ++ --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.vmem ++ OT_SW_TARGET = sim_verilator ++endif ++ ++COMPLIANCE_LIB_EXPORT = sw/device/riscv_compliance_lib/riscv_compliance_lib_export_$(OT_SW_TARGET) ++COMPLIANCE_LIB = ot_riscv_compliance_$(OT_SW_TARGET) ++ ++# The run target recipe does the following things: ++# Invoke pytest to run the test ++# Parse the resulting log for the output signatures ++# Convert all signatures to lower case since the reference is in all lower case ++RUN_TARGET=\ ++ pytest -s -v $(OT_ROOT)/test/systemtest/functional_$(OT_TARGET)_test.py \ ++ $(PYTEST_OPT) \ ++ --log $(<).uart.log; \ ++ grep -o 'SIG: [a-zA-Z0-9_]*' $(<).uart.log | sed 's/SIG: //' \ ++ > $(*).signature.temp.output; \ ++ tr '[:upper:]' '[:lower:]' < $(*).signature.temp.output > $(*).signature.output; ++ ++ ++RISCV_PREFIX ?= ${OT_TOOLS}/riscv32-unknown-elf- ++RISCV_GCC ?= ${OT_TOOLS}/riscv32-unknown-elf-gcc ++RISCV_OBJDUMP ?= ${OT_TOOLS}/riscv32-unknown-elf-objdump ++RISCV_OBJCOPY ?= ${OT_TOOLS}/riscv32-unknown-elf-objcopy ++RISCV_NM ?= ${OT_TOOLS}/riscv32-unknown-elf-nm ++RISCV_READELF ?= ${OT_TOOLS}/riscv32-unknown-elf-readelf ++RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -fno-builtin -g -Wl,--no-relax ++ ++ ++ ++ ++# Build the verilator boot rom if we're running on verilator and build the ++# support library. These builds can be disabled by setting ++# OT_RV_NO_LIB_ROM_BUILD=1 which is used in CI. ++ifneq ($(OT_RV_NO_LIB_ROM_BUILD), 1) ++ifeq ($(OT_TARGET), verilator) ++ COMPILE_TARGET = ninja -C $(OT_BUILD) sw/device/boot_rom/boot_rom_export_$(OT_SW_TARGET); ++endif ++ COMPILE_TARGET += ninja -C $(OT_BUILD) $(COMPLIANCE_LIB_EXPORT); ++endif ++COMPILE_TARGET += \ ++ $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ ++ -I$(ROOTDIR)/riscv-test-env/ \ ++ -I$(ROOTDIR)/riscv-test-env/p/ \ ++ -I$(OT_ROOT) \ ++ -I$(TARGETDIR)/$(RISCV_TARGET)/ \ ++ -I$(TARGETDIR)/$(RISCV_TARGET)/ \ ++ $(DEFINES) -T$(LDSCRIPT) $$< \ ++ $(OPENTITAN)/main.c \ ++ $(OPENTITAN)/run_rvc_test.S \ ++ $(OT_ROOT)/sw/device/lib/irq_vectors.S \ ++ $(OT_ROOT)/sw/device/exts/common/flash_crt.S \ ++ -L$(OT_BIN)/sw/device/riscv_compliance_lib \ ++ -l$(COMPLIANCE_LIB) \ ++ -o $$(@); \ ++ $$(RISCV_OBJDUMP) -SD $$(@) > $$(@).objdump; \ ++ $$(RISCV_READELF) -a $$(@) > $$(@).readelf; \ ++ $$(RISCV_NM) $$(@) > $$(@).nm; \ ++ $$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin; \ ++ srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).vmem -vmem +diff --git a/riscv-target/opentitan/device/rv32imc/isa.yaml b/riscv-target/opentitan/device/rv32imc/isa.yaml +new file mode 100644 +index 0000000..c526fec +--- /dev/null ++++ b/riscv-target/opentitan/device/rv32imc/isa.yaml +@@ -0,0 +1,49 @@ ++## Copyright lowRISC contributors. ++## Licensed under the Apache License, Version 2.0, see LICENSE for details. ++## SPDX-License-Identifier: Apache-2.0 ++ ++Device: rv32imc ++Vendor: opentitan ++ ++ISA: RV32IMC ++misa: ++ implemented: True ++ MXL: ++ range: ++ rangelist: [[1]] ++ mode: Unchanged ++ Extensions: ++ bitmask: ++ mask: 0x0 ++ default: 0x1104 ++hw_data_misaligned_support: True ++mtvec: ++ MODE: ++ range: ++ rangelist: [[1]] ++ BASE: ++ range: ++ rangelist: [[0x20000020]] ++ ++mstatus: ++ MPP: ++ range: ++ rangelist: [[3]] ++ ++User_Spec_Version: "2.3" ++Privilege_Spec_Version: "1.11" ++ ++mvendorid: ++ implemented: false ++marchid: ++ implemented: false ++mimpid: ++ implemented: false ++mhartid: 0 ++ ++mcycle: ++ is_hardwired: true ++ implemented: true ++minstret: ++ is_hardwired: true ++ implemented: true +diff --git a/riscv-target/opentitan/device/rv32imc/link.ld b/riscv-target/opentitan/device/rv32imc/link.ld +new file mode 100644 +index 0000000..2ae1f1c +--- /dev/null ++++ b/riscv-target/opentitan/device/rv32imc/link.ld +@@ -0,0 +1,56 @@ ++/* Copyright lowRISC contributors. ++ Licensed under the Apache License, Version 2.0, see LICENSE for details. ++ SPDX-License-Identifier: Apache-2.0 ++*/ ++ ++OUTPUT_ARCH("riscv") ++ENTRY(_start) ++ ++/* required to correctly link newlib */ ++GROUP(-lc -lgloss -lgcc -lsupc++) ++ ++SEARCH_DIR(.) ++__DYNAMIC = 0; ++ ++MEMORY ++{ ++ flash (rx) : ORIGIN = 0x20000000, LENGTH = 0x100000 ++ ram (wx) : ORIGIN = 0x10000000, LENGTH = 0x10000 ++} ++ ++_stack_start = ORIGIN(ram) + LENGTH(ram); ++ ++/* need to move signature data to modifiable memory */ ++SECTIONS ++{ ++ .text.init ORIGIN(flash) : { ++ *(.text.init) ++ } > flash ++ ++ .text.trap : { ++ . = ALIGN(0x100); ++ *(.text.trap) ++ } > flash ++ ++ .text : { ++ . = ALIGN(0x100); ++ *(.text) ++ } > flash ++ ++ .data : { ++ . = ALIGN(0x100); ++ *(.data.*) ++ } > flash ++ ++ .tohost ORIGIN(ram) (NOLOAD) : { ++ *(.tohost) ++ *(.test.output) ++ } > ram ++ ++ .bss : { ++ . = ALIGN(0x100); ++ *(.bss) ++ } > ram ++ ++ _end = .; ++} +diff --git a/riscv-target/opentitan/device/rv32imc/main.c b/riscv-target/opentitan/device/rv32imc/main.c +new file mode 100644 +index 0000000..4691578 +--- /dev/null ++++ b/riscv-target/opentitan/device/rv32imc/main.c +@@ -0,0 +1,39 @@ ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// Wrapper for RISC-V compliance tests, it saves architectural state before ++// jumping into the test (via run_rvc_test). After the test completes it dumps ++// the signature out via the UART. ++ ++#include "sw/device/lib/uart.h" ++#include "sw/device/lib/arch/device.h" ++#include "sw/device/lib/common.h" ++ ++extern void run_rvc_test(void); ++ ++extern uint32_t begin_signature[]; ++extern uint32_t end_signature[]; ++ ++int main(int argc, char **argv) { ++ uart_init(kUartBaudrate); ++ base_set_stdout(uart_stdout); ++ ++ run_rvc_test(); ++ ++ uint32_t size = end_signature - begin_signature; ++ ++ for (uint32_t i = 0; i < size; ++i) { ++ base_printf("SIG: %08x\r\n", REG32(begin_signature + i)); ++ } ++ ++ base_printf("PASS!\r\n"); ++ ++ // The "End" string here is a workaround to pytest console parsing. ++ // Without additional characters, the "\n" from above is not always ++ // detected, and this causes pytest to register the test as a false failure. ++ // This needs to be debugged further to see if it's a setup or hw issue. ++ base_printf("End"); ++ ++ return 0; ++} +diff --git a/riscv-target/opentitan/device/rv32imc/platform.yaml b/riscv-target/opentitan/device/rv32imc/platform.yaml +new file mode 100644 +index 0000000..7d547d9 +--- /dev/null ++++ b/riscv-target/opentitan/device/rv32imc/platform.yaml +@@ -0,0 +1,10 @@ ++# Copyright lowRISC contributors. ++# Licensed under the Apache License, Version 2.0, see LICENSE for details. ++# SPDX-License-Identifier: Apache-2.0 ++ ++mtime: ++ implemented: False ++nmi: ++ address: 0x800000FC # trap vec (mtvec base) + 0x7C ++reset: ++ address: 0x80000080 # boot address + 0x80 +diff --git a/riscv-target/opentitan/device/rv32imc/run_rvc_test.S b/riscv-target/opentitan/device/rv32imc/run_rvc_test.S +new file mode 100644 +index 0000000..aef6a23 +--- /dev/null ++++ b/riscv-target/opentitan/device/rv32imc/run_rvc_test.S +@@ -0,0 +1,85 @@ ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// Allocate space in .bss for saving architectural state before jumping into the ++// test ++ .lcomm arch_state_store, 4 * 17 //(ra, sp, gp, tp, s0-s11, mtvec) ++ ++ .section .text ++ ++run_rvc_test: ++ .globl run_rvc_test ++ ++ // Save the architectural state. There is no need to save caller preserved ++ // registers as C calling run_rvc_test will expect them to be clobbered anyway ++ // and act appropriately. RA is the exception as we need to know where to jump ++ // back to after the test is complete. mtvec is saved as the compliance test ++ // environment alters it, other CSRs may also be changed but no adverse ++ // effects have yet been observed from this. ++ la t0, arch_state_store ++ ++ sw ra, 0(t0) ++ sw sp, 4(t0) ++ sw gp, 8(t0) ++ sw tp, 12(t0) ++ sw s0, 16(t0) ++ sw s1, 20(t0) ++ sw s2, 24(t0) ++ sw s3, 28(t0) ++ sw s4, 32(t0) ++ sw s5, 36(t0) ++ sw s6, 40(t0) ++ sw s7, 44(t0) ++ sw s8, 48(t0) ++ sw s9, 52(t0) ++ sw s10, 56(t0) ++ sw s11, 60(t0) ++ ++ csrr t1, mtvec ++ sw t1, 64(t0) ++ ++// jump to compliance test ++ j _rvc_start ++ ++end_rvc_test: ++ .globl end_rvc_test ++ ++ // restore architectural state ++ la t0, arch_state_store ++ ++ lw ra, 0(t0) ++ lw sp, 4(t0) ++ lw gp, 8(t0) ++ lw tp, 12(t0) ++ lw s0, 16(t0) ++ lw s1, 20(t0) ++ lw s2, 24(t0) ++ lw s3, 28(t0) ++ lw s4, 32(t0) ++ lw s5, 36(t0) ++ lw s6, 40(t0) ++ lw s7, 44(t0) ++ lw s8, 48(t0) ++ lw s9, 52(t0) ++ lw s10, 56(t0) ++ lw s11, 60(t0) ++ ++ lw t1, 64(t0) ++ csrw mtvec, t1 ++ ++ jr ra ++ ++// riscv-compliance loads its own mtvec that will jump to mtvec_handler if the ++// symbol exists ++mtvec_handler: ++ .globl mtvec_handler ++ ++ // restore gp/sp so handler from OT library can work ++ la t0, arch_state_store ++ ++ lw sp, 4(t0) ++ lw gp, 8(t0) ++ ++ // jump to the handler from the OT library ++ j _vectors_start +-- +2.17.1 +
diff --git a/sw/vendor/patches/riscv_compliance/0002-Remove-specific-tests-that-do-not-pass-on-ibex.patch b/sw/vendor/patches/riscv_compliance/0002-Remove-specific-tests-that-do-not-pass-on-ibex.patch deleted file mode 100644 index 5e6ab8a..0000000 --- a/sw/vendor/patches/riscv_compliance/0002-Remove-specific-tests-that-do-not-pass-on-ibex.patch +++ /dev/null
@@ -1,459 +0,0 @@ -From d57e5fa67c1b27a5812b0b1c63c406e2eb65e44b Mon Sep 17 00:00:00 2001 -From: Timothy Chen <timothytim@google.com> -Date: Thu, 7 Nov 2019 21:54:13 -0800 -Subject: [PATCH 2/2] Remove specific tests that do not pass on ibex. - -When FENCE.I is implemented in the future, add these tests back. - -Signed-off-by: Timothy Chen <timothytim@google.com> ---- - riscv-target/opentitan/README.md | 92 ++++++------------- - riscv-target/opentitan/compliance_test.h | 2 +- - .../opentitan/device/rv32imc/Makefile.include | 68 +++++++------- - riscv-target/opentitan/device/rv32imc/link.ld | 33 +++---- - .../opentitan/device/rv32imc/platform.yaml | 6 +- - riscv-target/opentitan/device/rv32imc/wrap.c | 5 +- - riscv-test-suite/rv32i/Makefrag | 21 +++-- - 7 files changed, 96 insertions(+), 131 deletions(-) - -diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md -index 7fceaae..bca8749 100644 ---- a/riscv-target/opentitan/README.md -+++ b/riscv-target/opentitan/README.md -@@ -1,15 +1,15 @@ ----- --title: "OpenTitan RISC-V Compliance Testing" ----- - - # Overview --The RISC-V compliance test can be run on either FPGA or Verilator. -+The RISC-V compliance test can be run on either OpenTitan FPGA or Verilator. -+OpenTitan is an open source project to build transparent, high-quality reference designs for silicon root of trust chips. -+Please see the [OpenTitan website](https://opentitan.org) for more details. -+ - To run on Verilator, set the variables below - - ```console - $ export RISCV_TARGET=opentitan - $ export RISCV_DEVICE=rv32imc --$ export TARGET=verilator -+$ export OPENTITAN_TARGET=verilator - ``` - - To run on FPGA, set the variables below. -@@ -18,31 +18,30 @@ The `FPGA_UART` variable must be set to wherever a valid device is connected. - ```console - $ export RISCV_TARGET=opentitan - $ export RISCV_DEVICE=rv32imc --$ export TARGET=fpga --$ export FPGA_UART=/dev/tty* -+$ export OT_TARGET=fpga -+$ export OT_FPGA_UART=/dev/tty* - ``` - - By default, the test assumes there exists a valid Verilator build at `${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`. - If your Verilator build is at a different location, please set that as well when running with Verilator. --For instructions on how to create a Verilator build, please refer to the [Verilator guide]({{< relref "doc/ug/getting_started_verilator" >}}). - - ```console - $ export TARGET_SIM=${PATH_TO_VERILATOR_BUILD} - ``` - - When running against FPGA, the test assumes the FPGA is already programmed and ready to go. --To find out how to properly build and flash FPGA, please refer to the [FPGA manual]({{< relref "doc/rm/ref_manual_fpga" >}}) -+To quickly get started with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/) - - --Now, run the tests. -+Now, run the tests from the riscv_compliance directory. - The following output will be seen (software build steps are truncated). - The example below uses Verilator as an example, but the FPGA output is nearly identical. - - ```console --$ cd $REPO_TOP --$ make -C sw/vendor/riscv_compliance RISCV_ISA=rv32i \ -- && make -C sw/vendor/riscv_compliance RISCV_ISA=rv32im \ -- && make -C sw/vendor/riscv_compliance RISCV_ISA=rv32imc -+$ cd $RISCV_COMPLIANCE_REPO_BASE -+$ make RISCV_ISA=rv32i \ -+ && make RISCV_ISA=rv32im \ -+ && make RISCV_ISA=rv32imc - - - Rom initialized with program at $REPO_TOP/sw/vendor/riscv_compliance/../../boot_rom/rom.vmem -@@ -77,59 +76,22 @@ Check I-ADD-01 ... OK - Check I-ADDI-01 ... OK - Check I-AND-01 ... OK - Check I-ANDI-01 ... OK --Check I-AUIPC-01 ... OK --Check I-BEQ-01 ... OK --Check I-BGE-01 ... OK --Check I-BGEU-01 ... OK --Check I-BLT-01 ... OK --Check I-BLTU-01 ... OK --Check I-BNE-01 ... OK --Check I-CSRRC-01 ... OK --Check I-CSRRCI-01 ... OK --Check I-CSRRS-01 ... OK --Check I-CSRRSI-01 ... OK --Check I-CSRRW-01 ... OK --Check I-CSRRWI-01 ... OK --Check I-DELAY_SLOTS-01 ... OK --Check I-EBREAK-01 ... OK --Check I-ECALL-01 ... OK --Check I-ENDIANESS-01 ... OK --Check I-FENCE.I-01 ... OK --Check I-IO ... OK --Check I-JAL-01 ... OK --Check I-JALR-01 ... OK --Check I-LB-01 ... OK --Check I-LBU-01 ... OK --Check I-LH-01 ... OK --Check I-LHU-01 ... OK --Check I-LUI-01 ... OK --Check I-LW-01 ... OK --Check I-MISALIGN_JMP-01 ... OK --Check I-MISALIGN_LDST-01 ... OK --Check I-NOP-01 ... OK --Check I-OR-01 ... OK --Check I-ORI-01 ... OK --Check I-RF_size-01 ... OK --Check I-RF_width-01 ... OK --Check I-RF_x0-01 ... OK --Check I-SB-01 ... OK --Check I-SH-01 ... OK --Check I-SLL-01 ... OK --Check I-SLLI-01 ... OK --Check I-SLT-01 ... OK --Check I-SLTI-01 ... OK --Check I-SLTIU-01 ... OK --Check I-SLTU-01 ... OK --Check I-SRA-01 ... OK --Check I-SRAI-01 ... OK --Check I-SRL-01 ... OK --Check I-SRLI-01 ... OK --Check I-SUB-01 ... OK --Check I-SW-01 ... OK --Check I-XOR-01 ... OK --Check I-XORI-01 ... OK -+ -+... -+ - -------------------------------- - OK: 55/55 - - - ``` -+ -+ -+## Removed Tests -+A small number of tests are not run for OpenTitan riscv_compliance since the underlying core does not yet support specific features. -+The removed tests are the following: -+ -+* I-MISALIGN_JMP-01 -+* I-MISALIGN_LDST-01 -+* I-FENCE.I-01 -+* I-ECALL-01 -+* I-EBREAK-01 -diff --git a/riscv-target/opentitan/compliance_test.h b/riscv-target/opentitan/compliance_test.h -index 7f1bdd3..5d56101 100644 ---- a/riscv-target/opentitan/compliance_test.h -+++ b/riscv-target/opentitan/compliance_test.h -@@ -7,7 +7,7 @@ - #ifndef _COMPLIANCE_TEST_H - #define _COMPLIANCE_TEST_H - --#include "sw/vendor/riscv_compliance/riscv-test-env/p/riscv_test.h" -+#include "riscv_test.h" - - //----------------------------------------------------------------------- - // RV Compliance Macros -diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include -index c18820f..6b32d29 100644 ---- a/riscv-target/opentitan/device/rv32imc/Makefile.include -+++ b/riscv-target/opentitan/device/rv32imc/Makefile.include -@@ -1,29 +1,28 @@ --## Copyright lowRISC contributors. --## Licensed under the Apache License, Version 2.0, see LICENSE for details. --## SPDX-License-Identifier: Apache-2.0 -+# Copyright lowRISC contributors. -+# Licensed under the Apache License, Version 2.0, see LICENSE for details. -+# SPDX-License-Identifier: Apache-2.0 - -+OPENTITAN = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc -+OT_SW = $(ROOTDIR)/../../device -+OT_ROOT = $(OT_SW)/../../ -+OT_TOOLS ?= /tools/riscv/bin -+OT_FPGA_UART ?= -+OT_TARGET ?= fpga -+LDSCRIPT = $(OPENTITAN)/link.ld -+TRAPHANDLER = $(OPENTITAN)/handler.S -+DEFINES = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DTRAPHANDLER="\"$(TRAPHANDLER)\"" -+TARGET_SIM ?= $(OT_ROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator - --OT = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc --OTSW = $(ROOTDIR)/../../device --OTROOT = $(OTSW)/../../ --LDSCRIPT = $(OT)/link.ld --TRAPHANDLER = $(OT)/handler.S --DEFINES = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DTRAPHANDLER="\"$(TRAPHANDLER)\"" --RV_TOOLS ?= /tools/riscv/bin --FPGA_UART ?= --TARGET_SIM ?= $(OTROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator --TARGET ?= fpga -- --ifeq ($(TARGET),fpga) -+ifeq ($(OT_TARGET),fpga) - CARG = - MAKEARG = -- PYTEST_OPT = --fpga_uart $(FPGA_UART) --spiflash $(OTROOT)/sw/host/spiflash/spiflash \ -+ PYTEST_OPT = --fpga_uart $(OT_FPGA_UART) --spiflash $(OT_ROOT)/sw/host/spiflash/spiflash \ - --test_bin $(work_dir_isa)/$<.bin - else - CARG = -DSIMULATION=1 - MAKEARG = SIM=1 - PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(work_dir_isa)/$<.vmem \ -- --rom_bin $(OTSW)/boot_rom/rom.vmem -+ --rom_bin $(OT_SW)/boot_rom/rom.vmem - endif - - -@@ -32,7 +31,7 @@ endif - # Parse the resulting log for the output signatures - # Convert all signatures to lower case since the reference is in all lower case - RUN_TARGET=\ -- pytest -s -v $(OTROOT)/test/systemtest/functional_$(TARGET)_test.py \ -+ pytest -s -v $(OT_ROOT)/test/systemtest/functional_$(OT_TARGET)_test.py \ - $(PYTEST_OPT) \ - --log $(work_dir_isa)/$<.uart.log; \ - grep -o 'SIG: [a-zA-Z0-9_]*' $(work_dir_isa)/$<.uart.log | sed 's/SIG: //' \ -@@ -40,12 +39,12 @@ RUN_TARGET=\ - tr '[:upper:]' '[:lower:]' < $(work_dir_isa)/$(*).signature.temp.output > $(work_dir_isa)/$(*).signature.output; - - --RISCV_PREFIX ?= ${RV_TOOLS}/riscv32-unknown-elf- --RISCV_GCC ?= ${RV_TOOLS}/riscv32-unknown-elf-gcc --RISCV_OBJDUMP ?= ${RV_TOOLS}/riscv32-unknown-elf-objdump --RISCV_OBJCOPY ?= ${RV_TOOLS}/riscv32-unknown-elf-objcopy --RISCV_NM ?= ${RV_TOOLS}/riscv32-unknown-elf-nm --RISCV_READELF ?= ${RV_TOOLS}/riscv32-unknown-elf-readelf -+RISCV_PREFIX ?= ${OT_TOOLS}/riscv32-unknown-elf- -+RISCV_GCC ?= ${OT_TOOLS}/riscv32-unknown-elf-gcc -+RISCV_OBJDUMP ?= ${OT_TOOLS}/riscv32-unknown-elf-objdump -+RISCV_OBJCOPY ?= ${OT_TOOLS}/riscv32-unknown-elf-objcopy -+RISCV_NM ?= ${OT_TOOLS}/riscv32-unknown-elf-nm -+RISCV_READELF ?= ${OT_TOOLS}/riscv32-unknown-elf-readelf - RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g - - -@@ -55,22 +54,21 @@ RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostart - # After the libraries are built, the necessary collateral (vmem for verilator, bin - # for fpga) are created - COMPILE_TARGET=\ -- make -C $$(OTSW) SW_DIR=boot_rom $(MAKEARG) clean all; \ -+ make -C $$(OT_SW) SW_DIR=boot_rom $(MAKEARG) RV_TOOLS=$(OT_TOOLS) clean all; \ - $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ - -I$(ROOTDIR)/riscv-test-env/ \ - -I$(ROOTDIR)/riscv-test-env/p/ \ -- -I$(OTSW)/boot_rom/lib \ -- -I$(OTSW)/lib \ -- -I$(OTROOT) \ -+ -I$(OT_SW)/boot_rom/lib \ -+ -I$(OT_SW)/lib \ - -I$(TARGETDIR)/$(RISCV_TARGET)/ \ - -I$(TARGETDIR)/$(RISCV_TARGET)/ \ - $(DEFINES) -T$(LDSCRIPT) $$< \ -- $(OT)/wrap.c \ -- -L$(OTSW)/boot_rom/lib \ -+ $(OPENTITAN)/wrap.c \ -+ -L$(OT_SW)/boot_rom/lib \ - -lot \ - -o $(work_dir_isa)/$$@; \ -- $$(RISCV_OBJDUMP) -SD $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \ -- $$(RISCV_READELF) -a $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.readelf; \ -- $$(RISCV_NM) $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.nm; \ -- $$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@ $(work_dir_isa)/$$@.bin; \ -- srec_cat $(work_dir_isa)/$$@.bin -binary -offset 0x0000 -byte-swap 4 -o $(work_dir_isa)/$$@.vmem -vmem -+ $$(RISCV_OBJDUMP) -SD $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \ -+ $$(RISCV_READELF) -a $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.readelf; \ -+ $$(RISCV_NM) $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.nm; \ -+ $$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@ $(work_dir_isa)/$$@.bin; \ -+ srec_cat $(work_dir_isa)/$$@.bin -binary -offset 0x0000 -byte-swap 4 -o $(work_dir_isa)/$$@.vmem -vmem -diff --git a/riscv-target/opentitan/device/rv32imc/link.ld b/riscv-target/opentitan/device/rv32imc/link.ld -index 9259121..2ae1f1c 100644 ---- a/riscv-target/opentitan/device/rv32imc/link.ld -+++ b/riscv-target/opentitan/device/rv32imc/link.ld -@@ -3,19 +3,19 @@ - SPDX-License-Identifier: Apache-2.0 - */ - --OUTPUT_ARCH( "riscv" ) -+OUTPUT_ARCH("riscv") - ENTRY(_start) - - /* required to correctly link newlib */ --GROUP( -lc -lgloss -lgcc -lsupc++ ) -+GROUP(-lc -lgloss -lgcc -lsupc++) - - SEARCH_DIR(.) - __DYNAMIC = 0; - - MEMORY - { -- flash (rx) : ORIGIN = 0x20000000, LENGTH = 0x100000 -- ram (wx) : ORIGIN = 0x10000000, LENGTH = 0x10000 -+ flash (rx) : ORIGIN = 0x20000000, LENGTH = 0x100000 -+ ram (wx) : ORIGIN = 0x10000000, LENGTH = 0x10000 - } - - _stack_start = ORIGIN(ram) + LENGTH(ram); -@@ -24,32 +24,33 @@ _stack_start = ORIGIN(ram) + LENGTH(ram); - SECTIONS - { - .text.init ORIGIN(flash) : { -- *(.text.init) -+ *(.text.init) - } > flash - - .text.trap : { -- . = ALIGN(0x100); -- *(.text.trap) -+ . = ALIGN(0x100); -+ *(.text.trap) - } > flash - - .text : { -- . = ALIGN(0x100); -- *(.text) -+ . = ALIGN(0x100); -+ *(.text) - } > flash - - .data : { -- . = ALIGN(0x100); -- *(.data.*) -+ . = ALIGN(0x100); -+ *(.data.*) - } > flash - - .tohost ORIGIN(ram) (NOLOAD) : { -- *(.tohost) -- *(.test.output) -- } > ram -+ *(.tohost) -+ *(.test.output) -+ } > ram - - .bss : { -- . = ALIGN(0x100); -- *(.bss) -+ . = ALIGN(0x100); -+ *(.bss) - } > ram -+ - _end = .; - } -diff --git a/riscv-target/opentitan/device/rv32imc/platform.yaml b/riscv-target/opentitan/device/rv32imc/platform.yaml -index e834efb..7d547d9 100644 ---- a/riscv-target/opentitan/device/rv32imc/platform.yaml -+++ b/riscv-target/opentitan/device/rv32imc/platform.yaml -@@ -1,6 +1,6 @@ --## Copyright lowRISC contributors. --## Licensed under the Apache License, Version 2.0, see LICENSE for details. --## SPDX-License-Identifier: Apache-2.0 -+# Copyright lowRISC contributors. -+# Licensed under the Apache License, Version 2.0, see LICENSE for details. -+# SPDX-License-Identifier: Apache-2.0 - - mtime: - implemented: False -diff --git a/riscv-target/opentitan/device/rv32imc/wrap.c b/riscv-target/opentitan/device/rv32imc/wrap.c -index 5834199..37e2224 100644 ---- a/riscv-target/opentitan/device/rv32imc/wrap.c -+++ b/riscv-target/opentitan/device/rv32imc/wrap.c -@@ -8,10 +8,11 @@ - #include "uart.h" - - #define SIM_TERM_ADDR 0x10008000 -+extern uint32_t begin_signature[]; -+extern uint32_t end_signature[]; - - void dump_signature(void) { -- extern uint32_t begin_signature[]; -- extern uint32_t end_signature[]; -+ - - uint32_t size = end_signature - begin_signature; - uart_init(UART_BAUD_RATE); -diff --git a/riscv-test-suite/rv32i/Makefrag b/riscv-test-suite/rv32i/Makefrag -index 4334916..9e5991b 100644 ---- a/riscv-test-suite/rv32i/Makefrag -+++ b/riscv-test-suite/rv32i/Makefrag -@@ -2,7 +2,7 @@ - # - # Copyright (c) 2017, Codasip Ltd. - # All rights reserved. --# -+# - # Redistribution and use in source and binary forms, with or without - # modification, are permitted provided that the following conditions are met: - # * Redistributions of source code must retain the above copyright -@@ -13,8 +13,8 @@ - # * Neither the name of the Codasip Ltd. nor the - # names of its contributors may be used to endorse or promote products - # derived from this software without specific prior written permission. --# --# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS - # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY -@@ -22,7 +22,7 @@ - # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT --# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - # - # Description: Makefrag for RV32I compliance tests -@@ -32,8 +32,6 @@ rv32i_sc_tests = \ - I-RF_x0-01 \ - I-RF_size-01 \ - I-RF_width-01 \ -- I-MISALIGN_JMP-01 \ -- I-MISALIGN_LDST-01 \ - I-DELAY_SLOTS-01 \ - I-JAL-01 \ - I-JALR-01 \ -@@ -56,7 +54,6 @@ rv32i_sc_tests = \ - I-XOR-01 \ - I-SUB-01 \ - I-ANDI-01 \ -- I-FENCE.I-01 \ - I-SLTI-01 \ - I-SLTIU-01 \ - I-BEQ-01 \ -@@ -80,10 +77,16 @@ rv32i_sc_tests = \ - I-CSRRSI-01 \ - I-CSRRC-01 \ - I-CSRRCI-01 \ -- I-ECALL-01 \ -- I-EBREAK-01 \ - I-IO \ - -+ # These tests are currently removed since the underlying core in opentitan -+ # does not yet support FENCE.I instructions -+ #I-MISALIGN_JMP-01 -+ #I-MISALIGN_LDST-01 -+ #I-FENCE.I-01 -+ #I-ECALL-01 -+ #I-EBREAK-01 -+ - - rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) - --- -2.24.0.rc1.363.gb1bccd3e3d-goog -
diff --git a/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch new file mode 100644 index 0000000..5e346d9 --- /dev/null +++ b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch
@@ -0,0 +1,66 @@ +From 1523e781df791f91cea59caeaa870087c744bf37 Mon Sep 17 00:00:00 2001 +From: Greg Chadwick <gac@lowrisc.org> +Date: Wed, 15 Apr 2020 18:39:08 +0100 +Subject: [PATCH 3/3] Remove tests that do not pass on OpenTitan + +--- + riscv-test-suite/rv32i/Makefrag | 15 +++++++++------ + 1 file changed, 9 insertions(+), 6 deletions(-) + +diff --git a/riscv-test-suite/rv32i/Makefrag b/riscv-test-suite/rv32i/Makefrag +index a19fff8..36b8068 100644 +--- a/riscv-test-suite/rv32i/Makefrag ++++ b/riscv-test-suite/rv32i/Makefrag +@@ -2,7 +2,7 @@ + # + # Copyright (c) 2017, Codasip Ltd. + # All rights reserved. +-# ++# + # Redistribution and use in source and binary forms, with or without + # modification, are permitted provided that the following conditions are met: + # * Redistributions of source code must retain the above copyright +@@ -13,8 +13,8 @@ + # * Neither the name of the Codasip Ltd. nor the + # names of its contributors may be used to endorse or promote products + # derived from this software without specific prior written permission. +-# +-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY +@@ -22,7 +22,7 @@ + # (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + # + # Description: Makefrag for RV32I compliance tests +@@ -32,8 +32,6 @@ rv32i_sc_tests = \ + I-RF_x0-01 \ + I-RF_size-01 \ + I-RF_width-01 \ +- I-MISALIGN_JMP-01 \ +- I-MISALIGN_LDST-01 \ + I-DELAY_SLOTS-01 \ + I-JAL-01 \ + I-JALR-01 \ +@@ -76,6 +74,11 @@ rv32i_sc_tests = \ + I-ECALL-01 \ + I-EBREAK-01 \ + I-IO-01 \ ++ ++ # These tests are broken due to flaws in riscv-compliance rather than ++ # Ibex/OpenTitan (see https://github.com/lowRISC/ibex/issues/100) ++ #I-MISALIGN_JMP-01 ++ #I-MISALIGN_LDST-01 + + + rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) +-- +2.17.1 +
diff --git a/sw/vendor/riscv_compliance.lock.hjson b/sw/vendor/riscv_compliance.lock.hjson index 6a7cd1a..4abee73 100644 --- a/sw/vendor/riscv_compliance.lock.hjson +++ b/sw/vendor/riscv_compliance.lock.hjson
@@ -2,13 +2,13 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -// This file is generated by the vendor_hw script. Please do not modify it +// This file is generated by the util/vendor script. Please do not modify it // manually. { upstream: { url: https://github.com/riscv/riscv-compliance.git - rev: 7fdd4099dc2ebbdbc0f4aa22696996d3cb3564bf + rev: 5a978cfd444d5e640150d46703deda99057b2bbb } }
diff --git a/sw/vendor/riscv_compliance/.gitignore b/sw/vendor/riscv_compliance/.gitignore index 9c59836..4ff1094 100644 --- a/sw/vendor/riscv_compliance/.gitignore +++ b/sw/vendor/riscv_compliance/.gitignore
@@ -5,3 +5,5 @@ /.project /work/ /setup.env +#ignore Mac file system artifacts +*.DS_Store
diff --git a/sw/vendor/riscv_compliance/ChangeLog b/sw/vendor/riscv_compliance/ChangeLog index 0642481..4d6fa14 100644 --- a/sw/vendor/riscv_compliance/ChangeLog +++ b/sw/vendor/riscv_compliance/ChangeLog
@@ -1,3 +1,71 @@ +2020-03-19 Neel Gala <neelgala@gmail.com> + * restructuring the riscv-test-suite to indicate clearly what is deprecated, wip and usable + tests. + * based on the above fixed the directory structure for riscv-targets where-ever applicable. Only + tested riscvOVPsim and spike. + * fixed script bugs for spike as well + * renamed rv32i/I-IO.S to rv32i/I-IO-01.S along with necessary changes to the reference files + and Makefrag + * renamed mbadaddr csr to mtval as raised in issue #31 + * C.SWSP-01.S test updated to fix issue #37 + +2020-03-18 Neel Gala <neelgala@gmail.com> + * fixed doc/README.adoc with correct version to pass the sanity-check in the doc/Makefile + +2020-02-07 Prashanth Mundkur <prashanth.mundkur@gmail.com> + * Support F extension on RV32 sail-riscv-c. + +2019-12-01 Allen Baum <allen.baum@esperantotech.com> + * modified macro names to conformn to riscof naming convention of model specific vs. pre-defined + * add more complete list of macros, their uses, parameters, and whether they are required or optional + * minor structural changes (moving sentences, renumbering) and typo fixes + * clarified impact of debug macros + * clarified how SIGUPD and BASEUPD must be used + * remove section about test taxonomy, binary tests, emulated ops + * clarify/fix boundary between test target and framework responsibilities + (split test target into test target and test shell) + * remove To Be discussed items that have been discussed + * remove default case condition; if conditions are unchanged, part of same case + * minor grammatical changes related to the above + +2019-10-16 Allen Baum <allen.baum@esperantotech.com> + * spec/TestFormatSpec.adoc: changed the format of the signature to fixed physical address size, fixed 32b data size extracted from COMPLIANCE_DATA_BEGIN/END range. + + * more gramatical fixes, clarifications added + * added To Be Discussed items regarding emulated instruction and binary tests + +2019-09-11 Allen Baum <allen.baum@esperantotech.com> + * spec/TestFormatSpec.adoc: more grammar and typo corrections and changes + clarified and added To Be Discussed issues + +2019-09-11 Allen Baum <allen.baum@esperantotech.com> + * spec/TestFormatSpec.adoc: many grammar and typo corrections and changes + removed many "to Be Discussed items and made them official + Added wording to clarify spec intent (work in progress/goal rather than final) + Added macros to ease test authoring: RVTEST_SIGBASE, RVTEST_SIGUPDATE, RVTEST_CASE + Added detail on proposals for connection to framework (how framework selects tests). + Expanded definition of signature format + Changed the (proposed) directory structure and naming convention to eliminate ambiguities, add consistancy and slightly better match existing structure + Added many "future work" items related to the above + Added examples and comments to code examples to indicate how proposed macros would be used + * .gitignore: added condition to ignore Mac file system artifacts + + +2019-11-05 Lee Moore <moore@imperas.com> + * Restructured RV32I to move Zicsr and Zifencei into their own suites + +2019-10-14 Lee Moore <moore@imperas.com> + * Added Ability to run a single test by using the Make Variable RISCV_TEST + for example, to only run the test I-ADD-01 from the rv32i suite + make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 + * Added Top Level Variable to Makefile RISCV_TARGET_FLAGS, + in the case of the RISCV_TARGET this can be passed and appended to the invocation + commandline configuration, for example to pass a command line flag to the RISCV_TARGET + to perform tracing. The value of this flag will be target specific + make RISCV_ISA=rv32i RISCV_TEST=I-ADD-01 RISCV_TARGET_FLAGS="--trace" + This is has also been added to all other targets to allow target configuration from + the commandline + 2019-10-07 Philipp Wagner <phw@lowrisc.org> * When executing the test suite, Ibex always writes an instruction log. Update the Makefile to write it to a test-specific location
diff --git a/sw/vendor/riscv_compliance/Makefile b/sw/vendor/riscv_compliance/Makefile index 2502a8f..25557c1 100644 --- a/sw/vendor/riscv_compliance/Makefile +++ b/sw/vendor/riscv_compliance/Makefile
@@ -11,14 +11,14 @@ empty:= space:= $(empty) $(empty) -export RISCV_TARGET ?= riscvOVPsim -export RISCV_DEVICE ?= rv32i -export RISCV_PREFIX ?= riscv64-unknown-elf- +export RISCV_TARGET ?= riscvOVPsim +export RISCV_DEVICE ?= rv32i +export RISCV_PREFIX ?= riscv64-unknown-elf- +export RISCV_TARGET_FLAGS ?= RISCV_ISA_ALL = $(shell ls $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device) RISCV_ISA_OPT = $(subst $(space),$(pipe),$(RISCV_ISA_ALL)) - ifeq ($(RISCV_ISA),) RISCV_ISA = rv32i DEFAULT_TARGET=all_variant @@ -26,46 +26,68 @@ DEFAULT_TARGET=variant endif -export ROOTDIR = $(shell pwd) -export WORK = $(ROOTDIR)/work -export SUITEDIR = $(ROOTDIR)/riscv-test-suite/$(RISCV_ISA) +export ROOTDIR = $(shell pwd) +export WORK = $(ROOTDIR)/work +export SUITEDIR = $(ROOTDIR)/riscv-test-suite/$(RISCV_ISA) export TARGETDIR ?= $(ROOTDIR)/riscv-target +VERBOSE ?= 0 +ifeq ($(VERBOSE),1) + export V= + export REDIR= +else + export V=@ + export REDIR=>/dev/null +endif + +PARALLEL ?= 1 +ifeq ($(RISCV_TARGET),spike) + PARALLEL = 0 +endif +ifeq ($(PARALLEL),0) + JOBS = +else + ifeq ($(RISCV_TARGET),riscvOVPsim) + JOBS ?= -j8 --max-load=4 + endif +endif + default: $(DEFAULT_TARGET) variant: simulate verify all_variant: for isa in $(RISCV_ISA_ALL); do \ - echo $$isa; \ - $(MAKE) RISCV_TARGET=$(RISCV_TARGET) RISCV_DEVICE=$$isa RISCV_ISA=$$isa variant; \ - rc=$$?; \ - if [ $$rc -ne 0 ]; then \ - exit $$rc; \ - fi \ + $(MAKE) $(JOBS) RISCV_TARGET=$(RISCV_TARGET) RISCV_TARGET_FLAGS="$(RISCV_TARGET_FLAGS)" RISCV_DEVICE=$$isa RISCV_ISA=$$isa variant; \ + rc=$$?; \ + if [ $$rc -ne 0 ]; then \ + exit $$rc; \ + fi \ done simulate: - make \ + $(MAKE) $(JOBS) \ RISCV_TARGET=$(RISCV_TARGET) \ RISCV_DEVICE=$(RISCV_DEVICE) \ RISCV_PREFIX=$(RISCV_PREFIX) \ run -C $(SUITEDIR) -verify: +verify: simulate riscv-test-env/verify.sh clean: - make \ + $(MAKE) $(JOBS) \ RISCV_TARGET=$(RISCV_TARGET) \ RISCV_DEVICE=$(RISCV_DEVICE) \ RISCV_PREFIX=$(RISCV_PREFIX) \ clean -C $(SUITEDIR) help: - @echo "make" - @echo "RISCV_TARGET='riscvOVPsim|spike'" + @echo "eg, make" + @echo "RISCV_TARGET='riscvOVPsim|spike|sid32'" + @echo "RISCV_TARGET_FLAGS=" @echo "RISCV_DEVICE='rv32i|rv32im|...'" - @echo "RISCV_ISA=$(RISCV_ISA_OPT)" + @echo "RISCV_ISA='$(RISCV_ISA_OPT)'" + @echo "RISCV_TEST='I-ADD-01'" @echo "make all_variant // all combinations"
diff --git a/sw/vendor/riscv_compliance/README.md b/sw/vendor/riscv_compliance/README.md index b731578..97b6fdb 100644 --- a/sw/vendor/riscv_compliance/README.md +++ b/sw/vendor/riscv_compliance/README.md
@@ -12,7 +12,7 @@ - Where a pull request is non-controversial one of the repository owners will immediately merge it. The repository uses rebase merges to maintain a linear history. -- Other pull requests will be publicised to the task group for comment and decision at a subsequent meeting of the group. Everyone is encouraged to comment on a pull request. Such pull requests will be merged by when a concensus/decision has been reached by the task group. +- Other pull requests will be publicised to the task group for comment and decision at a subsequent meeting of the group. Everyone is encouraged to comment on a pull request. Such pull requests will be merged by when a consensus/decision has been reached by the task group. ## Licensing @@ -90,4 +90,4 @@ Note that the I-MISALIGN_LDST test fails for GRIFT because GRIFT currently supports misaligned loads and stores in hardware, while the test is specifically -written for systems that trap on misaligned loads and stores. \ No newline at end of file +written for systems that trap on misaligned loads and stores.
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md index 8a4b207..301e9ad 100644 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
@@ -22,6 +22,12 @@ $ export OT_FPGA_UART=/dev/tty* ``` +In addition the UART device must be appropriately configured. + +```console +$ stty -F $OT_FPGA_UART 230400 raw +``` + By default, the test assumes there exists a valid Verilator build at `${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`. If your Verilator build is at a different location, please set that as well when running with Verilator. @@ -29,9 +35,15 @@ $ export TARGET_SIM=${PATH_TO_VERILATOR_BUILD} ``` -When running against FPGA, the test assumes the FPGA is already programmed and ready to go. -To quickly get started with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/) +When running against FPGA, the test assumes the FPGA is already programmed and ready to go with spiflash available at `${REPO_TOP}/build-bin/sw/host/spiflash/spiflash_export` +To quickly get started with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/). +The meson build environment must be setup before running the compliance test. + +```console +$ cd $REPO_TOP +$ ./meson_init.sh +``` Now, run the tests from the riscv_compliance directory. The following output will be seen (software build steps are truncated). @@ -39,36 +51,9 @@ ```console $ cd $RISCV_COMPLIANCE_REPO_BASE -$ make RISCV_ISA=rv32i \ - && make RISCV_ISA=rv32im \ - && make RISCV_ISA=rv32imc +$ make RISCV_ISA=rv32i - -Rom initialized with program at $REPO_TOP/sw/vendor/riscv_compliance/../../boot_rom/rom.vmem - -Flash initialized with program at $REPO_TOP/sw/vendor/riscv_compliance/work/rv32i/I-ENDIANESS-01.elf.vmem - -JTAG: Virtual JTAG interface jtag0 is listening on port 44853. Use -OpenOCD and the following configuration to connect: - interface remote_bitbang - remote_bitbang_host localhost - remote_bitbang_port 44853 - -SPI: Created /dev/pts/21 for spi0. Connect to it with any terminal program, e.g. -$ screen /dev/pts/21 -NOTE: a SPI transaction is run for every 4 characters entered. -SPI: Monitor output file created at $REPO_TOP/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/spi0.log. Works well with tail: -$ tail -f $REPO_TOP/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/spi0.log - -UART: Created /dev/pts/22 for uart0. Connect to it with any terminal program, e.g. -$ screen /dev/pts/22 - -Simulation running, end by pressing CTRL-c. -TOP.top_earlgrey_verilator.top_earlgrey.core.ibex_tracer_i: Writing execution trace to trace_core_00000000.log -Verilator sim termination requested -Your simulation wrote to 0x10008000 - -... +... verbose test output ... Compare to reference files ... @@ -76,22 +61,66 @@ Check I-ADDI-01 ... OK Check I-AND-01 ... OK Check I-ANDI-01 ... OK - -... - +Check I-AUIPC-01 ... OK +Check I-BEQ-01 ... OK +Check I-BGE-01 ... OK +Check I-BGEU-01 ... OK +Check I-BLT-01 ... OK +Check I-BLTU-01 ... OK +Check I-BNE-01 ... OK +Check I-DELAY_SLOTS-01 ... OK +Check I-EBREAK-01 ... OK +Check I-ECALL-01 ... OK +Check I-ENDIANESS-01 ... OK +Check I-IO-01 ... OK +Check I-JAL-01 ... OK +Check I-JALR-01 ... OK +Check I-LB-01 ... OK +Check I-LBU-01 ... OK +Check I-LH-01 ... OK +Check I-LHU-01 ... OK +Check I-LUI-01 ... OK +Check I-LW-01 ... OK +Check I-MISALIGN_JMP-01 ... IGNORE +Check I-MISALIGN_LDST-01 ... IGNORE +Check I-NOP-01 ... OK +Check I-OR-01 ... OK +Check I-ORI-01 ... OK +Check I-RF_size-01 ... OK +Check I-RF_width-01 ... OK +Check I-RF_x0-01 ... OK +Check I-SB-01 ... OK +Check I-SH-01 ... OK +Check I-SLL-01 ... OK +Check I-SLLI-01 ... OK +Check I-SLT-01 ... OK +Check I-SLTI-01 ... OK +Check I-SLTIU-01 ... OK +Check I-SLTU-01 ... OK +Check I-SRA-01 ... OK +Check I-SRAI-01 ... OK +Check I-SRL-01 ... OK +Check I-SRLI-01 ... OK +Check I-SUB-01 ... OK +Check I-SW-01 ... OK +Check I-XOR-01 ... OK +Check I-XORI-01 ... OK -------------------------------- -OK: 55/55 - - +OK: 48/48 ``` +There are several test suites that can be run `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr`. +Change the `RISCV_ISA` argument passed to `make` to choose between them. -## Removed Tests -A small number of tests are not run for OpenTitan riscv_compliance since the underlying core does not yet support specific features. -The removed tests are the following: + +## Removed/Broken Tests +A small number of tests are not run for OpenTitan riscv_compliance as they fail +due to flaws in the compliance test suite rather than Ibex/OpenTitan itself (see +https://github.com/lowRISC/ibex/issues/100). The I-FENCE.I-01 test attempts to +write instruction memory which fails in the OT system as this writes to flash +which can't be done. * I-MISALIGN_JMP-01 * I-MISALIGN_LDST-01 * I-FENCE.I-01 -* I-ECALL-01 -* I-EBREAK-01 +
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h index 5d56101..978d578 100644 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h
@@ -13,11 +13,7 @@ // RV Compliance Macros //----------------------------------------------------------------------- #define RV_COMPLIANCE_HALT \ - la sp, _stack_start; \ - j dump_signature; \ - loop_forever: \ - wfi; \ - j loop_forever; \ + j end_rvc_test; \ #define RV_COMPLIANCE_RV32M \ RVTEST_RV32M \ @@ -30,7 +26,7 @@ RVTEST_CODE_END \ #define RV_COMPLIANCE_DATA_BEGIN \ - .section .test.output; \ + .section .data; \ RVTEST_DATA_BEGIN \ #define RV_COMPLIANCE_DATA_END \
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include index 50cfb62..1bfece7 100644 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
@@ -5,26 +5,31 @@ OPENTITAN = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc OT_SW = $(ROOTDIR)/../../device OT_ROOT = $(OT_SW)/../../ +OT_BIN ?= $(OT_ROOT)/build-bin +OT_BUILD = $(OT_ROOT)/build-out OT_TOOLS ?= /tools/riscv/bin OT_FPGA_UART ?= OT_TARGET ?= fpga -LDSCRIPT = $(OPENTITAN)/link.ld -TRAPHANDLER = $(OPENTITAN)/handler.S -DEFINES = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DTRAPHANDLER="\"$(TRAPHANDLER)\"" +LDSCRIPT = $(OT_ROOT)/sw/device/exts/common/flash_link.ld +DEFINES = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DRVTEST_ENTRY=_rvc_start -DTRAPALIGN=8 TARGET_SIM ?= $(OT_ROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator ifeq ($(OT_TARGET),fpga) CARG = MAKEARG = - PYTEST_OPT = --fpga_uart $(OT_FPGA_UART) --spiflash $(OT_ROOT)/sw/host/spiflash/spiflash \ - --test_bin $(work_dir_isa)/$<.bin + PYTEST_OPT = --fpga_uart $(OT_FPGA_UART) --spiflash $(OT_BIN)/sw/host/spiflash/spiflash \ + --test_bin $(<).bin + OT_SW_TARGET = fpga_nexysvideo else CARG = -DSIMULATION=1 MAKEARG = SIM=1 - PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(work_dir_isa)/$<.vmem \ - --rom_bin $(OT_ROOT)/build/sw/device/boot_rom/rom.vmem + PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).vmem \ + --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.vmem + OT_SW_TARGET = sim_verilator endif +COMPLIANCE_LIB_EXPORT = sw/device/riscv_compliance_lib/riscv_compliance_lib_export_$(OT_SW_TARGET) +COMPLIANCE_LIB = ot_riscv_compliance_$(OT_SW_TARGET) # The run target recipe does the following things: # Invoke pytest to run the test @@ -33,10 +38,10 @@ RUN_TARGET=\ pytest -s -v $(OT_ROOT)/test/systemtest/functional_$(OT_TARGET)_test.py \ $(PYTEST_OPT) \ - --log $(work_dir_isa)/$<.uart.log; \ - grep -o 'SIG: [a-zA-Z0-9_]*' $(work_dir_isa)/$<.uart.log | sed 's/SIG: //' \ - > $(work_dir_isa)/$(*).signature.temp.output; \ - tr '[:upper:]' '[:lower:]' < $(work_dir_isa)/$(*).signature.temp.output > $(work_dir_isa)/$(*).signature.output; + --log $(<).uart.log; \ + grep -o 'SIG: [a-zA-Z0-9_]*' $(<).uart.log | sed 's/SIG: //' \ + > $(*).signature.temp.output; \ + tr '[:upper:]' '[:lower:]' < $(*).signature.temp.output > $(*).signature.output; RISCV_PREFIX ?= ${OT_TOOLS}/riscv32-unknown-elf- @@ -45,30 +50,37 @@ RISCV_OBJCOPY ?= ${OT_TOOLS}/riscv32-unknown-elf-objcopy RISCV_NM ?= ${OT_TOOLS}/riscv32-unknown-elf-nm RISCV_READELF ?= ${OT_TOOLS}/riscv32-unknown-elf-readelf -RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -fno-builtin -g -Wl,--no-relax -# The compile target recipe re-uses the boot rom library. -# This will be changed in the future when the compliance tests directly build -# their own libraries -# After the libraries are built, the necessary collateral (vmem for verilator, bin -# for fpga) are created -COMPILE_TARGET=\ - make -C $$(OT_SW) SW_DIR=boot_rom $(MAKEARG) RV_TOOLS=$(OT_TOOLS) clean all; \ - $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ + + +# Build the verilator boot rom if we're running on verilator and build the +# support library. These builds can be disabled by setting +# OT_RV_NO_LIB_ROM_BUILD=1 which is used in CI. +ifneq ($(OT_RV_NO_LIB_ROM_BUILD), 1) +ifeq ($(OT_TARGET), verilator) + COMPILE_TARGET = ninja -C $(OT_BUILD) sw/device/boot_rom/boot_rom_export_$(OT_SW_TARGET); +endif + COMPILE_TARGET += ninja -C $(OT_BUILD) $(COMPLIANCE_LIB_EXPORT); +endif +COMPILE_TARGET += \ + $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \ -I$(ROOTDIR)/riscv-test-env/ \ -I$(ROOTDIR)/riscv-test-env/p/ \ - -I$(OT_SW)/lib \ - -I$(OT_ROOT)/build/sw/device/boot_rom/lib \ + -I$(OT_ROOT) \ -I$(TARGETDIR)/$(RISCV_TARGET)/ \ -I$(TARGETDIR)/$(RISCV_TARGET)/ \ $(DEFINES) -T$(LDSCRIPT) $$< \ - $(OPENTITAN)/wrap.c \ - -L$(OT_ROOT)/build/sw/device/boot_rom/lib \ - -lot \ - -o $(work_dir_isa)/$$@; \ - $$(RISCV_OBJDUMP) -SD $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \ - $$(RISCV_READELF) -a $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.readelf; \ - $$(RISCV_NM) $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.nm; \ - $$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@ $(work_dir_isa)/$$@.bin; \ - srec_cat $(work_dir_isa)/$$@.bin -binary -offset 0x0000 -byte-swap 4 -o $(work_dir_isa)/$$@.vmem -vmem + $(OPENTITAN)/main.c \ + $(OPENTITAN)/run_rvc_test.S \ + $(OT_ROOT)/sw/device/lib/irq_vectors.S \ + $(OT_ROOT)/sw/device/exts/common/flash_crt.S \ + -L$(OT_BIN)/sw/device/riscv_compliance_lib \ + -l$(COMPLIANCE_LIB) \ + -o $$(@); \ + $$(RISCV_OBJDUMP) -SD $$(@) > $$(@).objdump; \ + $$(RISCV_READELF) -a $$(@) > $$(@).readelf; \ + $$(RISCV_NM) $$(@) > $$(@).nm; \ + $$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin; \ + srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).vmem -vmem
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/handler.S b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/handler.S deleted file mode 100644 index 75dbb95..0000000 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/handler.S +++ /dev/null
@@ -1,22 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -.section .text.trap; -.align 4; - -_trap_start: - j _trap_exception - -// This could be exception or user interrupt -// 0xb is the environment call to indicate the end -_trap_exception: - csrr a0, mcause - addi a1, zero, 0xb - beq a0, a1, _int_exc - la a1, begin_signature - // write to value pointed by begin_signature and uses a1 as address scratch - sw a0, begin_signature, a1 -_int_exc: - la a0, write_tohost - jr a0
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/main.c b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/main.c new file mode 100644 index 0000000..4691578 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/main.c
@@ -0,0 +1,39 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Wrapper for RISC-V compliance tests, it saves architectural state before +// jumping into the test (via run_rvc_test). After the test completes it dumps +// the signature out via the UART. + +#include "sw/device/lib/uart.h" +#include "sw/device/lib/arch/device.h" +#include "sw/device/lib/common.h" + +extern void run_rvc_test(void); + +extern uint32_t begin_signature[]; +extern uint32_t end_signature[]; + +int main(int argc, char **argv) { + uart_init(kUartBaudrate); + base_set_stdout(uart_stdout); + + run_rvc_test(); + + uint32_t size = end_signature - begin_signature; + + for (uint32_t i = 0; i < size; ++i) { + base_printf("SIG: %08x\r\n", REG32(begin_signature + i)); + } + + base_printf("PASS!\r\n"); + + // The "End" string here is a workaround to pytest console parsing. + // Without additional characters, the "\n" from above is not always + // detected, and this causes pytest to register the test as a false failure. + // This needs to be debugged further to see if it's a setup or hw issue. + base_printf("End"); + + return 0; +}
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/run_rvc_test.S b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/run_rvc_test.S new file mode 100644 index 0000000..aef6a23 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/run_rvc_test.S
@@ -0,0 +1,85 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Allocate space in .bss for saving architectural state before jumping into the +// test + .lcomm arch_state_store, 4 * 17 //(ra, sp, gp, tp, s0-s11, mtvec) + + .section .text + +run_rvc_test: + .globl run_rvc_test + + // Save the architectural state. There is no need to save caller preserved + // registers as C calling run_rvc_test will expect them to be clobbered anyway + // and act appropriately. RA is the exception as we need to know where to jump + // back to after the test is complete. mtvec is saved as the compliance test + // environment alters it, other CSRs may also be changed but no adverse + // effects have yet been observed from this. + la t0, arch_state_store + + sw ra, 0(t0) + sw sp, 4(t0) + sw gp, 8(t0) + sw tp, 12(t0) + sw s0, 16(t0) + sw s1, 20(t0) + sw s2, 24(t0) + sw s3, 28(t0) + sw s4, 32(t0) + sw s5, 36(t0) + sw s6, 40(t0) + sw s7, 44(t0) + sw s8, 48(t0) + sw s9, 52(t0) + sw s10, 56(t0) + sw s11, 60(t0) + + csrr t1, mtvec + sw t1, 64(t0) + +// jump to compliance test + j _rvc_start + +end_rvc_test: + .globl end_rvc_test + + // restore architectural state + la t0, arch_state_store + + lw ra, 0(t0) + lw sp, 4(t0) + lw gp, 8(t0) + lw tp, 12(t0) + lw s0, 16(t0) + lw s1, 20(t0) + lw s2, 24(t0) + lw s3, 28(t0) + lw s4, 32(t0) + lw s5, 36(t0) + lw s6, 40(t0) + lw s7, 44(t0) + lw s8, 48(t0) + lw s9, 52(t0) + lw s10, 56(t0) + lw s11, 60(t0) + + lw t1, 64(t0) + csrw mtvec, t1 + + jr ra + +// riscv-compliance loads its own mtvec that will jump to mtvec_handler if the +// symbol exists +mtvec_handler: + .globl mtvec_handler + + // restore gp/sp so handler from OT library can work + la t0, arch_state_store + + lw sp, 4(t0) + lw gp, 8(t0) + + // jump to the handler from the OT library + j _vectors_start
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/wrap.c b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/wrap.c deleted file mode 100644 index 37e2224..0000000 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/wrap.c +++ /dev/null
@@ -1,39 +0,0 @@ -// Copyright lowRISC contributors. -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#include <string.h> - -#include "common.h" -#include "uart.h" - -#define SIM_TERM_ADDR 0x10008000 -extern uint32_t begin_signature[]; -extern uint32_t end_signature[]; - -void dump_signature(void) { - - - uint32_t size = end_signature - begin_signature; - uart_init(UART_BAUD_RATE); - for (uint32_t i = 0; i < size; ++i) { - uart_send_str("SIG: "); - uart_send_uint(REG32(begin_signature + i), 32); - uart_send_str("\r\n"); - } - - uart_send_str("PASS!\r\n"); - - // The "End" string here is a workaround to pytest console parsing. - // Without additional characters, the "\n" from above is not always - // detected, and this causes pytest to register the test as a false failure. - // This needs to be debugged further to see if it's a setup or hw issue. - uart_send_str("End"); - - // wait for all uart outputs to complete - while (!uart_tx_empty() || !uart_tx_idle()) { - } - - // terminate simulation - REG32(SIM_TERM_ADDR) = 0; -}
diff --git a/sw/vendor/riscv_compliance/riscv-test-env/p/riscv_test.h b/sw/vendor/riscv_compliance/riscv-test-env/p/riscv_test.h index eaa6758..9423523 100644 --- a/sw/vendor/riscv_compliance/riscv-test-env/p/riscv_test.h +++ b/sw/vendor/riscv_compliance/riscv-test-env/p/riscv_test.h
@@ -60,14 +60,14 @@ csrw pmpaddr0, t0; \ li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ csrw pmpcfg0, t0; \ - .align 2; \ + .align TRAPALIGN; \ 1: #define INIT_SPTBR \ la t0, 1f; \ csrw mtvec, t0; \ csrwi sptbr, 0; \ - .align 2; \ + .align TRAPALIGN; \ 1: #define DELEGATE_NO_TRAPS \ @@ -76,7 +76,7 @@ csrwi medeleg, 0; \ csrwi mideleg, 0; \ csrwi mie, 0; \ - .align 2; \ + .align TRAPALIGN; \ 1: #define RVTEST_ENABLE_SUPERVISOR \ @@ -125,6 +125,14 @@ #if defined(TRAPHANDLER) #include TRAPHANDLER #endif +#if !defined(TRAPALIGN) +#define TRAPALIGN 2 +#endif + +#if !defined(RVTEST_ENTRY) +#define RVTEST_ENTRY _start +#endif + #define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ @@ -133,11 +141,11 @@ .align 6; \ .weak stvec_handler; \ .weak mtvec_handler; \ - .globl _start; \ -_start: \ + .globl RVTEST_ENTRY; \ +RVTEST_ENTRY: \ /* reset vector */ \ j reset_vector; \ - .align 2; \ + .align TRAPALIGN; \ trap_vector: \ /* test whether the test came from pass/fail */ \ csrr t5, mcause; \
diff --git a/sw/vendor/riscv_compliance/riscv-test-env/riscv_test_macros.h b/sw/vendor/riscv_compliance/riscv-test-env/riscv_test_macros.h new file mode 100644 index 0000000..1a04591 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-env/riscv_test_macros.h
@@ -0,0 +1,462 @@ +// RISC-V Compliance IO Test Header File + +/* + * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * either express or implied. + * + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + + +// +// In general the following registers are reserved +// ra, a0, t0, t1 +// Additionally on an assertion violation, t1, t2 are overwritten +// x1, x10, x5, x6, x7 respectively +// Floating registers reserved +// f5 +// + +#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) + +#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) + +// Base function for integer operations +#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... ) \ + code; \ + sw destreg, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) \ + +// Base functions for single precision floating point operations +#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \ + la a0, test_ ## test_num ## _data; \ + flw reg1, 0(a0); \ + flw reg2, 4(a0); \ + lw t1, 8(a0); \ + code; \ + fsw destreg, offset(swreg); \ + RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \ + .pushsection .data; \ + .align 3; \ + test_ ## test_num ## _data: \ + .float val1; \ + .float val2; \ + .word correctval; \ + .popsection + +#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ + la a0, test_ ## test_num ## _data; \ + lw t1, 0(a0); \ + code; \ + fsw destreg, offset(swreg); \ + RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \ + .pushsection .data; \ + .align 1; \ + test_ ## test_num ## _data: \ + .word correctval; \ + .popsection + +#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ + la a0, test_ ## test_num ## _data; \ + flw reg, 0(a0); \ + lw t1, 4(a0); \ + code; \ + sw destreg, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ + .pushsection .data; \ + .align 2; \ + test_ ## test_num ## _data: \ + .float val; \ + .word correctval; \ + .popsection + +#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \ + la a0, test_ ## test_num ## _data; \ + flw reg1, 0(a0); \ + flw reg2, 4(a0); \ + flw reg3, 8(a0); \ + lw t1, 12(a0); \ + code; \ + fsw destreg, offset(swreg); \ + RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \ + .pushsection .data; \ + .align 4; \ + test_ ## test_num ## _data: \ + .float val1; \ + .float val2; \ + .float val3; \ + .word correctval; \ + .popsection + +#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ + la a0, test_ ## test_num ## _data; \ + flw reg, 0(a0); \ + code; \ + sw destreg, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ + .pushsection .data; \ + .align 1; \ + test_ ## test_num ## _data: \ + .float val; \ + .popsection + +#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \ + la a0, test_ ## test_num ## _data; \ + li reg, val; \ + code; \ + fsw destreg, offset(swreg); \ + lw a1, 0(a0); \ + RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \ + .pushsection .data; \ + .align 1; \ + test_ ## test_num ## _data: \ + .word correctval; \ + .popsection + +// Base functions for double precision floating point operations - rv32d +#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \ + la a0, test_ ## test_num ## _data; \ + fld reg1, 0(a0); \ + fld reg2, 8(a0); \ + code; \ + fsd destreg, offset(swreg); \ + lw t1, 16(a0); \ + lw t2, 20(a0); \ + la a0, store_ ## test_num ## _data; \ + fsd destreg, 0(a0); \ + lw a1, 0(a0); \ + lw a2, 4(a0); \ + RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \ + .pushsection .data; \ + .align 3; \ + test_ ## test_num ## _data: \ + .double val1; \ + .double val2; \ + .dword correctval; \ + .popsection; \ + .pushsection .data; \ + store_ ## test_num ## _data: \ + .fill 1, 8, -1; \ + .popsection + +#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ + la a0, test_ ## test_num ## _data; \ + code; \ + fsd destreg, offset(swreg); \ + lw t1, 0(a0); \ + lw t2, 4(a0); \ + la a0, store_ ## test_num ## _data; \ + fsd destreg, 0(a0); \ + lw a1, 0(a0); \ + lw a2, 4(a0); \ + RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \ + .pushsection .data; \ + .align 1; \ + test_ ## test_num ## _data: \ + .dword correctval; \ + .popsection; \ + store_ ## test_num ## _data: \ + .fill 1, 8, -1; \ + .popsection + +#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ + la a0, test_ ## test_num ## _data; \ + fld reg, 0(a0); \ + lw t1, 8(a0); \ + code; \ + sw destreg, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ + .pushsection .data; \ + .align 2; \ + test_ ## test_num ## _data: \ + .double val; \ + .word correctval; \ + .popsection + +#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \ + la a0, test_ ## test_num ## _data; \ + fld reg1, 0(a0); \ + fld reg2, 8(a0); \ + fld reg3, 16(a0); \ + code; \ + fsd destreg, offset(swreg); \ + lw t1, 24(a0); \ + lw t2, 28(a0); \ + la a0, store_ ## test_num ## _data; \ + fsd destreg, 0(a0); \ + lw a1, 0(a0); \ + lw a2, 4(a0); \ + RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \ + .pushsection .data; \ + .align 4; \ + test_ ## test_num ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .dword correctval; \ + .popsection; \ + .pushsection .data; \ + store_ ## test_num ## _data: \ + .fill 1, 8, -1; \ + .popsection + +//Tests for a instructions with register-register operand +#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li reg1, MASK_XLEN(val1); \ + li reg2, MASK_XLEN(val2); \ + inst destreg, reg1, reg2; \ + ) + +#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li destreg, MASK_XLEN(val1); \ + li reg, MASK_XLEN(val2); \ + inst destreg, destreg, reg; \ + ) + +#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li reg, MASK_XLEN(val1); \ + li destreg, MASK_XLEN(val2); \ + inst destreg, reg, destreg; \ + ) + +#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li destreg, MASK_XLEN(val1); \ + inst destreg, destreg, destreg; \ + ) + +#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li reg, MASK_XLEN(val); \ + inst destreg, x0, reg; \ + ) + +#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li reg, MASK_XLEN(val); \ + inst destreg, reg, x0; \ + ) + +#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + inst destreg, x0, x0; \ + ) + +#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, x0, 0, swreg, offset, \ + li reg1, MASK_XLEN(val1); \ + li reg2, MASK_XLEN(val2); \ + inst x0, reg1, reg2; \ + ) + +//Tests for a instructions with register-immediate operand +#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li reg, MASK_XLEN(val); \ + inst destreg, reg, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li destreg, MASK_XLEN(val); \ + inst destreg, destreg, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + inst destreg, x0, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, x0, 0, swreg, offset, \ + li reg, MASK_XLEN(val); \ + inst x0, reg, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + inst destreg, SEXT_IMM(imm); \ + ) + +#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + 1: \ + inst destreg, imm; \ + la swreg, 1b; \ + sub destreg, destreg, swreg; \ + ) + +//Tests for a compressed instruction +#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li reg, MASK_XLEN(val1); \ + li destreg, MASK_XLEN(val2); \ + inst destreg, reg; \ + ) + +#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \ + TEST_CASE(testreg, destreg, correctval, swreg, offset, \ + li destreg, MASK_XLEN(val); \ + inst destreg, imm; \ + ) + +#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg,x0, correctval, swreg, offset, \ + inst imm; \ + ) + +//Tests for floating point instructions - single precision +#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \ + TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \ + inst destreg, reg1, reg2; \ + ) + +#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ + TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \ + inst destreg, reg; \ + ) + +#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \ + TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \ + inst destreg, reg1, reg2, reg3; \ + ) + +#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ + TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \ + li reg, MASK_XLEN(val); \ + inst destreg, reg; \ + ) + +#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ + TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \ + inst destreg, reg; \ + ) + +//Tests for floating point instructions - double precision +#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \ + TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \ + inst destreg, reg1, reg2; \ + ) + +#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ + TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \ + inst destreg, reg; \ + ) + +#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \ + TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \ + inst destreg, reg1, reg2, reg3; \ + ) + +#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ + TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \ + li reg, MASK_XLEN(val); \ + inst destreg, reg; \ + ) + +#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ + TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \ + inst destreg, reg; \ + ) + +#define TEST_CADDI16SP(correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg,x2, correctval, swreg, offset, \ + c.addi16sp x2, imm; \ + ) + +#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset, testreg) \ + TEST_CASE(testreg,destreg, correctval, swreg, offset, \ + c.addi4spn destreg, x2, SEXT_IMM(imm); \ + ) + +#define TEST_CJL(inst, reg, val, swreg, offset) \ + li x10, val; \ + la reg, 1f; \ + inst reg; \ + li x10, 0x123ab; \ +1: \ + sw x10, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \ + +#define ABS(x) ((x >> 11) ^ x) - (x >> 11) + +#define TEST_CJ(inst, reg, val, swreg, offset) \ + li reg, val; \ + inst 1f; \ + li reg, 0x123ab; \ +1: \ + sw reg, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \ + +#define TEST_CL(inst, reg, imm, swreg, offset) \ + la reg, test_data; \ + inst reg, imm(reg); \ + sw reg, offset(swreg); \ + +// lw reg, imm(x2) +// c.lwsp reg, imm(x2) +#define TEST_CLWSP(reg, imm, swreg, offset) \ + la x2, test_data; \ + c.lwsp reg, imm(x2); \ + sw reg, offset(swreg); \ + +#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \ + li reg1, val; \ + la reg2, test_data; \ + inst reg1, imm(reg2); \ + lw reg1, imm(reg2); \ + sw reg1, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \ + +#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \ + la x2, test_data; \ + li reg, val; \ + c.swsp reg, imm(x2); \ + lw reg, imm(x2); \ + sw reg, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \ + +#define TEST_CBEQZ(reg, val, swreg, offset) \ + li reg, val; \ + c.sub reg, reg; \ + c.beqz reg, 3f; \ + li reg, 0x123ab; \ +3: \ + sw reg, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \ + +#define TEST_CBNEZ(reg, val, swreg, offset) \ + li reg, val; \ + c.bnez reg, 4f; \ + li reg, 0x0; \ +4: \ + sw reg, offset(swreg); \ + RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \ + +#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \ + TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \ + fmv.x.s destreg, reg; \ + ) + +#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \ + TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \ + fmv.s.x destreg, reg; \ + ) + +#define SWSIG(a,b) +
diff --git a/sw/vendor/riscv_compliance/riscv-test-env/verify.sh b/sw/vendor/riscv_compliance/riscv-test-env/verify.sh index 82b7e27..87bcad0 100755 --- a/sw/vendor/riscv_compliance/riscv-test-env/verify.sh +++ b/sw/vendor/riscv_compliance/riscv-test-env/verify.sh
@@ -21,7 +21,7 @@ echo "Check $(printf %16s ${stub}) ... IGNORE" continue fi - diff --strip-trailing-cr ${ref} ${sig} #&> /dev/null + diff --ignore-case --strip-trailing-cr ${ref} ${sig} #&> /dev/null if [ $? == 0 ] then echo " ... OK"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/README.md b/sw/vendor/riscv_compliance/riscv-test-suite/README.md index db0930e..fffdb12 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/README.md +++ b/sw/vendor/riscv_compliance/riscv-test-suite/README.md
@@ -4,43 +4,35 @@ For information on the test framework and other documentation on the compliance tests look at : [../doc/README.adoc](../doc/README.adoc) -Currently there are twelve test suites checked into this repository. +Currently there are five solid test suites checked into this repository along with a few deprecated/WIP tests. -If you are looking to check compliance of RV32I in user mode then run the suites: RV32I and RV32UI +If you are looking to check compliance of RV32I in user mode then run the suites: RV32I, RV32ICSR and RV32IFENCEI + +To see the coverage of the suites see the riscv-test-suite coverage directory for the summary/detailed reports. These are generated by Imperas by using the github.com/google/riscv-dv UVM coverage testbench and the Mentor Questa SystemVerilog simulator. Test suites status: Pretty Solid: -* RV32I (originally developed by Codasip, assertions and debug macros added by Imperas) - * 55 focused tests, using the correct style/macros, excellent coverage of most instructions - * no coverage of fence, scall, sbreak, pseudo and csr instructions +* RV32I (significant improvements (Nov2019) by Imperas) + * 48 focused tests, using the correct style/macros, excellent coverage of most instructions + * Coverage 97.23% * RV32IM (developed by Imperas) - * 7 focused tests, using the correct style/macros, excellent coverage + * 8 focused tests, using the correct style/macros, excellent coverage + * Coverage 89.95% * RV32IMC (developed by Imperas) - * 24 focused tests, using the correct style/macros + * 25 focused tests, using the correct style/macros + * Coverage 59.68% +* RV32ICSR + * 6 focused tests +* RV32IFENCEI + * 1 test + +Work in progress (64-bit tests): * RV64I (developed by Imperas) * 8 focused tests, using the correct style/macros * RV64IM (developed by Imperas) * 3 focused tests, using the correct style/macros -Work in progress (user mode): -* RV32UI (from github/riscv-tests with poor coverage. Ported by Imperas) - * 39 tests, uses original style, user mode, Imperas added signature -* RV32UA (from github/riscv-tests with poor coverage. Ported by Imperas) - * 10 tests, uses original style, user mode, Imperas added signature -* RV32UC (from github/riscv-tests with poor coverage. Ported by Imperas) - * 1 test, uses original style, user mode, Imperas added signature -* RV32UF (from github/riscv-tests with poor coverage. Ported by Imperas) - * 11 tests, uses original style, user mode, Imperas added signature -* RV32UD (from github/riscv-tests with poor coverage. Ported by Imperas) - * 10 tests, uses original style, user mode, Imperas added signature - -Work in progress (starting on privilege modes): -* RV32SI (from github/riscv-tests with poor coverage. Ported by Imperas) - * 6 tests, uses original style, Imperas added signature -* RV32MI (from github/riscv-tests with poor coverage. Ported by Imperas) - * 8 tests, uses original style, Imperas added signature - To be worked on: * RV64C * RV32A @@ -51,4 +43,4 @@ * RV32EC * RV32EA * RV32EF -* RV32ED \ No newline at end of file +* RV32ED
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/Makefile new file mode 100644 index 0000000..9da7ab8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv32i -mabi=ilp32)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/Makefrag new file mode 100644 index 0000000..d9ed3ca --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/Makefrag
@@ -0,0 +1,18 @@ +rv32mi_sc_tests = \ + breakpoint \ + ma_fetch \ + ma_addr \ + scall \ + sbreak \ + shamt \ + csr \ + mcsr \ + illegal + +ifeq ($(RISCV_TARGET),riscvOVPsim) + rv32mi_sc_tests := $(subst breakpoint,,$(rv32mi_sc_tests)) +endif + +rv32mi_tests = $(addsuffix .elf, $(rv32mi_sc_tests)) + +target_tests += $(rv32mi_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/breakpoint.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/breakpoint.reference_output new file mode 100644 index 0000000..3c9770d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/breakpoint.reference_output
@@ -0,0 +1,32 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +ffffffff +0000000a +0000000b +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/csr.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/csr.reference_output new file mode 100644 index 0000000..ad674f5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/csr.reference_output
@@ -0,0 +1,8 @@ +00000001 +ffffffff +00000003 +00000003 +00000002 +00000006 +00000002 +0bad1dea
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/illegal.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/illegal.reference_output new file mode 100644 index 0000000..f34edbc --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/illegal.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/ma_addr.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/ma_addr.reference_output new file mode 100644 index 0000000..8a092ba --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/ma_addr.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/ma_fetch.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/ma_fetch.reference_output new file mode 100644 index 0000000..fc83973 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/ma_fetch.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/mcsr.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/mcsr.reference_output new file mode 100644 index 0000000..9393ec6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/mcsr.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000001 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/sbreak.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/sbreak.reference_output new file mode 100644 index 0000000..7e19fd6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/sbreak.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/scall.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/scall.reference_output new file mode 100644 index 0000000..e593eb6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/scall.reference_output
@@ -0,0 +1,40 @@ +00000001 +00000001 +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/shamt.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/shamt.reference_output new file mode 100644 index 0000000..23c8b3f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/references/shamt.reference_output
@@ -0,0 +1,8 @@ +00000001 +ffffffff +00010000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/Makefrag new file mode 100644 index 0000000..c81c24e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/Makefrag
@@ -0,0 +1,18 @@ +#======================================================================= +# Makefrag for rv64mi tests +#----------------------------------------------------------------------- + +rv64mi_sc_tests = \ + access \ + breakpoint \ + csr \ + mcsr \ + illegal \ + ma_fetch \ + ma_addr \ + scall \ + sbreak \ + +rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests)) + +spike_tests += $(rv64mi_p_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/access.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/access.S new file mode 100644 index 0000000..7c674f9 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/access.S
@@ -0,0 +1,70 @@ +# See LICENSE for license details. + +#***************************************************************************** +# access.S +#----------------------------------------------------------------------------- +# +# Test access-exception behavior. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RV_COMPLIANCE_CODE_BEGIN + + .align 2 + + # Flipping just the MSB should result in an illegal address for RV64. + la t2, fail + li t0, 1 << (__riscv_xlen - 1) + xor t0, t0, t2 + + # jalr to an illegal address should commit (hence should write rd). + # after the pc is set to rs1, an access exception should be raised. + li TESTNUM, 2 + li t1, CAUSE_FETCH_ACCESS + la t3, 1f + li t2, 0 + jalr t2, t0 +1: + + # A load to an illegal address should not commit. + li TESTNUM, 3 + li t1, CAUSE_LOAD_ACCESS + la t3, 1f + mv t2, t3 + lb t2, (t0) + j fail +1: + + j pass + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + li a0, 2 + beq TESTNUM, a0, 2f + li a0, 3 + beq TESTNUM, a0, 2f + j fail + +2: + bne t2, t3, fail + + csrr t2, mcause + bne t2, t1, fail + + csrw mepc, t3 + mret + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/breakpoint.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/breakpoint.S new file mode 100644 index 0000000..35cc83b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/breakpoint.S
@@ -0,0 +1,174 @@ +# See LICENSE for license details. + +#***************************************************************************** +# breakpoint.S +#----------------------------------------------------------------------------- +# +# Test breakpoints, if they are implemented. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64M +RV_COMPLIANCE_CODE_BEGIN + + # Set up breakpoint to trap on M-mode fetches. + li TESTNUM, 2 + SWSIG(2, TESTNUM) + + # Skip tselect if hard-wired. + csrw tselect, x0 + csrr a1, tselect + bne x0, a1, sign_pass + + # Make sure there's a breakpoint there. + csrr a0, tdata1 + srli a0, a0, __riscv_xlen - 4 + li a1, 2 + bne a0, a1, sign_pass + + la a2, 1f + csrw tdata2, a2 + li a0, MCONTROL_M | MCONTROL_EXECUTE + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + andi a1, a1, 0x7ff + bne a0, a1, 2f + .align 2 +1: + # Trap handler should skip this instruction. + beqz x0, fail + + # Make sure reads don't trap. + li TESTNUM, 3 + SWSIG(3, TESTNUM) + lw a0, (a2) + +2: + # Set up breakpoint to trap on M-mode reads. + li TESTNUM, 4 + SWSIG(4, TESTNUM) + li a0, MCONTROL_M | MCONTROL_LOAD + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + andi a1, a1, 0x7ff + bne a0, a1, 2f + la a2, data1 + csrw tdata2, a2 + + # Trap handler should skip this instruction. + lw a2, (a2) + beqz a2, fail + + # Make sure writes don't trap. + li TESTNUM, 5 + SWSIG(5, TESTNUM) + sw x0, (a2) + +2: + # Set up breakpoint to trap on M-mode stores. + li TESTNUM, 6 + SWSIG(6, TESTNUM) + li a0, MCONTROL_M | MCONTROL_STORE + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + andi a1, a1, 0x7ff + bne a0, a1, 2f + + # Trap handler should skip this instruction. + sw a2, (a2) + + # Make sure store didn't succeed. + li TESTNUM, 7 + SWSIG(7, TESTNUM) + lw a2, (a2) + bnez a2, fail + + # Try to set up a second breakpoint. + li a0, 1 + csrw tselect, a0 + csrr a1, tselect + bne a0, a1, sign_pass + + # Make sure there's a breakpoint there. + csrr a0, tdata1 + srli a0, a0, __riscv_xlen - 4 + li a1, 2 + bne a0, a1, sign_pass + + li a0, MCONTROL_M | MCONTROL_LOAD + csrw tdata1, a0 + la a3, data2 + csrw tdata2, a3 + + # Make sure the second breakpoint triggers. + li TESTNUM, 8 + SWSIG(8, TESTNUM) + lw a3, (a3) + beqz a3, fail + + # Make sure the first breakpoint still triggers. + li TESTNUM, 10 + SWSIG(10, TESTNUM) + la a2, data1 + sw a2, (a2) + li TESTNUM, 11 + SWSIG(11, TESTNUM) + lw a2, (a2) + bnez a2, fail + +2: + TEST_PASSFAIL + +sign_pass: + li TESTNUM, 3 + SWSIG(3, TESTNUM) + li TESTNUM, 4 + SWSIG(4, TESTNUM) + li TESTNUM, 5 + SWSIG(5, TESTNUM) + li TESTNUM, 6 + SWSIG(6, TESTNUM) + li TESTNUM, 7 + SWSIG(7, TESTNUM) + li TESTNUM, 8 + SWSIG(8, TESTNUM) + li TESTNUM, 10 + SWSIG(10, TESTNUM) + li TESTNUM, 11 + SWSIG(11, TESTNUM) + j pass + + .align 2 + .global mtvec_handler +mtvec_handler: + # Only even-numbered tests should trap. + andi t0, TESTNUM, 1 + bnez t0, fail + + li t0, CAUSE_BREAKPOINT + csrr t1, mcause + bne t0, t1, fail + + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 + mret + +RV_COMPLIANCE_CODE_END + + .data +data1: .word 0 +data2: .word 0 + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 32, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/csr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/csr.S new file mode 100644 index 0000000..77e7619 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/csr.S
@@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/csr.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/illegal.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/illegal.S new file mode 100644 index 0000000..4d859a8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/illegal.S
@@ -0,0 +1,198 @@ +# See LICENSE for license details. + +#***************************************************************************** +# illegal.S +#----------------------------------------------------------------------------- +# +# Test illegal instruction trap. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +#RVTEST_RV64S +RVTEST_RV64M + +RV_COMPLIANCE_CODE_BEGIN + + .align 2 + .option norvc + + li TESTNUM, 2 +bad2: + .word 0 + j fail + + # Skip the rest of the test if S-mode is not present. + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 + csrr t2, mstatus + and t2, t2, t0 + bne t1, t2, pass + + # Test vectored interrupts if they are supported. +test_vectored_interrupts: + csrwi mip, MIP_SSIP + csrwi mie, MIP_SSIP + la t0, mtvec_handler + 1 + csrrw s0, mtvec, t0 + csrr t0, mtvec + andi t0, t0, 1 + beqz t0, msip + csrsi mstatus, MSTATUS_MIE +1: + j 1b +msip: + csrw mtvec, s0 + + # Delegate supervisor software interrupts so WFI won't stall. + csrwi mideleg, MIP_SSIP + # Enter supervisor mode. + la t0, 1f + csrw mepc, t0 + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 + mret + +1: + # Make sure WFI doesn't trap when TW=0. + wfi +bad3: + .word 0 + j fail + +bad4: + # Make sure WFI does trap when TW=1. + wfi + j fail + + # Make sure SFENCE.VMA and sptbr don't trap when TVM=0. + sfence.vma + csrr t0, sptbr +bad5: + .word 0 + j fail + +bad6: + # Make sure SFENCE.VMA and sptbr do trap when TVM=1. + sfence.vma + j fail +bad7: + csrr t0, sptbr + j fail + + # Make sure SRET doesn't trap when TSR=0. + la t0, bad8 + csrw sepc, t0 + li t0, SSTATUS_SPP + csrs sstatus, t0 + li t0, SSTATUS_SPIE + csrc sstatus, t0 + sret +bad8: + .word 0 + j fail + + # Make sure SRET does trap when TSR=1. + la t0, 1f + csrw sepc, t0 +bad9: + sret +1: + j fail + + TEST_PASSFAIL + + .align 8 + .global mtvec_handler +mtvec_handler: + j synchronous_exception + j msip + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + +synchronous_exception: + li t1, CAUSE_ILLEGAL_INSTRUCTION + csrr t0, mcause + bne t0, t1, fail + csrr t0, mepc + + # Make sure mbadaddr contains either 0 or the instruction word. + csrr t2, mbadaddr + beqz t2, 1f + lhu t3, 0(t0) + lhu t4, 2(t0) + slli t4, t4, 16 + or t3, t3, t4 + bne t2, t3, fail +1: + + la t1, bad2 + beq t0, t1, 2f + la t1, bad3 + beq t0, t1, 3f + la t1, bad4 + beq t0, t1, 4f + la t1, bad5 + beq t0, t1, 5f + la t1, bad6 + beq t0, t1, 6f + la t1, bad7 + beq t0, t1, 7f + la t1, bad8 + beq t0, t1, 8f + la t1, bad9 + beq t0, t1, 9f + j fail +2: +4: +6: +7: + addi t0, t0, 8 + csrw mepc, t0 + mret + +3: + li t1, MSTATUS_TW + csrs mstatus, t1 + j 2b + +5: + li t1, MSTATUS_TVM + csrs mstatus, t1 + j 2b + +8: + li t1, MSTATUS_TSR + csrs mstatus, t1 + j 2b + +9: + j 2b + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/ma_addr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/ma_addr.S new file mode 100644 index 0000000..c35f147 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/ma_addr.S
@@ -0,0 +1,130 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_addr.S +#----------------------------------------------------------------------------- +# +# Test misaligned ld/st trap. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64M +RV_COMPLIANCE_CODE_BEGIN + + .align 2 + .option norvc + + la s0, data + + # indicate it's a load test + li s1, CAUSE_MISALIGNED_LOAD + +#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1))) + +/* Check that a misaligned load either writes the correct value, or + takes an exception and performs no writeback. */ +#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \ + li TESTNUM, testnum; \ + SWSIG(testnum, TESTNUM) \ + la t2, 1f; \ + addi t1, base, offset; \ + insn t1, offset(base); \ + li t2, res; \ + bne t1, t2, fail; \ +1: + + MISALIGNED_LOAD_TEST(2, lh, s0, 1, SEXT(0xbbcc, 16)) + MISALIGNED_LOAD_TEST(3, lhu, s0, 1, 0xbbcc) + MISALIGNED_LOAD_TEST(4, lw, s0, 1, SEXT(0x99aabbcc, 32)) + MISALIGNED_LOAD_TEST(5, lw, s0, 2, SEXT(0x8899aabb, 32)) + MISALIGNED_LOAD_TEST(6, lw, s0, 3, SEXT(0x778899aa, 32)) + +#if __riscv_xlen == 64 + MISALIGNED_LOAD_TEST(7, lwu, s0, 1, 0x99aabbcc) + MISALIGNED_LOAD_TEST(8, lwu, s0, 2, 0x8899aabb) + MISALIGNED_LOAD_TEST(9, lwu, s0, 3, 0x778899aa) + + MISALIGNED_LOAD_TEST(10, ld, s0, 1, 0x5566778899aabbcc) + MISALIGNED_LOAD_TEST(11, ld, s0, 2, 0x445566778899aabb) + MISALIGNED_LOAD_TEST(12, ld, s0, 3, 0x33445566778899aa) + MISALIGNED_LOAD_TEST(13, ld, s0, 4, 0x2233445566778899) + MISALIGNED_LOAD_TEST(14, ld, s0, 5, 0x1122334455667788) + MISALIGNED_LOAD_TEST(15, ld, s0, 6, 0xee11223344556677) + MISALIGNED_LOAD_TEST(16, ld, s0, 7, 0xffee112233445566) +#endif + + # indicate it's a store test + li s1, CAUSE_MISALIGNED_STORE + +/* Check that a misaligned store has some effect and takes no exception, + or takes no effect and generates an exception. This is not very + thorough. */ +#define MISALIGNED_STORE_TEST(testnum, insn, base, offset, size) \ + li TESTNUM, testnum; \ + la t2, 1f; \ + addi t1, base, offset; \ + insn x0, offset(base); \ + lb t1, (offset - 1)(base); \ + beqz t1, fail; \ + lb t1, (offset + size)(base); \ + beqz t1, fail; \ + lb t1, (offset + 0)(base); \ + bnez t1, fail; \ + lb t1, (offset + size - 1)(base); \ + bnez t1, fail; \ +1: + + MISALIGNED_STORE_TEST(22, sh, s0, 1, 2) + MISALIGNED_STORE_TEST(23, sw, s0, 5, 4) + MISALIGNED_STORE_TEST(24, sw, s0, 10, 4) + MISALIGNED_STORE_TEST(25, sw, s0, 15, 4) + +#if __riscv_xlen == 64 + MISALIGNED_STORE_TEST(26, sd, s0, 25, 8) + MISALIGNED_STORE_TEST(27, sd, s0, 34, 8) + MISALIGNED_STORE_TEST(28, sd, s0, 43, 8) + MISALIGNED_STORE_TEST(29, sd, s0, 52, 8) + MISALIGNED_STORE_TEST(30, sd, s0, 61, 8) + MISALIGNED_STORE_TEST(31, sd, s0, 70, 8) + MISALIGNED_STORE_TEST(32, sd, s0, 79, 8) +#endif + + TEST_PASSFAIL + + .align 3 + .global mtvec_handler +mtvec_handler: + csrr t0, mcause + bne t0, s1, fail + + csrr t0, mbadaddr + bne t0, t1, fail + + lb t0, (t0) + beqz t0, fail + + csrw mepc, t2 + mret + +RV_COMPLIANCE_CODE_END + + .data + +data: + .align 3 +.word 0xaabbccdd +.word 0x66778899 +.word 0x22334455 +.word 0xeeffee11 +.fill 0xff, 1, 80 + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/ma_fetch.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/ma_fetch.S new file mode 100644 index 0000000..cfcb90c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/ma_fetch.S
@@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/ma_fetch.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/mcsr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/mcsr.S new file mode 100644 index 0000000..94c5654 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/mcsr.S
@@ -0,0 +1,47 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mcsr.S +#----------------------------------------------------------------------------- +# +# Test various M-mode CSRs. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +#RVTEST_RV64S +RVTEST_RV64M + +RV_COMPLIANCE_CODE_BEGIN + # Check that mcpuid reports the correct XLEN +#if __riscv_xlen == 64 + TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62) +#else + TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30) +#endif + + # Check that mhartid reports 0 + TEST_CASE(3, a0, 0x0, csrr a0, mhartid) + + # Check that reading the following CSRs doesn't cause an exception + csrr a0, mimpid + csrr a0, marchid + csrr a0, mvendorid + + # Check that writing hte following CSRs doesn't cause an exception + li t0, 0 + csrs mtvec, t0 + csrs mepc, t0 + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/sbreak.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/sbreak.S new file mode 100644 index 0000000..f36a9f8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/sbreak.S
@@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/sbreak.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/scall.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/scall.S new file mode 100644 index 0000000..22e9eb5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64mi/scall.S
@@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/scall.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/Makefrag new file mode 100644 index 0000000..c0dbce8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/Makefrag
@@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv64si tests +#----------------------------------------------------------------------- + +rv64si_sc_tests = \ + csr \ + dirty \ + ma_fetch \ + scall \ + wfi \ + sbreak \ + +rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests)) + +spike_tests += $(rv64si_p_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/csr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/csr.S new file mode 100644 index 0000000..4ef7664 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/csr.S
@@ -0,0 +1,151 @@ +# See LICENSE for license details. + +#***************************************************************************** +# csr.S +#----------------------------------------------------------------------------- +# +# Test CSRRx and CSRRxI instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler + #undef SSTATUS_SPP + #define SSTATUS_SPP MSTATUS_MPP +#endif + + # For RV64, make sure UXL encodes RV64. (UXL does not exist for RV32.) +#if __riscv_xlen == 64 + # If running in M mode, use mstatus.MPP to check existence of U mode. + # Otherwise, if in S mode, then U mode must exist and we don't need to check. +#ifdef __MACHINE_MODE + li t0, MSTATUS_MPP + csrc mstatus, t0 + csrr t1, mstatus + and t0, t0, t1 + bnez t0, 1f +#endif + # If U mode is present, UXL should be 2 (XLEN = 64-bit) + TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1) +#ifdef __MACHINE_MODE + j 2f +1: + # If U mode is not present, UXL should be 0 + TEST_CASE(14, a0, 0, csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1) +2: +#endif +#endif + + csrwi sscratch, 3 + TEST_CASE( 2, a0, 3, csrr a0, sscratch); + TEST_CASE( 3, a1, 3, csrrci a1, sscratch, 1); + TEST_CASE( 4, a2, 2, csrrsi a2, sscratch, 4); + TEST_CASE( 5, a3, 6, csrrwi a3, sscratch, 2); + TEST_CASE( 6, a1, 2, li a0, 0xbad1dea; csrrw a1, sscratch, a0); + TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0); + TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0); + TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch); + +#ifdef __MACHINE_MODE + # Is F extension present? + csrr a0, misa + andi a0, a0, (1 << ('F' - 'A')) + beqz a0, 1f + # If so, make sure FP stores have no effect when mstatus.FS is off. + li a1, MSTATUS_FS + csrs mstatus, a1 +#ifdef __riscv_flen + fmv.s.x f0, x0 + csrc mstatus, a1 + la a1, fsw_data + TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1)); +#else + # Fail if this test is compiled without F but executed on a core with F. + TEST_CASE(10, zero, 1) +#endif +1: + + # Figure out if 'U' is set in misa + csrr a0, misa # a0 = csr(misa) + srli a0, a0, 20 # a0 = a0 >> 20 + andi a0, a0, 1 # a0 = a0 & 1 + beqz a0, finish # if no user mode, skip the rest of these checks +#endif /* __MACHINE_MODE */ + + # jump to user land + li t0, SSTATUS_SPP + csrc sstatus, t0 + la t0, 1f + csrw sepc, t0 + sret + 1: + + # Make sure writing the cycle counter causes an exception. + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE + TEST_CASE(11, a0, 255, li a0, 255; csrrw a0, cycle, x0); +#endif + + # Make sure reading status in user mode causes an exception. + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE + TEST_CASE(12, a0, 255, li a0, 255; csrr a0, sstatus) +#else + TEST_CASE(12, x0, 0, nop) +#endif + +finish: + RV_COMPLIANCE_HALT + + # We should only fall through to this if scall failed. + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + # Trapping on tests 10-12 is good news. + # Note that since the test didn't complete, TESTNUM is smaller by 1. + li t0, 9 + bltu TESTNUM, t0, 1f + li t0, 11 + bleu TESTNUM, t0, privileged +1: + + # catch RV_COMPLIANCE_HALT and kick it up to M-mode + csrr t0, scause + li t1, CAUSE_USER_ECALL + bne t0, t1, fail + RV_COMPLIANCE_HALT + +privileged: + # Make sure scause indicates a lack of privilege. + csrr t0, scause + li t1, CAUSE_ILLEGAL_INSTRUCTION + bne t0, t1, fail + # Return to user mode, but skip the trapping instruction. + csrr t0, sepc + addi t0, t0, 4 + csrw sepc, t0 + sret + +RV_COMPLIANCE_CODE_END + + .data +fsw_data: .word 1 +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 8, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/dirty.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/dirty.S new file mode 100644 index 0000000..26f185f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/dirty.S
@@ -0,0 +1,129 @@ +# See LICENSE for license details. + +#***************************************************************************** +# dirty.S +#----------------------------------------------------------------------------- +# +# Test VM referenced and dirty bits. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RV_COMPLIANCE_CODE_BEGIN + + # Turn on VM + li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39 + la a1, page_table_1 + srl a1, a1, RISCV_PGSHIFT + or a1, a1, a0 + csrw sptbr, a1 + sfence.vma + + # Set up MPRV with MPP=S, so loads and stores use S-mode + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV + csrs mstatus, a1 + + # Try a faulting store to make sure dirty bit is not set + li TESTNUM, 2 + li t2, 1 + sw t2, dummy - DRAM_BASE, a0 + + # Set SUM=1 so user memory access is permitted + li TESTNUM, 3 + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM + csrs mstatus, a1 + + # Make sure SUM=1 works + lw t0, dummy - DRAM_BASE + bnez t0, die + + # Try a non-faulting store to make sure dirty bit is set + sw t2, dummy - DRAM_BASE, a0 + + # Make sure it succeeded + lw t0, dummy - DRAM_BASE + bne t0, t2, die + + # Leave MPRV + li t0, MSTATUS_MPRV + csrc mstatus, t0 + + # Make sure D bit is set + lw t0, page_table_1 + li a0, PTE_A | PTE_D + and t0, t0, a0 + bne t0, a0, die + + # Enter MPRV again + li t0, MSTATUS_MPRV + csrs mstatus, t0 + + # Make sure that superpage entries trap when PPN LSBs are set. + li TESTNUM, 4 + lw a0, page_table_1 - DRAM_BASE + or a0, a0, 1 << PTE_PPN_SHIFT + sw a0, page_table_1 - DRAM_BASE, t0 + sfence.vma + sw a0, page_table_1 - DRAM_BASE, t0 + j die + + RV_COMPLIANCE_HALT + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + csrr t0, mcause + add t0, t0, -CAUSE_STORE_PAGE_FAULT + bnez t0, die + + li t1, 2 + bne TESTNUM, t1, 1f + # Make sure D bit is clear + lw t0, page_table_1 + and t1, t0, PTE_D + bnez t1, die +skip: + csrr t0, mepc + add t0, t0, 4 + csrw mepc, t0 + mret + +1: + li t1, 3 + bne TESTNUM, t1, 1f + # The implementation doesn't appear to set D bits in HW. + # Make sure the D bit really is clear. + lw t0, page_table_1 + and t1, t0, PTE_D + bnez t1, die + # Set the D bit. + or t0, t0, PTE_D + sw t0, page_table_1, t1 + sfence.vma + mret + +1: + li t1, 4 + bne TESTNUM, t1, 1f + j pass + +1: +die: + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +.align 12 +page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A +dummy: .dword 0 + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/ma_fetch.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/ma_fetch.S new file mode 100644 index 0000000..e52ab83 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/ma_fetch.S
@@ -0,0 +1,213 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_fetch.S +#----------------------------------------------------------------------------- +# +# Test misaligned fetch trap. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sbadaddr mbadaddr + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler +#endif + + .align 2 + .option norvc + + # Without RVC, the jalr should trap, and the handler will skip ahead. + # With RVC, the jalr should not trap, and "j fail" should get skipped. + li TESTNUM, 2 + SWSIG(2, TESTNUM) + li t1, 0 + la t0, 1f + jalr t1, t0, 2 +1: + .option rvc + c.j 1f + c.j 2f + .option norvc +1: + j fail +2: + + // This test should pass, since JALR ignores the target LSB + li TESTNUM, 3 + SWSIG(3, TESTNUM) + la t0, 1f + jalr t1, t0, 1 +1: + j 1f + j fail +1: + + li TESTNUM, 4 + SWSIG(4, TESTNUM) + li t1, 0 + la t0, 1f + jalr t1, t0, 3 +1: + .option rvc + c.j 1f + c.j 2f + .option norvc +1: + j fail +2: + + # Like test 2, but with jal instead of jalr. + li TESTNUM, 5 + SWSIG(5, TESTNUM) + li t1, 0 + la t0, 1f + jal t1, 2f +1: + .option rvc + c.j 1f +2: + c.j 2f + .option norvc +1: + j fail +2: + + # Like test 2, but with a taken branch instead of jalr. + li TESTNUM, 6 + SWSIG(6, TESTNUM) + li t1, 0 + la t0, 1f + beqz x0, 2f +1: + .option rvc + c.j 1f +2: + c.j 2f + .option norvc +1: + j fail +2: + + # Not-taken branches should not trap, even without RVC. + li TESTNUM, 7 + SWSIG(7, TESTNUM) + bnez x0, 1f + j 2f + .option rvc + c.j 1f +1: + c.j 1f + .option norvc +1: + j fail +2: + +#ifdef __MACHINE_MODE + # RVC cannot be disabled if doing so would cause a misaligned instruction + # exception on the next instruction fetch. (This test assumes no other + # extensions that support misalignment are present.) + li TESTNUM, 8 + SWSIG(8, TESTNUM) + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + beqz t2, 2f + + .option rvc + c.nop + csrci misa, 1 << ('c' - 'a') +1: + c.nop + .option norvc + + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + beqz t2, fail + + # When RVC is disabled, mret to a misaligned mepc should succeed, + # masking off mepc[1]. + la t0, 1f + addi t0, t0, -2 + csrw mepc, t0 + + # Try to disable RVC; if it can't be disabled, skip the test. + csrci misa, 1 << ('c' - 'a') + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + bnez t2, 2f + + li t2, MSTATUS_MPP + csrs mstatus, t2 + mret + + # mret should transfer control to this branch. Otherwise, it will + # transfer control two bytes into the branch, which happens to be the + # illegal instruction c.unimp. + beqz x0, 1f +1: + csrsi misa, 1 << ('c' - 'a') +2: +#endif + + j pass + + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + # tests 2, 4, 5, 6, and 8 should trap + li a0, 2 + beq TESTNUM, a0, 1f + li a0, 4 + beq TESTNUM, a0, 1f + li a0, 5 + beq TESTNUM, a0, 1f + li a0, 6 + beq TESTNUM, a0, 1f + j fail +1: + + # verify that return address was not written + bnez t1, fail + + # verify trap cause + li a1, CAUSE_MISALIGNED_FETCH + csrr a0, scause + bne a0, a1, fail + + # verify that epc == &jalr (== t0 - 4) + csrr a1, sepc + addi a1, a1, 4 + bne t0, a1, fail + + # verify that badaddr == 0 or badaddr == t0+2. + csrr a0, sbadaddr + beqz a0, 1f + addi a0, a0, -2 + bne a0, t0, fail +1: + + addi a1, a1, 8 + csrw sepc, a1 + sret + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/sbreak.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/sbreak.S new file mode 100644 index 0000000..366cf6e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/sbreak.S
@@ -0,0 +1,55 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler +#endif + + li TESTNUM, 2 + SWSIG(2, TESTNUM) + +do_break: + sbreak + j fail + + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + li t1, CAUSE_BREAKPOINT + csrr t0, scause + bne t0, t1, fail + la t1, do_break + csrr t0, sepc + bne t0, t1, fail + j pass + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/scall.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/scall.S new file mode 100644 index 0000000..78334f8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/scall.S
@@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler + #undef SSTATUS_SPP + #define SSTATUS_SPP MSTATUS_MPP +#endif + + li TESTNUM, 2 + SWSIG(2, TESTNUM) + + # This is the expected trap code. + li t1, CAUSE_USER_ECALL + +#ifdef __MACHINE_MODE + # If running in M mode, use mstatus.MPP to check existence of U mode. + # Otherwise, if in S mode, then U mode must exist and we don't need to check. + li t0, MSTATUS_MPP + csrc mstatus, t0 + csrr t2, mstatus + and t0, t0, t2 + beqz t0, 1f + + # If U mode doesn't exist, mcause should indicate ECALL from M mode. + li t1, CAUSE_MACHINE_ECALL +#endif + +1: + li t0, SSTATUS_SPP + csrc sstatus, t0 + la t0, 1f + csrw sepc, t0 + sret +1: + + li TESTNUM, 1 + SWSIG(1, TESTNUM) +do_scall: + li TESTNUM, 1; + SWSIG (0, TESTNUM); # say it is a pass + scall + j fail + + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + csrr t0, scause + bne t0, t1, fail + la t2, do_scall + csrr t0, sepc + bne t0, t2, fail + j pass + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/wfi.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/wfi.S new file mode 100644 index 0000000..03880ac --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/rv64si/wfi.S
@@ -0,0 +1,33 @@ +# See LICENSE for license details. + +#***************************************************************************** +# wfi.S +#----------------------------------------------------------------------------- +# +# Test wait-for-interrupt instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + + # Make sure wfi doesn't halt the hart, even if interrupts are disabled + csrc sstatus, SSTATUS_SIE + csrs sie, SIP_SSIP + csrs sip, SIP_SSIP + wfi + + RV_COMPLIANCE_HALT + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/breakpoint.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/breakpoint.S new file mode 100644 index 0000000..ecbec6a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/breakpoint.S
@@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64mi/breakpoint.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/csr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/csr.S new file mode 100644 index 0000000..6361f86 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/csr.S
@@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64si/csr.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/illegal.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/illegal.S new file mode 100644 index 0000000..e167c71 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/illegal.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M + +#include "../rv64mi/illegal.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/ma_addr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/ma_addr.S new file mode 100644 index 0000000..7575a3f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/ma_addr.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M + +#include "../rv64mi/ma_addr.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/ma_fetch.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/ma_fetch.S new file mode 100644 index 0000000..ec0e0f6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/ma_fetch.S
@@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64si/ma_fetch.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/mcsr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/mcsr.S new file mode 100644 index 0000000..0d5a5cd --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/mcsr.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M + +#include "../rv64mi/mcsr.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/sbreak.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/sbreak.S new file mode 100644 index 0000000..c1b127d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/sbreak.S
@@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64si/sbreak.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/scall.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/scall.S new file mode 100644 index 0000000..e5b3153 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/scall.S
@@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32M +#define __MACHINE_MODE + +#include "../rv64si/scall.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/shamt.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/shamt.S new file mode 100644 index 0000000..76b505f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32mi/src/shamt.S
@@ -0,0 +1,46 @@ +# See LICENSE for license details. + +#***************************************************************************** +# csr.S +#----------------------------------------------------------------------------- +# +# Test CSRRx and CSRRxI instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV32M +RV_COMPLIANCE_CODE_BEGIN + + # Make sure slli with shamt[4] set is legal. + TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16); + + # Make sure slli with shamt[5] set is not legal. + TEST_CASE( 3, x0, 1, .word 0x02051513); # slli a0, a0, 32 + + TEST_PASSFAIL + +.global mtvec_handler +mtvec_handler: + # Trapping on test 3 is good. + # Note that since the test didn't complete, TESTNUM is smaller by 1. + li t0, 2 + bne TESTNUM, t0, fail + + # Make sure CAUSE indicates an illegal instructino. + csrr t0, mcause + li t1, CAUSE_ILLEGAL_INSTRUCTION + bne t0, t1, fail + j pass + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 8, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/Makefile new file mode 100644 index 0000000..9da7ab8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv32i -mabi=ilp32)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/Makefrag new file mode 100644 index 0000000..27a0526 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/Makefrag
@@ -0,0 +1,14 @@ +rv32si_sc_tests = \ + csr \ + ma_fetch \ + scall \ + sbreak \ + wfi \ + dirty + +# ma_fetch - needs signature and it says it failed.. + +rv32si_tests = $(addsuffix .elf, $(rv32si_sc_tests)) + +target_tests += $(rv32si_tests) +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/csr.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/csr.reference_output new file mode 100644 index 0000000..74bf1bc --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/csr.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000003 +00000003 +00000002 +00000006 +00000002 +0bad1dea +0bad0000 +0badbeef +ffffffff +ffffffff +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/dirty.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/dirty.reference_output new file mode 100644 index 0000000..f34edbc --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/dirty.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/ma_fetch.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/ma_fetch.reference_output new file mode 100644 index 0000000..45bbed0 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/ma_fetch.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/sbreak.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/sbreak.reference_output new file mode 100644 index 0000000..7e19fd6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/sbreak.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/scall.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/scall.reference_output new file mode 100644 index 0000000..e593eb6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/scall.reference_output
@@ -0,0 +1,40 @@ +00000001 +00000001 +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/wfi.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/wfi.reference_output new file mode 100644 index 0000000..e593eb6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/references/wfi.reference_output
@@ -0,0 +1,40 @@ +00000001 +00000001 +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/Makefrag new file mode 100644 index 0000000..c0dbce8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/Makefrag
@@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv64si tests +#----------------------------------------------------------------------- + +rv64si_sc_tests = \ + csr \ + dirty \ + ma_fetch \ + scall \ + wfi \ + sbreak \ + +rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests)) + +spike_tests += $(rv64si_p_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/csr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/csr.S new file mode 100644 index 0000000..9899abf --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/csr.S
@@ -0,0 +1,154 @@ +# See LICENSE for license details. + +#***************************************************************************** +# csr.S +#----------------------------------------------------------------------------- +# +# Test CSRRx and CSRRxI instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler + #undef SSTATUS_SPP + #define SSTATUS_SPP MSTATUS_MPP +#endif + + # For RV64, make sure UXL encodes RV64. (UXL does not exist for RV32.) +#if __riscv_xlen == 64 + # If running in M mode, use mstatus.MPP to check existence of U mode. + # Otherwise, if in S mode, then U mode must exist and we don't need to check. +#ifdef __MACHINE_MODE + li t0, MSTATUS_MPP + csrc mstatus, t0 + csrr t1, mstatus + and t0, t0, t1 + bnez t0, 1f +#endif + # If U mode is present, UXL should be 2 (XLEN = 64-bit) + TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1) +#ifdef __MACHINE_MODE + j 2f +1: + # If U mode is not present, UXL should be 0 + TEST_CASE(14, a0, 0, csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1) +2: +#endif +#endif + + csrwi sscratch, 3 + TEST_CASE( 2, a0, 3, csrr a0, sscratch); + TEST_CASE( 3, a1, 3, csrrci a1, sscratch, 1); + TEST_CASE( 4, a2, 2, csrrsi a2, sscratch, 4); + TEST_CASE( 5, a3, 6, csrrwi a3, sscratch, 2); + TEST_CASE( 6, a1, 2, li a0, 0xbad1dea; csrrw a1, sscratch, a0); + TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0); + TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0); + TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch); + +#ifdef __MACHINE_MODE + # Is F extension present? + csrr a0, misa + andi a0, a0, (1 << ('F' - 'A')) + beqz a0, 1f + # If so, make sure FP stores have no effect when mstatus.FS is off. + li a1, MSTATUS_FS + csrs mstatus, a1 +#ifdef __riscv_flen + fmv.s.x f0, x0 + csrc mstatus, a1 + la a1, fsw_data + TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1)); +#else + # Fail if this test is compiled without F but executed on a core with F. + TEST_CASE(10, zero, 1) +#endif +1: + + # Figure out if 'U' is set in misa + csrr a0, misa # a0 = csr(misa) + srli a0, a0, 20 # a0 = a0 >> 20 + andi a0, a0, 1 # a0 = a0 & 1 + beqz a0, finish # if no user mode, skip the rest of these checks +#endif /* __MACHINE_MODE */ + + # jump to user land + li t0, SSTATUS_SPP + csrc sstatus, t0 + la t0, 1f + csrw sepc, t0 + sret + 1: + + # Make sure writing the cycle counter causes an exception. + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE + TEST_CASE(11, a0, 255, li a0, 255; csrrw a0, cycle, x0); +#endif + + # Make sure reading status in user mode causes an exception. + # Don't run in supervisor, as we don't delegate illegal instruction traps. +#ifdef __MACHINE_MODE + TEST_CASE(12, a0, 255, li a0, 255; csrr a0, sstatus) +#else + TEST_CASE(12, x0, 0, nop) +#endif + +finish: + RV_COMPLIANCE_HALT + + # We should only fall through to this if scall failed. + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + # Trapping on tests 10-12 is good news. + # Note that since the test didn't complete, TESTNUM is smaller by 1. + li t0, 9 + bltu TESTNUM, t0, 1f + li t0, 11 + bleu TESTNUM, t0, privileged +1: + + # catch RV_COMPLIANCE_HALT and kick it up to M-mode + csrr t0, scause + li t1, CAUSE_USER_ECALL + bne t0, t1, fail + RV_COMPLIANCE_HALT + +privileged: + # Make sure scause indicates a lack of privilege. + csrr t0, scause + li t1, CAUSE_ILLEGAL_INSTRUCTION + bne t0, t1, fail + # Return to user mode, but skip the trapping instruction. + csrr t0, sepc + addi t0, t0, 4 + csrw sepc, t0 + sret + +RV_COMPLIANCE_CODE_END + + .data + +fsw_data: .word 1 + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/dirty.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/dirty.S new file mode 100644 index 0000000..1a324a8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/dirty.S
@@ -0,0 +1,134 @@ +# See LICENSE for license details. + +#***************************************************************************** +# dirty.S +#----------------------------------------------------------------------------- +# +# Test VM referenced and dirty bits. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64M +RV_COMPLIANCE_CODE_BEGIN + + # Turn on VM + li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39 + la a1, page_table_1 + srl a1, a1, RISCV_PGSHIFT + or a1, a1, a0 + csrw sptbr, a1 + sfence.vma + + # Set up MPRV with MPP=S, so loads and stores use S-mode + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV + csrs mstatus, a1 + + # Try a faulting store to make sure dirty bit is not set + li TESTNUM, 2 + li t2, 1 + sw t2, dummy - DRAM_BASE, a0 + + # Set SUM=1 so user memory access is permitted + li TESTNUM, 3 + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM + csrs mstatus, a1 + + # Make sure SUM=1 works + lw t0, dummy - DRAM_BASE + bnez t0, die + + # Try a non-faulting store to make sure dirty bit is set + sw t2, dummy - DRAM_BASE, a0 + + # Make sure it succeeded + lw t0, dummy - DRAM_BASE + bne t0, t2, die + + # Leave MPRV + li t0, MSTATUS_MPRV + csrc mstatus, t0 + + # Make sure D bit is set + lw t0, page_table_1 + li a0, PTE_A | PTE_D + and t0, t0, a0 + bne t0, a0, die + + # Enter MPRV again + li t0, MSTATUS_MPRV + csrs mstatus, t0 + + # Make sure that superpage entries trap when PPN LSBs are set. + li TESTNUM, 4 + lw a0, page_table_1 - DRAM_BASE + or a0, a0, 1 << PTE_PPN_SHIFT + sw a0, page_table_1 - DRAM_BASE, t0 + sfence.vma + sw a0, page_table_1 - DRAM_BASE, t0 + j die + + RV_COMPLIANCE_HALT + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + csrr t0, mcause + add t0, t0, -CAUSE_STORE_PAGE_FAULT + bnez t0, die + + li t1, 2 + bne TESTNUM, t1, 1f + # Make sure D bit is clear + lw t0, page_table_1 + and t1, t0, PTE_D + bnez t1, die +skip: + csrr t0, mepc + add t0, t0, 4 + csrw mepc, t0 + mret + +1: + li t1, 3 + bne TESTNUM, t1, 1f + # The implementation doesn't appear to set D bits in HW. + # Make sure the D bit really is clear. + lw t0, page_table_1 + and t1, t0, PTE_D + bnez t1, die + # Set the D bit. + or t0, t0, PTE_D + sw t0, page_table_1, t1 + sfence.vma + mret + +1: + li t1, 4 + bne TESTNUM, t1, 1f + j pass + +1: +die: + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + + .data + TEST_DATA + +.align 12 +page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A +dummy: .dword 0 + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/ma_fetch.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/ma_fetch.S new file mode 100644 index 0000000..e52ab83 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/ma_fetch.S
@@ -0,0 +1,213 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_fetch.S +#----------------------------------------------------------------------------- +# +# Test misaligned fetch trap. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sbadaddr mbadaddr + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler +#endif + + .align 2 + .option norvc + + # Without RVC, the jalr should trap, and the handler will skip ahead. + # With RVC, the jalr should not trap, and "j fail" should get skipped. + li TESTNUM, 2 + SWSIG(2, TESTNUM) + li t1, 0 + la t0, 1f + jalr t1, t0, 2 +1: + .option rvc + c.j 1f + c.j 2f + .option norvc +1: + j fail +2: + + // This test should pass, since JALR ignores the target LSB + li TESTNUM, 3 + SWSIG(3, TESTNUM) + la t0, 1f + jalr t1, t0, 1 +1: + j 1f + j fail +1: + + li TESTNUM, 4 + SWSIG(4, TESTNUM) + li t1, 0 + la t0, 1f + jalr t1, t0, 3 +1: + .option rvc + c.j 1f + c.j 2f + .option norvc +1: + j fail +2: + + # Like test 2, but with jal instead of jalr. + li TESTNUM, 5 + SWSIG(5, TESTNUM) + li t1, 0 + la t0, 1f + jal t1, 2f +1: + .option rvc + c.j 1f +2: + c.j 2f + .option norvc +1: + j fail +2: + + # Like test 2, but with a taken branch instead of jalr. + li TESTNUM, 6 + SWSIG(6, TESTNUM) + li t1, 0 + la t0, 1f + beqz x0, 2f +1: + .option rvc + c.j 1f +2: + c.j 2f + .option norvc +1: + j fail +2: + + # Not-taken branches should not trap, even without RVC. + li TESTNUM, 7 + SWSIG(7, TESTNUM) + bnez x0, 1f + j 2f + .option rvc + c.j 1f +1: + c.j 1f + .option norvc +1: + j fail +2: + +#ifdef __MACHINE_MODE + # RVC cannot be disabled if doing so would cause a misaligned instruction + # exception on the next instruction fetch. (This test assumes no other + # extensions that support misalignment are present.) + li TESTNUM, 8 + SWSIG(8, TESTNUM) + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + beqz t2, 2f + + .option rvc + c.nop + csrci misa, 1 << ('c' - 'a') +1: + c.nop + .option norvc + + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + beqz t2, fail + + # When RVC is disabled, mret to a misaligned mepc should succeed, + # masking off mepc[1]. + la t0, 1f + addi t0, t0, -2 + csrw mepc, t0 + + # Try to disable RVC; if it can't be disabled, skip the test. + csrci misa, 1 << ('c' - 'a') + csrr t2, misa + andi t2, t2, 1 << ('c' - 'a') + bnez t2, 2f + + li t2, MSTATUS_MPP + csrs mstatus, t2 + mret + + # mret should transfer control to this branch. Otherwise, it will + # transfer control two bytes into the branch, which happens to be the + # illegal instruction c.unimp. + beqz x0, 1f +1: + csrsi misa, 1 << ('c' - 'a') +2: +#endif + + j pass + + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + # tests 2, 4, 5, 6, and 8 should trap + li a0, 2 + beq TESTNUM, a0, 1f + li a0, 4 + beq TESTNUM, a0, 1f + li a0, 5 + beq TESTNUM, a0, 1f + li a0, 6 + beq TESTNUM, a0, 1f + j fail +1: + + # verify that return address was not written + bnez t1, fail + + # verify trap cause + li a1, CAUSE_MISALIGNED_FETCH + csrr a0, scause + bne a0, a1, fail + + # verify that epc == &jalr (== t0 - 4) + csrr a1, sepc + addi a1, a1, 4 + bne t0, a1, fail + + # verify that badaddr == 0 or badaddr == t0+2. + csrr a0, sbadaddr + beqz a0, 1f + addi a0, a0, -2 + bne a0, t0, fail +1: + + addi a1, a1, 8 + csrw sepc, a1 + sret + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/sbreak.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/sbreak.S new file mode 100644 index 0000000..366cf6e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/sbreak.S
@@ -0,0 +1,55 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler +#endif + + li TESTNUM, 2 + SWSIG(2, TESTNUM) + +do_break: + sbreak + j fail + + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + li t1, CAUSE_BREAKPOINT + csrr t0, scause + bne t0, t1, fail + la t1, do_break + csrr t0, sepc + bne t0, t1, fail + j pass + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/scall.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/scall.S new file mode 100644 index 0000000..01c298c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/scall.S
@@ -0,0 +1,81 @@ +# See LICENSE for license details. + +#***************************************************************************** +# scall.S +#----------------------------------------------------------------------------- +# +# Test syscall trap. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + +#ifdef __MACHINE_MODE + #define sscratch mscratch + #define sstatus mstatus + #define scause mcause + #define sepc mepc + #define sret mret + #define stvec_handler mtvec_handler + #undef SSTATUS_SPP + #define SSTATUS_SPP MSTATUS_MPP +#endif + + li TESTNUM, 2 + SWSIG(2, TESTNUM) + + # This is the expected trap code. + li t1, CAUSE_USER_ECALL + +#ifdef __MACHINE_MODE + # If running in M mode, use mstatus.MPP to check existence of U mode. + # Otherwise, if in S mode, then U mode must exist and we don't need to check. + li t0, MSTATUS_MPP + csrc mstatus, t0 + csrr t2, mstatus + and t0, t0, t2 + beqz t0, 1f + + # If U mode doesn't exist, mcause should indicate ECALL from M mode. + li t1, CAUSE_MACHINE_ECALL +#endif + +1: + li t0, SSTATUS_SPP + csrc sstatus, t0 + la t0, 1f + csrw sepc, t0 + sret +1: + + li TESTNUM, 1 + SWSIG(1, TESTNUM) +do_scall: + scall + j fail + + TEST_PASSFAIL + + .align 2 + .global stvec_handler +stvec_handler: + csrr t0, scause + bne t0, t1, fail + la t2, do_scall + csrr t0, sepc + bne t0, t2, fail + j pass + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/wfi.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/wfi.S new file mode 100644 index 0000000..5d074f6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/rv64si/wfi.S
@@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# wfi.S +#----------------------------------------------------------------------------- +# +# Test wait-for-interrupt instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64S +RV_COMPLIANCE_CODE_BEGIN + + # Make sure wfi doesn't halt the hart, even if interrupts are disabled + csrc sstatus, SSTATUS_SIE + csrs sie, SIP_SSIP + csrs sip, SIP_SSIP + + li TESTNUM, 1 + SWSIG(1, TESTNUM) + wfi + li TESTNUM, 2 + SWSIG(2, TESTNUM) + + RV_COMPLIANCE_HALT + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/Makefrag new file mode 100644 index 0000000..f423788 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/Makefrag
@@ -0,0 +1,15 @@ +#======================================================================= +# Makefrag for rv32si tests +#----------------------------------------------------------------------- + +rv32si_sc_tests = \ + csr \ + dirty \ + ma_fetch \ + scall \ + sbreak \ + wfi \ + +rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests)) + +spike32_tests += $(rv32si_p_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/csr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/csr.S new file mode 100644 index 0000000..3c414c0 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/csr.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/csr.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/dirty.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/dirty.S new file mode 100644 index 0000000..bdbc1e4 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/dirty.S
@@ -0,0 +1,10 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64M +#define RVTEST_RV64M RVTEST_RV32M + +#undef SATP_MODE_SV39 +#define SATP_MODE_SV39 SATP_MODE_SV32 + +#include "../rv64si/dirty.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/ma_fetch.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/ma_fetch.S new file mode 100644 index 0000000..2e5254f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/ma_fetch.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/ma_fetch.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/sbreak.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/sbreak.S new file mode 100644 index 0000000..3dcfba2 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/sbreak.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/sbreak.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/scall.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/scall.S new file mode 100644 index 0000000..5b732c8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/scall.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/scall.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/wfi.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/wfi.S new file mode 100644 index 0000000..8bc9279 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32si/src/wfi.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV32S + +#include "../rv64si/wfi.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/Makefile new file mode 100644 index 0000000..8b1f1eb --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv32ia -mabi=ilp32)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/Makefrag new file mode 100644 index 0000000..bcd33a1 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/Makefrag
@@ -0,0 +1,19 @@ +rv32ua_sc_tests = \ + amoadd_w \ + amoand_w \ + amomax_w \ + amomin_w \ + amominu_w \ + amoxor_w \ + amoswap_w \ + lrsc \ + amomaxu_w \ + amoor_w + +# ToDo - investigate this test +rv32ua_sc_tests := $(subst lrsc,,$(rv32ua_sc_tests)) + +rv32ua_tests = $(addsuffix .elf, $(rv32ua_sc_tests)) + +target_tests += $(rv32ua_tests) +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoadd_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoadd_w.reference_output new file mode 100644 index 0000000..8783b15 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoadd_w.reference_output
@@ -0,0 +1,8 @@ +00000001 +ffffffff +80000000 +7ffff800 +7ffff800 +fffff800 +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoand_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoand_w.reference_output new file mode 100644 index 0000000..ad836ff --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoand_w.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +80000000 +80000000 +80000000 +80000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amomax_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amomax_w.reference_output new file mode 100644 index 0000000..10a5665 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amomax_w.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +80000000 +fffff800 +00000000 +00000001 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amomaxu_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amomaxu_w.reference_output new file mode 100644 index 0000000..a817762 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amomaxu_w.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +80000000 +fffff800 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amomin_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amomin_w.reference_output new file mode 100644 index 0000000..5c2dd97 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amomin_w.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +80000000 +80000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amominu_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amominu_w.reference_output new file mode 100644 index 0000000..449cc02 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amominu_w.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +80000000 +80000000 +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoor_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoor_w.reference_output new file mode 100644 index 0000000..59603b7 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoor_w.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +80000000 +fffff800 +fffff800 +fffff801 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoswap_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoswap_w.reference_output new file mode 100644 index 0000000..793aa00 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoswap_w.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +80000000 +fffff800 +fffff800 +80000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoxor_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoxor_w.reference_output new file mode 100644 index 0000000..43c6c50 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/amoxor_w.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +80000000 +7ffff800 +7ffff800 +bffff801 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/lrsc.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/lrsc.reference_output new file mode 100644 index 0000000..b870e73 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/references/lrsc.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000001 +00000001 +00000000 +00000001 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/Makefrag new file mode 100644 index 0000000..3af8856 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/Makefrag
@@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv64ua tests +#----------------------------------------------------------------------- + +rv64ua_sc_tests = \ + amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + lrsc \ + +rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests)) +rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests)) + +spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoadd_d.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoadd_d.S new file mode 100644 index 0000000..507dc49 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoadd_d.S
@@ -0,0 +1,47 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_d.S +#----------------------------------------------------------------------------- +# +# Test amoadd.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff7ffff800, \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoadd_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoadd_w.S new file mode 100644 index 0000000..f05355d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoadd_w.S
@@ -0,0 +1,52 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_w.S +#----------------------------------------------------------------------------- +# +# Test amoadd.w instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xffffffff80000000; \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + + .bss + .align 3 +amo_operand: + .dword 0 + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 8, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoand_d.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoand_d.S new file mode 100644 index 0000000..3c473f6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoand_d.S
@@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand_d.S +#----------------------------------------------------------------------------- +# +# Test amoand.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoand_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoand_w.S new file mode 100644 index 0000000..2a0a29e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoand_w.S
@@ -0,0 +1,51 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .bss + .align 3 +amo_operand: + .dword 0 + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomax_d.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomax_d.S new file mode 100644 index 0000000..fb1532b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomax_d.S
@@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sd x0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, ld a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomax_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomax_w.S new file mode 100644 index 0000000..37a4253 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomax_w.S
@@ -0,0 +1,50 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.w instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sw x0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .bss + .align 3 +amo_operand: + .dword 0 + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomaxu_d.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomaxu_d.S new file mode 100644 index 0000000..db4be50 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomaxu_d.S
@@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomaxu_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomaxu_w.S new file mode 100644 index 0000000..21c6e38 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomaxu_w.S
@@ -0,0 +1,50 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.w instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .bss + .align 3 +amo_operand: + .dword 0 + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomin_d.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomin_d.S new file mode 100644 index 0000000..09c50ec --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomin_d.S
@@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomin_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomin_w.S new file mode 100644 index 0000000..4967ce6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amomin_w.S
@@ -0,0 +1,51 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.w instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .bss + .align 3 +amo_operand: + .dword 0 + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amominu_d.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amominu_d.S new file mode 100644 index 0000000..8fa4ac9 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amominu_d.S
@@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, ld a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amominu_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amominu_w.S new file mode 100644 index 0000000..5b63467 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amominu_w.S
@@ -0,0 +1,51 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .bss + .align 3 +amo_operand: + .dword 0 + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoor_d.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoor_d.S new file mode 100644 index 0000000..98790c2 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoor_d.S
@@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor_d.S +#----------------------------------------------------------------------------- +# +# Test amoor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoor_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoor_w.S new file mode 100644 index 0000000..49b30ac --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoor_w.S
@@ -0,0 +1,51 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor.w.S +#----------------------------------------------------------------------------- +# +# Test amoor.w instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + + .bss + .align 3 +amo_operand: + .dword 0 + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoswap_d.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoswap_d.S new file mode 100644 index 0000000..862ba77 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoswap_d.S
@@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap.d.S +#----------------------------------------------------------------------------- +# +# Test amoswap.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoswap_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoswap_w.S new file mode 100644 index 0000000..7ac5a1b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoswap_w.S
@@ -0,0 +1,51 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap_w.S +#----------------------------------------------------------------------------- +# +# Test amoswap.w instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .bss + .align 3 +amo_operand: + .dword 0 + + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoxor_d.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoxor_d.S new file mode 100644 index 0000000..83189e3 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoxor_d.S
@@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_d.S +#----------------------------------------------------------------------------- +# +# Test amoxor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 1; \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoxor_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoxor_w.S new file mode 100644 index 0000000..a93bc0c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/amoxor_w.S
@@ -0,0 +1,53 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_w.S +#----------------------------------------------------------------------------- +# +# Test amoxor.w instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x7ffff800, \ + li a1, 0xc0000001; \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffbffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .bss + .align 3 +amo_operand: + .dword 0 + + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/lrsc.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/lrsc.S new file mode 100644 index 0000000..ae95fd5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/rv64ua/lrsc.S
@@ -0,0 +1,103 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lrsr.S +#----------------------------------------------------------------------------- +# +# Test LR/SC instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + +# get a unique core id +la a0, coreid +li a1, 1 +amoadd.w a2, a1, (a0) + +# for now, only run this on core 0 +1:li a3, 1 +bgeu a2, a3, 1b + +1: lw a1, (a0) +bltu a1, a3, 1b + +# make sure that sc without a reservation fails. +TEST_CASE( 2, a4, 1, \ + la a0, foo; \ + sc.w a4, x0, (a0); \ +) + +# make sure that sc with the wrong reservation fails. +# TODO is this actually mandatory behavior? +TEST_CASE( 3, a4, 1, \ + la a0, foo; \ + la a1, fooTest3; \ + lr.w a1, (a1); \ + sc.w a4, a1, (a0); \ +) + +#define LOG_ITERATIONS 10 + +# have each core add its coreid+1 to foo 1024 times +la a0, foo +li a1, 1<<LOG_ITERATIONS +addi a2, a2, 1 +1: lr.w a4, (a0) +add a4, a4, a2 +sc.w a4, a4, (a0) +bnez a4, 1b +add a1, a1, -1 +bnez a1, 1b + +# wait for all cores to finish +la a0, barrier +li a1, 1 +amoadd.w x0, a1, (a0) +1: lw a1, (a0) +blt a1, a3, 1b +fence + +# expected result is 512*ncores*(ncores+1) +TEST_CASE( 4, a0, 0, \ + lw a0, foo; \ + slli a1, a3, LOG_ITERATIONS-1; \ +1:sub a0, a0, a1; \ + addi a3, a3, -1; \ + bgez a3, 1b +) + +# make sure that sc-after-successful-sc fails. +TEST_CASE( 5, a1, 1, \ + la a0, foo; \ +1:lr.w a1, (a0); \ + sc.w a1, x0, (a0); \ + bnez a1, 1b; \ + sc.w a1, x0, (a0) +) + +TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + + TEST_DATA + +coreid: .word 0 +barrier: .word 0 +foo: .word 0 +.skip 1024 +fooTest3: .word 0 + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/Makefrag new file mode 100644 index 0000000..575dc6a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/Makefrag
@@ -0,0 +1,12 @@ +#======================================================================= +# Makefrag for rv32ua tests +#----------------------------------------------------------------------- + +rv32ua_sc_tests = \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + lrsc \ + +rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests)) +rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests)) + +spike32_tests += $(rv32ua_p_tests) $(rv32ua_v_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoadd_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoadd_w.S new file mode 100644 index 0000000..df4560d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoadd_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoadd_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoand_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoand_w.S new file mode 100644 index 0000000..b824483 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoand_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoand_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amomax_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amomax_w.S new file mode 100644 index 0000000..899d7d6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amomax_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amomax_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amomaxu_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amomaxu_w.S new file mode 100644 index 0000000..662f023 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amomaxu_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amomaxu_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amomin_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amomin_w.S new file mode 100644 index 0000000..cbd88e6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amomin_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amomin_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amominu_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amominu_w.S new file mode 100644 index 0000000..acb0d79 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amominu_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amominu_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoor_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoor_w.S new file mode 100644 index 0000000..0a2a57d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoor_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoor_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoswap_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoswap_w.S new file mode 100644 index 0000000..722b7bc --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoswap_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoswap_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoxor_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoxor_w.S new file mode 100644 index 0000000..1858d7e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/amoxor_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/amoxor_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/lrsc.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/lrsc.S new file mode 100644 index 0000000..695a5c8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ua/src/lrsc.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ua/lrsc.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/Makefile new file mode 100644 index 0000000..80d241b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv32ic -mabi=ilp32)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/Makefrag new file mode 100644 index 0000000..e78799f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/Makefrag
@@ -0,0 +1,7 @@ +rv32uc_sc_tests = \ + rvc \ + +rv32uc_tests = $(addsuffix .elf, $(rv32uc_sc_tests)) + +target_tests += $(rv32uc_tests) +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/references/rvc.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/references/rvc.reference_output new file mode 100644 index 0000000..42e5d2e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/references/rvc.reference_output
@@ -0,0 +1,48 @@ +00000001 +ffffffff +0000029b +00001630 +00001424 +00001224 +fedcba99 +ffffffff +fffffff1 +fffffff0 +ffffffff +ffffffe1 +000fffe1 +ffffffff +ffffffee +0000000e +00000012 +00000016 +00000004 +ffffffff +ffffffff +00012340 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +fffffffe +fffffffe +ffffffff +ffffffff +fedcba99 +ffffffff +00000246 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/rv64uc/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/rv64uc/Makefrag new file mode 100644 index 0000000..f5e49b7 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/rv64uc/Makefrag
@@ -0,0 +1,11 @@ +#======================================================================= +# Makefrag for rv64uc tests +#----------------------------------------------------------------------- + +rv64uc_sc_tests = \ + rvc \ + +rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sc_tests)) +rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests)) + +spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/rv64uc/rvc.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/rv64uc/rvc.S new file mode 100644 index 0000000..81afb72 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/rv64uc/rvc.S
@@ -0,0 +1,159 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rvc.S +#----------------------------------------------------------------------------- +# +# Test RVC corner cases. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + .align 2 + .option push + .option norvc + + #define RVC_TEST_CASE(n, r, v, code...) \ + TEST_CASE (n, r, v, .option push; .option rvc; code; .align 2; .option pop) + + // Make sure fetching a 4-byte instruction across a page boundary works. + li TESTNUM, 2 + li a1, 666 + TEST_CASE (2, a1, 667, \ + j 1f; \ + .align 3; \ + data: \ + .dword 0xfedcba9876543210; \ + .dword 0xfedcba9876543210; \ + .align 12; \ + .skip 4094; \ + 1: addi a1, a1, 1) + + li sp, 0x1234 + RVC_TEST_CASE (3, a0, 0x1234 + 1020, c.addi4spn a0, sp, 1020) + RVC_TEST_CASE (4, sp, 0x1234 + 496, c.addi16sp sp, 496) + RVC_TEST_CASE (5, sp, 0x1234 + 496 - 512, c.addi16sp sp, -512) + + la a1, data + RVC_TEST_CASE (6, a2, 0xfffffffffedcba99, c.lw a0, 4(a1); addi a0, a0, 1; c.sw a0, 4(a1); c.lw a2, 4(a1)) +#if __riscv_xlen == 64 + RVC_TEST_CASE (7, a2, 0xfedcba9976543211, c.ld a0, 0(a1); addi a0, a0, 1; c.sd a0, 0(a1); c.ld a2, 0(a1)) +#endif + + RVC_TEST_CASE (8, a0, -15, ori a0, x0, 1; c.addi a0, -16) + RVC_TEST_CASE (9, a5, -16, ori a5, x0, 1; c.li a5, -16) +#if __riscv_xlen == 64 + RVC_TEST_CASE (10, a0, 0x76543210, ld a0, (a1); c.addiw a0, -1) +#endif + + RVC_TEST_CASE (11, s0, 0xffffffffffffffe1, c.lui s0, 0xfffe1; c.srai s0, 12) +#if __riscv_xlen == 64 + RVC_TEST_CASE (12, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12) +#else + RVC_TEST_CASE (12, s0, 0x000fffe1, c.lui s0, 0xfffe1; c.srli s0, 12) +#endif + RVC_TEST_CASE (14, s0, ~0x11, c.li s0, -2; c.andi s0, ~0x10) + RVC_TEST_CASE (15, s1, 14, li s1, 20; li a0, 6; c.sub s1, a0) + RVC_TEST_CASE (16, s1, 18, li s1, 20; li a0, 6; c.xor s1, a0) + RVC_TEST_CASE (17, s1, 22, li s1, 20; li a0, 6; c.or s1, a0) + RVC_TEST_CASE (18, s1, 4, li s1, 20; li a0, 6; c.and s1, a0) +#if __riscv_xlen == 64 + RVC_TEST_CASE (19, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, -1; c.subw s1, a0) + RVC_TEST_CASE (20, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, 1; c.addw s1, a0) +#endif + RVC_TEST_CASE (21, s0, 0x12340, li s0, 0x1234; c.slli s0, 4) + + RVC_TEST_CASE (30, ra, 0, \ + li ra, 0; \ + c.j 1f; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:) + + RVC_TEST_CASE (31, x0, 0, \ + li a0, 0; \ + c.beqz a0, 1f; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:) + + RVC_TEST_CASE (32, x0, 0, \ + li a0, 1; \ + c.bnez a0, 1f; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:) + + RVC_TEST_CASE (33, x0, 0, \ + li a0, 1; \ + c.beqz a0, 1f; \ + c.j 2f; \ + 1:c.j fail; \ + 2:) + + RVC_TEST_CASE (34, x0, 0, \ + li a0, 0; \ + c.bnez a0, 1f; \ + c.j 2f; \ + 1:c.j fail; \ + 2:) + + RVC_TEST_CASE (35, ra, 0, \ + la t0, 1f; \ + li ra, 0; \ + c.jr t0; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:) + + RVC_TEST_CASE (36, ra, -2, \ + la t0, 1f; \ + li ra, 0; \ + c.jalr t0; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:sub ra, ra, t0) + +#if __riscv_xlen == 32 + RVC_TEST_CASE (37, ra, -2, \ + la t0, 1f; \ + li ra, 0; \ + c.jal 1f; \ + c.j 2f; \ + 1:c.j 1f; \ + 2:j fail; \ + 1:sub ra, ra, t0) +#endif + + la sp, data + RVC_TEST_CASE (40, a2, 0xfffffffffedcba99, c.lwsp a0, 12(sp); addi a0, a0, 1; c.swsp a0, 12(sp); c.lwsp a2, 12(sp)) +#if __riscv_xlen == 64 + RVC_TEST_CASE (41, a2, 0xfedcba9976543211, c.ldsp a0, 8(sp); addi a0, a0, 1; c.sdsp a0, 8(sp); c.ldsp a2, 8(sp)) +#endif + + RVC_TEST_CASE (42, t0, 0x246, li a0, 0x123; c.mv t0, a0; c.add t0, a0) + + .option pop + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 48, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/src/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/src/Makefrag new file mode 100644 index 0000000..0586843 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/src/Makefrag
@@ -0,0 +1,11 @@ +#======================================================================= +# Makefrag for rv32uc tests +#----------------------------------------------------------------------- + +rv32uc_sc_tests = \ + rvc \ + +rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests)) +rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests)) + +spike32_tests += $(rv32uc_p_tests) $(rv32uc_v_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/src/rvc.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/src/rvc.S new file mode 100644 index 0000000..debbbd8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uc/src/rvc.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64uc/rvc.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/Makefile new file mode 100644 index 0000000..75096b4 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv32g -mabi=ilp32)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/Makefrag new file mode 100644 index 0000000..ccb762d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/Makefrag
@@ -0,0 +1,20 @@ +rv32ud_sc_tests = \ + fadd \ + fdiv \ + fclass \ + fcmp \ + fcvt \ + fmadd \ + fmin \ + ldst \ + recoding \ + +# fcvt_w fails to asm + +# TODO: use this line instead of the last of the previous once move and structural tests have been implemented +# ldst move structural recoding \ + +rv32ud_tests = $(addsuffix .elf, $(rv32ud_sc_tests)) + +target_tests += $(rv32ud_tests) +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fadd.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fadd.reference_output new file mode 100644 index 0000000..1b0d7c1 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fadd.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fclass.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fclass.reference_output new file mode 100644 index 0000000..c70d71d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fclass.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000001 +00000002 +00000004 +00000008 +00000010 +00000020 +00000040 +00000080 +00000100 +00000200 +0000000c +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fcmp.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fcmp.reference_output new file mode 100644 index 0000000..58f69d3 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fcmp.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fcvt.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fcvt.reference_output new file mode 100644 index 0000000..458d44c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fcvt.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +ffffffff +ffffffff +ffffffff +ffffffff +0000000a +0000000b +0000000c +0000000d +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fdiv.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fdiv.reference_output new file mode 100644 index 0000000..eb7b73d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fdiv.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000010 +00000011 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fmadd.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fmadd.reference_output new file mode 100644 index 0000000..f0070ff --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fmadd.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fmin.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fmin.reference_output new file mode 100644 index 0000000..9ee418d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/fmin.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +ffffffff +ffffffff +ffffffff +ffffffff +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +ffffffff +ffffffff +00000014 +00000015 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +0000001e +0000001f +00000020 +00000021 +00000022 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/ldst.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/ldst.reference_output new file mode 100644 index 0000000..45bbed0 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/ldst.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/recoding.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/recoding.reference_output new file mode 100644 index 0000000..a38a338 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/references/recoding.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000001 +00000001 +00000000 +00000001 +00000001 +00000000 +ffffffff +ffffffff +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000001 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/Makefrag new file mode 100644 index 0000000..9cffb5d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/Makefrag
@@ -0,0 +1,12 @@ +#======================================================================= +# Makefrag for rv64ud tests +#----------------------------------------------------------------------- + +rv64ud_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst move structural recoding \ + +rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests)) +rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests)) + +spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fadd.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fadd.S new file mode 100644 index 0000000..943083c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fadd.S
@@ -0,0 +1,57 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fadd.S +#----------------------------------------------------------------------------- +# +# Test f{add|sub|mul}.d instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_OP2_D + #define TEST_FP_OP2_D TEST_FP_OP2_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fadd.d, 0, 3.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 3, fadd.d, 1, -1234, -1235.1, 1.1 ); + TEST_FP_OP2_D( 4, fadd.d, 1, 3.14159266, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_D( 5, fsub.d, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 6, fsub.d, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_D( 7, fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_D( 8, fmul.d, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 9, fmul.d, 1, 1358.61, -1235.1, -1.1 ); + TEST_FP_OP2_D(10, fmul.d, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); + + # Is the canonical NaN generated for Inf - Inf? + TEST_FP_OP2_D(11, fsub.d, 0x10, qNaN, Inf, Inf); + + # show finished. + li TESTNUM, 12; + SWSIG (12, TESTNUM); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fclass.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fclass.S new file mode 100644 index 0000000..356b244 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fclass.S
@@ -0,0 +1,53 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fclass.S +#----------------------------------------------------------------------------- +# +# Test fclass.d instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FCLASS_D + #define TEST_FCLASS_D TEST_FCLASS_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 ) + TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 ) + TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff ) + TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 ) + TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 ) + TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff ) + TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 ) + TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 ) + TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 ) + TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 ) + + # show finished. + li TESTNUM, 12; + SWSIG (12, TESTNUM); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fcmp.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fcmp.S new file mode 100644 index 0000000..af8d30a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fcmp.S
@@ -0,0 +1,64 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcmp.S +#----------------------------------------------------------------------------- +# +# Test f{eq|lt|le}.d instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_CMP_OP_D + #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32 +#endif + + TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_D( 4, flt.d, 0x00, 0, -1.36, -1.36) + + TEST_FP_CMP_OP_D( 5, feq.d, 0x00, 0, -1.37, -1.36) + TEST_FP_CMP_OP_D( 6, fle.d, 0x00, 1, -1.37, -1.36) + TEST_FP_CMP_OP_D( 7, flt.d, 0x00, 1, -1.37, -1.36) + + # Only sNaN should signal invalid for feq. + TEST_FP_CMP_OP_D( 8, feq.d, 0x00, 0, NaN, 0) + TEST_FP_CMP_OP_D( 9, feq.d, 0x00, 0, NaN, NaN) + TEST_FP_CMP_OP_D(10, feq.d, 0x10, 0, sNaN, 0) + + # qNaN should signal invalid for fle/flt. + TEST_FP_CMP_OP_D(11, flt.d, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_D(12, flt.d, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_D(13, flt.d, 0x10, 0, sNaN, 0) + TEST_FP_CMP_OP_D(14, fle.d, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_D(15, fle.d, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_D(16, fle.d, 0x10, 0, sNaN, 0) + + # show finished. + li TESTNUM, 17; + SWSIG (17, TESTNUM); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fcvt.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fcvt.S new file mode 100644 index 0000000..501eb9d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fcvt.S
@@ -0,0 +1,89 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt.S +#----------------------------------------------------------------------------- +# +# Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_INT_FP_OP_D + #define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32 + + #undef TEST_FCVT_S_D + #define TEST_FCVT_S_D TEST_FCVT_S_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_INT_FP_OP_D(2, fcvt.d.w, 2.0, 2); + TEST_INT_FP_OP_D(3, fcvt.d.w, -2.0, -2); + + TEST_INT_FP_OP_D(4, fcvt.d.wu, 2.0, 2); + TEST_INT_FP_OP_D(5, fcvt.d.wu, 4294967294, -2); + +#if __riscv_xlen >= 64 + TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2); + TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2); + + TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2); + TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2); +#endif + + TEST_FCVT_S_D(10, -1.5, -1.5) + TEST_FCVT_D_S(11, -1.5, -1.5) + +#if __riscv_xlen >= 64 + TEST_CASE(12, a0, 0x7ff8000000000000, + la a1, test_data_22; + ld a2, 0(a1); + fmv.d.x f2, a2; + fcvt.s.d f2, f2; + fcvt.d.s f2, f2; + fmv.x.d a0, f2; + ) +#else + TEST_CASE_D32(12, a0, a1, 0x7ff8000000000000, + la a1, test_data_22; + fld f2, 0(a1); + fcvt.s.d f2, f2; + fcvt.d.s f2, f2; + fsd f2, 0(a1); + lw a0, 0(a1); + lw a1, 4(a1) + ) +#endif + + # show finished. + li TESTNUM, 13; + SWSIG (13, TESTNUM); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + + TEST_DATA + +test_data_22: + .dword 0x7ffcffffffff8004 + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fcvt_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fcvt_w.S new file mode 100644 index 0000000..8bda002 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fcvt_w.S
@@ -0,0 +1,119 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt_w.S +#----------------------------------------------------------------------------- +# +# Test fcvt{wu|w|lu|l}.d instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_INT_OP_D( 2, fcvt.w.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D( 3, fcvt.w.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D( 4, fcvt.w.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D( 5, fcvt.w.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D( 6, fcvt.w.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D( 7, fcvt.w.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D( 8, fcvt.w.d, 0x10, -1<<31, -3e9, rtz); + TEST_FP_INT_OP_D( 9, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz); + + TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz); + +#if __riscv_xlen >= 64 + TEST_FP_INT_OP_D(22, fcvt.l.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D(23, fcvt.l.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D(24, fcvt.l.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(25, fcvt.l.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(26, fcvt.l.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(27, fcvt.l.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(28, fcvt.l.d, 0x00,-3000000000, -3e9, rtz); + TEST_FP_INT_OP_D(29, fcvt.l.d, 0x00, 3000000000, 3e9, rtz); + TEST_FP_INT_OP_D(20, fcvt.l.d, 0x10, -1<<63,-3e19, rtz); + TEST_FP_INT_OP_D(21, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz); + + TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz); +#endif + + # test negative NaN, negative infinity conversion + TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1) +#endif + TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1) +#endif + + # test positive NaN, positive infinity conversion + TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1) +#endif + TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1) +#endif + + # test NaN, infinity conversions to unsigned integer + TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1) + TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1) + TEST_CASE(64, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1) + TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1) + TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1) + TEST_CASE(68, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1) + TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1) +#endif + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + + TEST_DATA + +# -NaN, NaN, -inf, +inf +tdat: +.word 0xffffffff +.word 0x7fffffff +.word 0xff800000 +.word 0x7f800000 + +tdat_d: +.dword 0xffffffffffffffff +.dword 0x7fffffffffffffff +.dword 0xfff0000000000000 +.dword 0x7ff0000000000000 + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fdiv.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fdiv.S new file mode 100644 index 0000000..c0cb6a3 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fdiv.S
@@ -0,0 +1,61 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fdiv.S +#----------------------------------------------------------------------------- +# +# Test f{div|sqrt}.d instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the functions with the 32-bit variants defined in test_macros.h + #undef TEST_FP_OP2_D + #define TEST_FP_OP2_D TEST_FP_OP2_D32 + + #undef TEST_FP_OP1_D + #define TEST_FP_OP1_D TEST_FP_OP1_D32 + + #undef TEST_FP_OP1_D_DWORD_RESULT + #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_D( 3, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_D( 4, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 ); + + TEST_FP_OP1_D( 5, fsqrt.d, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_D( 6, fsqrt.d, 0, 100, 10000 ); + + TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 ); + + TEST_FP_OP1_D( 7, fsqrt.d, 1, 13.076696830622021, 171.0); + + TEST_FP_OP1_D( 8, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7); + + # show finished. + li TESTNUM, 17; + SWSIG (17, TESTNUM); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fmadd.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fmadd.S new file mode 100644 index 0000000..5f8c17c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fmadd.S
@@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd.S +#----------------------------------------------------------------------------- +# +# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_OP3_D + #define TEST_FP_OP3_D TEST_FP_OP3_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP3_D( 2, fmadd.d, 0, 3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 3, fmadd.d, 1, 1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 4, fmadd.d, 0, -12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 5, fnmadd.d, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 6, fnmadd.d, 1, -1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 7, fnmadd.d, 0, 12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 8, fmsub.d, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 9, fmsub.d, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(10, fmsub.d, 0, -8.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D(11, fnmsub.d, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D(12, fnmsub.d, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(13, fnmsub.d, 0, 8.0, 2.0, -5.0, -2.0 ); + + # show finished. + li TESTNUM, 14; + SWSIG (14, TESTNUM); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fmin.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fmin.S new file mode 100644 index 0000000..8ed0b0b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/fmin.S
@@ -0,0 +1,67 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin.S +#----------------------------------------------------------------------------- +# +# Test f{min|max}.d instructinos. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_OP2_D + #define TEST_FP_OP2_D TEST_FP_OP2_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fmin.d, 0, 1.0, 2.5, 1.0 ); + TEST_FP_OP2_D( 3, fmin.d, 0, -1235.1, -1235.1, 1.1 ); + TEST_FP_OP2_D( 4, fmin.d, 0, -1235.1, 1.1, -1235.1 ); + TEST_FP_OP2_D( 5, fmin.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D( 6, fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D( 7, fmin.d, 0, -2.0, -1.0, -2.0 ); + + TEST_FP_OP2_D(12, fmax.d, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_D(13, fmax.d, 0, 1.1, -1235.1, 1.1 ); + TEST_FP_OP2_D(14, fmax.d, 0, 1.1, 1.1, -1235.1 ); + TEST_FP_OP2_D(15, fmax.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D(16, fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D(17, fmax.d, 0, -1.0, -1.0, -2.0 ); + + # FMIN(sNaN, x) = x + TEST_FP_OP2_D(20, fmax.d, 0x10, 1.0, sNaN, 1.0); + # FMIN(qNaN, qNaN) = canonical NaN + TEST_FP_OP2_D(21, fmax.d, 0x00, qNaN, NaN, NaN); + + # -0.0 < +0.0 + TEST_FP_OP2_D(30, fmin.d, 0, -0.0, -0.0, 0.0 ); + TEST_FP_OP2_D(31, fmin.d, 0, -0.0, 0.0, -0.0 ); + TEST_FP_OP2_D(32, fmax.d, 0, 0.0, -0.0, 0.0 ); + TEST_FP_OP2_D(33, fmax.d, 0, 0.0, 0.0, -0.0 ); + + # show finished. + li TESTNUM, 34; + SWSIG (34, TESTNUM); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/ldst.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/ldst.S new file mode 100644 index 0000000..3727d93 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/ldst.S
@@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + la s0, tdat + TEST_CASE(2, a0, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(3, a0, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(4, a0, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(5, a0, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(6, a0, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/move.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/move.S new file mode 100644 index 0000000..f6e60fe --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/move.S
@@ -0,0 +1,113 @@ +# See LICENSE for license details. + +#***************************************************************************** +# move.S +#----------------------------------------------------------------------------- +# +# This test verifies that fmv.d.x, fmv.x.d, and fsgnj[x|n].d work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + +#TODO: make 32-bit compatible version +#define TEST_FSGNJD(n, insn, new_sign, rs1_sign, rs2_sign) \ + TEST_CASE(n, a0, 0x123456789abcdef0 | (-(new_sign) << 63), \ + li a1, ((rs1_sign) << 63) | 0x123456789abcdef0; \ + li a2, -(rs2_sign); \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + insn f0, f1, f2; \ + fmv.x.d a0, f0) + + TEST_FSGNJD(10, fsgnj.d, 0, 0, 0) + TEST_FSGNJD(11, fsgnj.d, 1, 0, 1) + TEST_FSGNJD(12, fsgnj.d, 0, 1, 0) + TEST_FSGNJD(13, fsgnj.d, 1, 1, 1) + + TEST_FSGNJD(20, fsgnjn.d, 1, 0, 0) + TEST_FSGNJD(21, fsgnjn.d, 0, 0, 1) + TEST_FSGNJD(22, fsgnjn.d, 1, 1, 0) + TEST_FSGNJD(23, fsgnjn.d, 0, 1, 1) + + TEST_FSGNJD(30, fsgnjx.d, 0, 0, 0) + TEST_FSGNJD(31, fsgnjx.d, 1, 0, 1) + TEST_FSGNJD(32, fsgnjx.d, 1, 1, 0) + TEST_FSGNJD(33, fsgnjx.d, 0, 1, 1) + +// Test fsgnj.s in conjunction with double-precision moves +#define TEST_FSGNJS(n, rd, rs1, rs2) \ + TEST_CASE(n, a0, (rd) | (-((rd) >> 31) << 32), \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.s f0, f1, f2; \ + fmv.x.s a0, f0); \ + TEST_CASE(1##n, a0, (rd) | 0xffffffff00000000, \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.s f0, f1, f2; \ + fmv.x.d a0, f0) + + TEST_FSGNJS(40, 0x7fc00000, 0x7ffffffe12345678, 0) + TEST_FSGNJS(41, 0x7fc00000, 0xfffffffe12345678, 0) + TEST_FSGNJS(42, 0x7fc00000, 0x7fffffff12345678, 0) + TEST_FSGNJS(43, 0x12345678, 0xffffffff12345678, 0) + + TEST_FSGNJS(50, 0x7fc00000, 0x7ffffffe12345678, 0x80000000) + TEST_FSGNJS(51, 0x7fc00000, 0xfffffffe12345678, 0x80000000) + TEST_FSGNJS(52, 0x7fc00000, 0x7fffffff12345678, 0x80000000) + TEST_FSGNJS(53, 0x12345678, 0xffffffff12345678, 0x80000000) + + TEST_FSGNJS(60, 0xffc00000, 0x7ffffffe12345678, 0xffffffff80000000) + TEST_FSGNJS(61, 0xffc00000, 0xfffffffe12345678, 0xffffffff80000000) + TEST_FSGNJS(62, 0x92345678, 0xffffffff12345678, 0xffffffff80000000) + TEST_FSGNJS(63, 0x12345678, 0xffffffff12345678, 0x7fffffff80000000) + +// Test fsgnj.d in conjunction with single-precision moves +#define TEST_FSGNJD_SP(n, isnan, rd, rs1, rs2) \ + TEST_CASE(n, a0, ((rd) & 0xffffffff) | (-(((rd) >> 31) & 1) << 32), \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.d f0, f1, f2; \ + feq.s a0, f0, f0; \ + addi a0, a0, -!(isnan); \ + bnez a0, 1f; \ + fmv.x.s a0, f0; \ + 1:); \ + TEST_CASE(1##n, a0, rd, \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.d f0, f1, f2; \ + fmv.x.d a0, f0; \ + 1:) + + TEST_FSGNJD_SP(70, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff11111111) + TEST_FSGNJD_SP(71, 1, 0x7fffffff11111111, 0xffffffff11111111, 0x7fffffff11111111) + TEST_FSGNJD_SP(72, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff91111111) + TEST_FSGNJD_SP(73, 0, 0xffffffff11111111, 0xffffffff11111111, 0x8000000000000000) + TEST_FSGNJD_SP(74, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff11111111) + TEST_FSGNJD_SP(75, 1, 0x7fffffff11111111, 0x7fffffff11111111, 0x7fffffff11111111) + TEST_FSGNJD_SP(76, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff91111111) + TEST_FSGNJD_SP(77, 0, 0xffffffff11111111, 0x7fffffff11111111, 0x8000000000000000) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/recoding.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/recoding.S new file mode 100644 index 0000000..9dffef8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/recoding.S
@@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# recoding.S +#----------------------------------------------------------------------------- +# +# Test corner cases of John Hauser's microarchitectural recoding scheme. +# There are twice as many recoded values as IEEE-754 values; some of these +# extras are redundant (e.g. Inf) and others are illegal (subnormals with +# too many bits set). +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + # Make sure infinities with different mantissas compare as equal. + fld f0, minf, a0 + fld f1, three, a0 + fmul.d f1, f1, f0 + TEST_CASE( 2, a0, 1, feq.d a0, f0, f1) + TEST_CASE( 3, a0, 1, fle.d a0, f0, f1) + TEST_CASE( 4, a0, 0, flt.d a0, f0, f1) + + # Likewise, but for zeroes. + fcvt.d.w f0, x0 + li a0, 1 + fcvt.d.w f1, a0 + fmul.d f1, f1, f0 + TEST_CASE(5, a0, 1, feq.d a0, f0, f1) + TEST_CASE(6, a0, 1, fle.d a0, f0, f1) + TEST_CASE(7, a0, 0, flt.d a0, f0, f1) + + # When converting small doubles to single-precision subnormals, + # ensure that the extra precision is discarded. + flw f0, big, a0 + fld f1, tiny, a0 + fcvt.s.d f1, f1 + fmul.s f0, f0, f1 + fmv.x.s a0, f0 + lw a1, small + TEST_CASE(10, a0, 0, sub a0, a0, a1) + + # Make sure FSD+FLD correctly saves and restores a single-precision value. + flw f0, three, a0 + fadd.s f1, f0, f0 + fadd.s f0, f0, f0 + fsd f0, tiny, a0 + fld f0, tiny, a0 + TEST_CASE(20, a0, 1, feq.s a0, f0, f1) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + +minf: .double -Inf +three: .double 3.0 +big: .float 1221 +small: .float 2.9133121e-37 +tiny: .double 2.3860049081905093e-40 + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/structural.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/structural.S new file mode 100644 index 0000000..be777ab --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/rv64ud/structural.S
@@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# structural.S +#----------------------------------------------------------------------------- +# +# This test verifies that the FPU correctly obviates structural hazards on its +# writeback port (e.g. fadd followed by fsgnj) +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + +li x25, 1 + +li x2, 0x3FF0000000000000 +li x1, 0x3F800000 + +#define TEST(nops, errcode) \ + fmv.d.x f4, x0 ;\ + fmv.s.x f3, x0 ;\ + fmv.d.x f2, x2 ;\ + fmv.s.x f1, x1 ;\ + j 1f ;\ + .align 5 ;\ +1:fmul.d f4, f2, f2 ;\ + nops ;\ + fsgnj.s f3, f1, f1 ;\ + fmv.x.d x4, f4 ;\ + fmv.x.s x5, f3 ;\ + beq x1, x5, 2f ;\ + RV_COMPLIANCE_HALT ;\ +2:beq x2, x4, 2f ;\ + RV_COMPLIANCE_HALT; \ +2:fmv.d.x f2, zero ;\ + fmv.s.x f1, zero ;\ + +TEST(;,2) +TEST(nop,4) +TEST(nop;nop,6) +TEST(nop;nop;nop,8) +TEST(nop;nop;nop;nop,10) +TEST(nop;nop;nop;nop;nop,12) +TEST(nop;nop;nop;nop;nop;nop,14) + +RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fadd.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fadd.S new file mode 100644 index 0000000..5fb9090 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fadd.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fadd.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fclass.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fclass.S new file mode 100644 index 0000000..c960ad6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fclass.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fclass.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fcmp.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fcmp.S new file mode 100644 index 0000000..55d1c3a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fcmp.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fcmp.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fcvt.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fcvt.S new file mode 100644 index 0000000..8811b6e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fcvt.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fcvt.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fcvt_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fcvt_w.S new file mode 100644 index 0000000..e5cbfa9 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fcvt_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fcvt_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fdiv.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fdiv.S new file mode 100644 index 0000000..793e51a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fdiv.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fdiv.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fmadd.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fmadd.S new file mode 100644 index 0000000..e60934c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fmadd.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fmadd.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fmin.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fmin.S new file mode 100644 index 0000000..c80c880 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/fmin.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/fmin.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/ldst.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/ldst.S new file mode 100644 index 0000000..c5e8b7c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/ldst.S
@@ -0,0 +1,51 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV32UF +RV_COMPLIANCE_CODE_BEGIN + + la s0, tdat + TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0)) + + # show finished. + li TESTNUM, 7; + SWSIG (7, TESTNUM); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/move.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/move.S new file mode 100644 index 0000000..4551ffd --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/move.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/move.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/recoding.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/recoding.S new file mode 100644 index 0000000..a926f18 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ud/src/recoding.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64ud/recoding.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/Makefile new file mode 100644 index 0000000..75096b4 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv32g -mabi=ilp32)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/Makefrag new file mode 100644 index 0000000..c45c058 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/Makefrag
@@ -0,0 +1,17 @@ +rv32uf_sc_tests = \ + fadd \ + fdiv \ + fclass \ + fcmp \ + fcvt \ + fcvt_w \ + fmadd \ + fmin \ + ldst \ + move \ + recoding + +rv32uf_tests = $(addsuffix .elf, $(rv32uf_sc_tests)) + +target_tests += $(rv32uf_tests) +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fadd.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fadd.reference_output new file mode 100644 index 0000000..4379142 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fadd.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fclass.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fclass.reference_output new file mode 100644 index 0000000..4c203b9 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fclass.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000001 +00000002 +00000004 +00000008 +00000010 +00000020 +00000040 +00000080 +00000100 +00000200 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fcmp.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fcmp.reference_output new file mode 100644 index 0000000..670991a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fcmp.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fcvt.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fcvt.reference_output new file mode 100644 index 0000000..cf300d0 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fcvt.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fcvt_w.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fcvt_w.reference_output new file mode 100644 index 0000000..70afd69 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fcvt_w.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +ffffffff +ffffffff +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fdiv.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fdiv.reference_output new file mode 100644 index 0000000..fc83973 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fdiv.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fmadd.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fmadd.reference_output new file mode 100644 index 0000000..b1c7a6d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fmadd.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fmin.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fmin.reference_output new file mode 100644 index 0000000..97bc706 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/fmin.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +ffffffff +ffffffff +ffffffff +ffffffff +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +ffffffff +ffffffff +00000014 +00000015 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +0000001e +0000001f +00000020 +00000021 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/ldst.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/ldst.reference_output new file mode 100644 index 0000000..dd945ff --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/ldst.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +40000000 +bf800000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/move.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/move.reference_output new file mode 100644 index 0000000..a26a81e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/move.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000001 +00000034 +00000014 +00000001 +00000054 +00000014 +00000050 +ffffffff +12345678 +92345678 +12345678 +92345678 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +92345678 +12345678 +92345678 +12345678 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +12345678 +92345678 +92345678 +12345678 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/recoding.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/recoding.reference_output new file mode 100644 index 0000000..9b04a04 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/references/recoding.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000001 +00000001 +00000000 +00000001 +00000001 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/Makefrag new file mode 100644 index 0000000..33c11db --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/Makefrag
@@ -0,0 +1,12 @@ +#======================================================================= +# Makefrag for rv64uf tests +#----------------------------------------------------------------------- + +rv64uf_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst move recoding \ + +rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests)) +rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests)) + +spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fadd.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fadd.S new file mode 100644 index 0000000..1c12db5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fadd.S
@@ -0,0 +1,47 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fadd.S +#----------------------------------------------------------------------------- +# +# Test f{add|sub|mul}.s instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_S( 2, fadd.s, 0, 3.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 3, fadd.s, 1, -1234, -1235.1, 1.1 ); + TEST_FP_OP2_S( 4, fadd.s, 1, 3.14159265, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_S( 5, fsub.s, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 6, fsub.s, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_S( 7, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_S( 8, fmul.s, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 9, fmul.s, 1, 1358.61, -1235.1, -1.1 ); + TEST_FP_OP2_S(10, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); + + # Is the canonical NaN generated for Inf - Inf? + TEST_FP_OP2_S(11, fsub.s, 0x10, qNaNf, Inf, Inf); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fclass.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fclass.S new file mode 100644 index 0000000..5b09d36 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fclass.S
@@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fclass.S +#----------------------------------------------------------------------------- +# +# Test fclass.s instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FCLASS_S( 2, 1 << 0, 0xff800000 ) + TEST_FCLASS_S( 3, 1 << 1, 0xbf800000 ) + TEST_FCLASS_S( 4, 1 << 2, 0x807fffff ) + TEST_FCLASS_S( 5, 1 << 3, 0x80000000 ) + TEST_FCLASS_S( 6, 1 << 4, 0x00000000 ) + TEST_FCLASS_S( 7, 1 << 5, 0x007fffff ) + TEST_FCLASS_S( 8, 1 << 6, 0x3f800000 ) + TEST_FCLASS_S( 9, 1 << 7, 0x7f800000 ) + TEST_FCLASS_S(10, 1 << 8, 0x7f800001 ) + TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fcmp.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fcmp.S new file mode 100644 index 0000000..215391c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fcmp.S
@@ -0,0 +1,54 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcmp.S +#----------------------------------------------------------------------------- +# +# Test f{eq|lt|le}.s instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_CMP_OP_S( 2, feq.s, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_S( 3, fle.s, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_S( 4, flt.s, 0x00, 0, -1.36, -1.36) + + TEST_FP_CMP_OP_S( 5, feq.s, 0x00, 0, -1.37, -1.36) + TEST_FP_CMP_OP_S( 6, fle.s, 0x00, 1, -1.37, -1.36) + TEST_FP_CMP_OP_S( 7, flt.s, 0x00, 1, -1.37, -1.36) + + # Only sNaN should signal invalid for feq. + TEST_FP_CMP_OP_S( 8, feq.s, 0x00, 0, NaN, 0) + TEST_FP_CMP_OP_S( 9, feq.s, 0x00, 0, NaN, NaN) + TEST_FP_CMP_OP_S(10, feq.s, 0x10, 0, sNaNf, 0) + + # qNaN should signal invalid for fle/flt. + TEST_FP_CMP_OP_S(11, flt.s, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_S(12, flt.s, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_S(13, flt.s, 0x10, 0, sNaNf, 0) + TEST_FP_CMP_OP_S(14, fle.s, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_S(15, fle.s, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_S(16, fle.s, 0x10, 0, sNaNf, 0) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fcvt.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fcvt.S new file mode 100644 index 0000000..9f60120 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fcvt.S
@@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt.S +#----------------------------------------------------------------------------- +# +# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_INT_FP_OP_S( 2, fcvt.s.w, 2.0, 2); + TEST_INT_FP_OP_S( 3, fcvt.s.w, -2.0, -2); + + TEST_INT_FP_OP_S( 4, fcvt.s.wu, 2.0, 2); + TEST_INT_FP_OP_S( 5, fcvt.s.wu, 4.2949673e9, -2); + +#if __riscv_xlen >= 64 + TEST_INT_FP_OP_S( 6, fcvt.s.l, 2.0, 2); + TEST_INT_FP_OP_S( 7, fcvt.s.l, -2.0, -2); + + TEST_INT_FP_OP_S( 8, fcvt.s.lu, 2.0, 2); + TEST_INT_FP_OP_S( 9, fcvt.s.lu, 1.8446744e19, -2); +#endif + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fcvt_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fcvt_w.S new file mode 100644 index 0000000..186ac1d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fcvt_w.S
@@ -0,0 +1,111 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt_w.S +#----------------------------------------------------------------------------- +# +# Test fcvt{wu|w|lu|l}.s instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_INT_OP_S( 2, fcvt.w.s, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_S( 3, fcvt.w.s, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_S( 4, fcvt.w.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S( 5, fcvt.w.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S( 6, fcvt.w.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S( 7, fcvt.w.s, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_S( 8, fcvt.w.s, 0x10, -1<<31, -3e9, rtz); + TEST_FP_INT_OP_S( 9, fcvt.w.s, 0x10, (1<<31)-1, 3e9, rtz); + + TEST_FP_INT_OP_S(12, fcvt.wu.s, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_S(13, fcvt.wu.s, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_S(14, fcvt.wu.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S(15, fcvt.wu.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S(16, fcvt.wu.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S(17, fcvt.wu.s, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_S(18, fcvt.wu.s, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_S(19, fcvt.wu.s, 0x00, 3000000000, 3e9, rtz); + +#if __riscv_xlen >= 64 + TEST_FP_INT_OP_S(22, fcvt.l.s, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_S(23, fcvt.l.s, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_S(24, fcvt.l.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S(25, fcvt.l.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S(26, fcvt.l.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S(27, fcvt.l.s, 0x01, 1, 1.1, rtz); + + TEST_FP_INT_OP_S(32, fcvt.lu.s, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_S(33, fcvt.lu.s, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_S(34, fcvt.lu.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S(35, fcvt.lu.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S(36, fcvt.lu.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10, 0, -3e9, rtz); +#endif + + # test negative NaN, negative infinity conversion + TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1) + TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1) + TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1) +#endif + + # test positive NaN, positive infinity conversion + TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1) + TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1) + TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1) +#endif + + # test NaN, infinity conversions to unsigned integer + TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.s x1, f1) + TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1) + TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1) + TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1) + TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1) + TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1) + TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.s x1, f1) +#endif + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + + TEST_DATA + +# -NaN, NaN, -inf, +inf +tdat: +.word 0xffffffff +.word 0x7fffffff +.word 0xff800000 +.word 0x7f800000 + +tdat_d: +.dword 0xffffffffffffffff +.dword 0x7fffffffffffffff +.dword 0xfff0000000000000 +.dword 0x7ff0000000000000 + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fdiv.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fdiv.S new file mode 100644 index 0000000..5d2ddfb --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fdiv.S
@@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fdiv.S +#----------------------------------------------------------------------------- +# +# Test f{div|sqrt}.s instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_S(2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_S(3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_S(4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 ); + + TEST_FP_OP1_S(5, fsqrt.s, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_S(6, fsqrt.s, 0, 100, 10000 ); + + TEST_FP_OP1_S_DWORD_RESULT(7, fsqrt.s, 0x10, 0x7FC00000, -1.0 ); + + TEST_FP_OP1_S(8, fsqrt.s, 1, 13.076696, 171.0); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fmadd.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fmadd.S new file mode 100644 index 0000000..40d84d0 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fmadd.S
@@ -0,0 +1,48 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd.S +#----------------------------------------------------------------------------- +# +# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP3_S( 2, fmadd.s, 0, 3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 3, fmadd.s, 1, 1236.2, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S( 4, fmadd.s, 0, -12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_S( 5, fnmadd.s, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 6, fnmadd.s, 1, -1236.2, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S( 7, fnmadd.s, 0, 12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_S( 8, fmsub.s, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 9, fmsub.s, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(10, fmsub.s, 0, -8.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_S(11, fnmsub.s, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S(12, fnmsub.s, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(13, fnmsub.s, 0, 8.0, 2.0, -5.0, -2.0 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fmin.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fmin.S new file mode 100644 index 0000000..63e1ee8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/fmin.S
@@ -0,0 +1,56 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin.S +#----------------------------------------------------------------------------- +# +# Test f{min|max}.s instructinos. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_S( 2, fmin.s, 0, 1.0, 2.5, 1.0 ); + TEST_FP_OP2_S( 3, fmin.s, 0, -1235.1, -1235.1, 1.1 ); + TEST_FP_OP2_S( 4, fmin.s, 0, -1235.1, 1.1, -1235.1 ); + TEST_FP_OP2_S( 5, fmin.s, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_S( 6, fmin.s, 0, 0.00000001, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S( 7, fmin.s, 0, -2.0, -1.0, -2.0 ); + + TEST_FP_OP2_S(12, fmax.s, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_S(13, fmax.s, 0, 1.1, -1235.1, 1.1 ); + TEST_FP_OP2_S(14, fmax.s, 0, 1.1, 1.1, -1235.1 ); + TEST_FP_OP2_S(15, fmax.s, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_S(16, fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S(17, fmax.s, 0, -1.0, -1.0, -2.0 ); + + # FMIN(sNaN, x) = x + TEST_FP_OP2_S(20, fmax.s, 0x10, 1.0, sNaNf, 1.0); + # FMIN(qNaN, qNaN) = canonical NaN + TEST_FP_OP2_S(21, fmax.s, 0x00, qNaNf, NaN, NaN); + + # -0.0 < +0.0 + TEST_FP_OP2_S(30, fmin.s, 0, -0.0, -0.0, 0.0 ); + TEST_FP_OP2_S(31, fmin.s, 0, -0.0, 0.0, -0.0 ); + TEST_FP_OP2_S(32, fmax.s, 0, 0.0, -0.0, 0.0 ); + TEST_FP_OP2_S(33, fmax.s, 0, 0.0, 0.0, -0.0 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/ldst.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/ldst.S new file mode 100644 index 0000000..38b447e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/ldst.S
@@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1)) + TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/move.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/move.S new file mode 100644 index 0000000..5bd0473 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/move.S
@@ -0,0 +1,60 @@ +# See LICENSE for license details. + +#***************************************************************************** +# move.S +#----------------------------------------------------------------------------- +# +# This test verifies that the fmv.s.x, fmv.x.s, and fsgnj[x|n].d instructions +# and the fcsr work properly. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0) + TEST_CASE(3, a0, 0x34, frsr a0) + TEST_CASE(4, a0, 0x14, frflags a0) + TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2) + TEST_CASE(6, a0, 0x54, frsr a0) + TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4) + TEST_CASE(8, a0, 0x50, frsr a0) + +#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \ + TEST_CASE(n, a0, 0x12345678 | (-(new_sign) << 31), \ + li a1, ((rs1_sign) << 31) | 0x12345678; \ + li a2, -(rs2_sign); \ + fmv.s.x f1, a1; \ + fmv.s.x f2, a2; \ + insn f0, f1, f2; \ + fmv.x.s a0, f0) + + TEST_FSGNJS(10, fsgnj.s, 0, 0, 0) + TEST_FSGNJS(11, fsgnj.s, 1, 0, 1) + TEST_FSGNJS(12, fsgnj.s, 0, 1, 0) + TEST_FSGNJS(13, fsgnj.s, 1, 1, 1) + + TEST_FSGNJS(20, fsgnjn.s, 1, 0, 0) + TEST_FSGNJS(21, fsgnjn.s, 0, 0, 1) + TEST_FSGNJS(22, fsgnjn.s, 1, 1, 0) + TEST_FSGNJS(23, fsgnjn.s, 0, 1, 1) + + TEST_FSGNJS(30, fsgnjx.s, 0, 0, 0) + TEST_FSGNJS(31, fsgnjx.s, 1, 0, 1) + TEST_FSGNJS(32, fsgnjx.s, 1, 1, 0) + TEST_FSGNJS(33, fsgnjx.s, 0, 1, 1) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/recoding.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/recoding.S new file mode 100644 index 0000000..efcef73 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/rv64uf/recoding.S
@@ -0,0 +1,52 @@ +# See LICENSE for license details. + +#***************************************************************************** +# recoding.S +#----------------------------------------------------------------------------- +# +# Test corner cases of John Hauser's microarchitectural recoding scheme. +# There are twice as many recoded values as IEEE-754 values; some of these +# extras are redundant (e.g. Inf) and others are illegal (subnormals with +# too many bits set). +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64UF +RV_COMPLIANCE_CODE_BEGIN + + # Make sure infinities with different mantissas compare as equal. + flw f0, minf, a0 + flw f1, three, a0 + fmul.s f1, f1, f0 + TEST_CASE( 2, a0, 1, feq.s a0, f0, f1) + TEST_CASE( 3, a0, 1, fle.s a0, f0, f1) + TEST_CASE( 4, a0, 0, flt.s a0, f0, f1) + + # Likewise, but for zeroes. + fcvt.s.w f0, x0 + li a0, 1 + fcvt.s.w f1, a0 + fmul.s f1, f1, f0 + TEST_CASE(5, a0, 1, feq.s a0, f0, f1) + TEST_CASE(6, a0, 1, fle.s a0, f0, f1) + TEST_CASE(7, a0, 0, flt.s a0, f0, f1) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + +minf: .float -Inf +three: .float 3.0 + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/Makefrag new file mode 100644 index 0000000..7dde664 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/Makefrag
@@ -0,0 +1,12 @@ +#======================================================================= +# Makefrag for rv32uf tests +#----------------------------------------------------------------------- + +rv32uf_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst move recoding \ + +rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests)) +rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests)) + +spike32_tests += $(rv32uf_p_tests) $(rv32uf_v_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fadd.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fadd.S new file mode 100644 index 0000000..b832c3d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fadd.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fadd.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fclass.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fclass.S new file mode 100644 index 0000000..19bbcc5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fclass.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fclass.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fcmp.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fcmp.S new file mode 100644 index 0000000..2dbf451 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fcmp.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fcmp.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fcvt.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fcvt.S new file mode 100644 index 0000000..627f1f2 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fcvt.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fcvt.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fcvt_w.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fcvt_w.S new file mode 100644 index 0000000..3447530 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fcvt_w.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fcvt_w.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fdiv.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fdiv.S new file mode 100644 index 0000000..12aaa3d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fdiv.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fdiv.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fmadd.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fmadd.S new file mode 100644 index 0000000..8a5aacb --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fmadd.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fmadd.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fmin.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fmin.S new file mode 100644 index 0000000..9231d01 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/fmin.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/fmin.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/ldst.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/ldst.S new file mode 100644 index 0000000..e66f942 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/ldst.S
@@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV32UF +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a0, 0x40000000, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); lw a0, 20(a1)) + TEST_CASE(3, a0, 0xbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); lw a0, 24(a1)) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/move.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/move.S new file mode 100644 index 0000000..949da6f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/move.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/move.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/recoding.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/recoding.S new file mode 100644 index 0000000..5dc0113 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32uf/src/recoding.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64UF +#define RVTEST_RV64UF RVTEST_RV32UF + +#include "../rv64uf/recoding.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/Makefile new file mode 100644 index 0000000..9da7ab8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv32i -mabi=ilp32)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/Makefrag new file mode 100644 index 0000000..21638c3 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/Makefrag
@@ -0,0 +1,22 @@ +rv32ui_sc_tests = \ + simple \ + add addi \ + and andi \ + auipc \ + beq bge bgeu blt bltu bne \ + fence_i \ + jal jalr \ + lb lbu lh lhu lw \ + lui \ + or ori \ + sb sh sw \ + sll slli \ + slt slti sltiu sltu \ + sra srai \ + srl srli \ + sub \ + xor xori + +rv32ui_tests = $(addsuffix .elf, $(rv32ui_sc_tests)) + +target_tests += $(rv32ui_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/add.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/add.reference_output new file mode 100644 index 0000000..eb17cbf --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/add.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000000 +00000002 +0000000a +ffff8000 +80000000 +7fff8000 +00007fff +7fffffff +80007ffe +80007fff +7fff7fff +ffffffff +00000000 +fffffffe +80000000 +00000018 +00000019 +0000001a +00000018 +00000019 +0000001a +00000018 +00000019 +0000001a +00000018 +00000019 +0000001a +00000018 +00000019 +0000001a +00000018 +00000019 +0000001a +0000000f +00000020 +00000000 +00000000 +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/addi.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/addi.reference_output new file mode 100644 index 0000000..7fbc354 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/addi.reference_output
@@ -0,0 +1,32 @@ +00000001 +ffffffff +00000000 +00000002 +0000000a +fffff800 +80000000 +7ffff800 +000007ff +7fffffff +800007fe +800007ff +7ffff7ff +ffffffff +00000000 +fffffffe +80000000 +00000018 +00000018 +00000017 +00000016 +00000018 +00000017 +00000016 +00000020 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/and.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/and.reference_output new file mode 100644 index 0000000..167316e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/and.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +0f000f00 +00f000f0 +000f000f +f000f000 +0f000f00 +00f000f0 +ff00ff00 +0f000f00 +00f000f0 +000f000f +0f000f00 +00f000f0 +000f000f +0f000f00 +00f000f0 +000f000f +0f000f00 +00f000f0 +000f000f +0f000f00 +00f000f0 +000f000f +00000000 +00000000 +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/andi.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/andi.reference_output new file mode 100644 index 0000000..ca148c0 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/andi.reference_output
@@ -0,0 +1,20 @@ +00000001 +ffffffff +ff00ff00 +000000f0 +0000000f +00000000 +00000000 +00000700 +000000f0 +f00ff00f +00000700 +000000f0 +0000000f +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/auipc.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/auipc.reference_output new file mode 100644 index 0000000..774e0d5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/auipc.reference_output
@@ -0,0 +1,4 @@ +00000001 +ffffffff +00002710 +ffffd8f0
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/beq.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/beq.reference_output new file mode 100644 index 0000000..7a48a72 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/beq.reference_output
@@ -0,0 +1,32 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000003 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bge.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bge.reference_output new file mode 100644 index 0000000..85004f0 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bge.reference_output
@@ -0,0 +1,32 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +00000003 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bgeu.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bgeu.reference_output new file mode 100644 index 0000000..85004f0 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bgeu.reference_output
@@ -0,0 +1,32 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +00000003 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/blt.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/blt.reference_output new file mode 100644 index 0000000..7a48a72 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/blt.reference_output
@@ -0,0 +1,32 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000003 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bltu.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bltu.reference_output new file mode 100644 index 0000000..7a48a72 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bltu.reference_output
@@ -0,0 +1,32 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000003 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bne.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bne.reference_output new file mode 100644 index 0000000..7a48a72 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/bne.reference_output
@@ -0,0 +1,32 @@ +00000001 +ffffffff +00000002 +00000003 +00000004 +00000005 +00000006 +00000007 +00000008 +00000009 +0000000a +0000000b +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000003 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/fence_i.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/fence_i.reference_output new file mode 100644 index 0000000..65286e1 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/fence_i.reference_output
@@ -0,0 +1,4 @@ +00000001 +ffffffff +000001bc +00000309
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/jal.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/jal.reference_output new file mode 100644 index 0000000..2ffe22c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/jal.reference_output
@@ -0,0 +1,12 @@ +00000001 +ffffffff +ffffffff +00000003 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/jalr.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/jalr.reference_output new file mode 100644 index 0000000..f568822 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/jalr.reference_output
@@ -0,0 +1,12 @@ +00000001 +ffffffff +ffffffff +ffffffff +00000004 +00000005 +00000006 +00000004 +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lb.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lb.reference_output new file mode 100644 index 0000000..b7f51f3 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lb.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +ffffffff +00000000 +fffffff0 +0000000f +ffffffff +00000000 +fffffff0 +0000000f +ffffffff +00000000 +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000002 +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lbu.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lbu.reference_output new file mode 100644 index 0000000..47c5820 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lbu.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +000000ff +00000000 +000000f0 +0000000f +000000ff +00000000 +000000f0 +0000000f +000000ff +00000000 +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000002 +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lh.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lh.reference_output new file mode 100644 index 0000000..0e84a09 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lh.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +000000ff +ffffff00 +00000ff0 +fffff00f +000000ff +ffffff00 +00000ff0 +fffff00f +000000ff +ffffff00 +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000002 +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lhu.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lhu.reference_output new file mode 100644 index 0000000..214caaa --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lhu.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +000000ff +0000ff00 +00000ff0 +0000f00f +000000ff +0000ff00 +00000ff0 +0000f00f +000000ff +0000ff00 +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000002 +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lui.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lui.reference_output new file mode 100644 index 0000000..12dac3f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lui.reference_output
@@ -0,0 +1,12 @@ +00000001 +ffffffff +00000000 +fffff800 +000007ff +fffff800 +00000000 +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lw.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lw.reference_output new file mode 100644 index 0000000..f94159f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/lw.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00ff00ff +ff00ff00 +0ff00ff0 +f00ff00f +00ff00ff +ff00ff00 +0ff00ff0 +f00ff00f +00ff00ff +ff00ff00 +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000002 +00000002 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/or.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/or.reference_output new file mode 100644 index 0000000..0057494 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/or.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +ff0fff0f +fff0fff0 +0fff0fff +f0fff0ff +ff0fff0f +ff0fff0f +ff00ff00 +ff0fff0f +fff0fff0 +0fff0fff +ff0fff0f +fff0fff0 +0fff0fff +ff0fff0f +fff0fff0 +0fff0fff +ff0fff0f +fff0fff0 +0fff0fff +ff0fff0f +fff0fff0 +0fff0fff +ff00ff00 +00ff00ff +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/ori.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/ori.reference_output new file mode 100644 index 0000000..b0a0cf3 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/ori.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +ffffff0f +0ff00ff0 +00ff07ff +f00ff0ff +ff00fff0 +0ff00ff0 +00ff07ff +f00ff0ff +0ff00ff0 +ffffffff +f00ff0ff +000000f0 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sb.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sb.reference_output new file mode 100644 index 0000000..e414f99 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sb.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +ffffffaa +00000000 +ffffefa0 +0000000a +ffffffaa +00000000 +ffffffa0 +0000000a +00000078 +ffffff98 +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sh.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sh.reference_output new file mode 100644 index 0000000..c03ab18 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sh.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +000000aa +ffffaa00 +beef0aa0 +ffffa00a +000000aa +ffffaa00 +00000aa0 +ffffa00a +00005678 +00003098 +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/simple.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/simple.reference_output new file mode 100644 index 0000000..7e9e9d5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/simple.reference_output
@@ -0,0 +1,8 @@ +00000001 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sll.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sll.reference_output new file mode 100644 index 0000000..a4349f2 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sll.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000001 +00000002 +00000080 +00004000 +80000000 +ffffffff +fffffffe +ffffff80 +ffffc000 +80000000 +21212121 +42424242 +90909080 +48484000 +80000000 +21212121 +42424242 +90909080 +48484000 +ffffffff +00000080 +00004000 +00000018 +00000080 +00004000 +80000000 +00000080 +00004000 +80000000 +00000080 +00004000 +80000000 +00000080 +00004000 +80000000 +00000080 +00004000 +80000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/slli.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/slli.reference_output new file mode 100644 index 0000000..19c6106 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/slli.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000001 +00000002 +00000080 +00004000 +80000000 +ffffffff +fffffffe +ffffff80 +ffffc000 +80000000 +21212121 +42424242 +90909080 +48484000 +80000000 +00000080 +00000080 +00004000 +80000000 +00000080 +00004000 +80000000 +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/slt.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/slt.reference_output new file mode 100644 index 0000000..964349a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/slt.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000000 +00000000 +00000001 +00000000 +00000000 +00000001 +00000001 +00000001 +00000000 +00000000 +00000001 +00000000 +00000000 +00000001 +00000000 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000000 +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/slti.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/slti.reference_output new file mode 100644 index 0000000..7b55b94 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/slti.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000000 +00000000 +00000001 +00000000 +00000000 +00000001 +00000001 +00000001 +00000000 +00000000 +00000001 +00000000 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sltiu.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sltiu.reference_output new file mode 100644 index 0000000..df66c1d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sltiu.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000000 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000001 +00000000 +00000000 +00000000 +00000001 +00000001 +00000000 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000001 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sltu.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sltu.reference_output new file mode 100644 index 0000000..a2d64f2 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sltu.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000000 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000001 +00000000 +00000000 +00000000 +00000001 +00000001 +00000000 +00000000 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000001 +00000000 +00000000 +00000000 +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sra.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sra.reference_output new file mode 100644 index 0000000..634716e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sra.reference_output
@@ -0,0 +1,52 @@ +00000001 +ffffffff +80000000 +c0000000 +ff000000 +fffe0000 +ffffffff +7fffffff +3fffffff +00ffffff +0001ffff +00000000 +81818181 +c0c0c0c0 +ff030303 +fffe0606 +ffffffff +81818181 +c0c0c0c0 +ff030303 +fffe0606 +ffffffff +ff000000 +fffe0000 +00000000 +ff000000 +fffe0000 +ffffffff +ff000000 +fffe0000 +ffffffff +ff000000 +fffe0000 +ffffffff +ff000000 +fffe0000 +ffffffff +ff000000 +fffe0000 +ffffffff +00000000 +00000020 +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/srai.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/srai.reference_output new file mode 100644 index 0000000..e989d7e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/srai.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00000000 +c0000000 +ff000000 +fffe0000 +ffffffff +7fffffff +3fffffff +00ffffff +0001ffff +00000000 +81818181 +c0c0c0c0 +ff030303 +fffe0606 +ffffffff +ff000000 +ff000000 +fffe0000 +ffffffff +ff000000 +fffe0000 +ffffffff +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/srl.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/srl.reference_output new file mode 100644 index 0000000..b7581dc --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/srl.reference_output
@@ -0,0 +1,60 @@ +00000001 +ffffffff +80000000 +40000000 +01000000 +00020000 +00000001 +ffffffff +7fffffff +01ffffff +0003ffff +00000001 +21212121 +10909090 +00424242 +00008484 +00000000 +21212121 +10909090 +00424242 +00008484 +00000000 +01000000 +00020000 +00000000 +01000000 +00020000 +00000001 +01000000 +00020000 +00000001 +01000000 +00020000 +00000001 +01000000 +00020000 +00000001 +01000000 +00020000 +00000001 +00000000 +00000020 +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/srli.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/srli.reference_output new file mode 100644 index 0000000..3c4eed7 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/srli.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +80000000 +40000000 +01000000 +00020000 +00000001 +ffffffff +7fffffff +01ffffff +0003ffff +00000001 +21212121 +10909090 +00424242 +00008484 +00000000 +01000000 +01000000 +00020000 +00000001 +01000000 +00020000 +00000001 +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sub.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sub.reference_output new file mode 100644 index 0000000..d582e30 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sub.reference_output
@@ -0,0 +1,52 @@ +00000001 +ffffffff +00000000 +00000000 +fffffffc +00008000 +80000000 +80008000 +ffff8001 +7fffffff +7fff8000 +7fff8001 +80007fff +00000001 +fffffffe +00000000 +00000002 +00000003 +00000000 +00000002 +00000003 +00000004 +00000002 +00000003 +00000004 +00000002 +00000003 +00000004 +00000002 +00000003 +00000004 +00000002 +00000003 +00000004 +0000000f +00000020 +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00000000 +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sw.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sw.reference_output new file mode 100644 index 0000000..045f195 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/sw.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +00aa00aa +aa00aa00 +0aa00aa0 +a00aa00a +00aa00aa +aa00aa00 +0aa00aa0 +a00aa00a +12345678 +58213098 +0000000c +0000000d +0000000e +0000000f +00000010 +00000011 +00000012 +00000013 +00000014 +00000015 +00000016 +00000017 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/xor.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/xor.reference_output new file mode 100644 index 0000000..319d872 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/xor.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +f00ff00f +ff00ff00 +0ff00ff0 +00ff00ff +f00ff00f +f00ff00f +00000000 +f00ff00f +ff00ff00 +0ff00ff0 +f00ff00f +ff00ff00 +0ff00ff0 +f00ff00f +ff00ff00 +0ff00ff0 +f00ff00f +ff00ff00 +0ff00ff0 +f00ff00f +ff00ff00 +0ff00ff0 +ff00ff00 +00ff00ff +00000000 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/xori.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/xori.reference_output new file mode 100644 index 0000000..a20983d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/references/xori.reference_output
@@ -0,0 +1,40 @@ +00000001 +ffffffff +ff00f00f +0ff00f00 +00ff0ff0 +f00ff0ff +ff00f00f +0ff00f00 +00ff0ff0 +f00ff0ff +0ff00f00 +00ff0ff0 +f00ff0ff +000000f0 +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/Makefrag new file mode 100644 index 0000000..1867ea5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/Makefrag
@@ -0,0 +1,27 @@ +#======================================================================= +# Makefrag for rv64ui tests +#----------------------------------------------------------------------- + +rv64ui_sc_tests = \ + add addi addiw addw \ + and andi \ + auipc \ + beq bge bgeu blt bltu bne \ + simple \ + fence_i \ + jal jalr \ + lb lbu lh lhu lw lwu ld \ + lui \ + or ori \ + sb sh sw sd \ + sll slli slliw sllw \ + slt slti sltiu sltu \ + sra srai sraiw sraw \ + srl srli srliw srlw \ + sub subw \ + xor xori \ + +rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests)) +rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests)) + +spike_tests += $(rv64ui_p_tests) $(rv64ui_v_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/add.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/add.S new file mode 100644 index 0000000..7c3e505 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/add.S
@@ -0,0 +1,88 @@ +# See LICENSE for license details. + +#***************************************************************************** +# add.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, add, 32, 32 ); + TEST_RR_ZEROSRC12( 37, add, 0 ); + TEST_RR_ZERODEST( 38, add, 16, 30 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/addi.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/addi.S new file mode 100644 index 0000000..2da570f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/addi.S
@@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# addi.S +#----------------------------------------------------------------------------- +# +# Test addi instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 ); + TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 ); + TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 ); + + TEST_IMM_OP( 5, addi, 0xfffffffffffff800, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 6, addi, 0xffffffff80000000, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 7, addi, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 8, addi, 0x00000000000007ff, 0x00000000, 0x7ff ); + TEST_IMM_OP( 9, addi, 0x000000007fffffff, 0x7fffffff, 0x000 ); + TEST_IMM_OP( 10, addi, 0x00000000800007fe, 0x7fffffff, 0x7ff ); + + TEST_IMM_OP( 11, addi, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 12, addi, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 13, addi, 0xffffffffffffffff, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 14, addi, 0x0000000000000000, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 15, addi, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff ); + + TEST_IMM_OP( 16, addi, 0x0000000080000000, 0x7fffffff, 0x001 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 ); + TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 ); + TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 ); + TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 ); + TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 ); + + TEST_IMM_ZEROSRC1( 24, addi, 32, 32 ); + TEST_IMM_ZERODEST( 25, addi, 33, 50 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 30, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/addiw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/addiw.S new file mode 100644 index 0000000..4e4a8ff --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/addiw.S
@@ -0,0 +1,71 @@ +# See LICENSE for license details. + +#***************************************************************************** +# addiw.S +#----------------------------------------------------------------------------- +# +# Test addiw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, addiw, 0x00000000, 0x00000000, 0x000 ); + TEST_IMM_OP( 3, addiw, 0x00000002, 0x00000001, 0x001 ); + TEST_IMM_OP( 4, addiw, 0x0000000a, 0x00000003, 0x007 ); + + TEST_IMM_OP( 5, addiw, 0xfffffffffffff800, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 6, addiw, 0xffffffff80000000, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 7, addiw, 0x000000007ffff800, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 8, addiw, 0x00000000000007ff, 0x00000000, 0x7ff ); + TEST_IMM_OP( 9, addiw, 0x000000007fffffff, 0x7fffffff, 0x000 ); + TEST_IMM_OP( 10, addiw, 0xffffffff800007fe, 0x7fffffff, 0x7ff ); + + TEST_IMM_OP( 11, addiw, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 12, addiw, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 13, addiw, 0xffffffffffffffff, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 14, addiw, 0x0000000000000000, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 15, addiw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff ); + + TEST_IMM_OP( 16, addiw, 0xffffffff80000000, 0x7fffffff, 0x001 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, addiw, 24, 13, 11 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, addiw, 24, 13, 11 ); + TEST_IMM_DEST_BYPASS( 19, 1, addiw, 23, 13, 10 ); + TEST_IMM_DEST_BYPASS( 20, 2, addiw, 22, 13, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, addiw, 24, 13, 11 ); + TEST_IMM_SRC1_BYPASS( 22, 1, addiw, 23, 13, 10 ); + TEST_IMM_SRC1_BYPASS( 23, 2, addiw, 22, 13, 9 ); + + TEST_IMM_ZEROSRC1( 24, addiw, 32, 32 ); + TEST_IMM_ZERODEST( 25, addiw, 33, 50 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/addw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/addw.S new file mode 100644 index 0000000..a4b9ea2 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/addw.S
@@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# addw.S +#----------------------------------------------------------------------------- +# +# Test addw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, addw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, addw, 0x00000002, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, addw, 0x0000000a, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, addw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, addw, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, addw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, addw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, addw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, addw, 0xffffffff80007ffe, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, addw, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, addw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, addw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, addw, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, addw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, addw, 0xffffffff80000000, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, addw, 24, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, addw, 25, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, addw, 26, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, addw, 24, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, addw, 25, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, addw, 26, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, addw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, addw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, addw, 26, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, addw, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, addw, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, addw, 26, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, addw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, addw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, addw, 26, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, addw, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, addw, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, addw, 26, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, addw, 15, 15 ); + TEST_RR_ZEROSRC2( 36, addw, 32, 32 ); + TEST_RR_ZEROSRC12( 37, addw, 0 ); + TEST_RR_ZERODEST( 38, addw, 16, 30 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/and.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/and.S new file mode 100644 index 0000000..9ede3bb --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/and.S
@@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# and.S +#----------------------------------------------------------------------------- +# +# Test and instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 ); + TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff ); + TEST_RR_ZEROSRC12( 26, and, 0 ); + TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/andi.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/andi.S new file mode 100644 index 0000000..282e7d5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/andi.S
@@ -0,0 +1,59 @@ +# See LICENSE for license details. + +#***************************************************************************** +# andi.S +#----------------------------------------------------------------------------- +# +# Test andi instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f ); + TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f ); + TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); + TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); + TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f ); + + TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); + TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); + TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f ); + + TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 ); + TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 20, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/auipc.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/auipc.S new file mode 100644 index 0000000..33102e3 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/auipc.S
@@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# auipc.S +#----------------------------------------------------------------------------- +# +# Test auipc instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + TEST_CASE(2, a0, 10000, \ + .align 3; \ + lla a0, 1f + 10000; \ + jal a1, 1f; \ + 1: sub a0, a0, a1; \ + ) + + TEST_CASE(3, a0, -10000, \ + .align 3; \ + lla a0, 1f - 10000; \ + jal a1, 1f; \ + 1: sub a0, a0, a1; \ + ) + + TEST_PASSFAIL + + RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 4, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/beq.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/beq.S new file mode 100644 index 0000000..72e8929 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/beq.S
@@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# beq.S +#----------------------------------------------------------------------------- +# +# Test beq instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, beq, 0, 0 ); + TEST_BR2_OP_TAKEN( 3, beq, 1, 1 ); + TEST_BR2_OP_TAKEN( 4, beq, -1, -1 ); + + TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 ); + TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 ); + TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 ); + TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + beq x0, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 30, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bge.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bge.S new file mode 100644 index 0000000..4dc53fe --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bge.S
@@ -0,0 +1,80 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bge.S +#----------------------------------------------------------------------------- +# +# Test bge instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bge, 0, 0 ); + TEST_BR2_OP_TAKEN( 3, bge, 1, 1 ); + TEST_BR2_OP_TAKEN( 4, bge, -1, -1 ); + TEST_BR2_OP_TAKEN( 5, bge, 1, 0 ); + TEST_BR2_OP_TAKEN( 6, bge, 1, -1 ); + TEST_BR2_OP_TAKEN( 7, bge, -1, -2 ); + + TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 ); + TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 ); + TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 ); + TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 ); + + TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 24, x1, 3, \ + li x1, 1; \ + bge x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 30, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bgeu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bgeu.S new file mode 100644 index 0000000..7fd8890 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bgeu.S
@@ -0,0 +1,80 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bgeu.S +#----------------------------------------------------------------------------- +# +# Test bgeu instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 ); + TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 ); + TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff ); + TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 ); + TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe ); + TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 ); + + TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 ); + TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff ); + TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff ); + TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); + + TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 24, x1, 3, \ + li x1, 1; \ + bgeu x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 30, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/blt.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/blt.S new file mode 100644 index 0000000..473066b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/blt.S
@@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# blt.S +#----------------------------------------------------------------------------- +# +# Test blt instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, blt, 0, 1 ); + TEST_BR2_OP_TAKEN( 3, blt, -1, 1 ); + TEST_BR2_OP_TAKEN( 4, blt, -2, -1 ); + + TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 ); + TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 ); + TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 ); + TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + blt x0, x1, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 30, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bltu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bltu.S new file mode 100644 index 0000000..9ceaf7a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bltu.S
@@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bltu.S +#----------------------------------------------------------------------------- +# +# Test bltu instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 ); + TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff ); + TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff ); + + TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 ); + TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe ); + TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 ); + TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + bltu x0, x1, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 30, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bne.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bne.S new file mode 100644 index 0000000..6e651e9 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/bne.S
@@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bne.S +#----------------------------------------------------------------------------- +# +# Test bne instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); + TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); + TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); + TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); + + TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); + TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); + TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + bne x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 30, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/fence_i.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/fence_i.S new file mode 100644 index 0000000..058bb80 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/fence_i.S
@@ -0,0 +1,57 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fence_i.S +#----------------------------------------------------------------------------- +# +# Test self-modifying code and the fence.i instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + +li a3, 111 +lh a0, insn +lh a1, insn+2 + +# test I$ hit +.align 6 +sh a0, 1f, t0 +sh a1, 1f+2, t0 +fence.i + +1: addi a3, a3, 222 +TEST_CASE( 2, a3, 444, nop ) + +# test prefetcher hit +li a4, 100 +1: addi a4, a4, -1 +bnez a4, 1b + +sh a0, 1f, t0 +sh a1, 1f+2, t0 +fence.i + +.align 6 +1: addi a3, a3, 555 +TEST_CASE( 3, a3, 777, nop ) + +TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +insn: + addi a3, a3, 333 +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 4, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/jal.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/jal.S new file mode 100644 index 0000000..eff5764 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/jal.S
@@ -0,0 +1,63 @@ +# See LICENSE for license details. + +#***************************************************************************** +# jal.S +#----------------------------------------------------------------------------- +# +# Test jal instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Test 2: Basic test + #------------------------------------------------------------- + +test_2: + li TESTNUM, 2 + li ra, 0 + + jal x4, target_2 +linkaddr_2: + nop + nop + + j fail + +target_2: + la x2, linkaddr_2 + bne x2, x4, fail + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 3, ra, 3, \ + li ra, 1; \ + jal x0, 1f; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ +1: addi ra, ra, 1; \ + addi ra, ra, 1; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 10, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/jalr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/jalr.S new file mode 100644 index 0000000..3a3c971 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/jalr.S
@@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# jalr.S +#----------------------------------------------------------------------------- +# +# Test jalr instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Test 2: Basic test + #------------------------------------------------------------- + +test_2: + li TESTNUM, 2 + li t0, 0 + la t1, target_2 + + jalr t0, t1, 0 +linkaddr_2: + j fail + +target_2: + la t1, linkaddr_2 + bne t0, t1, fail + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_JALR_SRC1_BYPASS( 4, 0, jalr ); + TEST_JALR_SRC1_BYPASS( 5, 1, jalr ); + TEST_JALR_SRC1_BYPASS( 6, 2, jalr ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + .option push + .align 2 + .option norvc + TEST_CASE( 7, t0, 4, \ + li t0, 1; \ + la t1, 1f; \ + jr t1, -4; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ +1: addi t0, t0, 1; \ + addi t0, t0, 1; \ + ) + .option pop + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 10, 4, -1 +RV_COMPLIANCE_DATA_END + + + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lb.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lb.S new file mode 100644 index 0000000..0a4492d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lb.S
@@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lb.S +#----------------------------------------------------------------------------- +# +# Test lb instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lb, 0xffffffffffffffff, 0, tdat ); + TEST_LD_OP( 3, lb, 0x0000000000000000, 1, tdat ); + TEST_LD_OP( 4, lb, 0xfffffffffffffff0, 2, tdat ); + TEST_LD_OP( 5, lb, 0x000000000000000f, 3, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lb, 0xffffffffffffffff, -3, tdat4 ); + TEST_LD_OP( 7, lb, 0x0000000000000000, -2, tdat4 ); + TEST_LD_OP( 8, lb, 0xfffffffffffffff0, -1, tdat4 ); + TEST_LD_OP( 9, lb, 0x000000000000000f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0xffffffffffffffff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lb x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x0000000000000000, \ + la x1, tdat; \ + addi x1, x1, -6; \ + lb x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lb, 0x000000000000000f, 1, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lb, 0x0000000000000000, 1, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x000000000000000f, 1, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x0000000000000000, 1, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lb x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lb x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + +.data +tdat: +tdat1: .byte 0xff +tdat2: .byte 0x00 +tdat3: .byte 0xf0 +tdat4: .byte 0x0f + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lbu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lbu.S new file mode 100644 index 0000000..4077c8e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lbu.S
@@ -0,0 +1,95 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lbu.S +#----------------------------------------------------------------------------- +# +# Test lbu instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0, tdat ); + TEST_LD_OP( 3, lbu, 0x0000000000000000, 1, tdat ); + TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2, tdat ); + TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 ); + TEST_LD_OP( 7, lbu, 0x0000000000000000, -2, tdat4 ); + TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1, tdat4 ); + TEST_LD_OP( 9, lbu, 0x000000000000000f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00000000000000ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lbu x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x0000000000000000, \ + la x1, tdat; \ + addi x1, x1, -6; \ + lbu x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lbu x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lbu x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +tdat: +tdat1: .byte 0xff +tdat2: .byte 0x00 +tdat3: .byte 0xf0 +tdat4: .byte 0x0f +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/ld.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/ld.S new file mode 100644 index 0000000..b5060e8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/ld.S
@@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ld.S +#----------------------------------------------------------------------------- +# +# Test ld instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, ld, 0x00ff00ff00ff00ff, 0, tdat ); + TEST_LD_OP( 3, ld, 0xff00ff00ff00ff00, 8, tdat ); + TEST_LD_OP( 4, ld, 0x0ff00ff00ff00ff0, 16, tdat ); + TEST_LD_OP( 5, ld, 0xf00ff00ff00ff00f, 24, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, ld, 0x00ff00ff00ff00ff, -24, tdat4 ); + TEST_LD_OP( 7, ld, 0xff00ff00ff00ff00, -16, tdat4 ); + TEST_LD_OP( 8, ld, 0x0ff00ff00ff00ff0, -8, tdat4 ); + TEST_LD_OP( 9, ld, 0xf00ff00ff00ff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00ff00ff00ff00ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + ld x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xff00ff00ff00ff00, \ + la x1, tdat; \ + addi x1, x1, -3; \ + ld x5, 11(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + ld x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + ld x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .dword 0x00ff00ff00ff00ff +tdat2: .dword 0xff00ff00ff00ff00 +tdat3: .dword 0x0ff00ff00ff00ff0 +tdat4: .dword 0xf00ff00ff00ff00f + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lh.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lh.S new file mode 100644 index 0000000..eda6b77 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lh.S
@@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lh.S +#----------------------------------------------------------------------------- +# +# Test lh instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lh, 0x00000000000000ff, 0, tdat ); + TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2, tdat ); + TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4, tdat ); + TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lh, 0x00000000000000ff, -6, tdat4 ); + TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4, tdat4 ); + TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2, tdat4 ); + TEST_LD_OP( 9, lh, 0xfffffffffffff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00000000000000ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lh x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xffffffffffffff00, \ + la x1, tdat; \ + addi x1, x1, -5; \ + lh x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lh x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lh x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +tdat: +tdat1: .half 0x00ff +tdat2: .half 0xff00 +tdat3: .half 0x0ff0 +tdat4: .half 0xf00f + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lhu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lhu.S new file mode 100644 index 0000000..209de8f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lhu.S
@@ -0,0 +1,98 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lhu.S +#----------------------------------------------------------------------------- +# +# Test lhu instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0, tdat ); + TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2, tdat ); + TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4, tdat ); + TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6, tdat4 ); + TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4, tdat4 ); + TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2, tdat4 ); + TEST_LD_OP( 9, lhu, 0x000000000000f00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00000000000000ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lhu x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x000000000000ff00, \ + la x1, tdat; \ + addi x1, x1, -5; \ + lhu x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lhu x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lhu x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +tdat: +tdat1: .half 0x00ff +tdat2: .half 0xff00 +tdat3: .half 0x0ff0 +tdat4: .half 0xf00f + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END + + + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lui.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lui.S new file mode 100644 index 0000000..6f42fd1 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lui.S
@@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lui.S +#----------------------------------------------------------------------------- +# +# Test lui instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 ); + TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1); + TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20); + TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20); + + TEST_CASE( 6, x0, 0, lui x0, 0x80000 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 10, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lw.S new file mode 100644 index 0000000..a4b93fd --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lw.S
@@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lw.S +#----------------------------------------------------------------------------- +# +# Test lw instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0, tdat ); + TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4, tdat ); + TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8, tdat ); + TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 ); + TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8, tdat4 ); + TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4, tdat4 ); + TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x0000000000ff00ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lw x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xffffffffff00ff00, \ + la x1, tdat; \ + addi x1, x1, -3; \ + lw x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lw x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lw x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +tdat: +tdat1: .word 0x00ff00ff +tdat2: .word 0xff00ff00 +tdat3: .word 0x0ff00ff0 +tdat4: .word 0xf00ff00f + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lwu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lwu.S new file mode 100644 index 0000000..825e52b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/lwu.S
@@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lwu.S +#----------------------------------------------------------------------------- +# +# Test lwu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lwu, 0x0000000000ff00ff, 0, tdat ); + TEST_LD_OP( 3, lwu, 0x00000000ff00ff00, 4, tdat ); + TEST_LD_OP( 4, lwu, 0x000000000ff00ff0, 8, tdat ); + TEST_LD_OP( 5, lwu, 0x00000000f00ff00f, 12, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lwu, 0x0000000000ff00ff, -12, tdat4 ); + TEST_LD_OP( 7, lwu, 0x00000000ff00ff00, -8, tdat4 ); + TEST_LD_OP( 8, lwu, 0x000000000ff00ff0, -4, tdat4 ); + TEST_LD_OP( 9, lwu, 0x00000000f00ff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x0000000000ff00ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lwu x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x00000000ff00ff00, \ + la x1, tdat; \ + addi x1, x1, -3; \ + lwu x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lwu, 0x00000000f00ff00f, 4, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lwu, 0x00000000ff00ff00, 4, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0x00000000f00ff00f, 4, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0x00000000ff00ff00, 4, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lwu x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lwu x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .word 0x00ff00ff +tdat2: .word 0xff00ff00 +tdat3: .word 0x0ff00ff0 +tdat4: .word 0xf00ff00f + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/or.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/or.S new file mode 100644 index 0000000..4cacf92 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/or.S
@@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# or.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 ); + TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff ); + TEST_RR_ZEROSRC12( 26, or, 0 ); + TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/ori.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/ori.S new file mode 100644 index 0000000..184233a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/ori.S
@@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ori.S +#----------------------------------------------------------------------------- +# +# Test ori instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f ); + TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); + TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); + TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f ); + TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 ); + TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sb.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sb.S new file mode 100644 index 0000000..ffc1acd --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sb.S
@@ -0,0 +1,98 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sb.S +#----------------------------------------------------------------------------- +# +# Test sb instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat ); + TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat ); + TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat ); + TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, lb, sb, 0xffffffffffffffaa, -3, tdat8 ); + TEST_ST_OP( 7, lb, sb, 0x0000000000000000, -2, tdat8 ); + TEST_ST_OP( 8, lb, sb, 0xffffffffffffffa0, -1, tdat8 ); + TEST_ST_OP( 9, lb, sb, 0x000000000000000a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x78, \ + la x1, tdat9; \ + li x2, 0x12345678; \ + addi x4, x1, -32; \ + sb x2, 32(x4); \ + lb x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xffffffffffffff98, \ + la x1, tdat9; \ + li x2, 0x00003098; \ + addi x1, x1, -6; \ + sb x2, 7(x1); \ + la x4, tdat10; \ + lb x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffffffffffdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffffffffffcd, 1, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffffffffffcc, 2, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffffffffffbc, 3, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffffffffffbb, 4, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffffffffffab, 5, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat ); + + li a0, 0xef + la a1, tdat + sb a0, 3(a1) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +tdat: +tdat1: .byte 0xef +tdat2: .byte 0xef +tdat3: .byte 0xef +tdat4: .byte 0xef +tdat5: .byte 0xef +tdat6: .byte 0xef +tdat7: .byte 0xef +tdat8: .byte 0xef +tdat9: .byte 0xef +tdat10: .byte 0xef + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sd.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sd.S new file mode 100644 index 0000000..00c0245 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sd.S
@@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sd.S +#----------------------------------------------------------------------------- +# +# Test sd instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, ld, sd, 0x00aa00aa00aa00aa, 0, tdat ); + TEST_ST_OP( 3, ld, sd, 0xaa00aa00aa00aa00, 8, tdat ); + TEST_ST_OP( 4, ld, sd, 0x0aa00aa00aa00aa0, 16, tdat ); + TEST_ST_OP( 5, ld, sd, 0xa00aa00aa00aa00a, 24, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, ld, sd, 0x00aa00aa00aa00aa, -24, tdat8 ); + TEST_ST_OP( 7, ld, sd, 0xaa00aa00aa00aa00, -16, tdat8 ); + TEST_ST_OP( 8, ld, sd, 0x0aa00aa00aa00aa0, -8, tdat8 ); + TEST_ST_OP( 9, ld, sd, 0xa00aa00aa00aa00a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x1234567812345678, \ + la x1, tdat9; \ + li x2, 0x1234567812345678; \ + addi x4, x1, -32; \ + sd x2, 32(x4); \ + ld x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x5821309858213098, \ + la x1, tdat9; \ + li x2, 0x5821309858213098; \ + addi x1, x1, -3; \ + sd x2, 11(x1); \ + la x4, tdat10; \ + ld x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, ld, sd, 0xabbccdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, ld, sd, 0xaabbccd, 8, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, ld, sd, 0xdaabbcc, 16, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, ld, sd, 0xddaabbc, 24, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, ld, sd, 0xcddaabb, 32, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, ld, sd, 0xccddaab, 40, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, ld, sd, 0x00112233, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, ld, sd, 0x30011223, 8, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, ld, sd, 0x33001122, 16, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, ld, sd, 0x23300112, 24, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, ld, sd, 0x22330011, 32, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, ld, sd, 0x12233001, 40, tdat ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .dword 0xdeadbeefdeadbeef +tdat2: .dword 0xdeadbeefdeadbeef +tdat3: .dword 0xdeadbeefdeadbeef +tdat4: .dword 0xdeadbeefdeadbeef +tdat5: .dword 0xdeadbeefdeadbeef +tdat6: .dword 0xdeadbeefdeadbeef +tdat7: .dword 0xdeadbeefdeadbeef +tdat8: .dword 0xdeadbeefdeadbeef +tdat9: .dword 0xdeadbeefdeadbeef +tdat10: .dword 0xdeadbeefdeadbeef + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sh.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sh.S new file mode 100644 index 0000000..927a1dd --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sh.S
@@ -0,0 +1,99 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh.S +#----------------------------------------------------------------------------- +# +# Test sh instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat ); + TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat ); + TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat ); + TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 ); + TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 ); + TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 ); + TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x5678, \ + la x1, tdat9; \ + li x2, 0x12345678; \ + addi x4, x1, -32; \ + sh x2, 32(x4); \ + lh x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x3098, \ + la x1, tdat9; \ + li x2, 0x00003098; \ + addi x1, x1, -5; \ + sh x2, 7(x1); \ + la x4, tdat10; \ + lh x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat ); + + li a0, 0xbeef + la a1, tdat + sh a0, 6(a1) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +tdat: +tdat1: .half 0xbeef +tdat2: .half 0xbeef +tdat3: .half 0xbeef +tdat4: .half 0xbeef +tdat5: .half 0xbeef +tdat6: .half 0xbeef +tdat7: .half 0xbeef +tdat8: .half 0xbeef +tdat9: .half 0xbeef +tdat10: .half 0xbeef + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/simple.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/simple.S new file mode 100644 index 0000000..d4f8a9b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/simple.S
@@ -0,0 +1,33 @@ +# See LICENSE for license details. + +#***************************************************************************** +# simple.S +#----------------------------------------------------------------------------- +# +# This is the most basic self checking test. If your simulator does not +# pass thiss then there is little chance that it will pass any of the +# more complicated self checking tests. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + +RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + + + .data + +RV_COMPLIANCE_DATA_BEGIN + +test_res: + .fill 8, 4, -1 + +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sll.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sll.S new file mode 100644 index 0000000..1466f47 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sll.S
@@ -0,0 +1,99 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sll.S +#----------------------------------------------------------------------------- +# +# Test sll instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sll, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, sll, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, sll, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, sll, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six bits + + TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, sll, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sll, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sll, 0 ); + TEST_RR_ZERODEST( 43, sll, 1024, 2048 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + +.data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slli.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slli.S new file mode 100644 index 0000000..c7e0706 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slli.S
@@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slli.S +#----------------------------------------------------------------------------- +# +# Test slli instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slli, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, slli, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, slli, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, slli, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, slli, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, slli, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, slli, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 ); + +#if __riscv_xlen == 64 + TEST_IMM_OP( 50, slli, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_IMM_OP( 51, slli, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_IMM_OP( 52, slli, 0x0909080000000000, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, slli, 0, 31 ); + TEST_IMM_ZERODEST( 25, slli, 33, 20 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slliw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slliw.S new file mode 100644 index 0000000..432493a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slliw.S
@@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slliw.S +#----------------------------------------------------------------------------- +# +# Test slliw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slliw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, slliw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, slliw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, slliw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, slliw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, slliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, slliw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, slliw, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, slliw, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, slliw, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, slliw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, slliw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, slliw, 0xffffffff90909080, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_IMM_OP( 44, slliw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_IMM_OP( 45, slliw, 0x0000000023456780, 0xffffffff12345678, 4 ); + TEST_IMM_OP( 46, slliw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_IMM_OP( 47, slliw, 0xffffffff93456780, 0x0000000099345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slliw, 0x00000080, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, slliw, 0, 31 ); + TEST_IMM_ZERODEST( 25, slliw, 31, 28 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sllw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sllw.S new file mode 100644 index 0000000..fb28343 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sllw.S
@@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sllw.S +#----------------------------------------------------------------------------- +# +# Test sllw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sllw, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, sllw, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, sllw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, sllw, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, sllw, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, sllw, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, sllw, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, sllw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, sllw, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, sllw, 0xffffffff90909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, sllw, 0x0000000048484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, sllw, 0xffffffff80000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, sllw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, sllw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, sllw, 0xffffffff90909080, 0x0000000021212121, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, sllw, 0x0000000048484000, 0x0000000021212121, 0xffffffffffffffee ); + TEST_RR_OP( 21, sllw, 0xffffffff80000000, 0x0000000021212121, 0xffffffffffffffff ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, sllw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, sllw, 0x0000000023456780, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, sllw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, sllw, 0xffffffff93456780, 0x0000000099345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sllw, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sllw, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sllw, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, sllw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sllw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sllw, 0 ); + TEST_RR_ZERODEST( 43, sllw, 1024, 2048 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slt.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slt.S new file mode 100644 index 0000000..2abc3c8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slt.S
@@ -0,0 +1,87 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slt.S +#----------------------------------------------------------------------------- +# +# Test slt instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, slt, 0, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, slt, 0, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, slt, 1, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, slt, 0, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, slt, 0, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, slt, 1, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, slt, 1, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, slt, 1, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, slt, 0, -1 ); + TEST_RR_ZEROSRC2( 36, slt, 1, -1 ); + TEST_RR_ZEROSRC12( 37, slt, 0 ); + TEST_RR_ZERODEST( 38, slt, 16, 30 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slti.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slti.S new file mode 100644 index 0000000..99a9b22 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/slti.S
@@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slti.S +#----------------------------------------------------------------------------- +# +# Test slti instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slti, 0, 0x0000000000000000, 0x000 ); + TEST_IMM_OP( 3, slti, 0, 0x0000000000000001, 0x001 ); + TEST_IMM_OP( 4, slti, 1, 0x0000000000000003, 0x007 ); + TEST_IMM_OP( 5, slti, 0, 0x0000000000000007, 0x003 ); + + TEST_IMM_OP( 6, slti, 0, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 7, slti, 1, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 8, slti, 1, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 9, slti, 1, 0x0000000000000000, 0x7ff ); + TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 ); + TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff ); + + TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 ); + TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 ); + TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 ); + + TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff ); + TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sltiu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sltiu.S new file mode 100644 index 0000000..864835d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sltiu.S
@@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sltiu.S +#----------------------------------------------------------------------------- +# +# Test sltiu instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, sltiu, 0, 0x0000000000000000, 0x000 ); + TEST_IMM_OP( 3, sltiu, 0, 0x0000000000000001, 0x001 ); + TEST_IMM_OP( 4, sltiu, 1, 0x0000000000000003, 0x007 ); + TEST_IMM_OP( 5, sltiu, 0, 0x0000000000000007, 0x003 ); + + TEST_IMM_OP( 6, sltiu, 1, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 7, sltiu, 0, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 8, sltiu, 1, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 9, sltiu, 1, 0x0000000000000000, 0x7ff ); + TEST_IMM_OP( 10, sltiu, 0, 0x000000007fffffff, 0x000 ); + TEST_IMM_OP( 11, sltiu, 0, 0x000000007fffffff, 0x7ff ); + + TEST_IMM_OP( 12, sltiu, 0, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 13, sltiu, 1, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 14, sltiu, 1, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 15, sltiu, 0, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 16, sltiu, 0, 0xffffffffffffffff, 0xfff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, sltiu, 0, 15, 10 ); + TEST_IMM_DEST_BYPASS( 19, 1, sltiu, 1, 10, 16 ); + TEST_IMM_DEST_BYPASS( 20, 2, sltiu, 0, 16, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, sltiu, 1, 11, 15 ); + TEST_IMM_SRC1_BYPASS( 22, 1, sltiu, 0, 17, 8 ); + TEST_IMM_SRC1_BYPASS( 23, 2, sltiu, 1, 12, 14 ); + + TEST_IMM_ZEROSRC1( 24, sltiu, 1, 0xfff ); + TEST_IMM_ZERODEST( 25, sltiu, 0x00ff00ff, 0xfff ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sltu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sltu.S new file mode 100644 index 0000000..c080ba9 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sltu.S
@@ -0,0 +1,86 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sltu.S +#----------------------------------------------------------------------------- +# +# Test sltu instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sltu, 0, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sltu, 0, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sltu, 1, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, sltu, 0, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, sltu, 1, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, sltu, 0, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, sltu, 1, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, sltu, 1, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, sltu, 1, -1 ); + TEST_RR_ZEROSRC2( 36, sltu, 0, -1 ); + TEST_RR_ZEROSRC12( 37, sltu, 0 ); + TEST_RR_ZERODEST( 38, sltu, 16, 30 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sra.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sra.S new file mode 100644 index 0000000..c7792c2 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sra.S
@@ -0,0 +1,93 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sra.S +#----------------------------------------------------------------------------- +# +# Test sra instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sra, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_RR_OP( 3, sra, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_RR_OP( 4, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_OP( 5, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_OP( 6, sra, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_RR_OP( 7, sra, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_RR_OP( 8, sra, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_RR_OP( 9, sra, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce ); + TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, sra, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sra, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sra, 0 ); + TEST_RR_ZERODEST( 43, sra, 1024, 2048 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 50, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srai.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srai.S new file mode 100644 index 0000000..d387b6c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srai.S
@@ -0,0 +1,71 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srai.S +#----------------------------------------------------------------------------- +# +# Test srai instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, srai, 0xffffff8000000000, 0xffffff8000000000, 0 ); + TEST_IMM_OP( 3, srai, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_IMM_OP( 4, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_OP( 5, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_OP( 6, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_OP( 7, srai, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_IMM_OP( 8, srai, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_IMM_OP( 9, srai, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, srai, 0, 4 ); + TEST_IMM_ZERODEST( 25, srai, 33, 10 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sraiw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sraiw.S new file mode 100644 index 0000000..03cadd8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sraiw.S
@@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sraiw.S +#----------------------------------------------------------------------------- +# +# Test sraiw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, sraiw, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_IMM_OP( 3, sraiw, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_IMM_OP( 4, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_OP( 5, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_OP( 6, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_OP( 7, sraiw, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_IMM_OP( 8, sraiw, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_IMM_OP( 9, sraiw, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_IMM_OP( 10, sraiw, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_IMM_OP( 11, sraiw, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_IMM_OP( 12, sraiw, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_IMM_OP( 13, sraiw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_IMM_OP( 14, sraiw, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_IMM_OP( 15, sraiw, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_IMM_OP( 16, sraiw, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_IMM_OP( 44, sraiw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_IMM_OP( 45, sraiw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_IMM_OP( 46, sraiw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_IMM_OP( 47, sraiw, 0xfffffffff9234567, 0x0000000092345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, sraiw, 0, 31 ); + TEST_IMM_ZERODEST( 25, sraiw, 31, 28 ); + + TEST_IMM_OP( 26, sraiw, 0x0000000000000000, 0x00e0000000000000, 28) + TEST_IMM_OP( 27, sraiw, 0xffffffffff000000, 0x00000000f0000000, 4) + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sraw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sraw.S new file mode 100644 index 0000000..aa5ea77 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sraw.S
@@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sraw.S +#----------------------------------------------------------------------------- +# +# Test sraw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sraw, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_RR_OP( 3, sraw, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_RR_OP( 4, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_OP( 5, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_OP( 6, sraw, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_RR_OP( 7, sraw, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_RR_OP( 8, sraw, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_RR_OP( 9, sraw, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_RR_OP( 10, sraw, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_RR_OP( 11, sraw, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_RR_OP( 12, sraw, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_RR_OP( 13, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_RR_OP( 14, sraw, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_RR_OP( 15, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_RR_OP( 16, sraw, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, sraw, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, sraw, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffee ); + TEST_RR_OP( 21, sraw, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, sraw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, sraw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, sraw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, sraw, 0xfffffffff9234567, 0x0000000092345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sraw, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, sraw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sraw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sraw, 0 ); + TEST_RR_ZERODEST( 43, sraw, 1024, 2048 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srl.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srl.S new file mode 100644 index 0000000..240d95d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srl.S
@@ -0,0 +1,95 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srl.S +#----------------------------------------------------------------------------- +# +# Test srl instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + +#define TEST_SRL(n, v, a) \ + TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) + + TEST_SRL( 2, 0xffffffff80000000, 0 ); + TEST_SRL( 3, 0xffffffff80000000, 1 ); + TEST_SRL( 4, 0xffffffff80000000, 7 ); + TEST_SRL( 5, 0xffffffff80000000, 14 ); + TEST_SRL( 6, 0xffffffff80000001, 31 ); + + TEST_SRL( 7, 0xffffffffffffffff, 0 ); + TEST_SRL( 8, 0xffffffffffffffff, 1 ); + TEST_SRL( 9, 0xffffffffffffffff, 7 ); + TEST_SRL( 10, 0xffffffffffffffff, 14 ); + TEST_SRL( 11, 0xffffffffffffffff, 31 ); + + TEST_SRL( 12, 0x0000000021212121, 0 ); + TEST_SRL( 13, 0x0000000021212121, 1 ); + TEST_SRL( 14, 0x0000000021212121, 7 ); + TEST_SRL( 15, 0x0000000021212121, 14 ); + TEST_SRL( 16, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce ); + TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, srl, 0, 15 ); + TEST_RR_ZEROSRC2( 41, srl, 32, 32 ); + TEST_RR_ZEROSRC12( 42, srl, 0 ); + TEST_RR_ZERODEST( 43, srl, 1024, 2048 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 60, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srli.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srli.S new file mode 100644 index 0000000..6924d3f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srli.S
@@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srli.S +#----------------------------------------------------------------------------- +# +# Test srli instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + +#define TEST_SRL(n, v, a) \ + TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) + + TEST_SRL( 2, 0xffffffff80000000, 0 ); + TEST_SRL( 3, 0xffffffff80000000, 1 ); + TEST_SRL( 4, 0xffffffff80000000, 7 ); + TEST_SRL( 5, 0xffffffff80000000, 14 ); + TEST_SRL( 6, 0xffffffff80000001, 31 ); + + TEST_SRL( 7, 0xffffffffffffffff, 0 ); + TEST_SRL( 8, 0xffffffffffffffff, 1 ); + TEST_SRL( 9, 0xffffffffffffffff, 7 ); + TEST_SRL( 10, 0xffffffffffffffff, 14 ); + TEST_SRL( 11, 0xffffffffffffffff, 31 ); + + TEST_SRL( 12, 0x0000000021212121, 0 ); + TEST_SRL( 13, 0x0000000021212121, 1 ); + TEST_SRL( 14, 0x0000000021212121, 7 ); + TEST_SRL( 15, 0x0000000021212121, 14 ); + TEST_SRL( 16, 0x0000000021212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, srli, 0, 4 ); + TEST_IMM_ZERODEST( 25, srli, 33, 10 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srliw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srliw.S new file mode 100644 index 0000000..7e65e96 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srliw.S
@@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srliw.S +#----------------------------------------------------------------------------- +# +# Test srliw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, srliw, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_IMM_OP( 3, srliw, 0x0000000040000000, 0xffffffff80000000, 1 ); + TEST_IMM_OP( 4, srliw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_IMM_OP( 5, srliw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_IMM_OP( 6, srliw, 0x0000000000000001, 0xffffffff80000001, 31 ); + + TEST_IMM_OP( 7, srliw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, srliw, 0x000000007fffffff, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, srliw, 0x0000000001ffffff, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, srliw, 0x000000000003ffff, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, srliw, 0x0000000000000001, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, srliw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, srliw, 0x0000000010909090, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, srliw, 0x0000000000424242, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, srliw, 0x0000000000008484, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, srliw, 0x0000000000000000, 0x0000000021212121, 31 ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_IMM_OP( 44, srliw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_IMM_OP( 45, srliw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_IMM_OP( 46, srliw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_IMM_OP( 47, srliw, 0x0000000009234567, 0x0000000092345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, srliw, 0x0000000001000000, 0xffffffff80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, srliw, 0, 31 ); + TEST_IMM_ZERODEST( 25, srliw, 31, 28 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srlw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srlw.S new file mode 100644 index 0000000..23b708e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/srlw.S
@@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srlw.S +#----------------------------------------------------------------------------- +# +# Test srlw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, srlw, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_RR_OP( 3, srlw, 0x0000000040000000, 0xffffffff80000000, 1 ); + TEST_RR_OP( 4, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_OP( 5, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_OP( 6, srlw, 0x0000000000000001, 0xffffffff80000001, 31 ); + + TEST_RR_OP( 7, srlw, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, srlw, 0x000000007fffffff, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, srlw, 0x0000000001ffffff, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, srlw, 0x000000000003ffff, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, srlw, 0x0000000000000001, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, srlw, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, srlw, 0x0000000010909090, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, srlw, 0x0000000000424242, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, srlw, 0x0000000000008484, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, srlw, 0x0000000000000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, srlw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 ); + TEST_RR_OP( 18, srlw, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffe1 ); + TEST_RR_OP( 19, srlw, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffe7 ); + TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee ); + TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, srlw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, srlw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, srlw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, srlw, 0x0000000009234567, 0x0000000092345678, 4 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, srlw, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, srlw, 0, 15 ); + TEST_RR_ZEROSRC2( 41, srlw, 32, 32 ); + TEST_RR_ZEROSRC12( 42, srlw, 0 ); + TEST_RR_ZERODEST( 43, srlw, 1024, 2048 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sub.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sub.S new file mode 100644 index 0000000..5645d53 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sub.S
@@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sub.S +#----------------------------------------------------------------------------- +# +# Test sub instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 ); + + TEST_RR_OP( 5, sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 7, sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 ); + TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 ); + TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 ); + TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 ); + TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 ); + + TEST_RR_ZEROSRC1( 34, sub, 15, -15 ); + TEST_RR_ZEROSRC2( 35, sub, 32, 32 ); + TEST_RR_ZEROSRC12( 36, sub, 0 ); + TEST_RR_ZERODEST( 37, sub, 16, 30 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 50, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/subw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/subw.S new file mode 100644 index 0000000..3527290 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/subw.S
@@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# subw.S +#----------------------------------------------------------------------------- +# +# Test subw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, subw, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, subw, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, subw, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 ); + + TEST_RR_OP( 5, subw, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, subw, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 7, subw, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, subw, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, subw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, subw, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, subw, 0x000000007fff8001, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, subw, 0xffffffff80007fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, subw, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, subw, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, subw, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 16, subw, 2, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 17, subw, 3, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 18, subw, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 19, 0, subw, 2, 13, 11 ); + TEST_RR_DEST_BYPASS( 20, 1, subw, 3, 14, 11 ); + TEST_RR_DEST_BYPASS( 21, 2, subw, 4, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 22, 0, 0, subw, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 23, 0, 1, subw, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 2, subw, 4, 15, 11 ); + TEST_RR_SRC12_BYPASS( 25, 1, 0, subw, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 1, subw, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 27, 2, 0, subw, 4, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 28, 0, 0, subw, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 29, 0, 1, subw, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 2, subw, 4, 15, 11 ); + TEST_RR_SRC21_BYPASS( 31, 1, 0, subw, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 1, subw, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 33, 2, 0, subw, 4, 15, 11 ); + + TEST_RR_ZEROSRC1( 34, subw, 15, -15 ); + TEST_RR_ZEROSRC2( 35, subw, 32, 32 ); + TEST_RR_ZEROSRC12( 36, subw, 0 ); + TEST_RR_ZERODEST( 37, subw, 16, 30 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sw.S new file mode 100644 index 0000000..b775d90 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/sw.S
@@ -0,0 +1,97 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sw.S +#----------------------------------------------------------------------------- +# +# Test sw instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0, tdat ); + TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4, tdat ); + TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8, tdat ); + TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 ); + TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8, tdat8 ); + TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4, tdat8 ); + TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x12345678, \ + la x1, tdat9; \ + li x2, 0x12345678; \ + addi x4, x1, -32; \ + sw x2, 32(x4); \ + lw x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x58213098, \ + la x1, tdat9; \ + li x2, 0x58213098; \ + addi x1, x1, -3; \ + sw x2, 7(x1); \ + la x4, tdat10; \ + lw x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data + +tdat: +tdat1: .word 0xdeadbeef +tdat2: .word 0xdeadbeef +tdat3: .word 0xdeadbeef +tdat4: .word 0xdeadbeef +tdat5: .word 0xdeadbeef +tdat6: .word 0xdeadbeef +tdat7: .word 0xdeadbeef +tdat8: .word 0xdeadbeef +tdat9: .word 0xdeadbeef +tdat10: .word 0xdeadbeef + +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/xor.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/xor.S new file mode 100644 index 0000000..1cd7a22 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/xor.S
@@ -0,0 +1,71 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xor.S +#----------------------------------------------------------------------------- +# +# Test xor instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 ); + TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff ); + TEST_RR_ZEROSRC12( 26, xor, 0 ); + TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/xori.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/xori.S new file mode 100644 index 0000000..5d39be8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/rv64ui/xori.S
@@ -0,0 +1,59 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xori.S +#----------------------------------------------------------------------------- +# +# Test xori instruction. +# + +#include "riscv_test.h" +#include "compliance_test.h" +#include "compliance_io.h" +#include "aw_test_macros.h" + + +RVTEST_RV64U +RV_COMPLIANCE_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f ); + TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); + TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); + TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f ); + TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 ); + TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f ); + + TEST_PASSFAIL + +RV_COMPLIANCE_CODE_END + + .data +RV_COMPLIANCE_DATA_BEGIN +test_res: + .fill 40, 4, -1 +RV_COMPLIANCE_DATA_END + +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/Makefrag.spike b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/Makefrag.spike new file mode 100644 index 0000000..7903b15 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/Makefrag.spike
@@ -0,0 +1,27 @@ +#======================================================================= +# Makefrag for rv32ui tests +#----------------------------------------------------------------------- + +rv32ui_sc_tests = \ + simple \ + add addi \ + and andi \ + auipc \ + beq bge bgeu blt bltu bne \ + fence_i \ + jal jalr \ + lb lbu lh lhu lw \ + lui \ + or ori \ + sb sh sw \ + sll slli \ + slt slti sltiu sltu \ + sra srai \ + srl srli \ + sub \ + xor xori \ + +rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests)) +rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests)) + +spike32_tests += $(rv32ui_p_tests) $(rv32ui_v_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/add.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/add.S new file mode 100644 index 0000000..3ab883d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/add.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/add.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/addi.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/addi.S new file mode 100644 index 0000000..fa80a68 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/addi.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/addi.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/and.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/and.S new file mode 100644 index 0000000..4ee105b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/and.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/and.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/andi.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/andi.S new file mode 100644 index 0000000..e6b1529 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/andi.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/andi.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/auipc.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/auipc.S new file mode 100644 index 0000000..0827f7d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/auipc.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/auipc.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/beq.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/beq.S new file mode 100644 index 0000000..7c3996d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/beq.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/beq.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bge.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bge.S new file mode 100644 index 0000000..d47c304 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bge.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/bge.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bgeu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bgeu.S new file mode 100644 index 0000000..560ec45 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bgeu.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/bgeu.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/blt.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/blt.S new file mode 100644 index 0000000..72017dd --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/blt.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/blt.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bltu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bltu.S new file mode 100644 index 0000000..80f7468 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bltu.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/bltu.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bne.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bne.S new file mode 100644 index 0000000..ddb7d9f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/bne.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/bne.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/fence_i.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/fence_i.S new file mode 100644 index 0000000..cd1dbc3 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/fence_i.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/fence_i.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/jal.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/jal.S new file mode 100644 index 0000000..93f407b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/jal.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/jal.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/jalr.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/jalr.S new file mode 100644 index 0000000..59f6425 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/jalr.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/jalr.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lb.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lb.S new file mode 100644 index 0000000..6cf4d44 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lb.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lb.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lbu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lbu.S new file mode 100644 index 0000000..a479a0f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lbu.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lbu.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lh.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lh.S new file mode 100644 index 0000000..f1b2390 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lh.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lh.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lhu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lhu.S new file mode 100644 index 0000000..775765f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lhu.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lhu.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lui.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lui.S new file mode 100644 index 0000000..a127d61 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lui.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lui.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lw.S new file mode 100644 index 0000000..3b747d8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/lw.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/lw.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/or.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/or.S new file mode 100644 index 0000000..1cf5674 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/or.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/or.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/ori.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/ori.S new file mode 100644 index 0000000..3399649 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/ori.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/ori.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sb.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sb.S new file mode 100644 index 0000000..b2f99ac --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sb.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sb.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sh.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sh.S new file mode 100644 index 0000000..eb5a72d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sh.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sh.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/simple.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/simple.S new file mode 100644 index 0000000..20e5546 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/simple.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/simple.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sll.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sll.S new file mode 100644 index 0000000..237df9e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sll.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sll.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/slli.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/slli.S new file mode 100644 index 0000000..5f950e1 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/slli.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/slli.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/slt.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/slt.S new file mode 100644 index 0000000..64a3dd9 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/slt.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/slt.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/slti.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/slti.S new file mode 100644 index 0000000..7484505 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/slti.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/slti.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sltiu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sltiu.S new file mode 100644 index 0000000..4185f9b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sltiu.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sltiu.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sltu.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sltu.S new file mode 100644 index 0000000..bd92b26 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sltu.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sltu.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sra.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sra.S new file mode 100644 index 0000000..08abe19 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sra.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sra.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/srai.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/srai.S new file mode 100644 index 0000000..b62a880 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/srai.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/srai.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/srl.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/srl.S new file mode 100644 index 0000000..c0ac841 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/srl.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/srl.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/srli.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/srli.S new file mode 100644 index 0000000..ef0203b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/srli.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/srli.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sub.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sub.S new file mode 100644 index 0000000..330f478 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sub.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sub.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sw.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sw.S new file mode 100644 index 0000000..3098133 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/sw.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/sw.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/xor.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/xor.S new file mode 100644 index 0000000..a9c1e41 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/xor.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/xor.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/xori.S b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/xori.S new file mode 100644 index 0000000..9e71152 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/deprecated/rv32ui/src/xori.S
@@ -0,0 +1,7 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64U +#define RVTEST_RV64U RVTEST_RV32U + +#include "../rv64ui/xori.S"
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/.gitignore b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/.gitignore new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/.gitignore
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/Makefile new file mode 100644 index 0000000..9da7ab8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv32i -mabi=ilp32)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/Makefrag new file mode 100644 index 0000000..5500ac5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/Makefrag
@@ -0,0 +1,40 @@ +# RISC-V Compliance Test RV32I Makefrag +# +# Copyright (c) 2017, Codasip Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Codasip Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Description: Makefrag for RV32Zicsr compliance tests + +rv32Zicsr_sc_tests = \ + I-CSRRW-01 \ + I-CSRRWI-01 \ + I-CSRRS-01 \ + I-CSRRSI-01 \ + I-CSRRC-01 \ + I-CSRRCI-01 \ + +rv32Zicsr_tests = $(addsuffix .elf, $(rv32Zicsr_sc_tests)) + +target_tests += $(rv32Zicsr_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRC-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRC-01.reference_output similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRC-01.reference_output rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRC-01.reference_output
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRCI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRCI-01.reference_output similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRCI-01.reference_output rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRCI-01.reference_output
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRS-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRS-01.reference_output similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRS-01.reference_output rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRS-01.reference_output
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRSI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRSI-01.reference_output similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRSI-01.reference_output rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRSI-01.reference_output
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRW-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRW-01.reference_output similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRW-01.reference_output rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRW-01.reference_output
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRWI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRWI-01.reference_output similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-CSRRWI-01.reference_output rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/references/I-CSRRWI-01.reference_output
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRC-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRC-01.S rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRC-01.S
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRCI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRCI-01.S rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRCI-01.S
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRS-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRS-01.S rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRS-01.S
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRSI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRSI-01.S rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRSI-01.S
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRW-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRW-01.S rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRW-01.S
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRWI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-CSRRWI-01.S rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32Zicsr/src/I-CSRRWI-01.S
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/Makefile index cd2f39a..9da7ab8 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/Makefile +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/Makefile
@@ -8,6 +8,9 @@ work_dir_isa := $(work_dir)/$(RISCV_ISA) include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif default: all @@ -26,33 +29,28 @@ #------------------------------------------------------------ # Build and run assembly tests -%.out32: %.elf - $(RUN_TARGET) +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) define compile_template -$$($(1)_tests): %.elf: $(src_dir)/%.S - @mkdir -p $(work_dir_isa)/$$(@D) - $(COMPILE_TARGET) -$(1)_tests += $$($(1)_p_tests) +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) -.PHONY: $(1) - -tests += $$($(1)_tests) +.PRECIOUS: $(work_dir_isa)/%.elf endef -$(eval $(call compile_template,rv32i,-march=rv32i -mabi=ilp32)) +$(eval $(call compile_template,-march=rv32i -mabi=ilp32)) -tests32_out = $(patsubst %.elf,%.out32,$(target32_tests)) +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) -run: $(tests32_out) - -#------------------------------------------------------------ -# Default - -all: $(tests_dump) +run: $(target_log) #------------------------------------------------------------ # Clean up
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/Makefrag index 9e5991b..36b8068 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/Makefrag +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/Makefrag
@@ -70,24 +70,17 @@ I-SRA-01 \ I-SLT-01 \ I-SLTU-01 \ - I-CSRRW-01 \ - I-CSRRWI-01 \ I-NOP-01 \ - I-CSRRS-01 \ - I-CSRRSI-01 \ - I-CSRRC-01 \ - I-CSRRCI-01 \ - I-IO \ - - # These tests are currently removed since the underlying core in opentitan - # does not yet support FENCE.I instructions + I-ECALL-01 \ + I-EBREAK-01 \ + I-IO-01 \ + + # These tests are broken due to flaws in riscv-compliance rather than + # Ibex/OpenTitan (see https://github.com/lowRISC/ibex/issues/100) #I-MISALIGN_JMP-01 #I-MISALIGN_LDST-01 - #I-FENCE.I-01 - #I-ECALL-01 - #I-EBREAK-01 rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) -target32_tests += $(rv32i_tests) +target_tests += $(rv32i_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/coverage/report.txt b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/coverage/report.txt new file mode 100644 index 0000000..482c079 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/coverage/report.txt
@@ -0,0 +1,3938 @@ +This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv + +COVERGROUP COVERAGE: +---------------------------------------------------------------------------------------------------------- +Covergroup Metric Goal Status + +---------------------------------------------------------------------------------------------------------- + TYPE /riscv_instr_pkg/riscv_instr_cover_group/add_cg + 100.00% 100 Covered + covered/total bins: 110 110 + missing/total bins: 0 110 + % Hit: 100.00% 100 + Coverpoint add_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 6 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 7 1 Covered + bin auto[TP] 2 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 6 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 6 1 Covered + bin auto[A4] 2 1 Covered + bin auto[A5] 2 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 6 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 6 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 2 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 4 1 Covered + bin auto[T4] 2 1 Covered + bin auto[T5] 2 1 Covered + bin auto[T6] 2 1 Covered + Coverpoint add_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 8 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 2 1 Covered + bin auto[T0] 3 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 2 1 Covered + bin auto[S0] 2 1 Covered + bin auto[S1] 2 1 Covered + bin auto[A0] 2 1 Covered + bin auto[A1] 2 1 Covered + bin auto[A2] 2 1 Covered + bin auto[A3] 2 1 Covered + bin auto[A4] 2 1 Covered + bin auto[A5] 2 1 Covered + bin auto[A6] 3 1 Covered + bin auto[A7] 2 1 Covered + bin auto[S2] 2 1 Covered + bin auto[S3] 2 1 Covered + bin auto[S4] 2 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 2 1 Covered + bin auto[S7] 2 1 Covered + bin auto[S8] 2 1 Covered + bin auto[S9] 3 1 Covered + bin auto[S10] 2 1 Covered + bin auto[S11] 10 1 Covered + bin auto[T3] 2 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint add_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 4 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 2 1 Covered + bin auto[TP] 3 1 Covered + bin auto[T0] 4 1 Covered + bin auto[T1] 3 1 Covered + bin auto[T2] 2 1 Covered + bin auto[S0] 2 1 Covered + bin auto[S1] 2 1 Covered + bin auto[A0] 2 1 Covered + bin auto[A1] 2 1 Covered + bin auto[A2] 2 1 Covered + bin auto[A3] 2 1 Covered + bin auto[A4] 3 1 Covered + bin auto[A5] 3 1 Covered + bin auto[A6] 3 1 Covered + bin auto[A7] 2 1 Covered + bin auto[S2] 2 1 Covered + bin auto[S3] 2 1 Covered + bin auto[S4] 2 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 2 1 Covered + bin auto[S7] 2 1 Covered + bin auto[S8] 2 1 Covered + bin auto[S9] 3 1 Covered + bin auto[S10] 3 1 Covered + bin auto[S11] 3 1 Covered + bin auto[T3] 2 1 Covered + bin auto[T4] 2 1 Covered + bin auto[T5] 2 1 Covered + bin auto[T6] 2 1 Covered + Coverpoint add_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 53 1 Covered + bin auto[NEGATIVE] 23 1 Covered + Coverpoint add_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 52 1 Covered + bin auto[NEGATIVE] 24 1 Covered + Coverpoint add_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 43 1 Covered + bin auto[NEGATIVE] 33 1 Covered + Cross add_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 8 8 + missing/total bins: 0 8 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE],auto[POSITIVE]> + 29 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE],auto[POSITIVE]> + 5 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE],auto[POSITIVE]> + 5 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE],auto[POSITIVE]> + 4 1 Covered + bin <auto[POSITIVE],auto[POSITIVE],auto[NEGATIVE]> + 7 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE],auto[NEGATIVE]> + 11 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE],auto[NEGATIVE]> + 12 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE],auto[NEGATIVE]> + 3 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/sub_cg + 98.21% 100 Uncovered + covered/total bins: 109 110 + missing/total bins: 1 110 + % Hit: 99.09% 100 + Coverpoint sub_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 3 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 2 1 Covered + bin auto[TP] 2 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 2 1 Covered + bin auto[S0] 2 1 Covered + bin auto[S1] 3 1 Covered + bin auto[A0] 2 1 Covered + bin auto[A1] 2 1 Covered + bin auto[A2] 2 1 Covered + bin auto[A3] 2 1 Covered + bin auto[A4] 2 1 Covered + bin auto[A5] 2 1 Covered + bin auto[A6] 2 1 Covered + bin auto[A7] 2 1 Covered + bin auto[S2] 2 1 Covered + bin auto[S3] 2 1 Covered + bin auto[S4] 2 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 2 1 Covered + bin auto[S7] 2 1 Covered + bin auto[S8] 2 1 Covered + bin auto[S9] 2 1 Covered + bin auto[S10] 2 1 Covered + bin auto[S11] 2 1 Covered + bin auto[T3] 2 1 Covered + bin auto[T4] 2 1 Covered + bin auto[T5] 2 1 Covered + bin auto[T6] 2 1 Covered + Coverpoint sub_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 21 1 Covered + bin auto[SP] 8 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 6 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 3 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sub_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 3 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 2 1 Covered + bin auto[TP] 2 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 2 1 Covered + bin auto[S0] 2 1 Covered + bin auto[S1] 3 1 Covered + bin auto[A0] 2 1 Covered + bin auto[A1] 2 1 Covered + bin auto[A2] 2 1 Covered + bin auto[A3] 2 1 Covered + bin auto[A4] 2 1 Covered + bin auto[A5] 2 1 Covered + bin auto[A6] 2 1 Covered + bin auto[A7] 2 1 Covered + bin auto[S2] 2 1 Covered + bin auto[S3] 2 1 Covered + bin auto[S4] 2 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 2 1 Covered + bin auto[S7] 2 1 Covered + bin auto[S8] 2 1 Covered + bin auto[S9] 2 1 Covered + bin auto[S10] 2 1 Covered + bin auto[S11] 2 1 Covered + bin auto[T3] 2 1 Covered + bin auto[T4] 2 1 Covered + bin auto[T5] 2 1 Covered + bin auto[T6] 2 1 Covered + Coverpoint sub_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 26 1 Covered + bin auto[NEGATIVE] 40 1 Covered + Coverpoint sub_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 45 1 Covered + Coverpoint sub_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 47 1 Covered + bin auto[NEGATIVE] 19 1 Covered + Cross sub_cg::cp_sign_cross 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin <auto[POSITIVE],auto[POSITIVE],auto[POSITIVE]> + 7 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE],auto[POSITIVE]> + 1 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE],auto[POSITIVE]> + 9 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE],auto[POSITIVE]> + 30 1 Covered + bin <auto[POSITIVE],auto[POSITIVE],auto[NEGATIVE]> + 4 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE],auto[NEGATIVE]> + 9 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE],auto[NEGATIVE]> + 6 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE],auto[NEGATIVE]> + 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/addi_cg + 100.00% 100 Covered + covered/total bins: 78 78 + missing/total bins: 0 78 + % Hit: 100.00% 100 + Coverpoint addi_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1237 1 Covered + bin auto[RA] 556 1 Covered + bin auto[SP] 178 1 Covered + bin auto[GP] 50 1 Covered + bin auto[TP] 23 1 Covered + bin auto[T0] 376 1 Covered + bin auto[T1] 26 1 Covered + bin auto[T2] 36 1 Covered + bin auto[S0] 48 1 Covered + bin auto[S1] 38 1 Covered + bin auto[A0] 86 1 Covered + bin auto[A1] 26 1 Covered + bin auto[A2] 11 1 Covered + bin auto[A3] 23 1 Covered + bin auto[A4] 10 1 Covered + bin auto[A5] 10 1 Covered + bin auto[A6] 13 1 Covered + bin auto[A7] 12 1 Covered + bin auto[S2] 10 1 Covered + bin auto[S3] 35 1 Covered + bin auto[S4] 13 1 Covered + bin auto[S5] 35 1 Covered + bin auto[S6] 27 1 Covered + bin auto[S7] 23 1 Covered + bin auto[S8] 48 1 Covered + bin auto[S9] 39 1 Covered + bin auto[S10] 39 1 Covered + bin auto[S11] 29 1 Covered + bin auto[T3] 10 1 Covered + bin auto[T4] 23 1 Covered + bin auto[T5] 34 1 Covered + bin auto[T6] 15 1 Covered + Coverpoint addi_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 9 1 Covered + bin auto[RA] 549 1 Covered + bin auto[SP] 208 1 Covered + bin auto[GP] 170 1 Covered + bin auto[TP] 46 1 Covered + bin auto[T0] 494 1 Covered + bin auto[T1] 77 1 Covered + bin auto[T2] 73 1 Covered + bin auto[S0] 60 1 Covered + bin auto[S1] 60 1 Covered + bin auto[A0] 156 1 Covered + bin auto[A1] 60 1 Covered + bin auto[A2] 47 1 Covered + bin auto[A3] 59 1 Covered + bin auto[A4] 60 1 Covered + bin auto[A5] 60 1 Covered + bin auto[A6] 63 1 Covered + bin auto[A7] 61 1 Covered + bin auto[S2] 59 1 Covered + bin auto[S3] 60 1 Covered + bin auto[S4] 35 1 Covered + bin auto[S5] 57 1 Covered + bin auto[S6] 60 1 Covered + bin auto[S7] 59 1 Covered + bin auto[S8] 60 1 Covered + bin auto[S9] 61 1 Covered + bin auto[S10] 61 1 Covered + bin auto[S11] 63 1 Covered + bin auto[T3] 46 1 Covered + bin auto[T4] 59 1 Covered + bin auto[T5] 83 1 Covered + bin auto[T6] 64 1 Covered + Coverpoint addi_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 1995 1 Covered + bin auto[NEGATIVE] 1144 1 Covered + Coverpoint addi_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 1692 1 Covered + bin auto[NEGATIVE] 1447 1 Covered + Coverpoint addi_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 1531 1 Covered + bin auto[NEGATIVE] 1608 1 Covered + Cross addi_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 8 8 + missing/total bins: 0 8 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE],auto[POSITIVE]> + 1148 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE],auto[POSITIVE]> + 1 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE],auto[POSITIVE]> + 456 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE],auto[POSITIVE]> + 87 1 Covered + bin <auto[POSITIVE],auto[POSITIVE],auto[NEGATIVE]> + 2 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE],auto[NEGATIVE]> + 380 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE],auto[NEGATIVE]> + 389 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE],auto[NEGATIVE]> + 676 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/lui_cg + 100.00% 100 Covered + covered/total bins: 34 34 + missing/total bins: 0 34 + % Hit: 100.00% 100 + Coverpoint lui_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 5 1 Covered + bin auto[RA] 274 1 Covered + bin auto[SP] 46 1 Covered + bin auto[GP] 29 1 Covered + bin auto[TP] 32 1 Covered + bin auto[T0] 34 1 Covered + bin auto[T1] 20 1 Covered + bin auto[T2] 18 1 Covered + bin auto[S0] 43 1 Covered + bin auto[S1] 32 1 Covered + bin auto[A0] 80 1 Covered + bin auto[A1] 20 1 Covered + bin auto[A2] 18 1 Covered + bin auto[A3] 18 1 Covered + bin auto[A4] 4 1 Covered + bin auto[A5] 4 1 Covered + bin auto[A6] 4 1 Covered + bin auto[A7] 5 1 Covered + bin auto[S2] 5 1 Covered + bin auto[S3] 29 1 Covered + bin auto[S4] 32 1 Covered + bin auto[S5] 32 1 Covered + bin auto[S6] 21 1 Covered + bin auto[S7] 18 1 Covered + bin auto[S8] 42 1 Covered + bin auto[S9] 32 1 Covered + bin auto[S10] 32 1 Covered + bin auto[S11] 23 1 Covered + bin auto[T3] 18 1 Covered + bin auto[T4] 17 1 Covered + bin auto[T5] 4 1 Covered + bin auto[T6] 4 1 Covered + Coverpoint lui_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 723 1 Covered + bin auto[NEGATIVE] 272 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/auipc_cg + 100.00% 100 Covered + covered/total bins: 34 34 + missing/total bins: 0 34 + % Hit: 100.00% 100 + Coverpoint auipc_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 196 1 Covered + bin auto[SP] 106 1 Covered + bin auto[GP] 22 1 Covered + bin auto[TP] 17 1 Covered + bin auto[T0] 331 1 Covered + bin auto[T1] 7 1 Covered + bin auto[T2] 19 1 Covered + bin auto[S0] 8 1 Covered + bin auto[S1] 8 1 Covered + bin auto[A0] 7 1 Covered + bin auto[A1] 7 1 Covered + bin auto[A2] 7 1 Covered + bin auto[A3] 7 1 Covered + bin auto[A4] 7 1 Covered + bin auto[A5] 7 1 Covered + bin auto[A6] 10 1 Covered + bin auto[A7] 8 1 Covered + bin auto[S2] 7 1 Covered + bin auto[S3] 7 1 Covered + bin auto[S4] 7 1 Covered + bin auto[S5] 7 1 Covered + bin auto[S6] 7 1 Covered + bin auto[S7] 7 1 Covered + bin auto[S8] 7 1 Covered + bin auto[S9] 8 1 Covered + bin auto[S10] 8 1 Covered + bin auto[S11] 7 1 Covered + bin auto[T3] 7 1 Covered + bin auto[T4] 7 1 Covered + bin auto[T5] 7 1 Covered + bin auto[T6] 12 1 Covered + Coverpoint auipc_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 54 1 Covered + bin auto[NEGATIVE] 827 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/sra_cg + 85.71% 100 Uncovered + covered/total bins: 103 106 + missing/total bins: 3 106 + % Hit: 97.16% 100 + Coverpoint sra_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sra_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sra_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sra_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint sra_cg::cp_rs2_sign 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[POSITIVE] 33 1 Covered + bin auto[NEGATIVE] 0 1 ZERO + Coverpoint sra_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 22 1 Covered + bin auto[NEGATIVE] 11 1 Covered + Cross sra_cg::cp_sign_cross 50.00% 100 Uncovered + covered/total bins: 2 4 + missing/total bins: 2 4 + % Hit: 50.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 21 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 12 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 0 1 ZERO + bin <auto[NEGATIVE],auto[NEGATIVE]> 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/sll_cg + 85.71% 100 Uncovered + covered/total bins: 103 106 + missing/total bins: 3 106 + % Hit: 97.16% 100 + Coverpoint sll_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sll_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sll_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sll_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint sll_cg::cp_rs2_sign 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[POSITIVE] 33 1 Covered + bin auto[NEGATIVE] 0 1 ZERO + Coverpoint sll_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 22 1 Covered + bin auto[NEGATIVE] 11 1 Covered + Cross sll_cg::cp_sign_cross 50.00% 100 Uncovered + covered/total bins: 2 4 + missing/total bins: 2 4 + % Hit: 50.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 21 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 12 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 0 1 ZERO + bin <auto[NEGATIVE],auto[NEGATIVE]> 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/srl_cg + 85.71% 100 Uncovered + covered/total bins: 103 106 + missing/total bins: 3 106 + % Hit: 97.16% 100 + Coverpoint srl_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint srl_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 2 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint srl_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint srl_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint srl_cg::cp_rs2_sign 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[POSITIVE] 33 1 Covered + bin auto[NEGATIVE] 0 1 ZERO + Coverpoint srl_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 30 1 Covered + bin auto[NEGATIVE] 3 1 Covered + Cross srl_cg::cp_sign_cross 50.00% 100 Uncovered + covered/total bins: 2 4 + missing/total bins: 2 4 + % Hit: 50.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 21 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 12 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 0 1 ZERO + bin <auto[NEGATIVE],auto[NEGATIVE]> 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/srai_cg + 100.00% 100 Covered + covered/total bins: 68 68 + missing/total bins: 0 68 + % Hit: 100.00% 100 + Coverpoint srai_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint srai_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint srai_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint srai_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 22 1 Covered + bin auto[NEGATIVE] 11 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/slli_cg + 100.00% 100 Covered + covered/total bins: 68 68 + missing/total bins: 0 68 + % Hit: 100.00% 100 + Coverpoint slli_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 2 1 Covered + bin auto[TP] 2 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 2 1 Covered + bin auto[S0] 2 1 Covered + bin auto[S1] 2 1 Covered + bin auto[A0] 50 1 Covered + bin auto[A1] 2 1 Covered + bin auto[A2] 2 1 Covered + bin auto[A3] 2 1 Covered + bin auto[A4] 2 1 Covered + bin auto[A5] 2 1 Covered + bin auto[A6] 2 1 Covered + bin auto[A7] 2 1 Covered + bin auto[S2] 2 1 Covered + bin auto[S3] 2 1 Covered + bin auto[S4] 2 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 2 1 Covered + bin auto[S7] 2 1 Covered + bin auto[S8] 2 1 Covered + bin auto[S9] 2 1 Covered + bin auto[S10] 2 1 Covered + bin auto[S11] 2 1 Covered + bin auto[T3] 2 1 Covered + bin auto[T4] 2 1 Covered + bin auto[T5] 2 1 Covered + bin auto[T6] 2 1 Covered + Coverpoint slli_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 2 1 Covered + bin auto[TP] 2 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 2 1 Covered + bin auto[S0] 2 1 Covered + bin auto[S1] 2 1 Covered + bin auto[A0] 50 1 Covered + bin auto[A1] 2 1 Covered + bin auto[A2] 2 1 Covered + bin auto[A3] 2 1 Covered + bin auto[A4] 2 1 Covered + bin auto[A5] 2 1 Covered + bin auto[A6] 2 1 Covered + bin auto[A7] 2 1 Covered + bin auto[S2] 2 1 Covered + bin auto[S3] 2 1 Covered + bin auto[S4] 2 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 2 1 Covered + bin auto[S7] 2 1 Covered + bin auto[S8] 2 1 Covered + bin auto[S9] 2 1 Covered + bin auto[S10] 2 1 Covered + bin auto[S11] 2 1 Covered + bin auto[T3] 2 1 Covered + bin auto[T4] 2 1 Covered + bin auto[T5] 2 1 Covered + bin auto[T6] 2 1 Covered + Coverpoint slli_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 100 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint slli_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 22 1 Covered + bin auto[NEGATIVE] 90 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/srli_cg + 100.00% 100 Covered + covered/total bins: 68 68 + missing/total bins: 0 68 + % Hit: 100.00% 100 + Coverpoint srli_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint srli_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint srli_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint srli_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 30 1 Covered + bin auto[NEGATIVE] 3 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/xor_cg + 100.00% 100 Covered + covered/total bins: 110 110 + missing/total bins: 0 110 + % Hit: 100.00% 100 + Coverpoint xor_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint xor_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 2 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint xor_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint xor_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint xor_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 20 1 Covered + bin auto[NEGATIVE] 13 1 Covered + Coverpoint xor_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 14 1 Covered + bin auto[NEGATIVE] 19 1 Covered + Coverpoint xor_cg::cp_logical 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin auto[IDENTICAL] 4 1 Covered + bin auto[OPPOSITE] 4 1 Covered + bin auto[SIMILAR] 4 1 Covered + bin auto[DIFFERENT] 21 1 Covered + Cross xor_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 11 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/or_cg + 100.00% 100 Covered + covered/total bins: 110 110 + missing/total bins: 0 110 + % Hit: 100.00% 100 + Coverpoint or_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint or_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint or_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint or_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint or_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint or_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 12 1 Covered + bin auto[NEGATIVE] 21 1 Covered + Coverpoint or_cg::cp_logical 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin auto[IDENTICAL] 4 1 Covered + bin auto[OPPOSITE] 4 1 Covered + bin auto[SIMILAR] 4 1 Covered + bin auto[DIFFERENT] 21 1 Covered + Cross or_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 11 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/and_cg + 100.00% 100 Covered + covered/total bins: 110 110 + missing/total bins: 0 110 + % Hit: 100.00% 100 + Coverpoint and_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint and_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 2 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint and_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint and_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint and_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint and_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 31 1 Covered + bin auto[NEGATIVE] 2 1 Covered + Coverpoint and_cg::cp_logical 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin auto[IDENTICAL] 4 1 Covered + bin auto[OPPOSITE] 4 1 Covered + bin auto[SIMILAR] 4 1 Covered + bin auto[DIFFERENT] 21 1 Covered + Cross and_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 11 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/xori_cg + 100.00% 100 Covered + covered/total bins: 78 78 + missing/total bins: 0 78 + % Hit: 100.00% 100 + Coverpoint xori_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint xori_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint xori_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint xori_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 10 1 Covered + bin auto[NEGATIVE] 23 1 Covered + Coverpoint xori_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 12 1 Covered + bin auto[NEGATIVE] 21 1 Covered + Coverpoint xori_cg::cp_logical 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin auto[IDENTICAL] 4 1 Covered + bin auto[OPPOSITE] 4 1 Covered + bin auto[SIMILAR] 2 1 Covered + bin auto[DIFFERENT] 23 1 Covered + Cross xori_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 4 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 8 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 17 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/ori_cg + 100.00% 100 Covered + covered/total bins: 78 78 + missing/total bins: 0 78 + % Hit: 100.00% 100 + Coverpoint ori_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint ori_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint ori_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint ori_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 6 1 Covered + bin auto[NEGATIVE] 27 1 Covered + Coverpoint ori_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 13 1 Covered + bin auto[NEGATIVE] 20 1 Covered + Coverpoint ori_cg::cp_logical 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin auto[IDENTICAL] 4 1 Covered + bin auto[OPPOSITE] 4 1 Covered + bin auto[SIMILAR] 3 1 Covered + bin auto[DIFFERENT] 22 1 Covered + Cross ori_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 5 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 8 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 16 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/andi_cg + 100.00% 100 Covered + covered/total bins: 78 78 + missing/total bins: 0 78 + % Hit: 100.00% 100 + Coverpoint andi_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 24 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint andi_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 24 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint andi_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 35 1 Covered + Coverpoint andi_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 52 1 Covered + bin auto[NEGATIVE] 4 1 Covered + Coverpoint andi_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 36 1 Covered + bin auto[NEGATIVE] 20 1 Covered + Coverpoint andi_cg::cp_logical 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin auto[IDENTICAL] 4 1 Covered + bin auto[OPPOSITE] 4 1 Covered + bin auto[SIMILAR] 12 1 Covered + bin auto[DIFFERENT] 36 1 Covered + Cross andi_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 5 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 31 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 16 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/slt_cg + 100.00% 100 Covered + covered/total bins: 106 106 + missing/total bins: 0 106 + % Hit: 100.00% 100 + Coverpoint slt_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint slt_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint slt_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint slt_cg::cp_result 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 20 1 Covered + bin auto[1] 13 1 Covered + Coverpoint slt_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint slt_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Cross slt_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 11 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/sltu_cg + 100.00% 100 Covered + covered/total bins: 106 106 + missing/total bins: 0 106 + % Hit: 100.00% 100 + Coverpoint sltu_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sltu_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sltu_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint sltu_cg::cp_result 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 19 1 Covered + bin auto[1] 14 1 Covered + Coverpoint sltu_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sltu_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Cross sltu_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 11 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/slti_cg + 100.00% 100 Covered + covered/total bins: 74 74 + missing/total bins: 0 74 + % Hit: 100.00% 100 + Coverpoint slti_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint slti_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint slti_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint slti_cg::cp_result 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 26 1 Covered + bin auto[1] 7 1 Covered + Coverpoint slti_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 13 1 Covered + bin auto[NEGATIVE] 20 1 Covered + Cross slti_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 5 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 8 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 16 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/sltiu_cg + 100.00% 100 Covered + covered/total bins: 74 74 + missing/total bins: 0 74 + % Hit: 100.00% 100 + Coverpoint sltiu_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sltiu_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sltiu_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint sltiu_cg::cp_result 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 17 1 Covered + bin auto[1] 16 1 Covered + Coverpoint sltiu_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 13 1 Covered + bin auto[NEGATIVE] 20 1 Covered + Cross sltiu_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 5 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 8 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 16 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/beq_cg + 100.00% 100 Covered + covered/total bins: 76 76 + missing/total bins: 0 76 + % Hit: 100.00% 100 + Coverpoint beq_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 52 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint beq_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 49 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 3 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint beq_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 71 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint beq_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 71 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint beq_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 77 1 Covered + bin auto[NEGATIVE] 6 1 Covered + Coverpoint beq_cg::cp_branch_hit 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 29 1 Covered + bin auto[1] 54 1 Covered + Cross beq_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 61 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/bne_cg + 100.00% 100 Covered + covered/total bins: 76 76 + missing/total bins: 0 76 + % Hit: 100.00% 100 + Coverpoint bne_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 4 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 49 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint bne_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 49 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 3 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint bne_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 71 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint bne_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 71 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint bne_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 77 1 Covered + bin auto[NEGATIVE] 6 1 Covered + Coverpoint bne_cg::cp_branch_hit 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 30 1 Covered + bin auto[1] 53 1 Covered + Cross bne_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 61 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/blt_cg + 100.00% 100 Covered + covered/total bins: 76 76 + missing/total bins: 0 76 + % Hit: 100.00% 100 + Coverpoint blt_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 2 1 Covered + bin auto[TP] 2 1 Covered + bin auto[T0] 4 1 Covered + bin auto[T1] 3 1 Covered + bin auto[T2] 2 1 Covered + bin auto[S0] 2 1 Covered + bin auto[S1] 2 1 Covered + bin auto[A0] 50 1 Covered + bin auto[A1] 2 1 Covered + bin auto[A2] 2 1 Covered + bin auto[A3] 2 1 Covered + bin auto[A4] 2 1 Covered + bin auto[A5] 2 1 Covered + bin auto[A6] 2 1 Covered + bin auto[A7] 2 1 Covered + bin auto[S2] 2 1 Covered + bin auto[S3] 2 1 Covered + bin auto[S4] 2 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 2 1 Covered + bin auto[S7] 2 1 Covered + bin auto[S8] 2 1 Covered + bin auto[S9] 2 1 Covered + bin auto[S10] 2 1 Covered + bin auto[S11] 2 1 Covered + bin auto[T3] 2 1 Covered + bin auto[T4] 2 1 Covered + bin auto[T5] 2 1 Covered + bin auto[T6] 2 1 Covered + Coverpoint blt_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 80 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 3 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint blt_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 23 1 Covered + bin auto[NEGATIVE] 91 1 Covered + Coverpoint blt_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 102 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint blt_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 108 1 Covered + bin auto[NEGATIVE] 6 1 Covered + Coverpoint blt_cg::cp_branch_hit 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 19 1 Covered + bin auto[1] 95 1 Covered + Cross blt_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 13 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 89 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/bge_cg + 100.00% 100 Covered + covered/total bins: 76 76 + missing/total bins: 0 76 + % Hit: 100.00% 100 + Coverpoint bge_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 3 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint bge_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 3 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint bge_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 23 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint bge_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 23 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint bge_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 29 1 Covered + bin auto[NEGATIVE] 6 1 Covered + Coverpoint bge_cg::cp_branch_hit 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 19 1 Covered + bin auto[1] 16 1 Covered + Cross bge_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 13 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/bltu_cg + 100.00% 100 Covered + covered/total bins: 76 76 + missing/total bins: 0 76 + % Hit: 100.00% 100 + Coverpoint bltu_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 3 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint bltu_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 3 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint bltu_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 23 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint bltu_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 23 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint bltu_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 29 1 Covered + bin auto[NEGATIVE] 6 1 Covered + Coverpoint bltu_cg::cp_branch_hit 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 19 1 Covered + bin auto[1] 16 1 Covered + Cross bltu_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 13 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/bgeu_cg + 100.00% 100 Covered + covered/total bins: 76 76 + missing/total bins: 0 76 + % Hit: 100.00% 100 + Coverpoint bgeu_cg::cp_rs1 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 3 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint bgeu_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 3 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint bgeu_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 23 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint bgeu_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 23 1 Covered + bin auto[NEGATIVE] 12 1 Covered + Coverpoint bgeu_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 29 1 Covered + bin auto[NEGATIVE] 6 1 Covered + Coverpoint bgeu_cg::cp_branch_hit 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 19 1 Covered + bin auto[1] 16 1 Covered + Cross bgeu_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 13 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 10 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 10 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/lb_cg + 98.95% 100 Uncovered + covered/total bins: 65 66 + missing/total bins: 1 66 + % Hit: 98.48% 100 + Coverpoint lb_cg::cp_rs1 96.87% 100 Uncovered + covered/total bins: 31 32 + missing/total bins: 1 32 + % Hit: 96.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 3 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lb_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lb_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 21 1 Covered + bin auto[NEGATIVE] 12 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/lh_cg + 99.21% 100 Uncovered + covered/total bins: 67 68 + missing/total bins: 1 68 + % Hit: 98.52% 100 + Coverpoint lh_cg::cp_rs1 96.87% 100 Uncovered + covered/total bins: 31 32 + missing/total bins: 1 32 + % Hit: 96.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 3 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 5 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lh_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 5 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lh_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 29 1 Covered + bin auto[NEGATIVE] 8 1 Covered + Coverpoint lh_cg::cp_align 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 35 1 Covered + bin auto[1] 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/lw_cg + 99.21% 100 Uncovered + covered/total bins: 67 68 + missing/total bins: 1 68 + % Hit: 98.52% 100 + Coverpoint lw_cg::cp_rs1 96.87% 100 Uncovered + covered/total bins: 31 32 + missing/total bins: 1 32 + % Hit: 96.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 11 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 5 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 2 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 2 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lw_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 2 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 3 1 Covered + bin auto[TP] 5 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 2 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 2 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 2 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 2 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 4 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lw_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 43 1 Covered + bin auto[NEGATIVE] 4 1 Covered + Coverpoint lw_cg::cp_align 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 44 1 Covered + bin auto[1] 3 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/lbu_cg + 98.95% 100 Uncovered + covered/total bins: 65 66 + missing/total bins: 1 66 + % Hit: 98.48% 100 + Coverpoint lbu_cg::cp_rs1 96.87% 100 Uncovered + covered/total bins: 31 32 + missing/total bins: 1 32 + % Hit: 96.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 3 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 6 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lbu_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 2 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 2 1 Covered + bin auto[T0] 2 1 Covered + bin auto[T1] 2 1 Covered + bin auto[T2] 2 1 Covered + bin auto[S0] 2 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lbu_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 25 1 Covered + bin auto[NEGATIVE] 13 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/lhu_cg + 99.21% 100 Uncovered + covered/total bins: 67 68 + missing/total bins: 1 68 + % Hit: 98.52% 100 + Coverpoint lhu_cg::cp_rs1 96.87% 100 Uncovered + covered/total bins: 31 32 + missing/total bins: 1 32 + % Hit: 96.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 2 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 5 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 3 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lhu_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 1 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 2 1 Covered + bin auto[GP] 2 1 Covered + bin auto[TP] 5 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint lhu_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 30 1 Covered + bin auto[NEGATIVE] 8 1 Covered + Coverpoint lhu_cg::cp_align 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 36 1 Covered + bin auto[1] 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/sb_cg + 98.95% 100 Uncovered + covered/total bins: 65 66 + missing/total bins: 1 66 + % Hit: 98.48% 100 + Coverpoint sb_cg::cp_rs1 96.87% 100 Uncovered + covered/total bins: 31 32 + missing/total bins: 1 32 + % Hit: 96.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 22 1 Covered + bin auto[SP] 8 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 6 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sb_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 33 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sb_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 40 1 Covered + bin auto[NEGATIVE] 24 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/sh_cg + 99.21% 100 Uncovered + covered/total bins: 67 68 + missing/total bins: 1 68 + % Hit: 98.52% 100 + Coverpoint sh_cg::cp_rs1 96.87% 100 Uncovered + covered/total bins: 31 32 + missing/total bins: 1 32 + % Hit: 96.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 22 1 Covered + bin auto[SP] 12 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 6 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sh_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 33 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 5 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint sh_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 52 1 Covered + bin auto[NEGATIVE] 16 1 Covered + Coverpoint sh_cg::cp_misalign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 66 1 Covered + bin auto[1] 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/sw_cg + 99.21% 100 Uncovered + covered/total bins: 67 68 + missing/total bins: 1 68 + % Hit: 98.52% 100 + Coverpoint sw_cg::cp_rs1 96.87% 100 Uncovered + covered/total bins: 31 32 + missing/total bins: 1 32 + % Hit: 96.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 701 1 Covered + bin auto[SP] 354 1 Covered + bin auto[GP] 44 1 Covered + bin auto[TP] 21 1 Covered + bin auto[T0] 146 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 61 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 33 1 Covered + bin auto[A7] 9 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 9 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 13 1 Covered + Coverpoint sw_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 81 1 Covered + bin auto[RA] 214 1 Covered + bin auto[SP] 70 1 Covered + bin auto[GP] 36 1 Covered + bin auto[TP] 47 1 Covered + bin auto[T0] 43 1 Covered + bin auto[T1] 38 1 Covered + bin auto[T2] 34 1 Covered + bin auto[S0] 35 1 Covered + bin auto[S1] 34 1 Covered + bin auto[A0] 33 1 Covered + bin auto[A1] 33 1 Covered + bin auto[A2] 33 1 Covered + bin auto[A3] 34 1 Covered + bin auto[A4] 33 1 Covered + bin auto[A5] 33 1 Covered + bin auto[A6] 33 1 Covered + bin auto[A7] 33 1 Covered + bin auto[S2] 34 1 Covered + bin auto[S3] 33 1 Covered + bin auto[S4] 33 1 Covered + bin auto[S5] 33 1 Covered + bin auto[S6] 33 1 Covered + bin auto[S7] 34 1 Covered + bin auto[S8] 33 1 Covered + bin auto[S9] 33 1 Covered + bin auto[S10] 34 1 Covered + bin auto[S11] 35 1 Covered + bin auto[T3] 34 1 Covered + bin auto[T4] 33 1 Covered + bin auto[T5] 80 1 Covered + bin auto[T6] 33 1 Covered + Coverpoint sw_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 1404 1 Covered + bin auto[NEGATIVE] 8 1 Covered + Coverpoint sw_cg::cp_misalign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 943 1 Covered + bin auto[1] 469 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/jal_cg + 83.33% 100 Uncovered + covered/total bins: 35 36 + missing/total bins: 1 36 + % Hit: 97.22% 100 + Coverpoint jal_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 9 1 Covered + bin auto[NEGATIVE] 164 1 Covered + Coverpoint jal_cg::cp_rd 100.00% 100 Covered + covered/total bins: 32 32 + missing/total bins: 0 32 + % Hit: 100.00% 100 + bin auto[ZERO] 142 1 Covered + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint jal_cg::cp_rd_align 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[0] 173 1 Covered + bin auto[1] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/jalr_cg + 66.14% 100 Uncovered + covered/total bins: 37 44 + missing/total bins: 7 44 + % Hit: 84.09% 100 + Coverpoint jalr_cg::cp_imm_sign 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[POSITIVE] 31 1 Covered + bin auto[NEGATIVE] 0 1 ZERO + Coverpoint jalr_cg::cp_rd 96.87% 100 Uncovered + covered/total bins: 31 32 + missing/total bins: 1 32 + % Hit: 96.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 1 1 Covered + bin auto[SP] 1 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 1 1 Covered + bin auto[T1] 1 1 Covered + bin auto[T2] 1 1 Covered + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 1 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 1 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 1 1 Covered + Coverpoint jalr_cg::cp_rd_align 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[0] 31 1 Covered + bin auto[1] 0 1 ZERO + Coverpoint jalr_cg::cp_rs1_link 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin ra 2 1 Covered + bin t1 1 1 Covered + default bin non_link 28 Occurred + Coverpoint jalr_cg::cp_rd_link 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin ra 1 1 Covered + bin t1 1 1 Covered + default bin non_link 29 Occurred + Cross jalr_cg::cp_ras 0.00% 100 ZERO + covered/total bins: 0 4 + missing/total bins: 4 4 + % Hit: 0.00% 100 + bin <ra,ra> 0 1 ZERO + bin <t1,ra> 0 1 ZERO + bin <ra,t1> 0 1 ZERO + bin <t1,t1> 0 1 ZERO + +TOTAL COVERGROUP COVERAGE: 97.23% COVERGROUP TYPES: 37
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/coverage/summary.txt b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/coverage/summary.txt new file mode 100644 index 0000000..ab655e6 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/coverage/summary.txt
@@ -0,0 +1,174 @@ +This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv + + Coverpoint add_cg::cp_rs1 100.00% 100 Covered + Coverpoint add_cg::cp_rs2 100.00% 100 Covered + Coverpoint add_cg::cp_rd 100.00% 100 Covered + Coverpoint add_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint add_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint add_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint sub_cg::cp_rs1 100.00% 100 Covered + Coverpoint sub_cg::cp_rs2 100.00% 100 Covered + Coverpoint sub_cg::cp_rd 100.00% 100 Covered + Coverpoint sub_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint sub_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint sub_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint addi_cg::cp_rs1 100.00% 100 Covered + Coverpoint addi_cg::cp_rd 100.00% 100 Covered + Coverpoint addi_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint addi_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint addi_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint lui_cg::cp_rd 100.00% 100 Covered + Coverpoint lui_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint auipc_cg::cp_rd 100.00% 100 Covered + Coverpoint auipc_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint sra_cg::cp_rs1 100.00% 100 Covered + Coverpoint sra_cg::cp_rs2 100.00% 100 Covered + Coverpoint sra_cg::cp_rd 100.00% 100 Covered + Coverpoint sra_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint sra_cg::cp_rs2_sign 50.00% 100 Uncovered + Coverpoint sra_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint sll_cg::cp_rs1 100.00% 100 Covered + Coverpoint sll_cg::cp_rs2 100.00% 100 Covered + Coverpoint sll_cg::cp_rd 100.00% 100 Covered + Coverpoint sll_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint sll_cg::cp_rs2_sign 50.00% 100 Uncovered + Coverpoint sll_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint srl_cg::cp_rs1 100.00% 100 Covered + Coverpoint srl_cg::cp_rs2 100.00% 100 Covered + Coverpoint srl_cg::cp_rd 100.00% 100 Covered + Coverpoint srl_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint srl_cg::cp_rs2_sign 50.00% 100 Uncovered + Coverpoint srl_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint srai_cg::cp_rs1 100.00% 100 Covered + Coverpoint srai_cg::cp_rd 100.00% 100 Covered + Coverpoint srai_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint srai_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint slli_cg::cp_rs1 100.00% 100 Covered + Coverpoint slli_cg::cp_rd 100.00% 100 Covered + Coverpoint slli_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint slli_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint srli_cg::cp_rs1 100.00% 100 Covered + Coverpoint srli_cg::cp_rd 100.00% 100 Covered + Coverpoint srli_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint srli_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint xor_cg::cp_rs1 100.00% 100 Covered + Coverpoint xor_cg::cp_rs2 100.00% 100 Covered + Coverpoint xor_cg::cp_rd 100.00% 100 Covered + Coverpoint xor_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint xor_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint xor_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint or_cg::cp_rs1 100.00% 100 Covered + Coverpoint or_cg::cp_rs2 100.00% 100 Covered + Coverpoint or_cg::cp_rd 100.00% 100 Covered + Coverpoint or_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint or_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint or_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint and_cg::cp_rs1 100.00% 100 Covered + Coverpoint and_cg::cp_rs2 100.00% 100 Covered + Coverpoint and_cg::cp_rd 100.00% 100 Covered + Coverpoint and_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint and_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint and_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint xori_cg::cp_rs1 100.00% 100 Covered + Coverpoint xori_cg::cp_rd 100.00% 100 Covered + Coverpoint xori_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint xori_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint xori_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint ori_cg::cp_rs1 100.00% 100 Covered + Coverpoint ori_cg::cp_rd 100.00% 100 Covered + Coverpoint ori_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint ori_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint ori_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint andi_cg::cp_rs1 100.00% 100 Covered + Coverpoint andi_cg::cp_rd 100.00% 100 Covered + Coverpoint andi_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint andi_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint andi_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint slt_cg::cp_rs1 100.00% 100 Covered + Coverpoint slt_cg::cp_rd 100.00% 100 Covered + Coverpoint slt_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint slt_cg::cp_result 100.00% 100 Covered + Coverpoint slt_cg::cp_rs2 100.00% 100 Covered + Coverpoint slt_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint sltu_cg::cp_rs1 100.00% 100 Covered + Coverpoint sltu_cg::cp_rd 100.00% 100 Covered + Coverpoint sltu_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint sltu_cg::cp_result 100.00% 100 Covered + Coverpoint sltu_cg::cp_rs2 100.00% 100 Covered + Coverpoint sltu_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint slti_cg::cp_rs1 100.00% 100 Covered + Coverpoint slti_cg::cp_rd 100.00% 100 Covered + Coverpoint slti_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint slti_cg::cp_result 100.00% 100 Covered + Coverpoint slti_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint sltiu_cg::cp_rs1 100.00% 100 Covered + Coverpoint sltiu_cg::cp_rd 100.00% 100 Covered + Coverpoint sltiu_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint sltiu_cg::cp_result 100.00% 100 Covered + Coverpoint sltiu_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint beq_cg::cp_rs1 100.00% 100 Covered + Coverpoint beq_cg::cp_rs2 100.00% 100 Covered + Coverpoint beq_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint beq_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint beq_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint beq_cg::cp_branch_hit 100.00% 100 Covered + Coverpoint bne_cg::cp_rs1 100.00% 100 Covered + Coverpoint bne_cg::cp_rs2 100.00% 100 Covered + Coverpoint bne_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint bne_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint bne_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint bne_cg::cp_branch_hit 100.00% 100 Covered + Coverpoint blt_cg::cp_rs1 100.00% 100 Covered + Coverpoint blt_cg::cp_rs2 100.00% 100 Covered + Coverpoint blt_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint blt_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint blt_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint blt_cg::cp_branch_hit 100.00% 100 Covered + Coverpoint bge_cg::cp_rs1 100.00% 100 Covered + Coverpoint bge_cg::cp_rs2 100.00% 100 Covered + Coverpoint bge_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint bge_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint bge_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint bge_cg::cp_branch_hit 100.00% 100 Covered + Coverpoint bltu_cg::cp_rs1 100.00% 100 Covered + Coverpoint bltu_cg::cp_rs2 100.00% 100 Covered + Coverpoint bltu_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint bltu_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint bltu_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint bltu_cg::cp_branch_hit 100.00% 100 Covered + Coverpoint bgeu_cg::cp_rs1 100.00% 100 Covered + Coverpoint bgeu_cg::cp_rs2 100.00% 100 Covered + Coverpoint bgeu_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint bgeu_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint bgeu_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint bgeu_cg::cp_branch_hit 100.00% 100 Covered + Coverpoint lb_cg::cp_rs1 96.87% 100 Uncovered + Coverpoint lb_cg::cp_rd 100.00% 100 Covered + Coverpoint lb_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint lh_cg::cp_rs1 96.87% 100 Uncovered + Coverpoint lh_cg::cp_rd 100.00% 100 Covered + Coverpoint lh_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint lw_cg::cp_rs1 96.87% 100 Uncovered + Coverpoint lw_cg::cp_rd 100.00% 100 Covered + Coverpoint lw_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint lbu_cg::cp_rs1 96.87% 100 Uncovered + Coverpoint lbu_cg::cp_rd 100.00% 100 Covered + Coverpoint lbu_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint lhu_cg::cp_rs1 96.87% 100 Uncovered + Coverpoint lhu_cg::cp_rd 100.00% 100 Covered + Coverpoint lhu_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint sb_cg::cp_rs1 96.87% 100 Uncovered + Coverpoint sb_cg::cp_rs2 100.00% 100 Covered + Coverpoint sb_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint sh_cg::cp_rs1 96.87% 100 Uncovered + Coverpoint sh_cg::cp_rs2 100.00% 100 Covered + Coverpoint sh_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint sw_cg::cp_rs1 96.87% 100 Uncovered + Coverpoint sw_cg::cp_rs2 100.00% 100 Covered + Coverpoint sw_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint jal_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint jal_cg::cp_rd 100.00% 100 Covered + Coverpoint jalr_cg::cp_imm_sign 50.00% 100 Uncovered + Coverpoint jalr_cg::cp_rd 96.87% 100 Uncovered + Coverpoint jalr_cg::cp_rs1_link 100.00% 100 Covered + Coverpoint jalr_cg::cp_rd_link 100.00% 100 Covered
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ADD-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ADD-01.reference_output index e560ff4..d9ab753 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ADD-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ADD-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000000 -00000001 +fffff802 ffffffff -7fffffff +fffff5cb 80000000 -00000001 -00000001 -00000002 -00000000 +00001a34 +07654320 80000000 -80000001 -ffffffff -ffffffff -00000000 +80000000 +07654320 +00001a34 +80000000 +fffff5cb fffffffe -7ffffffe -7fffffff -7fffffff -7fffffff +fffff802 +00000000 +ffffffff +fffff802 +ffffffff +fffff5cb 80000000 -7ffffffe +00001a34 +07654320 +80000000 +80000000 +07654320 +00001a34 +80000000 +fffff5cb fffffffe +fffff802 +00000000 ffffffff -80000000 -80000000 -80000001 -7fffffff +ffffffff ffffffff 00000000 -00000001 -0000abcd -0000abce -0000abcf -0000abd0 -0000abd1 -0000abd2 -0000abd3 -00000000 -00000000 -00000000 -36925814 -36925814 -36925814
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output index aa414fc..354cd38 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ADDI-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000001 -000007ff +fffff802 ffffffff -00000000 +ffffffff fffff800 -00000001 -00000002 -00000800 00000000 -00000001 +07653b21 +80000000 fffff801 -ffffffff -00000000 -000007fe -fffffffe -ffffffff fffff7ff -7fffffff +00000a34 80000000 -800007fe -7ffffffe -7fffffff -7ffff7ff -80000000 -80000001 -800007ff -7fffffff -80000000 -7ffff800 -0000abcd -0000abce -0000abcf -0000abd0 -0000abd1 -0000abd2 -0000abd3 +fffff5cb +fffffffe +fffff802 00000000 +ffffffff +fffff802 +ffffffff +ffffffff +fffff800 00000000 -00000001 -36925814 -36925814 -36925814 -36925814 +07653b21 +80000000 +fffff801 +fffff7ff +00000a34 +80000000 +fffff5cb +fffffffe +fffff802 +00000000 +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output index 5d636e8..a6c255f 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-AND-01.reference_output
@@ -1,44 +1,36 @@ 00000000 +00000001 +00000000 +000005cc 00000000 00000000 +07654321 +00000001 +00000001 +07654321 00000000 00000000 +000005cc +ffffffff +00000001 +00000000 00000000 00000001 00000000 +000005cc +00000000 +00000000 +07654321 00000001 00000001 +07654321 +00000000 +00000000 +000005cc +ffffffff 00000001 00000000 ffffffff -00000000 -00000001 ffffffff -7fffffff -80000000 -7fffffff +ffffffff 00000000 -00000001 -7fffffff -7fffffff -00000000 -80000000 -00000000 -00000000 -80000000 -00000000 -80000000 -0000007f -abcdffff -0000007f -0000003f -0000001f -0000000f -00000007 -00000003 -00000000 -00000000 -00000000 -36925814 -36925814 -36925814
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output index 30087a7..7f4f02a 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ANDI-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000001 -00000001 -00000001 00000001 00000000 00000000 -ffffffff +00000000 +00000800 +07654000 00000001 -000007ff -ffffffff 00000000 fffff800 -7fffffff +00001000 +00000000 +000005cc +ffffffff 00000001 -000007ff -7fffffff -00000000 -7ffff800 -80000000 00000000 00000000 -80000000 -00000000 -80000000 -abcdffff -0000007f -0000003f -0000001f -0000000f -00000007 -00000003 +00000001 00000000 00000000 00000000 -36925814 -36925814 -36925814 -36925814 +00000800 +07654000 +00000001 +00000000 +fffff800 +00001000 +00000000 +000005cc +ffffffff +00000001 +00000000 +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output index ffd2173..deab1d6 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-AUIPC-01.reference_output
@@ -1,16 +1,36 @@ 00000000 00000000 +007ff000 +00001000 +01234000 +80000000 +01234000 +fffff000 +00001000 +7ffff000 +54321000 +00800000 +00000000 +007ff000 +00000000 +00001000 00000000 00000000 +007ff000 +00001000 +01234000 +80000000 +01234000 +fffff000 +00001000 +7ffff000 +54321000 +00800000 00000000 +007ff000 00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 +00001000 +ffffffff +ffffffff +ffffffff 00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output index ab0505b..ed14a43 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BEQ-01.reference_output
@@ -1,40 +1,36 @@ -00000000 -00000000 -00000001 +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +0000cccc +000123ab +0000cccc +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +0000cccc +000123ab +0000cccc ffffffff -7fffffff -80000000 -0000001e -00000001 -00000000 -00000001 ffffffff -7fffffff -80000000 -0000001d ffffffff 00000000 -00000001 -ffffffff -7fffffff -80000000 -0000001b -7fffffff -00000000 -00000001 -ffffffff -7fffffff -80000000 -00000017 -80000000 -00000000 -00000001 -ffffffff -7fffffff -80000000 -0000000f -000003de -00000000 -9abcdef0 -87654321 -0fedcba9
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output index 7e840d4..7cf39c4 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BGE-01.reference_output
@@ -1,40 +1,36 @@ -00000000 -00000000 -00000001 +000123ab +0000cccc +0000cccc +0000cccc +0000cccc +000123ab +0000cccc +0000cccc +000123ab +000123ab +0000cccc +000123ab +000123ab +0000cccc +000123ab +0000cccc +000123ab +0000cccc +0000cccc +0000cccc +0000cccc +000123ab +0000cccc +0000cccc +000123ab +000123ab +0000cccc +000123ab +000123ab +0000cccc +000123ab +0000cccc ffffffff -7fffffff -80000000 -0000000a -00000001 -00000000 -00000001 ffffffff -7fffffff -80000000 -00000008 ffffffff 00000000 -00000001 -ffffffff -7fffffff -80000000 -0000000b -7fffffff -00000000 -00000001 -ffffffff -7fffffff -80000000 -00000000 -80000000 -00000000 -00000001 -ffffffff -7fffffff -80000000 -0000000f -00000154 -00000000 -9abcdef0 -87654321 -0fedcba9
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output index dde3742..5ac2956 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BGEU-01.reference_output
@@ -1,40 +1,36 @@ -00000000 -00000000 -00000001 +0000cccc +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +0000cccc +000123ab +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +0000cccc +000123ab +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc ffffffff -7fffffff -80000000 -0000001e -00000001 -00000000 -00000001 ffffffff -7fffffff -80000000 -0000001c ffffffff 00000000 -00000001 -ffffffff -7fffffff -80000000 -00000000 -7fffffff -00000000 -00000001 -ffffffff -7fffffff -80000000 -00000014 -80000000 -00000000 -00000001 -ffffffff -7fffffff -80000000 -00000004 -000003c0 -00000000 -9abcdef0 -87654321 -0fedcba9
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output index 10c0454..bc8d944 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BLT-01.reference_output
@@ -1,40 +1,36 @@ -00000000 -00000000 -00000001 +0000cccc +000123ab +000123ab +000123ab +000123ab +0000cccc +000123ab +000123ab +0000cccc +0000cccc +000123ab +0000cccc +0000cccc +000123ab +0000cccc +000123ab +0000cccc +000123ab +000123ab +000123ab +000123ab +0000cccc +000123ab +000123ab +0000cccc +0000cccc +000123ab +0000cccc +0000cccc +000123ab +0000cccc +000123ab ffffffff -7fffffff -80000000 -00000015 -00000001 -00000000 -00000001 ffffffff -7fffffff -80000000 -00000017 ffffffff 00000000 -00000001 -ffffffff -7fffffff -80000000 -00000014 -7fffffff -00000000 -00000001 -ffffffff -7fffffff -80000000 -0000001f -80000000 -00000000 -00000001 -ffffffff -7fffffff -80000000 -00000010 -000002ab -00000000 -9abcdef0 -87654321 -0fedcba9
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output index ba74e05..ea34398 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BLTU-01.reference_output
@@ -1,40 +1,36 @@ -00000000 -00000000 -00000001 +000123ab +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +000123ab +0000cccc +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +000123ab +0000cccc +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab +000123ab ffffffff -7fffffff -80000000 -00000001 -00000001 -00000000 -00000001 ffffffff -7fffffff -80000000 -00000003 ffffffff 00000000 -00000001 -ffffffff -7fffffff -80000000 -0000001f -7fffffff -00000000 -00000001 -ffffffff -7fffffff -80000000 -0000000b -80000000 -00000000 -00000001 -ffffffff -7fffffff -80000000 -0000001b -0000003f -00000000 -9abcdef0 -87654321 -0fedcba9
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output index 0d2708a..836e69f 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-BNE-01.reference_output
@@ -1,40 +1,36 @@ -00000000 -00000000 -00000001 +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +000123ab +0000cccc +000123ab +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +000123ab +0000cccc +000123ab ffffffff -7fffffff -80000000 -00000001 -00000001 -00000000 -00000001 ffffffff -7fffffff -80000000 -00000002 ffffffff 00000000 -00000001 -ffffffff -7fffffff -80000000 -00000004 -7fffffff -00000000 -00000001 -ffffffff -7fffffff -80000000 -00000008 -80000000 -00000000 -00000001 -ffffffff -7fffffff -80000000 -00000010 -00000021 -00000000 -9abcdef0 -87654321 -0fedcba9
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-FENCE.I-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-FENCE.I-01.reference_output deleted file mode 100644 index 1a31ff3..0000000 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-FENCE.I-01.reference_output +++ /dev/null
@@ -1,4 +0,0 @@ -00000030 -00000012 -00000042 -001101b3
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-IO.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-IO-01.reference_output similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-IO.reference_output rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-IO-01.reference_output
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output index 324fe56..5e6e467 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-JAL-01.reference_output
@@ -1,20 +1,36 @@ 00000000 -12345678 -00000000 -9abcdef0 -87654321 -0fedcba9 -11111111 -22222222 -33333333 -44444444 -55555555 -00000000 -00000000 -66666666 -77777777 -88888888 -99999999 -aaaaaaaa -00000000 +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +ffffffff +ffffffff +ffffffff 00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output index fb6def1..975966e 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-JALR-01.reference_output
@@ -1,24 +1,36 @@ +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc +0000cccc 00000000 -12345678 +ffffffff +ffffffff +ffffffff 00000000 -9abcdef0 -87654321 -0fedcba9 -11111111 -22222222 -33333333 -44444444 -55555555 -00000000 -00000000 -66666666 -77777777 -88888888 -99999999 -aaaaaaaa -00000000 -00000000 -11111111 -22222222 -33333333 -44444444
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output index 2e6a41f..f9590a9 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LB-01.reference_output
@@ -1,36 +1,36 @@ -00000022 -fffffff2 -fffffff1 -00000011 -fffffff4 -00000044 -00000033 -fffffff3 -00000066 -fffffff6 -fffffff5 -00000055 -fffffff8 -ffffff88 -00000077 -fffffff7 -ffffffaa -0000000a -00000009 -ffffff99 -0000000c -ffffffcc +00000000 ffffffbb -0000000b -ffffffee -0000000e -0000000d ffffffdd +0000000c +0000000d fffffff0 -00000000 +0000000b +0000000e +ffffffee +ffffffbb +ffffffdd +0000000c +0000000d +fffffff0 +0000000b +0000000e +ffffffee +ffffffbb +ffffffdd +0000000c +0000000d +fffffff0 +0000000b +0000000e +ffffffee +ffffffbb +ffffffdd +0000000c +0000000d +fffffff0 +0000000b +0000000e ffffffff -0000000f +ffffffff +ffffffff 00000000 -fffffff0 -00000010 -ffffff98
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LBU-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LBU-01.reference_output index f41aaca..8c19a1f 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LBU-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LBU-01.reference_output
@@ -1,36 +1,36 @@ -00000022 -000000f2 -000000f1 -00000011 -000000f4 -00000044 -00000033 -000000f3 -00000066 -000000f6 -000000f5 -00000055 -000000f8 -00000088 -00000077 -000000f7 -000000aa -0000000a -00000009 -00000099 -0000000c -000000cc +00000000 000000bb -0000000b -000000ee -0000000e -0000000d 000000dd +0000000c +0000000d 000000f0 -00000000 -000000ff -0000000f -00000000 +0000000b +0000000e +000000ee +000000bb +000000dd +0000000c +0000000d 000000f0 -00000010 -00000098 +0000000b +0000000e +000000ee +000000bb +000000dd +0000000c +0000000d +000000f0 +0000000b +0000000e +000000ee +000000bb +000000dd +0000000c +0000000d +000000f0 +0000000b +0000000e +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LH-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LH-01.reference_output index 985af8a..517a29f 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LH-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LH-01.reference_output
@@ -1,20 +1,36 @@ -fffff222 -000011f1 -000044f4 -fffff333 -fffff666 -000055f5 -ffff88f8 -fffff777 -00000aaa -ffff9909 -ffffcc0c +00000000 00000bbb -00000eee +ffffdd0d +ffffcc0c ffffdd0d 000000f0 -00000fff +00000eee +00000eee +00000eee +00000bbb +ffffdd0d +ffffcc0c +ffffdd0d +000000f0 +00000eee +00000eee +00000eee +00000bbb +ffffdd0d +ffffcc0c +ffffdd0d +000000f0 +00000eee +00000eee +00000eee +00000bbb +ffffdd0d +ffffcc0c +ffffdd0d +000000f0 +00000eee +00000eee +ffffffff +ffffffff +ffffffff 00000000 -ffffdef0 -00003210 -ffffba98
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LHU-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LHU-01.reference_output index f3f0b21..c1e3873 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LHU-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LHU-01.reference_output
@@ -1,20 +1,36 @@ -0000f222 -000011f1 -000044f4 -0000f333 -0000f666 -000055f5 -000088f8 -0000f777 -00000aaa -00009909 -0000cc0c +00000000 00000bbb -00000eee +0000dd0d +0000cc0c 0000dd0d 000000f0 -00000fff +00000eee +00000eee +00000eee +00000bbb +0000dd0d +0000cc0c +0000dd0d +000000f0 +00000eee +00000eee +00000eee +00000bbb +0000dd0d +0000cc0c +0000dd0d +000000f0 +00000eee +00000eee +00000eee +00000bbb +0000dd0d +0000cc0c +0000dd0d +000000f0 +00000eee +00000eee +ffffffff +ffffffff +ffffffff 00000000 -0000def0 -00003210 -0000ba98
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LUI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LUI-01.reference_output index cdc1765..deab1d6 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LUI-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LUI-01.reference_output
@@ -1,16 +1,36 @@ 00000000 +00000000 +007ff000 00001000 +01234000 +80000000 +01234000 fffff000 +00001000 7ffff000 -80000000 -80000000 -7ffff000 +54321000 +00800000 +00000000 +007ff000 00000000 00001000 +00000000 +00000000 +007ff000 +00001000 +01234000 +80000000 +01234000 fffff000 -42726e6f -12345678 -9abcdef0 -42726e6f -12345678 -9abcdef0 +00001000 +7ffff000 +54321000 +00800000 +00000000 +007ff000 +00000000 +00001000 +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LW-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LW-01.reference_output index 909bfaf..091b56e 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LW-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-LW-01.reference_output
@@ -1,12 +1,36 @@ -11f1f222 -f33344f4 -55f5f666 -f77788f8 -99090aaa +00000000 +dd0d0eee +dd0d0eee 0bbbcc0c dd0d0eee 0fff00f0 +dd0d0eee +dd0d0eee +dd0d0eee +dd0d0eee +dd0d0eee +0bbbcc0c +dd0d0eee +0fff00f0 +dd0d0eee +dd0d0eee +dd0d0eee +dd0d0eee +dd0d0eee +0bbbcc0c +dd0d0eee +0fff00f0 +dd0d0eee +dd0d0eee +dd0d0eee +dd0d0eee +dd0d0eee +0bbbcc0c +dd0d0eee +0fff00f0 +dd0d0eee +dd0d0eee +ffffffff +ffffffff +ffffffff 00000000 -9abcdef0 -76543210 -fedcba98
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-OR-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-OR-01.reference_output index c8b2c4d..904fbeb 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-OR-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-OR-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000000 -00000001 +fffff801 ffffffff -7fffffff +ffffefff 80000000 -00000001 -00000001 -00000001 -ffffffff -7fffffff -80000001 -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff +00001a34 ffffffff 7fffffff 7fffffff -7fffffff ffffffff -7fffffff -ffffffff +00001a34 80000000 +ffffefff +ffffffff +fffff801 +00000000 +ffffffff +fffff801 +ffffffff +ffffefff 80000000 -80000001 +00001a34 +ffffffff +7fffffff +7fffffff +ffffffff +00001a34 +80000000 +ffffefff +ffffffff +fffff801 +00000000 ffffffff ffffffff -80000000 -00000010 -0000000d -0000001d -0000003d -0000007d -000000fd -000001fd -fffff9fd +ffffffff 00000000 -00000000 -00000000 -36925814 -36925814 -36925814
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ORI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ORI-01.reference_output index 666d1c0..f7b6610 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ORI-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-ORI-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000001 -000007ff -ffffffff -00000000 -fffff800 -00000001 -00000001 -000007ff -ffffffff -00000001 fffff801 ffffffff ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -7fffffff -7fffffff -7fffffff -ffffffff -7fffffff -ffffffff -80000000 -80000001 -800007ff -ffffffff -80000000 fffff800 -0000000d -0000001d -0000003d -0000007d -000000fd -000001fd -fffff9fd +fffff800 +fffffb21 +7fffffff +fffff801 +ffffffff +fffffa34 +80000000 +ffffefff +ffffffff +fffff801 00000000 +ffffffff +fffff801 +ffffffff +ffffffff +fffff800 +fffff800 +fffffb21 +7fffffff +fffff801 +ffffffff +fffffa34 +80000000 +ffffefff +ffffffff +fffff801 00000000 -00000001 -36925814 -36925814 -36925814 -36925814 +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SB-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SB-01.reference_output index d230c87..5045d3a 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SB-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SB-01.reference_output
@@ -1,16 +1,36 @@ -aaaabb22 -000000f4 -00000066 -000000f8 -000000aa -0bbbcc0c -dd0d0eee -0fff00f0 -87654300 -00000044 -000000f0 -00000010 -000000ef -00000036 -00000036 -00000063 +0000ffff +ffffffff +ffffffff +ffffffff +21ffffff +ffffff01 +ffffff00 +ffffffff +ffffffff +01ffff00 +34ccffff +ffffffff +ffffffff +ffffffff +ff01ffff +00ff0000 +ffffffff +ffffffff +ffffffff +21ffffff +ff00ff01 +ffffff00 +ffffffff +ffffffff +ffffff00 +34ccffff +ffffffff +ffffffff +ffffffff +01ffffff +ffff00ff +ffffffff +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SH-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SH-01.reference_output index 3967d93..9ea76ed 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SH-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SH-01.reference_output
@@ -1,16 +1,36 @@ -aaaaf222 -000044f4 -0000f666 -000088f8 -00000aaa -0bbbcc0c -dd0d0eee -0fff00f0 -87650000 -00003344 -0000def0 -00003210 -0000cdef -00005836 -00005836 -00004963 +0000ffff +ffffffff +ffffffff +ffffffff +ffffffff +ffff0001 +ffff0800 +ffffffff +ffffffff +ffff0000 +edccf801 +ffffffff +ffffffff +ffffffff +000107ff +00000000 +ffffffff +ffffffff +ffffffff +ffffffff +00000001 +ffff0800 +ffffffff +ffffffff +ffff0000 +edccffff +ffffffff +ffffffff +ffffffff +ffffffff +ffff0000 +ffffffff +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLL-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLL-01.reference_output index 0ccb67d..8960430 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLL-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLL-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000000 -00000000 -00000000 -00000000 -00000000 00000001 -00000002 -00008000 -80000000 +00000000 +00007ff0 +00000000 +00000000 +43210000 +fffffffe 00000001 -00010000 ffffffff -fffffffe -ffff8000 +00002468 +00000000 +ffedcc00 80000000 +f8010000 +00000000 ffffffff -ffff0000 -7fffffff +00000001 +00000000 +00007ff0 +00000000 +00000000 +43210000 fffffffe -ffff8000 +00000001 +ffffffff +00002468 +00000000 +ffedcc00 80000000 -7fffffff -ffff0000 -80000000 +f8010000 00000000 +ffffffff +ffffffff +ffffffff 00000000 -00000000 -80000000 -00000000 -abcdef10 -579bde20 -af37bc40 -5e6f7880 -bcdef100 -79bde200 -f37bc400 -00000000 -00000000 -00000000 -87654321 -0eca8642 -a1908000 -80000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLLI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLLI-01.reference_output index bec79c5..8960430 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLLI-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLLI-01.reference_output
@@ -1,40 +1,36 @@ 00000000 -00000000 -00000000 -00000000 -00000000 -00000000 00000001 -00000002 -00008000 -80000000 +00000000 +00007ff0 +00000000 +00000000 +43210000 +fffffffe 00000001 -00010000 ffffffff -fffffffe -ffff8000 +00002468 +00000000 +ffedcc00 80000000 +f8010000 +00000000 ffffffff -ffff0000 -7fffffff +00000001 +00000000 +00007ff0 +00000000 +00000000 +43210000 fffffffe -ffff8000 +00000001 +ffffffff +00002468 +00000000 +ffedcc00 80000000 -7fffffff -ffff0000 -80000000 +f8010000 00000000 -00000000 -00000000 -80000000 -00000000 -abcdef10 -579bde20 -af37bc40 -5e6f7880 -bcdef100 -79bde200 -f37bc400 -00000000 -00000000 +ffffffff +ffffffff +ffffffff 00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLT-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLT-01.reference_output index 42db862..56b1248 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLT-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLT-01.reference_output
@@ -1,8 +1,16 @@ 00000000 -00000001 +00000000 +00000000 +00000000 +00000000 00000001 00000000 00000000 +00000001 +00000001 +00000000 +00000001 +00000001 00000000 00000001 00000000 @@ -10,39 +18,19 @@ 00000000 00000000 00000000 +00000000 +00000001 +00000000 +00000000 +00000001 +00000001 +00000000 +00000001 +00000001 +00000000 +00000001 +00000000 ffffffff -00000001 -00000001 -00000000 -00000001 -00000000 -7fffffff -00000000 -00000000 -00000000 -00000000 -00000000 -80000000 -00000001 -00000001 -00000001 -00000001 -00000000 -00000000 ffffffff -00000001 -00000001 -00000001 +ffffffff 00000000 -00000000 -00000000 -00000000 -00000000 -00000001 -00000000 -00000001 -00000001 -00000000 -00000001 -00000000 -00000001
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTI-01.reference_output index fc2ba30..b881592 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTI-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTI-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000001 -00000001 00000000 00000000 00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000001 +00000000 00000001 00000000 00000001 00000000 00000000 00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000001 +00000000 +00000001 +00000000 ffffffff -00000001 -00000001 -00000000 -00000001 -00000000 -7fffffff -00000000 -00000000 -00000000 -00000000 -00000000 -80000000 -00000001 -00000001 -00000001 -00000001 -00000001 +ffffffff ffffffff 00000000 -00000000 -00000001 -00000001 -00000000 -00000000 -00000000 -00000000 -00000001 -00000000 -00000001 -00000000 -00000001
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTIU-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTIU-01.reference_output index 9e50bf6..5bebffd 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTIU-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTIU-01.reference_output
@@ -2,43 +2,35 @@ 00000001 00000001 00000001 -00000000 +00000001 00000001 00000001 00000000 00000001 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000001 +00000001 +00000001 +00000001 00000001 00000000 00000001 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +ffffffff ffffffff 00000000 -00000000 -00000000 -00000000 -00000000 -7fffffff -00000000 -00000000 -00000001 -00000000 -00000001 -80000000 -00000000 -00000000 -00000001 -00000000 -00000001 -00000001 -00000000 -00000000 -00000001 -00000001 -00000001 -00000000 -00000001 -00000000 -00000001 -00000000 -00000001 -00000000 -00000001
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTU-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTU-01.reference_output index afb0cf4..cfeed4d 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTU-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SLTU-01.reference_output
@@ -2,47 +2,35 @@ 00000001 00000001 00000001 -00000000 +00000001 00000001 00000001 00000000 00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000001 +00000001 +00000001 +00000001 00000001 00000000 00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +ffffffff ffffffff 00000000 -00000000 -00000000 -00000000 -00000000 -7fffffff -00000000 -00000000 -00000001 -00000000 -00000001 -80000000 -00000000 -00000000 -00000001 -00000000 -00000000 -00000000 -00000001 -ffffffff -00000001 -00000001 -00000001 -00000000 -00000001 -00000000 -00000000 -00000000 -00000000 -00000000 -00000001 -00000000 -00000001 -00000000 -00000001
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRA-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRA-01.reference_output index c132749..61fd5c7 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRA-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRA-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000000 -00000000 -00000000 -00000000 -00000000 00000001 00000000 +0000007f 00000000 00000000 -00000001 -00000000 -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -7fffffff +00000765 3fffffff -0000ffff -00000000 -7fffffff -00007fff -80000000 -c0000000 -ffff0000 +00000001 ffffffff -80000000 -ffff8000 -abcdef10 -d5e6f788 -eaf37bc4 -f579bde2 -fabcdef1 -fd5e6f78 -feaf37bc -00000000 -00000000 -00000000 -87654321 -c3b2a190 -ffff0eca +0000091a +f8000000 +ffffffed ffffffff +ffffffff +00000000 +ffffffff +00000001 +00000000 +0000007f +00000000 +00000000 +00000765 +3fffffff +00000001 +ffffffff +0000091a +f8000000 +ffffffed +ffffffff +ffffffff +00000000 +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRAI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRAI-01.reference_output index 886c2dc..61fd5c7 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRAI-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRAI-01.reference_output
@@ -1,40 +1,36 @@ 00000000 -00000000 -00000000 -00000000 -00000000 -00000000 00000001 00000000 +0000007f 00000000 00000000 -00000001 -00000000 -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -7fffffff +00000765 3fffffff -0000ffff -00000000 -7fffffff -00007fff -80000000 -c0000000 -ffff0000 +00000001 ffffffff -80000000 -ffff8000 -abcdef10 -d5e6f788 -eaf37bc4 -f579bde2 -fabcdef1 -fd5e6f78 -feaf37bc +0000091a +f8000000 +ffffffed +ffffffff +ffffffff +00000000 +ffffffff +00000001 +00000000 +0000007f 00000000 00000000 +00000765 +3fffffff +00000001 +ffffffff +0000091a +f8000000 +ffffffed +ffffffff +ffffffff +00000000 +ffffffff +ffffffff +ffffffff 00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRL-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRL-01.reference_output index aa4dc2e..6737fda 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRL-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRL-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000000 -00000000 -00000000 -00000000 -00000000 00000001 00000000 +0000007f 00000000 00000000 -00000001 -00000000 -ffffffff -7fffffff -0001ffff -00000001 -ffffffff -0000ffff -7fffffff +00000765 3fffffff +00000001 +ffffffff +0000091a +08000000 +00ffffed +00000001 0000ffff 00000000 -7fffffff -00007fff -80000000 -40000000 -00010000 +ffffffff 00000001 -80000000 -00008000 -abcdef10 -55e6f788 -2af37bc4 -1579bde2 -0abcdef1 -055e6f78 -02af37bc +00000000 +0000007f 00000000 00000000 -00000000 -87654321 -43b2a190 -00010eca +00000765 +3fffffff 00000001 +ffffffff +0000091a +08000000 +00ffffed +00000001 +0000ffff +00000000 +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRLI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRLI-01.reference_output index f2cb4cd..6737fda 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRLI-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SRLI-01.reference_output
@@ -1,40 +1,36 @@ 00000000 -00000000 -00000000 -00000000 -00000000 -00000000 00000001 00000000 +0000007f 00000000 00000000 -00000001 -00000000 -ffffffff -7fffffff -0001ffff -00000001 -ffffffff -0000ffff -7fffffff +00000765 3fffffff +00000001 +ffffffff +0000091a +08000000 +00ffffed +00000001 0000ffff 00000000 -7fffffff -00007fff -80000000 -40000000 -00010000 +ffffffff 00000001 -80000000 -00008000 -abcdef10 -55e6f788 -2af37bc4 -1579bde2 -0abcdef1 -055e6f78 -02af37bc +00000000 +0000007f 00000000 00000000 +00000765 +3fffffff +00000001 +ffffffff +0000091a +08000000 +00ffffed +00000001 +0000ffff +00000000 +ffffffff +ffffffff +ffffffff 00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output index 298dca6..bbfdc30 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SUB-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000000 -ffffffff +00000800 00000001 -80000001 +00001a33 80000000 -00000001 -00000001 -00000000 -00000002 -80000002 -80000001 -ffffffff -ffffffff -fffffffe -00000000 -80000000 -7fffffff -7fffffff -7fffffff +fffff5cc +07654322 7ffffffe +80000002 +f89abcde +00000a34 80000000 +ffffe5cd +00000000 +fffff800 00000000 ffffffff -80000000 -80000000 -7fffffff -80000001 +00000800 00000001 +00001a33 +80000000 +fffff5cc +07654322 +7ffffffe +80000002 +f89abcde +00000a34 +80000000 +ffffe5cd 00000000 -00000001 -0000abcd -0000abcc -0000abcb -0000abca -0000abc9 -0000abc8 -0000abc7 +fffff800 00000000 +ffffffff +ffffffff +ffffffff 00000000 -00000000 -36925814 -c96da7ec -c96da7ec
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output index 3509222..364db51 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-SW-01.reference_output
@@ -1,16 +1,36 @@ -11f1f222 -f33344f4 -55f5f666 -f77788f8 -99090aaa -0bbbcc0c -dd0d0eee -0fff00f0 +ffffffff +00000001 00000000 -11223344 -9abcdef0 -76543210 -89abcdef -14725836 -14725836 -25814963 +000007ff +00000000 +00000800 +07654321 +7fffffff +00000001 +ffffffff +00001234 +80000000 +ffffedcc +ffffffff +fffff801 +fffffffe +00000000 +00000001 +00000000 +000007ff +00000000 +00000800 +07654321 +7fffffff +00000001 +ffffffff +00001234 +80000000 +ffffedcc +ffffffff +fffff801 +fffffffe +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output index f4bbd34..e8b700b 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-XOR-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000000 -00000001 +fffff800 ffffffff -7fffffff +ffffea33 80000000 -00000001 -00000001 -00000000 -fffffffe +00001a34 +f89abcde 7ffffffe -80000001 -ffffffff -ffffffff -fffffffe -00000000 -80000000 -7fffffff -7fffffff -7fffffff 7ffffffe +f89abcde +00001a34 80000000 +ffffea33 +00000000 +fffff800 00000000 ffffffff +fffff800 +ffffffff +ffffea33 80000000 +00001a34 +f89abcde +7ffffffe +7ffffffe +f89abcde +00001a34 80000000 -80000001 -7fffffff +ffffea33 +00000000 +fffff800 +00000000 +ffffffff +ffffffff ffffffff 00000000 -0000007f -abcdffff -abcdff80 -abcdffbf -abcdffa0 -abcdffaf -abcdffa8 -abcdffab -00000000 -00000000 -00000000 -36925814 -36925814 -36925814
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output index d335043..4b85ed7 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/references/I-XORI-01.reference_output
@@ -1,44 +1,36 @@ 00000000 -00000001 -000007ff -ffffffff -00000000 fffff800 -00000001 -00000000 -000007fe -fffffffe -00000001 -fffff801 ffffffff -fffffffe +ffffffff fffff800 -00000000 -ffffffff -000007ff -7fffffff +fffff000 +f89abb21 7ffffffe -7ffff800 +fffff801 +000007ff +ffffea34 80000000 -7fffffff -800007ff -80000000 -80000001 -800007ff -7fffffff -80000000 -7ffff800 -abcdffff -abcdff80 -abcdffbf -abcdffa0 -abcdffaf -abcdffa8 -abcdffab +ffffea33 00000000 +fffff800 00000000 -00000001 -36925814 -36925814 -36925814 -36925814 +ffffffff +fffff800 +ffffffff +ffffffff +fffff800 +fffff000 +f89abb21 +7ffffffe +fffff801 +000007ff +ffffea34 +80000000 +ffffea33 +00000000 +fffff800 +00000000 +ffffffff +ffffffff +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ADD-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ADD-01.S index dc7aaac..f2f17b1 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ADD-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ADD-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-ADD-01 +# RISC-V Compliance Test ADD-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,421 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction ADD. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'ADD'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region. RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - # Test - add x4, x3, x4 - add x5, x3, x5 - add x6, x3, x6 - add x7, x3, x7 - add x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(add, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(add, x1, x30, x15, 0xfffff802, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_RR_OP(add, x2, x29, x14, 0xffffffff, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(add, x3, x28, x13, 0xfffff5cb, 0x7ff, -0x1234, x5, 12, x6) # Testcase 3 + TEST_RR_OP(add, x4, x27, x12, 0x80000000, 0x0, 0x80000000, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(add, x5, x26, x11, 0x1a34, 0x800, 0x1234, x1, 0, x2) # Testcase 5 + TEST_RR_OP(add, x6, x25, x10, 0x7654320, 0x7654321, 0xffffffff, x1, 4, x2) # Testcase 6 + TEST_RR_OP(add, x7, x24, x9, 0x80000000, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(add, x8, x23, x8, 0x80000000, 0x1, 0x7fffffff, x1, 12, x2) # Testcase 8 + TEST_RR_OP(add, x9, x22, x7, 0x7654320, 0xffffffff, 0x7654321, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 0 - li x10, 1 - li x11, -1 - li x12, 0x7FFFFFFF - li x13, 0x80000000 - # Test - add x9, x8, x9 - add x10, x8, x10 - add x11, x8, x11 - add x12, x8, x12 - add x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000002) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x80000001) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(add, x10, x21, x6, 0x1a34, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_RR_OP(add, x11, x20, x5, 0x80000000, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_RR_OP(add, x12, x19, x4, 0xfffff5cb, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_RR_OP(add, x13, x18, x3, 0xfffffffe, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_RR_OP(add, x14, x17, x2, 0xfffff802, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 0 - li x15, 1 - li x16, -1 - li x17, 0x7FFFFFFF - li x18, 0x80000000 + # address for test results + la x2, test_4_res - # Test - add x14, x13, x14 - add x15, x13, x15 - add x16, x13, x16 - add x17, x13, x17 - add x18, x13, x18 + TEST_RR_OP(add, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_RR_OP(add, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(add, x17, x14, x31, 0xfffff802, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_RR_OP(add, x18, x13, x30, 0xffffffff, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(add, x19, x12, x29, 0xfffff5cb, 0x7ff, -0x1234, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x7FFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + TEST_RR_OP(add, x20, x11, x28, 0x80000000, 0x0, 0x80000000, x1, 0, x2) # Testcase 20 + TEST_RR_OP(add, x21, x10, x27, 0x1a34, 0x800, 0x1234, x1, 4, x2) # Testcase 21 + TEST_RR_OP(add, x22, x9, x26, 0x7654320, 0x7654321, 0xffffffff, x1, 8, x2) # Testcase 22 + TEST_RR_OP(add, x23, x8, x25, 0x80000000, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(add, x24, x7, x24, 0x80000000, 0x1, 0x7fffffff, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x1) - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test execution - add x19, x18, x19 - add x20, x18, x20 - add x21, x18, x21 - add x22, x18, x22 - add x23, x18, x23 - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x7FFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0xFFFFFFFF) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Register initialization - li x24, 0 - li x25, 1 - li x26, -1 - li x27, 0x7FFFFFFF - li x28, 0x80000000 - - # Test - add x24, x23, x24 - add x25, x23, x25 - add x26, x23, x26 - add x27, x23, x27 - add x28, x23, x28 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x80000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x25, test_B_data - la x26, test_B_res - - # Load testdata - lw x28, 0(x25) - - # Register initialization - li x27, 0x1 - - # Test - add x29, x28, x27 - add x30, x29, x27 - add x31, x30, x27 - add x1, x31, x27 - add x2, x1, x27 - add x3, x2, x27 - - # store results - sw x27, 0(x26) - sw x28, 4(x26) - sw x29, 8(x26) - sw x30, 12(x26) - sw x31, 16(x26) - sw x1, 20(x26) - sw x2, 24(x26) - sw x3, 28(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x27, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0x0000ABCD) - RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0x0000ABCE) - RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0x0000ABCF) - RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0x0000ABD0) - RVTEST_IO_ASSERT_GPR_EQ(x26, x1, 0x0000ABD1) - RVTEST_IO_ASSERT_GPR_EQ(x26, x2, 0x0000ABD2) - RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0x0000ABD3) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - add x0, x28, x27 - - # store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - add x0, x28, x27 - add x5, x0, x0 - - # store results - sw x0, 0(x2) - sw x5, 4(x2) - - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + TEST_RR_OP(add, x25, x6, x23, 0x7654320, 0xffffffff, 0x7654321, x1, 0, x7) # Testcase 25 + TEST_RR_OP(add, x26, x5, x22, 0x1a34, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_RR_OP(add, x27, x4, x21, 0x80000000, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_RR_OP(add, x28, x3, x20, 0xfffff5cb, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_RR_OP(add, x29, x2, x19, 0xfffffffe, -0x1, -0x1, x1, 16, x7) # Testcase 29 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving (add with x0)\n"); - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Load testdata - lw x3, 0(x1) - # Test - add x4, x3, x0 - add x5, x4, x0 - add x6, x0, x5 - add x14, x6, x0 - add x15, x14, x0 - add x16, x15, x0 - add x25, x0, x16 - add x26, x0, x25 - add x27, x26, x0 + # address for test results + la x2, test_7_res - # Store results - sw x4, 0(x2) - sw x26, 4(x2) - sw x27, 8(x2) + TEST_RR_OP(add, x30, x1, x18, 0xfffff802, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_RR_OP(add, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0x0000ABCD -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x36925814 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 8, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 3, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S index 8807739..264a439 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ADDI-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-ADDI-01 +# RISC-V Compliance Test ADDI-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,380 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction ADDI. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'ADDI'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - addi x4, x3, 1 - addi x5, x3, 0x7FF - addi x6, x3, 0xFFFFFFFF - addi x7, x3, 0 - addi x8, x3, 0xFFFFF800 - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + # address for test results + la x5, test_1_res - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x000007FF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0xFFFFF800) + TEST_IMM_OP(addi, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_IMM_OP(addi, x1, x30, 0xfffff802, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_IMM_OP(addi, x2, x29, 0xffffffff, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_IMM_OP(addi, x3, x28, 0xffffffff, 0x7ff, -0x800, x5, 12, x6) # Testcase 3 + TEST_IMM_OP(addi, x4, x27, 0xfffff800, 0x0, 0x800, x5, 16, x6) # Testcase 4 - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX immediate values\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - # Load testdata - lw x8, 0(x1) + # address for test results + la x1, test_2_res - # Test - addi x9, x8, 1 - addi x10, x8, 0x7FF - addi x11, x8, 0xFFFFFFFF - addi x12, x8, 0 - addi x13, x8, 0xFFFFF800 + TEST_IMM_OP(addi, x5, x26, 0x0, 0x800, 0x800, x1, 0, x2) # Testcase 5 + TEST_IMM_OP(addi, x6, x25, 0x7653b21, 0x7654321, 0x800, x1, 4, x2) # Testcase 6 + TEST_IMM_OP(addi, x7, x24, 0x80000000, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_IMM_OP(addi, x8, x23, 0xfffff801, 0x1, 0x800, x1, 12, x2) # Testcase 8 + TEST_IMM_OP(addi, x9, x22, 0xfffff7ff, 0xffffffff, 0x800, x1, 16, x2) # Testcase 9 - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000002) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000800) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFF801) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX immediate values\n"); + # address for test results + la x1, test_3_res - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + TEST_IMM_OP(addi, x10, x21, 0xa34, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_IMM_OP(addi, x11, x20, 0x80000000, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_IMM_OP(addi, x12, x19, 0xfffff5cb, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_IMM_OP(addi, x13, x18, 0xfffffffe, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_IMM_OP(addi, x14, x17, 0xfffff802, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # Load testdata - lw x13, 0(x1) - # Test - addi x14, x13, 1 - addi x15, x13, 0x7FF - addi x16, x13, 0xFFFFFFFF - addi x17, x13, 0 - addi x18, x13, 0xFFFFF800 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x000007FE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0xFFFFF7FF) + # address for test results + la x2, test_4_res - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + TEST_IMM_OP(addi, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_IMM_OP(addi, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_IMM_OP(addi, x17, x14, 0xfffff802, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_IMM_OP(addi, x18, x13, 0xffffffff, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_IMM_OP(addi, x19, x12, 0xffffffff, 0x7ff, -0x800, x2, 16, x3) # Testcase 19 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - # Load testdata - lw x18, 0(x1) - # Test - addi x19, x18, 1 - addi x20, x18, 0x7FF - addi x21, x18, 0xFFFFFFFF - addi x22, x18, 0 - addi x23, x18, 0xFFFFF800 + # address for test results + la x1, test_5_res - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + TEST_IMM_OP(addi, x20, x11, 0xfffff800, 0x0, 0x800, x1, 0, x2) # Testcase 20 + TEST_IMM_OP(addi, x21, x10, 0x0, 0x800, 0x800, x1, 4, x2) # Testcase 21 + TEST_IMM_OP(addi, x22, x9, 0x7653b21, 0x7654321, 0x800, x1, 8, x2) # Testcase 22 + TEST_IMM_OP(addi, x23, x8, 0x80000000, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_IMM_OP(addi, x24, x7, 0xfffff801, 0x1, 0x800, x1, 16, x2) # Testcase 24 - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x800007FE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x7FFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x7FFFF7FF) - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Test - addi x24, x23, 1 - addi x25, x23, 0x7FF - addi x26, x23, 0xFFFFFFFF - addi x27, x23, 0 - addi x28, x23, 0xFFFFF800 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x800007FF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x7FFFF800) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - - # Load testdata - lw x28, 0(x26) - - # Test - addi x29, x28, 1 - addi x30, x29, 1 - addi x31, x30, 1 - addi x1, x31, 1 - addi x2, x1, 1 - addi x3, x2, 1 - - # Store results - sw x28, 0(x27) - sw x29, 4(x27) - sw x30, 8(x27) - sw x31, 12(x27) - sw x1, 16(x27) - sw x2, 20(x27) - sw x3, 24(x27) - - - RVTEST_IO_ASSERT_GPR_EQ(x27, x28, 0x0000ABCD) - RVTEST_IO_ASSERT_GPR_EQ(x27, x29, 0x0000ABCE) - RVTEST_IO_ASSERT_GPR_EQ(x27, x30, 0x0000ABCF) - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x0000ABD0) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0x0000ABD1) - RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0x0000ABD2) - RVTEST_IO_ASSERT_GPR_EQ(x27, x3, 0x0000ABD3) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Test - addi x0, x5, 1 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Test - addi x0, x5, 1 - addi x5, x0, 1 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) + # address for test results + la x1, test_6_res - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + TEST_IMM_OP(addi, x25, x6, 0xfffff7ff, 0xffffffff, 0x800, x1, 0, x7) # Testcase 25 + TEST_IMM_OP(addi, x26, x5, 0xa34, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_IMM_OP(addi, x27, x4, 0x80000000, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_IMM_OP(addi, x28, x3, 0xfffff5cb, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_IMM_OP(addi, x29, x2, 0xfffffffe, -0x1, -0x1, x1, 16, x7) # Testcase 29 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving (addi with 0)\n"); - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Load testdata - lw x3, 0(x1) - # Test - addi x4, x3, 0 - addi x5, x4, 0 - addi x6, x5, 0 - addi x14, x6, 0 - addi x15, x14, 0 - addi x16, x15, 0 - addi x25, x16, 0 - addi x26, x25, 0 - addi x27, x26, 0 + # address for test results + la x2, test_7_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) + TEST_IMM_OP(addi, x30, x1, 0xfffff802, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_IMM_OP(addi, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0x0000ABCD -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x36925814 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-AND-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-AND-01.S index cb2e064..30124be 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-AND-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-AND-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-AND-01 +# RISC-V Compliance Test AND-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,431 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction AND. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'AND'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region. RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - # Test - and x4, x3, x4 - and x5, x3, x5 - and x6, x3, x6 - and x7, x3, x7 - and x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(and, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(and, x1, x30, x15, 0x1, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_RR_OP(and, x2, x29, x14, 0x0, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(and, x3, x28, x13, 0x5cc, 0x7ff, -0x1234, x5, 12, x6) # Testcase 3 + TEST_RR_OP(and, x4, x27, x12, 0x0, 0x0, 0x80000000, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(and, x5, x26, x11, 0x0, 0x800, 0x1234, x1, 0, x2) # Testcase 5 + TEST_RR_OP(and, x6, x25, x10, 0x7654321, 0x7654321, 0xffffffff, x1, 4, x2) # Testcase 6 + TEST_RR_OP(and, x7, x24, x9, 0x1, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(and, x8, x23, x8, 0x1, 0x1, 0x7fffffff, x1, 12, x2) # Testcase 8 + TEST_RR_OP(and, x9, x22, x7, 0x7654321, 0xffffffff, 0x7654321, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 0 - li x10, 1 - li x11, -1 - li x12, 0x7FFFFFFF - li x13, 0x80000000 - # Test - and x9, x8, x9 - and x10, x8, x10 - and x11, x8, x11 - and x12, x8, x12 - and x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(and, x10, x21, x6, 0x0, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_RR_OP(and, x11, x20, x5, 0x0, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_RR_OP(and, x12, x19, x4, 0x5cc, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_RR_OP(and, x13, x18, x3, 0xffffffff, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_RR_OP(and, x14, x17, x2, 0x1, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 0 - li x15, 1 - li x16, -1 - li x17, 0x7FFFFFFF - li x18, 0x80000000 + # address for test results + la x2, test_4_res - # Test - and x14, x13, x14 - and x15, x13, x15 - and x16, x13, x16 - and x17, x13, x17 - and x18, x13, x18 + TEST_RR_OP(and, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_RR_OP(and, x16, x15, x0, 0x0, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(and, x17, x14, x31, 0x1, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_RR_OP(and, x18, x13, x30, 0x0, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(and, x19, x12, x29, 0x5cc, 0x7ff, -0x1234, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x80000000) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + TEST_RR_OP(and, x20, x11, x28, 0x0, 0x0, 0x80000000, x1, 0, x2) # Testcase 20 + TEST_RR_OP(and, x21, x10, x27, 0x0, 0x800, 0x1234, x1, 4, x2) # Testcase 21 + TEST_RR_OP(and, x22, x9, x26, 0x7654321, 0x7654321, 0xffffffff, x1, 8, x2) # Testcase 22 + TEST_RR_OP(and, x23, x8, x25, 0x1, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(and, x24, x7, x24, 0x1, 0x1, 0x7fffffff, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x1) - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test execution - and x19, x18, x19 - and x20, x18, x20 - and x21, x18, x21 - and x22, x18, x22 - and x23, x18, x23 - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Register initialization - li x24, 0 - li x25, 1 - li x26, -1 - li x27, 0x7FFFFFFF - li x28, 0x80000000 - - # Test - and x24, x23, x24 - and x25, x23, x25 - and x26, x23, x26 - and x27, x23, x27 - and x28, x23, x28 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x80000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x25, test_B_data - la x26, test_B_res - - # Load testdata - lw x28, 0(x25) - - # Register initialization - li x4, 0x7F - li x5, 0x3F - li x6, 0x1F - li x7, 0x0F - li x8, 0x07 - li x9, 0x03 - - # Test - and x29, x28, x4 - and x30, x29, x5 - and x31, x30, x6 - and x1, x31, x7 - and x2, x1, x8 - and x3, x2, x9 - - # store results - sw x4, 0(x26) - sw x28, 4(x26) - sw x29, 8(x26) - sw x30, 12(x26) - sw x31, 16(x26) - sw x1, 20(x26) - sw x2, 24(x26) - sw x3, 28(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x4, 0x0000007F) - RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0xABCDFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0x0000007F) - RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0x0000003F) - RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0x0000001F) - RVTEST_IO_ASSERT_GPR_EQ(x26, x1, 0x0000000F) - RVTEST_IO_ASSERT_GPR_EQ(x26, x2, 0x00000007) - RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0x00000003) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - and x0, x28, x27 - - # store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - and x0, x28, x27 - and x5, x0, x0 - - # store results - sw x0, 0(x2) - sw x5, 4(x2) - - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving (and with -1)\n"); + TEST_RR_OP(and, x25, x6, x23, 0x7654321, 0xffffffff, 0x7654321, x1, 0, x7) # Testcase 25 + TEST_RR_OP(and, x26, x5, x22, 0x0, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_RR_OP(and, x27, x4, x21, 0x0, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_RR_OP(and, x28, x3, x20, 0x5cc, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_RR_OP(and, x29, x2, x19, 0xffffffff, -0x1, -0x1, x1, 16, x7) # Testcase 29 - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res - # Load testdata - lw x3, 0(x1) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Register initialization - li x7, 0xFFFFFFFF - # Test - and x4, x3, x7 - and x5, x4, x7 - and x6, x7, x5 - and x14, x6, x7 - and x15, x14, x7 - and x16, x15, x7 - and x25, x7, x16 - and x26, x7, x25 - and x27, x26, x7 + # address for test results + la x2, test_7_res - # Store results - sw x4, 0(x2) - sw x26, 4(x2) - sw x27, 8(x2) + TEST_RR_OP(and, x30, x1, x18, 0x1, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_RR_OP(and, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDFFFF -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x36925814 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 8, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 3, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S index 79b3753..39ff107 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ANDI-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-ANDI-01 +# RISC-V Compliance Test ANDI-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,380 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction ANDI. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'ANDI'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - andi x4, x3, 1 - andi x5, x3, 0x7FF - andi x6, x3, 0xFFFFFFFF - andi x7, x3, 0 - andi x8, x3, 0xFFFFF800 - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + # address for test results + la x5, test_1_res - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) + TEST_IMM_OP(andi, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_IMM_OP(andi, x1, x30, 0x1, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_IMM_OP(andi, x2, x29, 0x0, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_IMM_OP(andi, x3, x28, 0x0, 0x7ff, -0x800, x5, 12, x6) # Testcase 3 + TEST_IMM_OP(andi, x4, x27, 0x0, 0x0, 0x800, x5, 16, x6) # Testcase 4 - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX immediate values\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - # Load testdata - lw x8, 0(x1) + # address for test results + la x1, test_2_res - # Test - andi x9, x8, 1 - andi x10, x8, 0x7FF - andi x11, x8, 0xFFFFFFFF - andi x12, x8, 0 - andi x13, x8, 0xFFFFF800 + TEST_IMM_OP(andi, x5, x26, 0x800, 0x800, 0x800, x1, 0, x2) # Testcase 5 + TEST_IMM_OP(andi, x6, x25, 0x7654000, 0x7654321, 0x800, x1, 4, x2) # Testcase 6 + TEST_IMM_OP(andi, x7, x24, 0x1, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_IMM_OP(andi, x8, x23, 0x0, 0x1, 0x800, x1, 12, x2) # Testcase 8 + TEST_IMM_OP(andi, x9, x22, 0xfffff800, 0xffffffff, 0x800, x1, 16, x2) # Testcase 9 - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX immediate values\n"); + # address for test results + la x1, test_3_res - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + TEST_IMM_OP(andi, x10, x21, 0x1000, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_IMM_OP(andi, x11, x20, 0x0, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_IMM_OP(andi, x12, x19, 0x5cc, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_IMM_OP(andi, x13, x18, 0xffffffff, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_IMM_OP(andi, x14, x17, 0x1, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # Load testdata - lw x13, 0(x1) - # Test - andi x14, x13, 1 - andi x15, x13, 0x7FF - andi x16, x13, 0xFFFFFFFF - andi x17, x13, 0 - andi x18, x13, 0xFFFFF800 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x000007FF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0xFFFFF800) + # address for test results + la x2, test_4_res - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + TEST_IMM_OP(andi, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_IMM_OP(andi, x16, x15, 0x0, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_IMM_OP(andi, x17, x14, 0x1, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_IMM_OP(andi, x18, x13, 0x0, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_IMM_OP(andi, x19, x12, 0x0, 0x7ff, -0x800, x2, 16, x3) # Testcase 19 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - # Load testdata - lw x18, 0(x1) - # Test - andi x19, x18, 1 - andi x20, x18, 0x7FF - andi x21, x18, 0xFFFFFFFF - andi x22, x18, 0 - andi x23, x18, 0xFFFFF800 + # address for test results + la x1, test_5_res - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + TEST_IMM_OP(andi, x20, x11, 0x0, 0x0, 0x800, x1, 0, x2) # Testcase 20 + TEST_IMM_OP(andi, x21, x10, 0x800, 0x800, 0x800, x1, 4, x2) # Testcase 21 + TEST_IMM_OP(andi, x22, x9, 0x7654000, 0x7654321, 0x800, x1, 8, x2) # Testcase 22 + TEST_IMM_OP(andi, x23, x8, 0x1, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_IMM_OP(andi, x24, x7, 0x0, 0x1, 0x800, x1, 16, x2) # Testcase 24 - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x000007FF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x7FFFF800) - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Test - andi x24, x23, 1 - andi x25, x23, 0x7FF - andi x26, x23, 0xFFFFFFFF - andi x27, x23, 0 - andi x28, x23, 0xFFFFF800 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x80000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - - # Load testdata - lw x28, 0(x26) - - # Test - andi x29, x28, 0x7F - andi x30, x29, 0x3F - andi x31, x30, 0x1F - andi x1, x31, 0x0F - andi x2, x1, 0x07 - andi x3, x2, 0x03 - - # Store results - sw x28, 0(x27) - sw x29, 4(x27) - sw x30, 8(x27) - sw x31, 12(x27) - sw x1, 16(x27) - sw x2, 20(x27) - sw x3, 24(x27) - - - RVTEST_IO_ASSERT_GPR_EQ(x27, x28, 0xABCDFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x27, x29, 0x0000007F) - RVTEST_IO_ASSERT_GPR_EQ(x27, x30, 0x0000003F) - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x0000001F) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0x0000000F) - RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0x00000007) - RVTEST_IO_ASSERT_GPR_EQ(x27, x3, 0x00000003) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Test - andi x0, x5, 1 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Test - andi x0, x5, 1 - andi x5, x0, 1 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) + # address for test results + la x1, test_6_res - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + TEST_IMM_OP(andi, x25, x6, 0xfffff800, 0xffffffff, 0x800, x1, 0, x7) # Testcase 25 + TEST_IMM_OP(andi, x26, x5, 0x1000, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_IMM_OP(andi, x27, x4, 0x0, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_IMM_OP(andi, x28, x3, 0x5cc, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_IMM_OP(andi, x29, x2, 0xffffffff, -0x1, -0x1, x1, 16, x7) # Testcase 29 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving (andi with -1)\n"); - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Load testdata - lw x3, 0(x1) - # Test - andi x4, x3, 0xFFFFFFFF - andi x5, x4, 0xFFFFFFFF - andi x6, x5, 0xFFFFFFFF - andi x14, x6, 0xFFFFFFFF - andi x15, x14, 0xFFFFFFFF - andi x16, x15, 0xFFFFFFFF - andi x25, x16, 0xFFFFFFFF - andi x26, x25, 0xFFFFFFFF - andi x27, x26, 0xFFFFFFFF + # address for test results + la x2, test_7_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) + TEST_IMM_OP(andi, x30, x1, 0x1, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_IMM_OP(andi, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDFFFF -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x36925814 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S index 64e4a74..b8e5008 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-AUIPC-01.S
@@ -1,243 +1,391 @@ # RISC-V Compliance Test I-AUIPC-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions -# All rights reserved. # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. +# Copyright (c) 2019 Imperas Software Ltd., www.imperas.com # -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction AUIPC. +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. +# +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +# +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'AUIPC'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A - general test of AUIPC\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x14, test_A_data - la x15, test_A_res + # --------------------------------------------------------------------------------------------- - # Register initialization - lw x1, 0(x14) - li x2, 0x00001004 - li x3, 0xFFFFF008 - li x4, 0x7FFFF00C - li x5, 0x80000010 + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - add x2, x1, x2 - add x3, x1, x3 - add x4, x1, x4 - add x5, x1, x5 - # Test -test_A: - auipc x6, 0x0 - auipc x7, 0x1 - auipc x16, 0xFFFFF - auipc x29, 0x7FFFF - auipc x31, 0x80000 + # address for test results + la x5, test_1_res - xor x6, x6, x1 - xor x7, x7, x2 - xor x16, x16, x3 - xor x29, x29, x4 - xor x31, x31, x5 + # Testcase 0: imm:0x0, result rd:x0(0x0) +1: + auipc x0, 0x0 + la x7, 1b + sub x0, x0, x7 + sw x0, 0(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x0, 0x0) - # Store results - sw x6, 0(x15) - sw x7, 4(x15) - sw x16, 8(x15) - sw x29, 12(x15) - sw x31, 16(x15) + # Testcase 1: imm:0x0, result rd:x1(0x0) +1: + auipc x1, 0x0 + la x7, 1b + sub x1, x1, x7 + sw x1, 4(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x1, 0x0) - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x15, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x15, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x15, x16, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x15, x29, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x15, x31, 0x00000000) + # Testcase 2: imm:0x7ff, result rd:x2(0x7ff000) +1: + auipc x2, 0x7ff + la x7, 1b + sub x2, x2, x7 + sw x2, 8(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x2, 0x7ff000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # Testcase 3: imm:0x1, result rd:x3(0x1000) +1: + auipc x3, 0x1 + la x7, 1b + sub x3, x3, x7 + sw x3, 12(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x3, 0x1000) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test AUIPC overwrites low bits\n"); + # Testcase 4: imm:0x1234, result rd:x4(0x1234000) +1: + auipc x4, 0x1234 + la x7, 1b + sub x4, x4, x7 + sw x4, 16(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x4, 0x1234000) - # Addresses for test data and results - la x17, test_B_data - la x16, test_B_res - # Register initialization - li x1, 0x11111111 - li x2, 0x22222222 - li x15, 0x33333333 - li x28, 0x44444444 - li x30, 0x55555555 - lw x3, 0(x17) - li x4, 0x80000000 - li x5, 0x7FFFF004 - li x6, 0x00000008 - li x7, 0x0000100C - li x8, 0xFFFFF010 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - add x4, x3, x4 - add x5, x3, x5 - add x6, x3, x6 - add x7, x3, x7 - add x8, x3, x8 - # Test -test_B: - auipc x1, 0x80000 - auipc x2, 0x7FFFF - auipc x15, 0 - auipc x28, 1 - auipc x30, 0xFFFFF + # address for test results + la x1, test_2_res - xor x1, x1, x4 - xor x2, x2, x5 - xor x15, x15, x6 - xor x28, x28, x7 - xor x30, x30, x8 + # Testcase 5: imm:0x80000, result rd:x5(0x80000000) +1: + auipc x5, 0x80000 + la x3, 1b + sub x5, x5, x3 + sw x5, 0(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x80000000) - # Store results - sw x1, 0(x16) - sw x2, 4(x16) - sw x15, 8(x16) - sw x28, 12(x16) - sw x30, 16(x16) + # Testcase 6: imm:0x1234, result rd:x6(0x1234000) +1: + auipc x6, 0x1234 + la x3, 1b + sub x6, x6, x3 + sw x6, 4(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x1234000) - RVTEST_IO_ASSERT_GPR_EQ(x16, x1, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x16, x2, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x16, x15, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x16, x28, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x16, x30, 0x00000000) + # Testcase 7: imm:0xfffff, result rd:x7(0xfffff000) +1: + auipc x7, 0xfffff + la x3, 1b + sub x7, x7, x3 + sw x7, 8(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0xfffff000) - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + # Testcase 8: imm:0x1, result rd:x8(0x1000) +1: + auipc x8, 0x1 + la x3, 1b + sub x8, x8, x3 + sw x8, 12(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x1000) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test loading address using auipc + addi or la alias\n"); + # Testcase 9: imm:0x7ffff, result rd:x9(0x7ffff000) +1: + auipc x9, 0x7ffff + la x3, 1b + sub x9, x9, x3 + sw x9, 16(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x7ffff000) - # Addresses for test data and results - la x18, test_C_data - la x17, test_C_res -test_C1: - # Register initialization - lw x1, 0(x18) - lw x2, 4(x18) - lw x3, 8(x18) - # Test - la x4, test_C1 - la x15, test_C2 - la x30, test_C3 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # C1 - auipc x5, 0x0 - addi x5, x5, 0xFFFFFFDC -test_C2: - # C2 - auipc x16, 0x0 - addi x16, x16, 0x0 + # address for test results + la x1, test_3_res - # C3 - auipc x31, 0x0 - addi x31, x31, 0x28 + # Testcase 10: imm:0x54321, result rd:x10(0x54321000) +1: + auipc x10, 0x54321 + la x8, 1b + sub x10, x10, x8 + sw x10, 0(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x10, 0x54321000) - xor x4, x4, x1 - xor x15, x15, x2 - xor x30, x30, x3 - sub x5, x5, x1 - xor x16, x16, x2 - xor x31, x31, x3 + # Testcase 11: imm:0x800, result rd:x11(0x800000) +1: + auipc x11, 0x800 + la x8, 1b + sub x11, x11, x8 + sw x11, 4(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x11, 0x800000) - # Store results - sw x4, 0(x17) - sw x15, 4(x17) -test_C3: - sw x30, 8(x17) - sw x5, 12(x17) - sw x16, 16(x17) - sw x31, 20(x17) + # Testcase 12: imm:0x0, result rd:x12(0x0) +1: + auipc x12, 0x0 + la x8, 1b + sub x12, x12, x8 + sw x12, 8(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x12, 0x0) - RVTEST_IO_ASSERT_GPR_EQ(x17, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x17, x15, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x17, x29, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x17, x5, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x17, x16, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x17, x31, 0x00000000) + # Testcase 13: imm:0x7ff, result rd:x13(0x7ff000) +1: + auipc x13, 0x7ff + la x8, 1b + sub x13, x13, x8 + sw x13, 12(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x13, 0x7ff000) - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + # Testcase 14: imm:0x0, result rd:x14(0x0) +1: + auipc x14, 0x0 + la x8, 1b + sub x14, x14, x8 + sw x14, 16(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x14, 0x0) - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # address for test results + la x2, test_4_res + + # Testcase 15: imm:0x1, result rd:x15(0x1000) +1: + auipc x15, 0x1 + la x4, 1b + sub x15, x15, x4 + sw x15, 0(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x15, 0x1000) + + # Testcase 16: imm:0x0, result rd:x16(0x0) +1: + auipc x16, 0x0 + la x4, 1b + sub x16, x16, x4 + sw x16, 4(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x16, 0x0) + + # Testcase 17: imm:0x0, result rd:x17(0x0) +1: + auipc x17, 0x0 + la x4, 1b + sub x17, x17, x4 + sw x17, 8(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x17, 0x0) + + # Testcase 18: imm:0x7ff, result rd:x18(0x7ff000) +1: + auipc x18, 0x7ff + la x4, 1b + sub x18, x18, x4 + sw x18, 12(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x18, 0x7ff000) + + # Testcase 19: imm:0x1, result rd:x19(0x1000) +1: + auipc x19, 0x1 + la x4, 1b + sub x19, x19, x4 + sw x19, 16(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x19, 0x1000) + + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x1, test_5_res + + # Testcase 20: imm:0x1234, result rd:x20(0x1234000) +1: + auipc x20, 0x1234 + la x3, 1b + sub x20, x20, x3 + sw x20, 0(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x1234000) + + # Testcase 21: imm:0x80000, result rd:x21(0x80000000) +1: + auipc x21, 0x80000 + la x3, 1b + sub x21, x21, x3 + sw x21, 4(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x80000000) + + # Testcase 22: imm:0x1234, result rd:x22(0x1234000) +1: + auipc x22, 0x1234 + la x3, 1b + sub x22, x22, x3 + sw x22, 8(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x1234000) + + # Testcase 23: imm:0xfffff, result rd:x23(0xfffff000) +1: + auipc x23, 0xfffff + la x3, 1b + sub x23, x23, x3 + sw x23, 12(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0xfffff000) + + # Testcase 24: imm:0x1, result rd:x24(0x1000) +1: + auipc x24, 0x1 + la x3, 1b + sub x24, x24, x3 + sw x24, 16(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x1000) + + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x1, test_6_res + + # Testcase 25: imm:0x7ffff, result rd:x25(0x7ffff000) +1: + auipc x25, 0x7ffff + la x8, 1b + sub x25, x25, x8 + sw x25, 0(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x25, 0x7ffff000) + + # Testcase 26: imm:0x54321, result rd:x26(0x54321000) +1: + auipc x26, 0x54321 + la x8, 1b + sub x26, x26, x8 + sw x26, 4(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x26, 0x54321000) + + # Testcase 27: imm:0x800, result rd:x27(0x800000) +1: + auipc x27, 0x800 + la x8, 1b + sub x27, x27, x8 + sw x27, 8(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x27, 0x800000) + + # Testcase 28: imm:0x0, result rd:x28(0x0) +1: + auipc x28, 0x0 + la x8, 1b + sub x28, x28, x8 + sw x28, 12(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x28, 0x0) + + # Testcase 29: imm:0x7ff, result rd:x29(0x7ff000) +1: + auipc x29, 0x7ff + la x8, 1b + sub x29, x29, x8 + sw x29, 16(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x29, 0x7ff000) + + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x2, test_7_res + + # Testcase 30: imm:0x0, result rd:x30(0x0) +1: + auipc x30, 0x0 + la x4, 1b + sub x30, x30, x4 + sw x30, 0(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x30, 0x0) + + # Testcase 31: imm:0x1, result rd:x31(0x1000) +1: + auipc x31, 0x1 + la x4, 1b + sub x31, x31, x4 + sw x31, 4(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x31, 0x1000) + + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A_data: - .word test_A -test_B_data: - .word test_B -test_C_data: - .word test_C1 - .word test_C2 - .word test_C3 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A_res: - .fill 5, 4, -1 -test_B_res: - .fill 5, 4, -1 -test_C_res: - .fill 6, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S index e4a97d5..acf1cf0 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BEQ-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-BEQ-01 +# RISC-V Compliance Test BEQ-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,456 +10,487 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction BEQ. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'BEQ'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - li x31, 0 - # Test - beq x3, x4, 1f - ori x31, x31, 0x1 -1: - beq x3, x5, 1f - ori x31, x31, 0x2 -1: - beq x3, x6, 1f - ori x31, x31, 0x4 -1: - beq x3, x7, 1f - ori x31, x31, 0x8 -1: - beq x3, x8, 1f - ori x31, x31, 0x10 -1: + # address for test results + la x2, test_1_res + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 0, \ + li x1, 0xcccc; \ + li x31, -0x1; \ + li x16, 0x0; \ + beq x31, x16, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 4, \ + li x1, 0xcccc; \ + li x30, 0x1; \ + li x15, -0x7ff; \ + beq x30, x15, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) - sw x31, 24(x2) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000001E) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - - # Load testdata - lw x6, 0(x1) - - # Register initialization - li x7, 0 - li x8, 1 - li x9, -1 - li x10, 0x7FFFFFFF - li x11, 0x80000000 - li x31, 0 - - # Test - beq x6, x7, 1f - ori x31, x31, 0x1 -1: - beq x6, x8, 1f - ori x31, x31, 0x2 -1: - beq x6, x9, 1f - ori x31, x31, 0x4 -1: - beq x6, x10, 1f - ori x31, x31, 0x8 -1: - beq x6, x11, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x6, 0(x2) - sw x7, 4(x2) - sw x8, 8(x2) - sw x9, 12(x2) - sw x10, 16(x2) - sw x11, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000001D) - - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res - - # Load testdata - lw x12, 0(x1) - - # Register initialization - li x13, 0 - li x14, 1 - li x15, -1 - li x16, 0x7FFFFFFF - li x17, 0x80000000 - li x31, 0 - - # Test - beq x12, x13, 1f - ori x31, x31, 0x1 -1: - beq x12, x14, 1f - ori x31, x31, 0x2 -1: - beq x12, x15, 1f - ori x31, x31, 0x4 -1: - beq x12, x16, 1f - ori x31, x31, 0x8 -1: - beq x12, x17, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x12, 0(x2) - sw x13, 4(x2) - sw x14, 8(x2) - sw x15, 12(x2) - sw x16, 16(x2) - sw x17, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000001B) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res - - # Load testdata - lw x18, 0(x1) - - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 - li x31, 0 - - # Test - beq x18, x19, 1f - ori x31, x31, 0x1 -1: - beq x18, x20, 1f - ori x31, x31, 0x2 -1: - beq x18, x21, 1f - ori x31, x31, 0x4 -1: - beq x18, x22, 1f - ori x31, x31, 0x8 -1: - beq x18, x23, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000017) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x24, 0(x1) - - # Register initialization - li x25, 0 - li x26, 1 - li x27, -1 - li x28, 0x7FFFFFFF - li x29, 0x80000000 - li x31, 0 - - # Test - beq x24, x25, 1f - ori x31, x31, 0x1 -1: - beq x24, x26, 1f - ori x31, x31, 0x2 -1: - beq x24, x27, 1f - ori x31, x31, 0x4 -1: - beq x24, x28, 1f - ori x31, x31, 0x8 -1: - beq x24, x29, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x24, 0(x2) - sw x25, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) - sw x28, 16(x2) - sw x29, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x29, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000000F) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing compare with x0\n"); - - # Address for test results - la x27, test_B_res - - # Register initialization - li x1, 0 - li x2, 1 - li x3, -1 - li x4, 0x7FFFFFFF - li x5, 0x80000000 - li x31, 0 - - # Test - beq x1, x0, 1f - ori x31, x31, 0x1 -1: - beq x2, x0, 1f - ori x31, x31, 0x2 -1: - beq x3, x0, 1f - ori x31, x31, 0x4 -1: - beq x4, x0, 1f - ori x31, x31, 0x8 -1: - beq x5, x0, 1f - ori x31, x31, 0x10 -1: - beq x0, x1, 1f - ori x31, x31, 0x20 -1: - beq x0, x2, 1f - ori x31, x31, 0x40 -1: - beq x0, x3, 1f - ori x31, x31, 0x80 -1: - beq x0, x4, 1f - ori x31, x31, 0x100 -1: - beq x0, x5, 1f - ori x31, x31, 0x200 -1: - - # Store results - sw x31, 0(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x000003DE) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - jumps forward, backward\n"); - - # Address for test data and results - la x21, test_C_data - la x22, test_C_res - - # Load testdata - lw x31, 0(x21) - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0x0FEDCBA9 - - # Test - beq x31, x0, 2f - li x2, 0 - li x3, 0 - li x4, 0 - -1: - li x3, 0x87654321 - beq x31, x0, 3f - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 3f 2: - li x2, 0x9ABCDEF0 - beq x31, x0, 1b - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 4f 3: + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 8, \ + li x1, 0xcccc; \ + li x29, 0x0; \ + li x14, -0x1; \ + beq x29, x14, 2b; \ + li x1, 0x123ab; \ +4: \ + ) - # Store results - sw x0, 0(x22) - sw x2, 4(x22) - sw x3, 8(x22) - sw x4, 12(x22) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 12, \ + li x1, 0xcccc; \ + li x28, 0x7ff; \ + li x13, -0x1234; \ + beq x28, x13, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 16, \ + li x1, 0xcccc; \ + li x27, 0x0; \ + li x12, 0x80000000; \ + beq x27, x12, 5f; \ + li x1, 0x123ab; \ +5: \ + ) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x22, x2, 0x9ABCDEF0) - RVTEST_IO_ASSERT_GPR_EQ(x22, x3, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x22, x4, 0x0FEDCBA9) - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + # address for test results + la x2, test_2_res + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 0, \ + li x1, 0xcccc; \ + li x26, 0x800; \ + li x11, 0x1234; \ + beq x26, x11, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 4, \ + li x1, 0xcccc; \ + li x25, 0x7654321; \ + li x10, 0xffffffff; \ + beq x25, x10, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 8, \ + li x1, 0xcccc; \ + li x24, 0x7fffffff; \ + li x9, 0x1; \ + beq x24, x9, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 12, \ + li x1, 0xcccc; \ + li x23, 0x1; \ + li x8, 0x7fffffff; \ + beq x23, x8, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 16, \ + li x1, 0xcccc; \ + li x22, 0xffffffff; \ + li x7, 0x7654321; \ + beq x22, x7, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") + + + # address for test results + la x7, test_3_res + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 0, \ + li x1, 0xcccc; \ + li x21, 0x1234; \ + li x6, 0x800; \ + beq x21, x6, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 4, \ + li x1, 0xcccc; \ + li x20, 0x80000000; \ + li x5, 0x0; \ + beq x20, x5, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 8, \ + li x1, 0xcccc; \ + li x19, -0x1234; \ + li x4, 0x7ff; \ + beq x19, x4, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 12, \ + li x1, 0xcccc; \ + li x18, -0x1; \ + li x3, -0x1; \ + beq x18, x3, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 16, \ + li x1, 0xcccc; \ + li x17, -0x7ff; \ + li x2, 0x1; \ + beq x17, x2, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # address for test results + la x3, test_4_res + + + // Result = 1 + TEST_CASE(x4, x2, 0xcccc, x3, 0, \ + li x2, 0xcccc; \ + li x16, 0x0; \ + li x1, 0x0; \ + beq x16, x1, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 4, \ + li x1, 0xcccc; \ + li x15, -0x1; \ + li x0, 0x0; \ + beq x15, x0, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 8, \ + li x1, 0xcccc; \ + li x14, 0x1; \ + li x31, -0x7ff; \ + beq x14, x31, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 12, \ + li x1, 0xcccc; \ + li x13, 0x0; \ + li x30, -0x1; \ + beq x13, x30, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 16, \ + li x1, 0xcccc; \ + li x12, 0x7ff; \ + li x29, -0x1234; \ + beq x12, x29, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x2, test_5_res + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 0, \ + li x1, 0xcccc; \ + li x11, 0x0; \ + li x28, 0x80000000; \ + beq x11, x28, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 4, \ + li x1, 0xcccc; \ + li x10, 0x800; \ + li x27, 0x1234; \ + beq x10, x27, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 8, \ + li x1, 0xcccc; \ + li x9, 0x7654321; \ + li x26, 0xffffffff; \ + beq x9, x26, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 12, \ + li x1, 0xcccc; \ + li x8, 0x7fffffff; \ + li x25, 0x1; \ + beq x8, x25, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 16, \ + li x1, 0xcccc; \ + li x7, 0x1; \ + li x24, 0x7fffffff; \ + beq x7, x24, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x7, test_6_res + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 0, \ + li x1, 0xcccc; \ + li x6, 0xffffffff; \ + li x23, 0x7654321; \ + beq x6, x23, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 4, \ + li x1, 0xcccc; \ + li x5, 0x1234; \ + li x22, 0x800; \ + beq x5, x22, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 8, \ + li x1, 0xcccc; \ + li x4, 0x80000000; \ + li x21, 0x0; \ + beq x4, x21, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 12, \ + li x1, 0xcccc; \ + li x3, -0x1234; \ + li x20, 0x7ff; \ + beq x3, x20, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 16, \ + li x1, 0xcccc; \ + li x2, -0x1; \ + li x19, -0x1; \ + beq x2, x19, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x3, test_7_res + + + // Result = 0 + TEST_CASE(x4, x2, 0x123ab, x3, 0, \ + li x2, 0xcccc; \ + li x1, -0x7ff; \ + li x18, 0x1; \ + beq x1, x18, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 4, \ + li x1, 0xcccc; \ + li x0, 0x0; \ + li x17, 0x0; \ + beq x0, x17, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_C_data: - .word 0 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 7, 4, -1 -test_A2_res: - .fill 7, 4, -1 -test_A3_res: - .fill 7, 4, -1 -test_A4_res: - .fill 7, 4, -1 -test_A5_res: - .fill 7, 4, -1 -test_B_res: - .fill 1, 4, -1 -test_C_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BGE-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BGE-01.S index 3873a9f..edbe3d0 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BGE-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BGE-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-BGE-01 +# RISC-V Compliance Test BGE-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,456 +10,487 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction BGE. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'BGE'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - li x31, 0 - # Test - bge x3, x4, 1f - ori x31, x31, 0x1 -1: - bge x3, x5, 1f - ori x31, x31, 0x2 -1: - bge x3, x6, 1f - ori x31, x31, 0x4 -1: - bge x3, x7, 1f - ori x31, x31, 0x8 -1: - bge x3, x8, 1f - ori x31, x31, 0x10 -1: + # address for test results + la x2, test_1_res + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 0, \ + li x1, 0xcccc; \ + li x31, -0x1; \ + li x16, 0x0; \ + bge x31, x16, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 4, \ + li x1, 0xcccc; \ + li x30, 0x1; \ + li x15, -0x7ff; \ + bge x30, x15, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) - sw x31, 24(x2) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000000A) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - - # Load testdata - lw x6, 0(x1) - - # Register initialization - li x7, 0 - li x8, 1 - li x9, -1 - li x10, 0x7FFFFFFF - li x11, 0x80000000 - li x31, 0 - - # Test - bge x6, x7, 1f - ori x31, x31, 0x1 -1: - bge x6, x8, 1f - ori x31, x31, 0x2 -1: - bge x6, x9, 1f - ori x31, x31, 0x4 -1: - bge x6, x10, 1f - ori x31, x31, 0x8 -1: - bge x6, x11, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x6, 0(x2) - sw x7, 4(x2) - sw x8, 8(x2) - sw x9, 12(x2) - sw x10, 16(x2) - sw x11, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000008) - - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res - - # Load testdata - lw x12, 0(x1) - - # Register initialization - li x13, 0 - li x14, 1 - li x15, -1 - li x16, 0x7FFFFFFF - li x17, 0x80000000 - li x31, 0 - - # Test - bge x12, x13, 1f - ori x31, x31, 0x1 -1: - bge x12, x14, 1f - ori x31, x31, 0x2 -1: - bge x12, x15, 1f - ori x31, x31, 0x4 -1: - bge x12, x16, 1f - ori x31, x31, 0x8 -1: - bge x12, x17, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x12, 0(x2) - sw x13, 4(x2) - sw x14, 8(x2) - sw x15, 12(x2) - sw x16, 16(x2) - sw x17, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000000B) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res - - # Load testdata - lw x18, 0(x1) - - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 - li x31, 0 - - # Test - bge x18, x19, 1f - ori x31, x31, 0x1 -1: - bge x18, x20, 1f - ori x31, x31, 0x2 -1: - bge x18, x21, 1f - ori x31, x31, 0x4 -1: - bge x18, x22, 1f - ori x31, x31, 0x8 -1: - bge x18, x23, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x24, 0(x1) - - # Register initialization - li x25, 0 - li x26, 1 - li x27, -1 - li x28, 0x7FFFFFFF - li x29, 0x80000000 - li x31, 0 - - # Test - bge x24, x25, 1f - ori x31, x31, 0x1 -1: - bge x24, x26, 1f - ori x31, x31, 0x2 -1: - bge x24, x27, 1f - ori x31, x31, 0x4 -1: - bge x24, x28, 1f - ori x31, x31, 0x8 -1: - bge x24, x29, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x24, 0(x2) - sw x25, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) - sw x28, 16(x2) - sw x29, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x29, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000000F) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing compare with x0\n"); - - # Address for test results - la x27, test_B_res - - # Register initialization - li x1, 0 - li x2, 1 - li x3, -1 - li x4, 0x7FFFFFFF - li x5, 0x80000000 - li x31, 0 - - # Test - bge x1, x0, 1f - ori x31, x31, 0x1 -1: - bge x2, x0, 1f - ori x31, x31, 0x2 -1: - bge x3, x0, 1f - ori x31, x31, 0x4 -1: - bge x4, x0, 1f - ori x31, x31, 0x8 -1: - bge x5, x0, 1f - ori x31, x31, 0x10 -1: - bge x0, x1, 1f - ori x31, x31, 0x20 -1: - bge x0, x2, 1f - ori x31, x31, 0x40 -1: - bge x0, x3, 1f - ori x31, x31, 0x80 -1: - bge x0, x4, 1f - ori x31, x31, 0x100 -1: - bge x0, x5, 1f - ori x31, x31, 0x200 -1: - - # Store results - sw x31, 0(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x000000154) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - jumps forward, backward\n"); - - # Address for test data and results - la x21, test_C_data - la x22, test_C_res - - # Load testdata - lw x31, 0(x21) - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0x0FEDCBA9 - - # Test - bge x31, x0, 2f - li x2, 0 - li x3, 0 - li x4, 0 - -1: - li x3, 0x87654321 - bge x31, x0, 3f - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 3f 2: - li x2, 0x9ABCDEF0 - bge x31, x0, 1b - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 4f 3: + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 8, \ + li x1, 0xcccc; \ + li x29, 0x0; \ + li x14, -0x1; \ + bge x29, x14, 2b; \ + li x1, 0x123ab; \ +4: \ + ) - # Store results - sw x0, 0(x22) - sw x2, 4(x22) - sw x3, 8(x22) - sw x4, 12(x22) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 12, \ + li x1, 0xcccc; \ + li x28, 0x7ff; \ + li x13, -0x1234; \ + bge x28, x13, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 16, \ + li x1, 0xcccc; \ + li x27, 0x0; \ + li x12, 0x80000000; \ + bge x27, x12, 5f; \ + li x1, 0x123ab; \ +5: \ + ) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x22, x2, 0x9ABCDEF0) - RVTEST_IO_ASSERT_GPR_EQ(x22, x3, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x22, x4, 0x0FEDCBA9) - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + # address for test results + la x2, test_2_res + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 0, \ + li x1, 0xcccc; \ + li x26, 0x800; \ + li x11, 0x1234; \ + bge x26, x11, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 4, \ + li x1, 0xcccc; \ + li x25, 0x7654321; \ + li x10, 0xffffffff; \ + bge x25, x10, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 8, \ + li x1, 0xcccc; \ + li x24, 0x7fffffff; \ + li x9, 0x1; \ + bge x24, x9, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 12, \ + li x1, 0xcccc; \ + li x23, 0x1; \ + li x8, 0x7fffffff; \ + bge x23, x8, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 16, \ + li x1, 0xcccc; \ + li x22, 0xffffffff; \ + li x7, 0x7654321; \ + bge x22, x7, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") + + + # address for test results + la x7, test_3_res + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 0, \ + li x1, 0xcccc; \ + li x21, 0x1234; \ + li x6, 0x800; \ + bge x21, x6, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 4, \ + li x1, 0xcccc; \ + li x20, 0x80000000; \ + li x5, 0x0; \ + bge x20, x5, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 8, \ + li x1, 0xcccc; \ + li x19, -0x1234; \ + li x4, 0x7ff; \ + bge x19, x4, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 12, \ + li x1, 0xcccc; \ + li x18, -0x1; \ + li x3, -0x1; \ + bge x18, x3, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 16, \ + li x1, 0xcccc; \ + li x17, -0x7ff; \ + li x2, 0x1; \ + bge x17, x2, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # address for test results + la x3, test_4_res + + + // Result = 1 + TEST_CASE(x4, x2, 0xcccc, x3, 0, \ + li x2, 0xcccc; \ + li x16, 0x0; \ + li x1, 0x0; \ + bge x16, x1, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 4, \ + li x1, 0xcccc; \ + li x15, -0x1; \ + li x0, 0x0; \ + bge x15, x0, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 8, \ + li x1, 0xcccc; \ + li x14, 0x1; \ + li x31, -0x7ff; \ + bge x14, x31, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 12, \ + li x1, 0xcccc; \ + li x13, 0x0; \ + li x30, -0x1; \ + bge x13, x30, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 16, \ + li x1, 0xcccc; \ + li x12, 0x7ff; \ + li x29, -0x1234; \ + bge x12, x29, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x2, test_5_res + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + li x11, 0x0; \ + li x28, 0x80000000; \ + bge x11, x28, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 4, \ + li x1, 0xcccc; \ + li x10, 0x800; \ + li x27, 0x1234; \ + bge x10, x27, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 8, \ + li x1, 0xcccc; \ + li x9, 0x7654321; \ + li x26, 0xffffffff; \ + bge x9, x26, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 12, \ + li x1, 0xcccc; \ + li x8, 0x7fffffff; \ + li x25, 0x1; \ + bge x8, x25, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 16, \ + li x1, 0xcccc; \ + li x7, 0x1; \ + li x24, 0x7fffffff; \ + bge x7, x24, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x7, test_6_res + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 0, \ + li x1, 0xcccc; \ + li x6, 0xffffffff; \ + li x23, 0x7654321; \ + bge x6, x23, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 4, \ + li x1, 0xcccc; \ + li x5, 0x1234; \ + li x22, 0x800; \ + bge x5, x22, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 8, \ + li x1, 0xcccc; \ + li x4, 0x80000000; \ + li x21, 0x0; \ + bge x4, x21, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 12, \ + li x1, 0xcccc; \ + li x3, -0x1234; \ + li x20, 0x7ff; \ + bge x3, x20, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 16, \ + li x1, 0xcccc; \ + li x2, -0x1; \ + li x19, -0x1; \ + bge x2, x19, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x3, test_7_res + + + // Result = 0 + TEST_CASE(x4, x2, 0x123ab, x3, 0, \ + li x2, 0xcccc; \ + li x1, -0x7ff; \ + li x18, 0x1; \ + bge x1, x18, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 4, \ + li x1, 0xcccc; \ + li x0, 0x0; \ + li x17, 0x0; \ + bge x0, x17, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_C_data: - .word 1 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 7, 4, -1 -test_A2_res: - .fill 7, 4, -1 -test_A3_res: - .fill 7, 4, -1 -test_A4_res: - .fill 7, 4, -1 -test_A5_res: - .fill 7, 4, -1 -test_B_res: - .fill 1, 4, -1 -test_C_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S index d0e275a..7497981 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BGEU-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-BGEU-01 +# RISC-V Compliance Test BGEU-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,456 +10,487 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction BGEU. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'BGEU'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - li x31, 0 - # Test - bgeu x3, x4, 1f - ori x31, x31, 0x1 -1: - bgeu x3, x5, 1f - ori x31, x31, 0x2 -1: - bgeu x3, x6, 1f - ori x31, x31, 0x4 -1: - bgeu x3, x7, 1f - ori x31, x31, 0x8 -1: - bgeu x3, x8, 1f - ori x31, x31, 0x10 -1: + # address for test results + la x2, test_1_res + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + li x31, -0x1; \ + li x16, 0x0; \ + bgeu x31, x16, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 4, \ + li x1, 0xcccc; \ + li x30, 0x1; \ + li x15, -0x7ff; \ + bgeu x30, x15, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) - sw x31, 24(x2) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000001E) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - - # Load testdata - lw x6, 0(x1) - - # Register initialization - li x7, 0 - li x8, 1 - li x9, -1 - li x10, 0x7FFFFFFF - li x11, 0x80000000 - li x31, 0 - - # Test - bgeu x6, x7, 1f - ori x31, x31, 0x1 -1: - bgeu x6, x8, 1f - ori x31, x31, 0x2 -1: - bgeu x6, x9, 1f - ori x31, x31, 0x4 -1: - bgeu x6, x10, 1f - ori x31, x31, 0x8 -1: - bgeu x6, x11, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x6, 0(x2) - sw x7, 4(x2) - sw x8, 8(x2) - sw x9, 12(x2) - sw x10, 16(x2) - sw x11, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000001C) - - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res - - # Load testdata - lw x12, 0(x1) - - # Register initialization - li x13, 0 - li x14, 1 - li x15, -1 - li x16, 0x7FFFFFFF - li x17, 0x80000000 - li x31, 0 - - # Test - bgeu x12, x13, 1f - ori x31, x31, 0x1 -1: - bgeu x12, x14, 1f - ori x31, x31, 0x2 -1: - bgeu x12, x15, 1f - ori x31, x31, 0x4 -1: - bgeu x12, x16, 1f - ori x31, x31, 0x8 -1: - bgeu x12, x17, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x12, 0(x2) - sw x13, 4(x2) - sw x14, 8(x2) - sw x15, 12(x2) - sw x16, 16(x2) - sw x17, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res - - # Load testdata - lw x18, 0(x1) - - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 - li x31, 0 - - # Test - bgeu x18, x19, 1f - ori x31, x31, 0x1 -1: - bgeu x18, x20, 1f - ori x31, x31, 0x2 -1: - bgeu x18, x21, 1f - ori x31, x31, 0x4 -1: - bgeu x18, x22, 1f - ori x31, x31, 0x8 -1: - bgeu x18, x23, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000014) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x24, 0(x1) - - # Register initialization - li x25, 0 - li x26, 1 - li x27, -1 - li x28, 0x7FFFFFFF - li x29, 0x80000000 - li x31, 0 - - # Test - bgeu x24, x25, 1f - ori x31, x31, 0x1 -1: - bgeu x24, x26, 1f - ori x31, x31, 0x2 -1: - bgeu x24, x27, 1f - ori x31, x31, 0x4 -1: - bgeu x24, x28, 1f - ori x31, x31, 0x8 -1: - bgeu x24, x29, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x24, 0(x2) - sw x25, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) - sw x28, 16(x2) - sw x29, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x29, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000004) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing compare with x0\n"); - - # Address for test results - la x27, test_B_res - - # Register initialization - li x1, 0 - li x2, 1 - li x3, -1 - li x4, 0x7FFFFFFF - li x5, 0x80000000 - li x31, 0 - - # Test - bgeu x1, x0, 1f - ori x31, x31, 0x1 -1: - bgeu x2, x0, 1f - ori x31, x31, 0x2 -1: - bgeu x3, x0, 1f - ori x31, x31, 0x4 -1: - bgeu x4, x0, 1f - ori x31, x31, 0x8 -1: - bgeu x5, x0, 1f - ori x31, x31, 0x10 -1: - bgeu x0, x1, 1f - ori x31, x31, 0x20 -1: - bgeu x0, x2, 1f - ori x31, x31, 0x40 -1: - bgeu x0, x3, 1f - ori x31, x31, 0x80 -1: - bgeu x0, x4, 1f - ori x31, x31, 0x100 -1: - bgeu x0, x5, 1f - ori x31, x31, 0x200 -1: - - # Store results - sw x31, 0(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x000003C0) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - jumps forward, backward\n"); - - # Address for test data and results - la x21, test_C_data - la x22, test_C_res - - # Load testdata - lw x31, 0(x21) - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0x0FEDCBA9 - - # Test - bgeu x31, x0, 2f - li x2, 0 - li x3, 0 - li x4, 0 - -1: - li x3, 0x87654321 - bgeu x31, x0, 3f - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 3f 2: - li x2, 0x9ABCDEF0 - bgeu x31, x0, 1b - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 4f 3: + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 8, \ + li x1, 0xcccc; \ + li x29, 0x0; \ + li x14, -0x1; \ + bgeu x29, x14, 2b; \ + li x1, 0x123ab; \ +4: \ + ) - # Store results - sw x0, 0(x22) - sw x2, 4(x22) - sw x3, 8(x22) - sw x4, 12(x22) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 12, \ + li x1, 0xcccc; \ + li x28, 0x7ff; \ + li x13, -0x1234; \ + bgeu x28, x13, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 16, \ + li x1, 0xcccc; \ + li x27, 0x0; \ + li x12, 0x80000000; \ + bgeu x27, x12, 5f; \ + li x1, 0x123ab; \ +5: \ + ) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x22, x2, 0x9ABCDEF0) - RVTEST_IO_ASSERT_GPR_EQ(x22, x3, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x22, x4, 0x0FEDCBA9) - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + # address for test results + la x2, test_2_res + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 0, \ + li x1, 0xcccc; \ + li x26, 0x800; \ + li x11, 0x1234; \ + bgeu x26, x11, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 4, \ + li x1, 0xcccc; \ + li x25, 0x7654321; \ + li x10, 0xffffffff; \ + bgeu x25, x10, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 8, \ + li x1, 0xcccc; \ + li x24, 0x7fffffff; \ + li x9, 0x1; \ + bgeu x24, x9, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 12, \ + li x1, 0xcccc; \ + li x23, 0x1; \ + li x8, 0x7fffffff; \ + bgeu x23, x8, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 16, \ + li x1, 0xcccc; \ + li x22, 0xffffffff; \ + li x7, 0x7654321; \ + bgeu x22, x7, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") + + + # address for test results + la x7, test_3_res + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 0, \ + li x1, 0xcccc; \ + li x21, 0x1234; \ + li x6, 0x800; \ + bgeu x21, x6, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 4, \ + li x1, 0xcccc; \ + li x20, 0x80000000; \ + li x5, 0x0; \ + bgeu x20, x5, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 8, \ + li x1, 0xcccc; \ + li x19, -0x1234; \ + li x4, 0x7ff; \ + bgeu x19, x4, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 12, \ + li x1, 0xcccc; \ + li x18, -0x1; \ + li x3, -0x1; \ + bgeu x18, x3, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 16, \ + li x1, 0xcccc; \ + li x17, -0x7ff; \ + li x2, 0x1; \ + bgeu x17, x2, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # address for test results + la x3, test_4_res + + + // Result = 1 + TEST_CASE(x4, x2, 0xcccc, x3, 0, \ + li x2, 0xcccc; \ + li x16, 0x0; \ + li x1, 0x0; \ + bgeu x16, x1, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 4, \ + li x1, 0xcccc; \ + li x15, -0x1; \ + li x0, 0x0; \ + bgeu x15, x0, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 8, \ + li x1, 0xcccc; \ + li x14, 0x1; \ + li x31, -0x7ff; \ + bgeu x14, x31, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 12, \ + li x1, 0xcccc; \ + li x13, 0x0; \ + li x30, -0x1; \ + bgeu x13, x30, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 16, \ + li x1, 0xcccc; \ + li x12, 0x7ff; \ + li x29, -0x1234; \ + bgeu x12, x29, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x2, test_5_res + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 0, \ + li x1, 0xcccc; \ + li x11, 0x0; \ + li x28, 0x80000000; \ + bgeu x11, x28, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 4, \ + li x1, 0xcccc; \ + li x10, 0x800; \ + li x27, 0x1234; \ + bgeu x10, x27, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 8, \ + li x1, 0xcccc; \ + li x9, 0x7654321; \ + li x26, 0xffffffff; \ + bgeu x9, x26, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 12, \ + li x1, 0xcccc; \ + li x8, 0x7fffffff; \ + li x25, 0x1; \ + bgeu x8, x25, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 16, \ + li x1, 0xcccc; \ + li x7, 0x1; \ + li x24, 0x7fffffff; \ + bgeu x7, x24, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x7, test_6_res + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 0, \ + li x1, 0xcccc; \ + li x6, 0xffffffff; \ + li x23, 0x7654321; \ + bgeu x6, x23, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 4, \ + li x1, 0xcccc; \ + li x5, 0x1234; \ + li x22, 0x800; \ + bgeu x5, x22, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 8, \ + li x1, 0xcccc; \ + li x4, 0x80000000; \ + li x21, 0x0; \ + bgeu x4, x21, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 12, \ + li x1, 0xcccc; \ + li x3, -0x1234; \ + li x20, 0x7ff; \ + bgeu x3, x20, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 16, \ + li x1, 0xcccc; \ + li x2, -0x1; \ + li x19, -0x1; \ + bgeu x2, x19, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x3, test_7_res + + + // Result = 1 + TEST_CASE(x4, x2, 0xcccc, x3, 0, \ + li x2, 0xcccc; \ + li x1, -0x7ff; \ + li x18, 0x1; \ + bgeu x1, x18, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 4, \ + li x1, 0xcccc; \ + li x0, 0x0; \ + li x17, 0x0; \ + bgeu x0, x17, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_C_data: - .word 1 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 7, 4, -1 -test_A2_res: - .fill 7, 4, -1 -test_A3_res: - .fill 7, 4, -1 -test_A4_res: - .fill 7, 4, -1 -test_A5_res: - .fill 7, 4, -1 -test_B_res: - .fill 1, 4, -1 -test_C_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BLT-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BLT-01.S index 95eac5c..2e402af 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BLT-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BLT-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-BLT-01 +# RISC-V Compliance Test BLT-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,456 +10,487 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction BLT. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'BLT'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - li x31, 0 - # Test - blt x3, x4, 1f - ori x31, x31, 0x1 -1: - blt x3, x5, 1f - ori x31, x31, 0x2 -1: - blt x3, x6, 1f - ori x31, x31, 0x4 -1: - blt x3, x7, 1f - ori x31, x31, 0x8 -1: - blt x3, x8, 1f - ori x31, x31, 0x10 -1: + # address for test results + la x2, test_1_res + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + li x31, -0x1; \ + li x16, 0x0; \ + blt x31, x16, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 4, \ + li x1, 0xcccc; \ + li x30, 0x1; \ + li x15, -0x7ff; \ + blt x30, x15, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) - sw x31, 24(x2) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000015) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - - # Load testdata - lw x6, 0(x1) - - # Register initialization - li x7, 0 - li x8, 1 - li x9, -1 - li x10, 0x7FFFFFFF - li x11, 0x80000000 - li x31, 0 - - # Test - blt x6, x7, 1f - ori x31, x31, 0x1 -1: - blt x6, x8, 1f - ori x31, x31, 0x2 -1: - blt x6, x9, 1f - ori x31, x31, 0x4 -1: - blt x6, x10, 1f - ori x31, x31, 0x8 -1: - blt x6, x11, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x6, 0(x2) - sw x7, 4(x2) - sw x8, 8(x2) - sw x9, 12(x2) - sw x10, 16(x2) - sw x11, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000017) - - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res - - # Load testdata - lw x12, 0(x1) - - # Register initialization - li x13, 0 - li x14, 1 - li x15, -1 - li x16, 0x7FFFFFFF - li x17, 0x80000000 - li x31, 0 - - # Test - blt x12, x13, 1f - ori x31, x31, 0x1 -1: - blt x12, x14, 1f - ori x31, x31, 0x2 -1: - blt x12, x15, 1f - ori x31, x31, 0x4 -1: - blt x12, x16, 1f - ori x31, x31, 0x8 -1: - blt x12, x17, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x12, 0(x2) - sw x13, 4(x2) - sw x14, 8(x2) - sw x15, 12(x2) - sw x16, 16(x2) - sw x17, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000014) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res - - # Load testdata - lw x18, 0(x1) - - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 - li x31, 0 - - # Test - blt x18, x19, 1f - ori x31, x31, 0x1 -1: - blt x18, x20, 1f - ori x31, x31, 0x2 -1: - blt x18, x21, 1f - ori x31, x31, 0x4 -1: - blt x18, x22, 1f - ori x31, x31, 0x8 -1: - blt x18, x23, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000001F) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x24, 0(x1) - - # Register initialization - li x25, 0 - li x26, 1 - li x27, -1 - li x28, 0x7FFFFFFF - li x29, 0x80000000 - li x31, 0 - - # Test - blt x24, x25, 1f - ori x31, x31, 0x1 -1: - blt x24, x26, 1f - ori x31, x31, 0x2 -1: - blt x24, x27, 1f - ori x31, x31, 0x4 -1: - blt x24, x28, 1f - ori x31, x31, 0x8 -1: - blt x24, x29, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x24, 0(x2) - sw x25, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) - sw x28, 16(x2) - sw x29, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x29, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000010) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing compare with x0\n"); - - # Address for test results - la x27, test_B_res - - # Register initialization - li x1, 0 - li x2, 1 - li x3, -1 - li x4, 0x7FFFFFFF - li x5, 0x80000000 - li x31, 0 - - # Test - blt x1, x0, 1f - ori x31, x31, 0x1 -1: - blt x2, x0, 1f - ori x31, x31, 0x2 -1: - blt x3, x0, 1f - ori x31, x31, 0x4 -1: - blt x4, x0, 1f - ori x31, x31, 0x8 -1: - blt x5, x0, 1f - ori x31, x31, 0x10 -1: - blt x0, x1, 1f - ori x31, x31, 0x20 -1: - blt x0, x2, 1f - ori x31, x31, 0x40 -1: - blt x0, x3, 1f - ori x31, x31, 0x80 -1: - blt x0, x4, 1f - ori x31, x31, 0x100 -1: - blt x0, x5, 1f - ori x31, x31, 0x200 -1: - - # Store results - sw x31, 0(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x000002AB) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - jumps forward, backward\n"); - - # Address for test data and results - la x21, test_C_data - la x22, test_C_res - - # Load testdata - lw x31, 0(x21) - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0x0FEDCBA9 - - # Test - blt x31, x0, 2f - li x2, 0 - li x3, 0 - li x4, 0 - -1: - li x3, 0x87654321 - blt x31, x0, 3f - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 3f 2: - li x2, 0x9ABCDEF0 - blt x31, x0, 1b - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 4f 3: + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 8, \ + li x1, 0xcccc; \ + li x29, 0x0; \ + li x14, -0x1; \ + blt x29, x14, 2b; \ + li x1, 0x123ab; \ +4: \ + ) - # Store results - sw x0, 0(x22) - sw x2, 4(x22) - sw x3, 8(x22) - sw x4, 12(x22) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 12, \ + li x1, 0xcccc; \ + li x28, 0x7ff; \ + li x13, -0x1234; \ + blt x28, x13, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 16, \ + li x1, 0xcccc; \ + li x27, 0x0; \ + li x12, 0x80000000; \ + blt x27, x12, 5f; \ + li x1, 0x123ab; \ +5: \ + ) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x22, x2, 0x9ABCDEF0) - RVTEST_IO_ASSERT_GPR_EQ(x22, x3, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x22, x4, 0x0FEDCBA9) - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + # address for test results + la x2, test_2_res + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + li x26, 0x800; \ + li x11, 0x1234; \ + blt x26, x11, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 4, \ + li x1, 0xcccc; \ + li x25, 0x7654321; \ + li x10, 0xffffffff; \ + blt x25, x10, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 8, \ + li x1, 0xcccc; \ + li x24, 0x7fffffff; \ + li x9, 0x1; \ + blt x24, x9, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 12, \ + li x1, 0xcccc; \ + li x23, 0x1; \ + li x8, 0x7fffffff; \ + blt x23, x8, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 16, \ + li x1, 0xcccc; \ + li x22, 0xffffffff; \ + li x7, 0x7654321; \ + blt x22, x7, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") + + + # address for test results + la x7, test_3_res + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 0, \ + li x1, 0xcccc; \ + li x21, 0x1234; \ + li x6, 0x800; \ + blt x21, x6, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 4, \ + li x1, 0xcccc; \ + li x20, 0x80000000; \ + li x5, 0x0; \ + blt x20, x5, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 8, \ + li x1, 0xcccc; \ + li x19, -0x1234; \ + li x4, 0x7ff; \ + blt x19, x4, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 12, \ + li x1, 0xcccc; \ + li x18, -0x1; \ + li x3, -0x1; \ + blt x18, x3, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 16, \ + li x1, 0xcccc; \ + li x17, -0x7ff; \ + li x2, 0x1; \ + blt x17, x2, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # address for test results + la x3, test_4_res + + + // Result = 0 + TEST_CASE(x4, x2, 0x123ab, x3, 0, \ + li x2, 0xcccc; \ + li x16, 0x0; \ + li x1, 0x0; \ + blt x16, x1, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 4, \ + li x1, 0xcccc; \ + li x15, -0x1; \ + li x0, 0x0; \ + blt x15, x0, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 8, \ + li x1, 0xcccc; \ + li x14, 0x1; \ + li x31, -0x7ff; \ + blt x14, x31, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 12, \ + li x1, 0xcccc; \ + li x13, 0x0; \ + li x30, -0x1; \ + blt x13, x30, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 16, \ + li x1, 0xcccc; \ + li x12, 0x7ff; \ + li x29, -0x1234; \ + blt x12, x29, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x2, test_5_res + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 0, \ + li x1, 0xcccc; \ + li x11, 0x0; \ + li x28, 0x80000000; \ + blt x11, x28, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 4, \ + li x1, 0xcccc; \ + li x10, 0x800; \ + li x27, 0x1234; \ + blt x10, x27, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 8, \ + li x1, 0xcccc; \ + li x9, 0x7654321; \ + li x26, 0xffffffff; \ + blt x9, x26, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 12, \ + li x1, 0xcccc; \ + li x8, 0x7fffffff; \ + li x25, 0x1; \ + blt x8, x25, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 16, \ + li x1, 0xcccc; \ + li x7, 0x1; \ + li x24, 0x7fffffff; \ + blt x7, x24, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x7, test_6_res + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 0, \ + li x1, 0xcccc; \ + li x6, 0xffffffff; \ + li x23, 0x7654321; \ + blt x6, x23, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 4, \ + li x1, 0xcccc; \ + li x5, 0x1234; \ + li x22, 0x800; \ + blt x5, x22, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 8, \ + li x1, 0xcccc; \ + li x4, 0x80000000; \ + li x21, 0x0; \ + blt x4, x21, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 12, \ + li x1, 0xcccc; \ + li x3, -0x1234; \ + li x20, 0x7ff; \ + blt x3, x20, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 16, \ + li x1, 0xcccc; \ + li x2, -0x1; \ + li x19, -0x1; \ + blt x2, x19, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x3, test_7_res + + + // Result = 1 + TEST_CASE(x4, x2, 0xcccc, x3, 0, \ + li x2, 0xcccc; \ + li x1, -0x7ff; \ + li x18, 0x1; \ + blt x1, x18, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 4, \ + li x1, 0xcccc; \ + li x0, 0x0; \ + li x17, 0x0; \ + blt x0, x17, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_C_data: - .word -1 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 7, 4, -1 -test_A2_res: - .fill 7, 4, -1 -test_A3_res: - .fill 7, 4, -1 -test_A4_res: - .fill 7, 4, -1 -test_A5_res: - .fill 7, 4, -1 -test_B_res: - .fill 1, 4, -1 -test_C_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S index 0902d53..5e5b285 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BLTU-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-BLTU-01 +# RISC-V Compliance Test BLTU-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,456 +10,487 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction BLTU. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'BLTU'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - li x31, 0 - # Test - bltu x3, x4, 1f - ori x31, x31, 0x1 -1: - bltu x3, x5, 1f - ori x31, x31, 0x2 -1: - bltu x3, x6, 1f - ori x31, x31, 0x4 -1: - bltu x3, x7, 1f - ori x31, x31, 0x8 -1: - bltu x3, x8, 1f - ori x31, x31, 0x10 -1: + # address for test results + la x2, test_1_res + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 0, \ + li x1, 0xcccc; \ + li x31, -0x1; \ + li x16, 0x0; \ + bltu x31, x16, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 4, \ + li x1, 0xcccc; \ + li x30, 0x1; \ + li x15, -0x7ff; \ + bltu x30, x15, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) - sw x31, 24(x2) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - - # Load testdata - lw x6, 0(x1) - - # Register initialization - li x7, 0 - li x8, 1 - li x9, -1 - li x10, 0x7FFFFFFF - li x11, 0x80000000 - li x31, 0 - - # Test - bltu x6, x7, 1f - ori x31, x31, 0x1 -1: - bltu x6, x8, 1f - ori x31, x31, 0x2 -1: - bltu x6, x9, 1f - ori x31, x31, 0x4 -1: - bltu x6, x10, 1f - ori x31, x31, 0x8 -1: - bltu x6, x11, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x6, 0(x2) - sw x7, 4(x2) - sw x8, 8(x2) - sw x9, 12(x2) - sw x10, 16(x2) - sw x11, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000003) - - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res - - # Load testdata - lw x12, 0(x1) - - # Register initialization - li x13, 0 - li x14, 1 - li x15, -1 - li x16, 0x7FFFFFFF - li x17, 0x80000000 - li x31, 0 - - # Test - bltu x12, x13, 1f - ori x31, x31, 0x1 -1: - bltu x12, x14, 1f - ori x31, x31, 0x2 -1: - bltu x12, x15, 1f - ori x31, x31, 0x4 -1: - bltu x12, x16, 1f - ori x31, x31, 0x8 -1: - bltu x12, x17, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x12, 0(x2) - sw x13, 4(x2) - sw x14, 8(x2) - sw x15, 12(x2) - sw x16, 16(x2) - sw x17, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000001F) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res - - # Load testdata - lw x18, 0(x1) - - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 - li x31, 0 - - # Test - bltu x18, x19, 1f - ori x31, x31, 0x1 -1: - bltu x18, x20, 1f - ori x31, x31, 0x2 -1: - bltu x18, x21, 1f - ori x31, x31, 0x4 -1: - bltu x18, x22, 1f - ori x31, x31, 0x8 -1: - bltu x18, x23, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000000B) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x24, 0(x1) - - # Register initialization - li x25, 0 - li x26, 1 - li x27, -1 - li x28, 0x7FFFFFFF - li x29, 0x80000000 - li x31, 0 - - # Test - bltu x24, x25, 1f - ori x31, x31, 0x1 -1: - bltu x24, x26, 1f - ori x31, x31, 0x2 -1: - bltu x24, x27, 1f - ori x31, x31, 0x4 -1: - bltu x24, x28, 1f - ori x31, x31, 0x8 -1: - bltu x24, x29, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x24, 0(x2) - sw x25, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) - sw x28, 16(x2) - sw x29, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x29, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x0000001B) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing compare with x0\n"); - - # Address for test results - la x27, test_B_res - - # Register initialization - li x1, 0 - li x2, 1 - li x3, -1 - li x4, 0x7FFFFFFF - li x5, 0x80000000 - li x31, 0 - - # Test - bltu x1, x0, 1f - ori x31, x31, 0x1 -1: - bltu x2, x0, 1f - ori x31, x31, 0x2 -1: - bltu x3, x0, 1f - ori x31, x31, 0x4 -1: - bltu x4, x0, 1f - ori x31, x31, 0x8 -1: - bltu x5, x0, 1f - ori x31, x31, 0x10 -1: - bltu x0, x1, 1f - ori x31, x31, 0x20 -1: - bltu x0, x2, 1f - ori x31, x31, 0x40 -1: - bltu x0, x3, 1f - ori x31, x31, 0x80 -1: - bltu x0, x4, 1f - ori x31, x31, 0x100 -1: - bltu x0, x5, 1f - ori x31, x31, 0x200 -1: - - # Store results - sw x31, 0(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x0000003F) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - jumps forward, backward\n"); - - # Address for test data and results - la x21, test_C_data - la x22, test_C_res - - # Load testdata - lw x31, 0(x21) - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0x0FEDCBA9 - - # Test - bltu x0, x31, 2f - li x2, 0 - li x3, 0 - li x4, 0 - -1: - li x3, 0x87654321 - bltu x0, x31, 3f - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 3f 2: - li x2, 0x9ABCDEF0 - bltu x0, x31, 1b - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 4f 3: + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 8, \ + li x1, 0xcccc; \ + li x29, 0x0; \ + li x14, -0x1; \ + bltu x29, x14, 2b; \ + li x1, 0x123ab; \ +4: \ + ) - # Store results - sw x0, 0(x22) - sw x2, 4(x22) - sw x3, 8(x22) - sw x4, 12(x22) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 12, \ + li x1, 0xcccc; \ + li x28, 0x7ff; \ + li x13, -0x1234; \ + bltu x28, x13, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 16, \ + li x1, 0xcccc; \ + li x27, 0x0; \ + li x12, 0x80000000; \ + bltu x27, x12, 5f; \ + li x1, 0x123ab; \ +5: \ + ) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x22, x2, 0x9ABCDEF0) - RVTEST_IO_ASSERT_GPR_EQ(x22, x3, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x22, x4, 0x0FEDCBA9) - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + # address for test results + la x2, test_2_res + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + li x26, 0x800; \ + li x11, 0x1234; \ + bltu x26, x11, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 4, \ + li x1, 0xcccc; \ + li x25, 0x7654321; \ + li x10, 0xffffffff; \ + bltu x25, x10, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 8, \ + li x1, 0xcccc; \ + li x24, 0x7fffffff; \ + li x9, 0x1; \ + bltu x24, x9, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 12, \ + li x1, 0xcccc; \ + li x23, 0x1; \ + li x8, 0x7fffffff; \ + bltu x23, x8, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 16, \ + li x1, 0xcccc; \ + li x22, 0xffffffff; \ + li x7, 0x7654321; \ + bltu x22, x7, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") + + + # address for test results + la x7, test_3_res + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 0, \ + li x1, 0xcccc; \ + li x21, 0x1234; \ + li x6, 0x800; \ + bltu x21, x6, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 4, \ + li x1, 0xcccc; \ + li x20, 0x80000000; \ + li x5, 0x0; \ + bltu x20, x5, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 8, \ + li x1, 0xcccc; \ + li x19, -0x1234; \ + li x4, 0x7ff; \ + bltu x19, x4, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 12, \ + li x1, 0xcccc; \ + li x18, -0x1; \ + li x3, -0x1; \ + bltu x18, x3, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 16, \ + li x1, 0xcccc; \ + li x17, -0x7ff; \ + li x2, 0x1; \ + bltu x17, x2, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # address for test results + la x3, test_4_res + + + // Result = 0 + TEST_CASE(x4, x2, 0x123ab, x3, 0, \ + li x2, 0xcccc; \ + li x16, 0x0; \ + li x1, 0x0; \ + bltu x16, x1, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 4, \ + li x1, 0xcccc; \ + li x15, -0x1; \ + li x0, 0x0; \ + bltu x15, x0, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 8, \ + li x1, 0xcccc; \ + li x14, 0x1; \ + li x31, -0x7ff; \ + bltu x14, x31, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 12, \ + li x1, 0xcccc; \ + li x13, 0x0; \ + li x30, -0x1; \ + bltu x13, x30, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 16, \ + li x1, 0xcccc; \ + li x12, 0x7ff; \ + li x29, -0x1234; \ + bltu x12, x29, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x2, test_5_res + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + li x11, 0x0; \ + li x28, 0x80000000; \ + bltu x11, x28, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 4, \ + li x1, 0xcccc; \ + li x10, 0x800; \ + li x27, 0x1234; \ + bltu x10, x27, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 8, \ + li x1, 0xcccc; \ + li x9, 0x7654321; \ + li x26, 0xffffffff; \ + bltu x9, x26, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x3, x1, 0x123ab, x2, 12, \ + li x1, 0xcccc; \ + li x8, 0x7fffffff; \ + li x25, 0x1; \ + bltu x8, x25, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 16, \ + li x1, 0xcccc; \ + li x7, 0x1; \ + li x24, 0x7fffffff; \ + bltu x7, x24, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x7, test_6_res + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 0, \ + li x1, 0xcccc; \ + li x6, 0xffffffff; \ + li x23, 0x7654321; \ + bltu x6, x23, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 4, \ + li x1, 0xcccc; \ + li x5, 0x1234; \ + li x22, 0x800; \ + bltu x5, x22, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 8, \ + li x1, 0xcccc; \ + li x4, 0x80000000; \ + li x21, 0x0; \ + bltu x4, x21, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 12, \ + li x1, 0xcccc; \ + li x3, -0x1234; \ + li x20, 0x7ff; \ + bltu x3, x20, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 16, \ + li x1, 0xcccc; \ + li x2, -0x1; \ + li x19, -0x1; \ + bltu x2, x19, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x3, test_7_res + + + // Result = 0 + TEST_CASE(x4, x2, 0x123ab, x3, 0, \ + li x2, 0xcccc; \ + li x1, -0x7ff; \ + li x18, 0x1; \ + bltu x1, x18, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 4, \ + li x1, 0xcccc; \ + li x0, 0x0; \ + li x17, 0x0; \ + bltu x0, x17, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_C_data: - .word 1 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 7, 4, -1 -test_A2_res: - .fill 7, 4, -1 -test_A3_res: - .fill 7, 4, -1 -test_A4_res: - .fill 7, 4, -1 -test_A5_res: - .fill 7, 4, -1 -test_B_res: - .fill 1, 4, -1 -test_C_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BNE-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BNE-01.S index 5106814..96d2dcd 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BNE-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-BNE-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-BNE-01 +# RISC-V Compliance Test BNE-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,456 +10,487 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction BNE. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'BNE'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - li x31, 0 - # Test - bne x3, x4, 1f - ori x31, x31, 0x1 -1: - bne x3, x5, 1f - ori x31, x31, 0x2 -1: - bne x3, x6, 1f - ori x31, x31, 0x4 -1: - bne x3, x7, 1f - ori x31, x31, 0x8 -1: - bne x3, x8, 1f - ori x31, x31, 0x10 -1: + # address for test results + la x2, test_1_res + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + li x31, -0x1; \ + li x16, 0x0; \ + bne x31, x16, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 4, \ + li x1, 0xcccc; \ + li x30, 0x1; \ + li x15, -0x7ff; \ + bne x30, x15, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) - sw x31, 24(x2) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - - # Load testdata - lw x6, 0(x1) - - # Register initialization - li x7, 0 - li x8, 1 - li x9, -1 - li x10, 0x7FFFFFFF - li x11, 0x80000000 - li x31, 0 - - # Test - bne x6, x7, 1f - ori x31, x31, 0x1 -1: - bne x6, x8, 1f - ori x31, x31, 0x2 -1: - bne x6, x9, 1f - ori x31, x31, 0x4 -1: - bne x6, x10, 1f - ori x31, x31, 0x8 -1: - bne x6, x11, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x6, 0(x2) - sw x7, 4(x2) - sw x8, 8(x2) - sw x9, 12(x2) - sw x10, 16(x2) - sw x11, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x6 , 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000002) - - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res - - # Load testdata - lw x12, 0(x1) - - # Register initialization - li x13, 0 - li x14, 1 - li x15, -1 - li x16, 0x7FFFFFFF - li x17, 0x80000000 - li x31, 0 - - # Test - bne x12, x13, 1f - ori x31, x31, 0x1 -1: - bne x12, x14, 1f - ori x31, x31, 0x2 -1: - bne x12, x15, 1f - ori x31, x31, 0x4 -1: - bne x12, x16, 1f - ori x31, x31, 0x8 -1: - bne x12, x17, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x12, 0(x2) - sw x13, 4(x2) - sw x14, 8(x2) - sw x15, 12(x2) - sw x16, 16(x2) - sw x17, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000004) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res - - # Load testdata - lw x18, 0(x1) - - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 - li x31, 0 - - # Test - bne x18, x19, 1f - ori x31, x31, 0x1 -1: - bne x18, x20, 1f - ori x31, x31, 0x2 -1: - bne x18, x21, 1f - ori x31, x31, 0x4 -1: - bne x18, x22, 1f - ori x31, x31, 0x8 -1: - bne x18, x23, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000008) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x24, 0(x1) - - # Register initialization - li x25, 0 - li x26, 1 - li x27, -1 - li x28, 0x7FFFFFFF - li x29, 0x80000000 - li x31, 0 - - # Test - bne x24, x25, 1f - ori x31, x31, 0x1 -1: - bne x24, x26, 1f - ori x31, x31, 0x2 -1: - bne x24, x27, 1f - ori x31, x31, 0x4 -1: - bne x24, x28, 1f - ori x31, x31, 0x8 -1: - bne x24, x29, 1f - ori x31, x31, 0x10 -1: - - # Store results - sw x24, 0(x2) - sw x25, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) - sw x28, 16(x2) - sw x29, 20(x2) - sw x31, 24(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x29, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x31, 0x00000010) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing compare with x0\n"); - - # Address for test results - la x27, test_B_res - - # Register initialization - li x1, 0 - li x2, 1 - li x3, -1 - li x4, 0x7FFFFFFF - li x5, 0x80000000 - li x31, 0 - - # Test - bne x1, x0, 1f - ori x31, x31, 0x1 -1: - bne x2, x0, 1f - ori x31, x31, 0x2 -1: - bne x3, x0, 1f - ori x31, x31, 0x4 -1: - bne x4, x0, 1f - ori x31, x31, 0x8 -1: - bne x5, x0, 1f - ori x31, x31, 0x10 -1: - bne x0, x1, 1f - ori x31, x31, 0x20 -1: - bne x0, x2, 1f - ori x31, x31, 0x40 -1: - bne x0, x3, 1f - ori x31, x31, 0x80 -1: - bne x0, x4, 1f - ori x31, x31, 0x100 -1: - bne x0, x5, 1f - ori x31, x31, 0x200 -1: - - # Store results - sw x31, 0(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x00000021) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - jumps forward, backward\n"); - - # Address for test data and results - la x21, test_C_data - la x22, test_C_res - - # Load testdata - lw x31, 0(x21) - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0x0FEDCBA9 - - # Test - bne x31, x0, 2f - li x2, 0 - li x3, 0 - li x4, 0 - -1: - li x3, 0x87654321 - bne x31, x0, 3f - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 3f 2: - li x2, 0x9ABCDEF0 - bne x31, x0, 1b - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 4f 3: + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 8, \ + li x1, 0xcccc; \ + li x29, 0x0; \ + li x14, -0x1; \ + bne x29, x14, 2b; \ + li x1, 0x123ab; \ +4: \ + ) - # Store results - sw x0, 0(x22) - sw x2, 4(x22) - sw x3, 8(x22) - sw x4, 12(x22) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 12, \ + li x1, 0xcccc; \ + li x28, 0x7ff; \ + li x13, -0x1234; \ + bne x28, x13, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 16, \ + li x1, 0xcccc; \ + li x27, 0x0; \ + li x12, 0x80000000; \ + bne x27, x12, 5f; \ + li x1, 0x123ab; \ +5: \ + ) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x22, x2, 0x9ABCDEF0) - RVTEST_IO_ASSERT_GPR_EQ(x22, x3, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x22, x4, 0x0FEDCBA9) - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + # address for test results + la x2, test_2_res + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + li x26, 0x800; \ + li x11, 0x1234; \ + bne x26, x11, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 4, \ + li x1, 0xcccc; \ + li x25, 0x7654321; \ + li x10, 0xffffffff; \ + bne x25, x10, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 8, \ + li x1, 0xcccc; \ + li x24, 0x7fffffff; \ + li x9, 0x1; \ + bne x24, x9, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 12, \ + li x1, 0xcccc; \ + li x23, 0x1; \ + li x8, 0x7fffffff; \ + bne x23, x8, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 16, \ + li x1, 0xcccc; \ + li x22, 0xffffffff; \ + li x7, 0x7654321; \ + bne x22, x7, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") + + + # address for test results + la x7, test_3_res + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 0, \ + li x1, 0xcccc; \ + li x21, 0x1234; \ + li x6, 0x800; \ + bne x21, x6, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 4, \ + li x1, 0xcccc; \ + li x20, 0x80000000; \ + li x5, 0x0; \ + bne x20, x5, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 8, \ + li x1, 0xcccc; \ + li x19, -0x1234; \ + li x4, 0x7ff; \ + bne x19, x4, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 12, \ + li x1, 0xcccc; \ + li x18, -0x1; \ + li x3, -0x1; \ + bne x18, x3, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 16, \ + li x1, 0xcccc; \ + li x17, -0x7ff; \ + li x2, 0x1; \ + bne x17, x2, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # address for test results + la x3, test_4_res + + + // Result = 0 + TEST_CASE(x4, x2, 0x123ab, x3, 0, \ + li x2, 0xcccc; \ + li x16, 0x0; \ + li x1, 0x0; \ + bne x16, x1, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 4, \ + li x1, 0xcccc; \ + li x15, -0x1; \ + li x0, 0x0; \ + bne x15, x0, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 8, \ + li x1, 0xcccc; \ + li x14, 0x1; \ + li x31, -0x7ff; \ + bne x14, x31, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 12, \ + li x1, 0xcccc; \ + li x13, 0x0; \ + li x30, -0x1; \ + bne x13, x30, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x4, x1, 0xcccc, x3, 16, \ + li x1, 0xcccc; \ + li x12, 0x7ff; \ + li x29, -0x1234; \ + bne x12, x29, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x2, test_5_res + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + li x11, 0x0; \ + li x28, 0x80000000; \ + bne x11, x28, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 4, \ + li x1, 0xcccc; \ + li x10, 0x800; \ + li x27, 0x1234; \ + bne x10, x27, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 8, \ + li x1, 0xcccc; \ + li x9, 0x7654321; \ + li x26, 0xffffffff; \ + bne x9, x26, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 12, \ + li x1, 0xcccc; \ + li x8, 0x7fffffff; \ + li x25, 0x1; \ + bne x8, x25, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 1 + TEST_CASE(x3, x1, 0xcccc, x2, 16, \ + li x1, 0xcccc; \ + li x7, 0x1; \ + li x24, 0x7fffffff; \ + bne x7, x24, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x7, test_6_res + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 0, \ + li x1, 0xcccc; \ + li x6, 0xffffffff; \ + li x23, 0x7654321; \ + bne x6, x23, 1f; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 4, \ + li x1, 0xcccc; \ + li x5, 0x1234; \ + li x22, 0x800; \ + bne x5, x22, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 8, \ + li x1, 0xcccc; \ + li x4, 0x80000000; \ + li x21, 0x0; \ + bne x4, x21, 2b; \ + li x1, 0x123ab; \ +4: \ + ) + + + // Result = 1 + TEST_CASE(x8, x1, 0xcccc, x7, 12, \ + li x1, 0xcccc; \ + li x3, -0x1234; \ + li x20, 0x7ff; \ + bne x3, x20, 4f; \ + li x1, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x8, x1, 0x123ab, x7, 16, \ + li x1, 0xcccc; \ + li x2, -0x1; \ + li x19, -0x1; \ + bne x2, x19, 5f; \ + li x1, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x3, test_7_res + + + // Result = 1 + TEST_CASE(x4, x2, 0xcccc, x3, 0, \ + li x2, 0xcccc; \ + li x1, -0x7ff; \ + li x18, 0x1; \ + bne x1, x18, 1f; \ + li x2, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x4, x1, 0x123ab, x3, 4, \ + li x1, 0xcccc; \ + li x0, 0x0; \ + li x17, 0x0; \ + bne x0, x17, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_C_data: - .word -1 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 7, 4, -1 -test_A2_res: - .fill 7, 4, -1 -test_A3_res: - .fill 7, 4, -1 -test_A4_res: - .fill 7, 4, -1 -test_A5_res: - .fill 7, 4, -1 -test_B_res: - .fill 1, 4, -1 -test_C_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S index 958eebc..32c074c 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-EBREAK-01.S
@@ -71,6 +71,7 @@ # --------------------------------------------------------------------------------------------- # Exception handler +.align TRAPALIGN _trap_handler: # increment return address csrr x30, mepc
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S index 5278207..0bdee2a 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ECALL-01.S
@@ -73,6 +73,7 @@ # --------------------------------------------------------------------------------------------- # Exception handler +.align TRAPALIGN _trap_handler: # increment return address csrr x30, mepc
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-FENCE.I-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-FENCE.I-01.S deleted file mode 100644 index 60d7ccf..0000000 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-FENCE.I-01.S +++ /dev/null
@@ -1,112 +0,0 @@ -# RISC-V Compliance Test I-FENCE.I-01 -# -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction FENCE.I. - -#include "compliance_test.h" -#include "compliance_io.h" -#include "test_macros.h" - -# Test Virtual Machine (TVM) used by program. -RV_COMPLIANCE_RV32M - -# Test code region -RV_COMPLIANCE_CODE_BEGIN - - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A - test fence\n"); - - # Addresses for test data and results - la x16, test_A_data - la x17, test_A_res - - # Register initialization - li x3, 0 - - # Load testdata - lw x1, 0(x16) - lw x2, 4(x16) - - # Test - la x20, instr_A_src - la x21, instr_A_dst - lw x15, 0(x20) - sw x15, 0(x21) - fence.i -instr_A_dst: - lui x2, 0 - - # Store results - sw x1, 0(x17) - sw x2, 4(x17) - sw x3, 8(x17) - sw x15, 12(x17) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x17, x2, 0x00000012) - RVTEST_IO_ASSERT_GPR_EQ(x17, x3, 0x00000042) - RVTEST_IO_ASSERT_GPR_EQ(x17, x15, 0x001101B3) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT - -RV_COMPLIANCE_CODE_END - -# Input data section. - .data - .align 4 - -instr_A_src: - add x3, x2, x1 - -test_A_data: - .word 0x30 - .word 0x12 - - -# Output data section. -RV_COMPLIANCE_DATA_BEGIN - .align 4 - -test_A_res: - .fill 4, 4, -1 - -RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-IO.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-IO-01.S similarity index 100% rename from sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-IO.S rename to sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-IO-01.S
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-JAL-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-JAL-01.S index 4fdc5c1..79922b6 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-JAL-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-JAL-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-JAL-01 +# RISC-V Compliance Test JAL-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,290 +10,423 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction JAL. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'JAL'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region. RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of JAL\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Address for test results - la x1, test_A1_res + # --------------------------------------------------------------------------------------------- - # Register initialization - li x2, 0x12345678 + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - jal x0, 1f - li x2, 0 -1: + # address for test results + la x5, test_1_res + + + // Result = 0 + TEST_CASE(x6, x0, 0, x5, 0, \ + li x0, 0xcccc; \ + jal x31, 1f; \ + li x0, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x6, x1, 0xcccc, x5, 4, \ + li x1, 0xcccc; \ + jal x30, 2f; \ + li x1, 0x123ab; \ +2: \ + ) + - # Store results - sw x0, 0(x1) - sw x2, 4(x1) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x1, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x12345678) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test of JAL - jumps forward, backward\n"); - - # Address for test results - la x1, test_A2_res - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0x0FEDCBA9 - - # Test - jal x0, 2f - li x2, 0 - li x3, 0 - li x4, 0 - -1: - li x3, 0x87654321 - jal x0, 3f - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 3f 2: - li x2, 0x9ABCDEF0 - jal x0, 1b - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 4f 3: + // Result = 0 + TEST_CASE(x6, x2, 0xcccc, x5, 8, \ + li x2, 0xcccc; \ + jal x29, 2b; \ + li x2, 0x123ab; \ +4: \ + ) - # Store results - sw x0, 0(x1) - sw x2, 4(x1) - sw x3, 8(x1) - sw x4, 12(x1) + + // Result = 0 + TEST_CASE(x6, x3, 0xcccc, x5, 12, \ + li x3, 0xcccc; \ + jal x28, 4f; \ + li x3, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x6, x4, 0xcccc, x5, 16, \ + li x4, 0xcccc; \ + jal x27, 5f; \ + li x4, 0x123ab; \ +5: \ + ) - RVTEST_IO_ASSERT_GPR_EQ(x1, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x9ABCDEF0) - RVTEST_IO_ASSERT_GPR_EQ(x1, x3, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x1, x4, 0x0FEDCBA9) - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B1 - test of JAL - linking\n"); - # Addresses for test data and results - la x9, test_B1_data - la x10, test_B1_res + # address for test results + la x1, test_2_res + + + // Result = 0 + TEST_CASE(x2, x5, 0xcccc, x1, 0, \ + li x5, 0xcccc; \ + jal x26, 1f; \ + li x5, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x2, x6, 0xcccc, x1, 4, \ + li x6, 0xcccc; \ + jal x25, 2f; \ + li x6, 0x123ab; \ +2: \ + ) + - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0xFFFFFFFF - li x5, 0xFFFFFFFF - li x6, 0x55555555 - - # Load testdata - lw x25, 0(x9) - lw x24, 4(x9) - - # Test - jal x1, 1f - -B1a_link: - li x3, 0x22222222 - jal x31, 2f - -B1b_link: - li x5, 0x44444444 - jal x0, 3f - -1: - li x2, 0x11111111 - jalr x0, x1, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - + jal x0, 3f 2: - li x4, 0x33333333 - jalr x0, x31, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - + jal x0, 4f 3: - xor x7, x1, x25 - xor x8, x31, x24 + // Result = 0 + TEST_CASE(x2, x7, 0xcccc, x1, 8, \ + li x7, 0xcccc; \ + jal x24, 2b; \ + li x7, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x2, x8, 0xcccc, x1, 12, \ + li x8, 0xcccc; \ + jal x23, 4f; \ + li x8, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x2, x9, 0xcccc, x1, 16, \ + li x9, 0xcccc; \ + jal x22, 5f; \ + li x9, 0x123ab; \ +5: \ + ) - # Store results - sw x2, 0(x10) - sw x3, 4(x10) - sw x4, 8(x10) - sw x5, 12(x10) - sw x6, 16(x10) - sw x7, 20(x10) - sw x8, 24(x10) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_ASSERT_GPR_EQ(x10, x2, 0x11111111) - RVTEST_IO_ASSERT_GPR_EQ(x10, x3, 0x22222222) - RVTEST_IO_ASSERT_GPR_EQ(x10, x4, 0x33333333) - RVTEST_IO_ASSERT_GPR_EQ(x10, x5, 0x44444444) - RVTEST_IO_ASSERT_GPR_EQ(x10, x6, 0x55555555) - RVTEST_IO_ASSERT_GPR_EQ(x10, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x10, x8, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + # address for test results + la x1, test_3_res + + + // Result = 0 + TEST_CASE(x7, x10, 0xcccc, x1, 0, \ + li x10, 0xcccc; \ + jal x21, 1f; \ + li x10, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x7, x11, 0xcccc, x1, 4, \ + li x11, 0xcccc; \ + jal x20, 2f; \ + li x11, 0x123ab; \ +2: \ + ) + - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B2 - test of JAL - linking\n"); - - # Addresses for test data and results - la x9, test_B2_data - la x10, test_B2_res - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0xFFFFFFFF - li x5, 0xFFFFFFFF - li x6, 0xFFFFFFFF - - # Load testdata - lw x24, 0(x9) - lw x25, 4(x9) - - # Test - jal x0, 2f - -1: - li x3, 0x77777777 - jalr x0, x31, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - + jal x0, 3f 2: - li x2, 0x66666666 - jal x31, 1b - -B2b_link: - li x4, 0x88888888 - jal x1, 3f - -B2c_link: - li x6, 0xAAAAAAAA - jal x0, 4f - + jal x0, 4f 3: - li x5, 0x99999999 - jalr x0, x1, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 + // Result = 0 + TEST_CASE(x7, x12, 0xcccc, x1, 8, \ + li x12, 0xcccc; \ + jal x19, 2b; \ + li x12, 0x123ab; \ +4: \ + ) -4: - xor x7, x31, x24 - xor x8, x1, x25 - - # Store results - sw x2, 0(x10) - sw x3, 4(x10) - sw x4, 8(x10) - sw x5, 12(x10) - sw x6, 16(x10) - sw x7, 20(x10) - sw x8, 24(x10) - - RVTEST_IO_ASSERT_GPR_EQ(x10, x2, 0x66666666) - RVTEST_IO_ASSERT_GPR_EQ(x10, x3, 0x77777777) - RVTEST_IO_ASSERT_GPR_EQ(x10, x4, 0x88888888) - RVTEST_IO_ASSERT_GPR_EQ(x10, x5, 0x99999999) - RVTEST_IO_ASSERT_GPR_EQ(x10, x6, 0xAAAAAAAA) - RVTEST_IO_ASSERT_GPR_EQ(x10, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x10, x8, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + + // Result = 0 + TEST_CASE(x7, x13, 0xcccc, x1, 12, \ + li x13, 0xcccc; \ + jal x18, 4f; \ + li x13, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x7, x14, 0xcccc, x1, 16, \ + li x14, 0xcccc; \ + jal x17, 5f; \ + li x14, 0x123ab; \ +5: \ + ) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # address for test results + la x2, test_4_res + + + // Result = 0 + TEST_CASE(x3, x15, 0xcccc, x2, 0, \ + li x15, 0xcccc; \ + jal x16, 1f; \ + li x15, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x16, 0xcccc, x2, 4, \ + li x16, 0xcccc; \ + jal x15, 2f; \ + li x16, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x3, x17, 0xcccc, x2, 8, \ + li x17, 0xcccc; \ + jal x14, 2b; \ + li x17, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x3, x18, 0xcccc, x2, 12, \ + li x18, 0xcccc; \ + jal x13, 4f; \ + li x18, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x19, 0xcccc, x2, 16, \ + li x19, 0xcccc; \ + jal x12, 5f; \ + li x19, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x1, test_5_res + + + // Result = 0 + TEST_CASE(x2, x20, 0xcccc, x1, 0, \ + li x20, 0xcccc; \ + jal x11, 1f; \ + li x20, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x2, x21, 0xcccc, x1, 4, \ + li x21, 0xcccc; \ + jal x10, 2f; \ + li x21, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x2, x22, 0xcccc, x1, 8, \ + li x22, 0xcccc; \ + jal x9, 2b; \ + li x22, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x2, x23, 0xcccc, x1, 12, \ + li x23, 0xcccc; \ + jal x8, 4f; \ + li x23, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x2, x24, 0xcccc, x1, 16, \ + li x24, 0xcccc; \ + jal x7, 5f; \ + li x24, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x1, test_6_res + + + // Result = 0 + TEST_CASE(x7, x25, 0xcccc, x1, 0, \ + li x25, 0xcccc; \ + jal x6, 1f; \ + li x25, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x7, x26, 0xcccc, x1, 4, \ + li x26, 0xcccc; \ + jal x5, 2f; \ + li x26, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x7, x27, 0xcccc, x1, 8, \ + li x27, 0xcccc; \ + jal x4, 2b; \ + li x27, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x7, x28, 0xcccc, x1, 12, \ + li x28, 0xcccc; \ + jal x3, 4f; \ + li x28, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x7, x29, 0xcccc, x1, 16, \ + li x29, 0xcccc; \ + jal x2, 5f; \ + li x29, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x2, test_7_res + + + // Result = 0 + TEST_CASE(x3, x30, 0xcccc, x2, 0, \ + li x30, 0xcccc; \ + jal x1, 1f; \ + li x30, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x31, 0xcccc, x2, 4, \ + li x31, 0xcccc; \ + jal x0, 2f; \ + li x31, 0x123ab; \ +2: \ + ) + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_B1_data: - .word B1a_link - .word B1b_link -test_B2_data: - .word B2b_link - .word B2c_link - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 2, 4, -1 -test_A2_res: - .fill 4, 4, -1 -test_B1_res: - .fill 7, 4, -1 -test_B2_res: - .fill 7, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-JALR-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-JALR-01.S index fe675a2..5fcff87 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-JALR-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-JALR-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-JALR-01 +# RISC-V Compliance Test JALR-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,346 +10,455 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction JALR. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'JALR'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region. RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of JALR\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Address for test results - la x1, test_A1_res + # --------------------------------------------------------------------------------------------- - # Register initialization - li x2, 0x12345678 + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - la x3, 1f - jalr x0, x3, 0 - li x2, 0 -1: + # address for test results + la x5, test_1_res + + + // Result = 0 + TEST_CASE(x6, x31, 0xcccc, x5, 0, \ + li x31, 0xcccc; \ + la x16, 1f - 0; \ + jalr x0, x16, 0; \ + li x31, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x6, x30, 0xcccc, x5, 4, \ + li x30, 0xcccc; \ + la x15, 2f - 1; \ + jalr x1, x15, 1; \ + li x30, 0x123ab; \ +2: \ + ) + - # Store results - sw x0, 0(x1) - sw x2, 4(x1) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x1, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x12345678) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test of JALR - jumps forward, backward\n"); - - # Address for test results - la x1, test_A2_res - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0x0FEDCBA9 - - # Test - la x31, 2f - jalr x0, x31, 0 - li x2, 0 - li x3, 0 - li x4, 0 - -1: - li x3, 0x87654321 - la x5, 3f - jalr x0, x5, 0 - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 3f 2: - li x2, 0x9ABCDEF0 - la x15, 1b - jalr x0, x15, 0 - li x2, 0 - li x3, 0 - li x4, 0 - + jal x0, 4f 3: + // Result = 0 + TEST_CASE(x6, x29, 0xcccc, x5, 8, \ + li x29, 0xcccc; \ + la x14, 2b - 1; \ + jalr x2, x14, 1; \ + li x29, 0x123ab; \ +4: \ + ) - # Store results - sw x0, 0(x1) - sw x2, 4(x1) - sw x3, 8(x1) - sw x4, 12(x1) + + // Result = 0 + TEST_CASE(x6, x28, 0xcccc, x5, 12, \ + li x28, 0xcccc; \ + la x13, 4f - 4; \ + jalr x3, x13, 4; \ + li x28, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x6, x27, 0xcccc, x5, 16, \ + li x27, 0xcccc; \ + la x12, 5f - 2; \ + jalr x4, x12, 2; \ + li x27, 0x123ab; \ +5: \ + ) - RVTEST_IO_ASSERT_GPR_EQ(x1, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x9ABCDEF0) - RVTEST_IO_ASSERT_GPR_EQ(x1, x3, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x1, x4, 0x0FEDCBA9) - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B1 - test of JALR - linking\n"); - # Addresses for test data and results - la x9, test_B1_data - la x10, test_B1_res + # address for test results + la x1, test_2_res + + + // Result = 0 + TEST_CASE(x2, x26, 0xcccc, x1, 0, \ + li x26, 0xcccc; \ + la x11, 1f - 4; \ + jalr x5, x11, 4; \ + li x26, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x2, x25, 0xcccc, x1, 4, \ + li x25, 0xcccc; \ + la x10, 2f - 3; \ + jalr x6, x10, 3; \ + li x25, 0x123ab; \ +2: \ + ) + - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0xFFFFFFFF - li x5, 0xFFFFFFFF - li x6, 0x55555555 - - # Load testdata - lw x25, 0(x9) - lw x24, 4(x9) - - # Test - la x7, 1f - jalr x1, x7, 0 - -B1a_link: - li x3, 0x22222222 - la x8, 2f - jalr x31, x8, 0 - -B1b_link: - li x5, 0x44444444 - la x30, 3f - jalr x0, x30, 0 - -1: - li x2, 0x11111111 - jalr x0, x1, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - + jal x0, 3f 2: - li x4, 0x33333333 - jalr x0, x31, 0 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - + jal x0, 4f 3: - xor x7, x1, x25 - xor x8, x31, x24 + // Result = 0 + TEST_CASE(x2, x24, 0xcccc, x1, 8, \ + li x24, 0xcccc; \ + la x9, 2b - 2; \ + jalr x7, x9, 2; \ + li x24, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x2, x23, 0xcccc, x1, 12, \ + li x23, 0xcccc; \ + la x8, 4f - 0; \ + jalr x8, x8, 0; \ + li x23, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x2, x22, 0xcccc, x1, 16, \ + li x22, 0xcccc; \ + la x7, 5f - 1; \ + jalr x9, x7, 1; \ + li x22, 0x123ab; \ +5: \ + ) - # Store results - sw x2, 0(x10) - sw x3, 4(x10) - sw x4, 8(x10) - sw x5, 12(x10) - sw x6, 16(x10) - sw x7, 20(x10) - sw x8, 24(x10) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_ASSERT_GPR_EQ(x10, x2, 0x11111111) - RVTEST_IO_ASSERT_GPR_EQ(x10, x3, 0x22222222) - RVTEST_IO_ASSERT_GPR_EQ(x10, x4, 0x33333333) - RVTEST_IO_ASSERT_GPR_EQ(x10, x5, 0x44444444) - RVTEST_IO_ASSERT_GPR_EQ(x10, x6, 0x55555555) - RVTEST_IO_ASSERT_GPR_EQ(x10, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x10, x8, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + # address for test results + la x1, test_3_res + + + // Result = 0 + TEST_CASE(x7, x21, 0xcccc, x1, 0, \ + li x21, 0xcccc; \ + la x6, 1f - 1; \ + jalr x10, x6, 1; \ + li x21, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x7, x20, 0xcccc, x1, 4, \ + li x20, 0xcccc; \ + la x5, 2f - 4; \ + jalr x11, x5, 4; \ + li x20, 0x123ab; \ +2: \ + ) + - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B2 - test of JALR - linking, low bit of address is cleared\n"); - - # Addresses for test data and results - la x9, test_B2_data - la x10, test_B2_res - - # Register initialization - li x2, 0xFFFFFFFF - li x3, 0xFFFFFFFF - li x4, 0xFFFFFFFF - li x5, 0xFFFFFFFF - li x6, 0xFFFFFFFF - - # Load testdata - lw x24, 0(x9) - lw x25, 4(x9) - - # Test - la x15, 2f - jalr x0, x15, 0 - -1: - li x3, 0x77777777 - jalr x0, x31, 1 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 - + jal x0, 3f 2: - li x2, 0x66666666 - la x31, 1b + 1 - jalr x31, x31, 0 - -B2b_link: - li x4, 0x88888888 - la x1, 3f + 1 - jalr x1, x1, 0 - -B2c_link: - li x6, 0xAAAAAAAA - la x30, 4f - jalr x0, x30, 0 - + jal x0, 4f 3: - li x5, 0x99999999 - jalr x0, x1, 1 - li x2, 0 - li x3, 0 - li x4, 0 - li x5, 0 - li x6, 0 + // Result = 0 + TEST_CASE(x7, x19, 0xcccc, x1, 8, \ + li x19, 0xcccc; \ + la x4, 2b - 2; \ + jalr x12, x4, 2; \ + li x19, 0x123ab; \ +4: \ + ) -4: - xor x7, x31, x24 - xor x8, x1, x25 - - # Store results - sw x2, 0(x10) - sw x3, 4(x10) - sw x4, 8(x10) - sw x5, 12(x10) - sw x6, 16(x10) - sw x7, 20(x10) - sw x8, 24(x10) - - RVTEST_IO_ASSERT_GPR_EQ(x10, x2, 0x66666666) - RVTEST_IO_ASSERT_GPR_EQ(x10, x3, 0x77777777) - RVTEST_IO_ASSERT_GPR_EQ(x10, x4, 0x88888888) - RVTEST_IO_ASSERT_GPR_EQ(x10, x5, 0x99999999) - RVTEST_IO_ASSERT_GPR_EQ(x10, x6, 0xAAAAAAAA) - RVTEST_IO_ASSERT_GPR_EQ(x10, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x10, x8, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - JALR using immediate\n"); - - # Address for test results - la x1, test_C_res - - # Test - li x4, 0x11111111 - la x3, 1f - 1 - jalr x0, x3, 1 - li x4, 0 - -1: - li x5, 0x22222222 - la x3, 1f + 1 - jalr x0, x3, 0xFFFFFFFF - li x5, 0 - -1: - li x6, 0x33333333 - la x3, 1f - 2047 - jalr x0, x3, 0x000007FF - li x6, 0 - -1: - li x7, 0x44444444 - la x3, 1f + 2048 - jalr x0, x3, 0xFFFFF800 - li x7, 0 - -1: - # Store results - sw x4, 0(x1) - sw x5, 4(x1) - sw x6, 8(x1) - sw x7, 12(x1) - - RVTEST_IO_ASSERT_GPR_EQ(x1, x4, 0x11111111) - RVTEST_IO_ASSERT_GPR_EQ(x1, x5, 0x22222222) - RVTEST_IO_ASSERT_GPR_EQ(x1, x6, 0x33333333) - RVTEST_IO_ASSERT_GPR_EQ(x1, x7, 0x44444444) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + + // Result = 0 + TEST_CASE(x7, x18, 0xcccc, x1, 12, \ + li x18, 0xcccc; \ + la x3, 4f - 4; \ + jalr x13, x3, 4; \ + li x18, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x7, x17, 0xcccc, x1, 16, \ + li x17, 0xcccc; \ + la x2, 5f - 3; \ + jalr x14, x2, 3; \ + li x17, 0x123ab; \ +5: \ + ) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # address for test results + la x2, test_4_res + + + // Result = 0 + TEST_CASE(x3, x16, 0xcccc, x2, 0, \ + li x16, 0xcccc; \ + la x1, 1f - 2; \ + jalr x15, x1, 2; \ + li x16, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x15, 0xcccc, x2, 4, \ + li x15, 0xcccc; \ + la x1, 2f - 0; \ + jalr x16, x1, 0; \ + li x15, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x3, x14, 0xcccc, x2, 8, \ + li x14, 0xcccc; \ + la x31, 2b - 1; \ + jalr x17, x31, 1; \ + li x14, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x3, x13, 0xcccc, x2, 12, \ + li x13, 0xcccc; \ + la x30, 4f - 1; \ + jalr x18, x30, 1; \ + li x13, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x3, x12, 0xcccc, x2, 16, \ + li x12, 0xcccc; \ + la x29, 5f - 4; \ + jalr x19, x29, 4; \ + li x12, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x1, test_5_res + + + // Result = 0 + TEST_CASE(x2, x11, 0xcccc, x1, 0, \ + li x11, 0xcccc; \ + la x28, 1f - 2; \ + jalr x20, x28, 2; \ + li x11, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x2, x10, 0xcccc, x1, 4, \ + li x10, 0xcccc; \ + la x27, 2f - 4; \ + jalr x21, x27, 4; \ + li x10, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x2, x9, 0xcccc, x1, 8, \ + li x9, 0xcccc; \ + la x26, 2b - 3; \ + jalr x22, x26, 3; \ + li x9, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x2, x8, 0xcccc, x1, 12, \ + li x8, 0xcccc; \ + la x25, 4f - 2; \ + jalr x23, x25, 2; \ + li x8, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x2, x7, 0xcccc, x1, 16, \ + li x7, 0xcccc; \ + la x24, 5f - 0; \ + jalr x24, x24, 0; \ + li x7, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x1, test_6_res + + + // Result = 0 + TEST_CASE(x7, x6, 0xcccc, x1, 0, \ + li x6, 0xcccc; \ + la x23, 1f - 1; \ + jalr x25, x23, 1; \ + li x6, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x7, x5, 0xcccc, x1, 4, \ + li x5, 0xcccc; \ + la x22, 2f - 1; \ + jalr x26, x22, 1; \ + li x5, 0x123ab; \ +2: \ + ) + + + jal x0, 3f +2: + jal x0, 4f +3: + // Result = 0 + TEST_CASE(x7, x4, 0xcccc, x1, 8, \ + li x4, 0xcccc; \ + la x21, 2b - 4; \ + jalr x27, x21, 4; \ + li x4, 0x123ab; \ +4: \ + ) + + + // Result = 0 + TEST_CASE(x7, x3, 0xcccc, x1, 12, \ + li x3, 0xcccc; \ + la x20, 4f - 2; \ + jalr x28, x20, 2; \ + li x3, 0x123ab; \ +4: \ + ) + + // Result = 0 + TEST_CASE(x7, x2, 0xcccc, x1, 16, \ + li x2, 0xcccc; \ + la x19, 5f - 4; \ + jalr x29, x19, 4; \ + li x2, 0x123ab; \ +5: \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x2, test_7_res + + + // Result = 0 + TEST_CASE(x3, x1, 0xcccc, x2, 0, \ + li x1, 0xcccc; \ + la x18, 1f - 3; \ + jalr x30, x18, 3; \ + li x1, 0x123ab; \ +1: \ + ) + + // Result = 0 + TEST_CASE(x3, x0, 0, x2, 4, \ + li x0, 0xcccc; \ + la x17, 2f - 2; \ + jalr x31, x17, 2; \ + li x0, 0x123ab; \ +2: \ + ) + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_B1_data: - .word B1a_link - .word B1b_link -test_B2_data: - .word B2b_link - .word B2c_link + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 2, 4, -1 -test_A2_res: - .fill 4, 4, -1 -test_B1_res: - .fill 7, 4, -1 -test_B2_res: - .fill 7, 4, -1 -test_C_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 -RV_COMPLIANCE_DATA_END # End of test output data region. +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LB-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LB-01.S index 9ef81f1..646c7c0 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LB-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LB-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-LB-01 +# RISC-V Compliance Test LB-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,353 +10,275 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction LB. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'LB'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # ------------------0x00000000--------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test base address + 0\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") + # Addresses for test data and results - la x31, test_A1_data - la x2, test_A1_res + la x5, test_1_res - # Test - lb x3, 0(x31) - lb x4, 1(x31) - lb x5, 2(x31) - lb x6, 3(x31) + TEST_CASE(x7, x0, 0x0, x5, 0, \ + la x31, test_data; \ + lb x0, 0x0(x31); \ + ) + TEST_CASE(x7, x1, 0xffffffbb, x5, 4, \ + la x30, test_data; \ + lb x1, -0x2(x30); \ + ) + TEST_CASE(x7, x2, 0xffffffdd, x5, 8, \ + la x29, test_data; \ + lb x2, 0x3(x29); \ + ) + TEST_CASE(x7, x3, 0xc, x5, 12, \ + la x28, test_data; \ + lb x3, -0x4(x28); \ + ) + TEST_CASE(x7, x4, 0xd, x5, 16, \ + la x27, test_data; \ + lb x4, 0x2(x27); \ + ) - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000022) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0xFFFFFFF2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0xFFFFFFF1) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000011) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test base address - 1\n"); # Addresses for test data and results - la x24, test_A2_data + 1 - la x5, test_A2_res + la x1, test_2_res - # Test - lb x25, -1(x24) - lb x26, +0(x24) - lb x27, +1(x24) - lb x28, +2(x24) + TEST_CASE(x3, x5, 0xfffffff0, x1, 0, \ + la x26, test_data; \ + lb x5, 0x4(x26); \ + ) + TEST_CASE(x3, x6, 0xb, x1, 4, \ + la x25, test_data; \ + lb x6, -0x1(x25); \ + ) + TEST_CASE(x3, x7, 0xe, x1, 8, \ + la x24, test_data; \ + lb x7, 0x1(x24); \ + ) + TEST_CASE(x3, x8, 0xffffffee, x1, 12, \ + la x23, test_data; \ + lb x8, 0x0(x23); \ + ) + TEST_CASE(x3, x9, 0xffffffbb, x1, 16, \ + la x22, test_data; \ + lb x9, -0x2(x22); \ + ) - # Store results - sw x25, 0(x5) - sw x26, 4(x5) - sw x27, 8(x5) - sw x28, 12(x5) - RVTEST_IO_ASSERT_GPR_EQ(x5, x25, 0xFFFFFFF4) - RVTEST_IO_ASSERT_GPR_EQ(x5, x26, 0x00000044) - RVTEST_IO_ASSERT_GPR_EQ(x5, x27, 0x00000033) - RVTEST_IO_ASSERT_GPR_EQ(x5, x28, 0xFFFFFFF3) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test base address + 1\n"); # Addresses for test data and results - la x7, test_A3_data - 1 - la x8, test_A3_res + la x1, test_3_res - # Test - lb x30, 1(x7) - lb x31, 2(x7) - lb x1, 3(x7) - lb x2, 4(x7) + TEST_CASE(x8, x10, 0xffffffdd, x1, 0, \ + la x21, test_data; \ + lb x10, 0x3(x21); \ + ) + TEST_CASE(x8, x11, 0xc, x1, 4, \ + la x20, test_data; \ + lb x11, -0x4(x20); \ + ) + TEST_CASE(x8, x12, 0xd, x1, 8, \ + la x19, test_data; \ + lb x12, 0x2(x19); \ + ) + TEST_CASE(x8, x13, 0xfffffff0, x1, 12, \ + la x18, test_data; \ + lb x13, 0x4(x18); \ + ) + TEST_CASE(x8, x14, 0xb, x1, 16, \ + la x17, test_data; \ + lb x14, -0x1(x17); \ + ) - # Store results - sw x30, 0(x8) - sw x31, 4(x8) - sw x1, 8(x8) - sw x2, 12(x8) - RVTEST_IO_ASSERT_GPR_EQ(x8, x30, 0x00000066) - RVTEST_IO_ASSERT_GPR_EQ(x8, x31, 0xFFFFFFF6) - RVTEST_IO_ASSERT_GPR_EQ(x8, x1, 0xFFFFFFF5) - RVTEST_IO_ASSERT_GPR_EQ(x8, x2, 0x00000055) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - test base address - 2048\n"); # Addresses for test data and results - la x10, test_A4_data + 2048 - la x11, test_A4_res + la x2, test_4_res - # Test - lb x12, 0xFFFFF800(x10) - lb x13, 0xFFFFF801(x10) - lb x14, 0xFFFFF802(x10) - lb x15, 0xFFFFF803(x10) + TEST_CASE(x4, x15, 0xe, x2, 0, \ + la x16, test_data; \ + lb x15, 0x1(x16); \ + ) + TEST_CASE(x4, x16, 0xffffffee, x2, 4, \ + la x15, test_data; \ + lb x16, 0x0(x15); \ + ) + TEST_CASE(x4, x17, 0xffffffbb, x2, 8, \ + la x14, test_data; \ + lb x17, -0x2(x14); \ + ) + TEST_CASE(x4, x18, 0xffffffdd, x2, 12, \ + la x13, test_data; \ + lb x18, 0x3(x13); \ + ) + TEST_CASE(x4, x19, 0xc, x2, 16, \ + la x12, test_data; \ + lb x19, -0x4(x12); \ + ) - # Store results - sw x12, 0(x11) - sw x13, 4(x11) - sw x14, 8(x11) - sw x15, 12(x11) - RVTEST_IO_ASSERT_GPR_EQ(x11, x12, 0xFFFFFFF8) - RVTEST_IO_ASSERT_GPR_EQ(x11, x13, 0xFFFFFF88) - RVTEST_IO_ASSERT_GPR_EQ(x11, x14, 0x00000077) - RVTEST_IO_ASSERT_GPR_EQ(x11, x15, 0xFFFFFFF7) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - test base address + 2047\n"); # Addresses for test data and results - la x13, test_A5_data - 2044 - la x14, test_A5_res + la x1, test_5_res - # Test - lb x15, 0x7FC(x13) - lb x16, 0x7FD(x13) - lb x17, 0x7FE(x13) - lb x18, 0x7FF(x13) + TEST_CASE(x3, x20, 0xd, x1, 0, \ + la x11, test_data; \ + lb x20, 0x2(x11); \ + ) + TEST_CASE(x3, x21, 0xfffffff0, x1, 4, \ + la x10, test_data; \ + lb x21, 0x4(x10); \ + ) + TEST_CASE(x3, x22, 0xb, x1, 8, \ + la x9, test_data; \ + lb x22, -0x1(x9); \ + ) + TEST_CASE(x3, x23, 0xe, x1, 12, \ + la x8, test_data; \ + lb x23, 0x1(x8); \ + ) + TEST_CASE(x3, x24, 0xffffffee, x1, 16, \ + la x7, test_data; \ + lb x24, 0x0(x7); \ + ) - # Store results - sw x15, 0(x14) - sw x16, 4(x14) - sw x17, 8(x14) - sw x18, 12(x14) - RVTEST_IO_ASSERT_GPR_EQ(x14, x15, 0xFFFFFFAA) - RVTEST_IO_ASSERT_GPR_EQ(x14, x16, 0x0000000A) - RVTEST_IO_ASSERT_GPR_EQ(x14, x17, 0x00000009) - RVTEST_IO_ASSERT_GPR_EQ(x14, x18, 0xFFFFFF99) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test base address + -4,-1, ..., 6, 7\n"); # Addresses for test data and results - la x16, test_B_data - la x17, test_B_res + la x1, test_6_res - # Test - lb x18, -4(x16) - lb x19, -3(x16) - lb x20, -2(x16) - lb x21, -1(x16) - lb x22, 0(x16) - lb x23, 1(x16) - lb x24, 2(x16) - lb x25, 3(x16) - lb x26, 4(x16) - lb x27, 5(x16) - lb x28, 6(x16) - lb x29, 7(x16) + TEST_CASE(x8, x25, 0xffffffbb, x1, 0, \ + la x6, test_data; \ + lb x25, -0x2(x6); \ + ) + TEST_CASE(x8, x26, 0xffffffdd, x1, 4, \ + la x5, test_data; \ + lb x26, 0x3(x5); \ + ) + TEST_CASE(x8, x27, 0xc, x1, 8, \ + la x4, test_data; \ + lb x27, -0x4(x4); \ + ) + TEST_CASE(x8, x28, 0xd, x1, 12, \ + la x3, test_data; \ + lb x28, 0x2(x3); \ + ) + TEST_CASE(x8, x29, 0xfffffff0, x1, 16, \ + la x2, test_data; \ + lb x29, 0x4(x2); \ + ) - # Store results - sw x18, 0(x17) - sw x19, 4(x17) - sw x20, 8(x17) - sw x21, 12(x17) - sw x22, 16(x17) - sw x23, 20(x17) - sw x24, 24(x17) - sw x25, 28(x17) - sw x26, 32(x17) - sw x27, 36(x17) - sw x28, 40(x17) - sw x29, 44(x17) - RVTEST_IO_ASSERT_GPR_EQ(x17, x18, 0x0000000C) - RVTEST_IO_ASSERT_GPR_EQ(x17, x19, 0xFFFFFFCC) - RVTEST_IO_ASSERT_GPR_EQ(x17, x20, 0xFFFFFFBB) - RVTEST_IO_ASSERT_GPR_EQ(x17, x21, 0x0000000B) - RVTEST_IO_ASSERT_GPR_EQ(x17, x22, 0xFFFFFFEE) - RVTEST_IO_ASSERT_GPR_EQ(x17, x23, 0x0000000E) - RVTEST_IO_ASSERT_GPR_EQ(x17, x24, 0x0000000D) - RVTEST_IO_ASSERT_GPR_EQ(x17, x25, 0xFFFFFFDD) - RVTEST_IO_ASSERT_GPR_EQ(x17, x26, 0xFFFFFFF0) - RVTEST_IO_ASSERT_GPR_EQ(x17, x27, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x17, x28, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x17, x29, 0x0000000F) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test load to x0\n"); # Addresses for test data and results - la x21, test_C_data - la x22, test_C_res + la x2, test_7_res - # Test - lb x0, 0(x21) + TEST_CASE(x4, x30, 0xb, x2, 0, \ + la x1, test_data; \ + lb x30, -0x1(x1); \ + ) + TEST_CASE(x4, x31, 0xe, x2, 4, \ + la x1, test_data; \ + lb x31, 0x1(x1); \ + ) - # Store results - sw x0, 0(x22) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - test for forwarding\n"); - - # Addresses for test data and results - la x21, test_D_data - la x22, test_D_res - - # Test - lw x23, 0(x21) - lb x24, 0(x23) - mv x25, x24 - - # Store results - sw x25, 0(x22) - - RVTEST_IO_ASSERT_GPR_EQ(x22, x25, 0xFFFFFFF0) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E1 - test store with same base and destination address\n"); - - # Addresses for test data and results - la x25, test_E1_data - la x26, test_E1_res - - # Test - lb x25, 0(x25) - - # Store results - sw x25, 0(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x25, 0x00000010) - - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E2 - test store with same base and destination address, base with offset\n"); - - # Addresses for test data and results - la x27, test_E2_data + 1 - la x28, test_E2_res - - # Test - lb x27, -1(x27) - - # Store results - sw x27, 0(x28) - - RVTEST_IO_ASSERT_GPR_EQ(x28, x27, 0xFFFFFF98) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 + .data + .align 4 +test_data_start: -test_A1_data: - .word 0x11F1F222 -test_A2_data: - .word 0xF33344F4 -test_A3_data: - .word 0x55F5F666 -test_A4_data: - .word 0xF77788F8 -test_A5_data: - .word 0x99090AAA - .word 0x0BBBCC0C -test_B_data: - .word 0xDD0D0EEE - .word 0x0FFF00F0 -test_C_data: - .word 0x12345678 -test_D_data: - .word test_D_data2_label -test_D_data2_label: - .word 0x9ABCDEF0 -test_E1_data: - .word 0x76543210 -test_E2_data: - .word 0xFEDCBA98 - + .word 0x11f1f222 + .word 0xf33344f4 + .word 0x55f5f666 + .word 0xf77788f8 + .word 0x99090aaa + .word 0xbbbcc0c +test_data: + .word 0xdd0d0eee + .word 0xfff00f0 + .word 0x12345678 + .word 0x9abcdef0 + .word 0x76543210 + .word 0xfedcba98 # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 4, 4, -1 -test_A2_res: - .fill 4, 4, -1 -test_A3_res: - .fill 4, 4, -1 -test_A4_res: - .fill 4, 4, -1 -test_A5_res: - .fill 4, 4, -1 -test_B_res: - .fill 12, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 1, 4, -1 -test_E1_res: - .fill 1, 4, -1 -test_E2_res: - .fill 1, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LBU-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LBU-01.S index 7d25763..40aa90b 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LBU-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LBU-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-LBU-01 +# RISC-V Compliance Test LBU-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,353 +10,275 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction LBU. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'LBU'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test base address + 0\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") + # Addresses for test data and results - la x31, test_A1_data - la x2, test_A1_res + la x5, test_1_res - # Test - lbu x3, 0(x31) - lbu x4, 1(x31) - lbu x5, 2(x31) - lbu x6, 3(x31) + TEST_CASE(x7, x0, 0x0, x5, 0, \ + la x31, test_data; \ + lbu x0, 0x0(x31); \ + ) + TEST_CASE(x7, x1, 0xbb, x5, 4, \ + la x30, test_data; \ + lbu x1, -0x2(x30); \ + ) + TEST_CASE(x7, x2, 0xdd, x5, 8, \ + la x29, test_data; \ + lbu x2, 0x3(x29); \ + ) + TEST_CASE(x7, x3, 0xc, x5, 12, \ + la x28, test_data; \ + lbu x3, -0x4(x28); \ + ) + TEST_CASE(x7, x4, 0xd, x5, 16, \ + la x27, test_data; \ + lbu x4, 0x2(x27); \ + ) - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000022) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x000000F2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x000000F1) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000011) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test base address - 1\n"); # Addresses for test data and results - la x24, test_A2_data + 1 - la x5, test_A2_res + la x1, test_2_res - # Test - lbu x25, -1(x24) - lbu x26, +0(x24) - lbu x27, +1(x24) - lbu x28, +2(x24) + TEST_CASE(x3, x5, 0xf0, x1, 0, \ + la x26, test_data; \ + lbu x5, 0x4(x26); \ + ) + TEST_CASE(x3, x6, 0xb, x1, 4, \ + la x25, test_data; \ + lbu x6, -0x1(x25); \ + ) + TEST_CASE(x3, x7, 0xe, x1, 8, \ + la x24, test_data; \ + lbu x7, 0x1(x24); \ + ) + TEST_CASE(x3, x8, 0xee, x1, 12, \ + la x23, test_data; \ + lbu x8, 0x0(x23); \ + ) + TEST_CASE(x3, x9, 0xbb, x1, 16, \ + la x22, test_data; \ + lbu x9, -0x2(x22); \ + ) - # Store results - sw x25, 0(x5) - sw x26, 4(x5) - sw x27, 8(x5) - sw x28, 12(x5) - RVTEST_IO_ASSERT_GPR_EQ(x5, x25, 0x000000F4) - RVTEST_IO_ASSERT_GPR_EQ(x5, x26, 0x00000044) - RVTEST_IO_ASSERT_GPR_EQ(x5, x27, 0x00000033) - RVTEST_IO_ASSERT_GPR_EQ(x5, x28, 0x000000F3) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test base address + 1\n"); # Addresses for test data and results - la x7, test_A3_data - 1 - la x8, test_A3_res + la x1, test_3_res - # Test - lbu x30, 1(x7) - lbu x31, 2(x7) - lbu x1, 3(x7) - lbu x2, 4(x7) + TEST_CASE(x8, x10, 0xdd, x1, 0, \ + la x21, test_data; \ + lbu x10, 0x3(x21); \ + ) + TEST_CASE(x8, x11, 0xc, x1, 4, \ + la x20, test_data; \ + lbu x11, -0x4(x20); \ + ) + TEST_CASE(x8, x12, 0xd, x1, 8, \ + la x19, test_data; \ + lbu x12, 0x2(x19); \ + ) + TEST_CASE(x8, x13, 0xf0, x1, 12, \ + la x18, test_data; \ + lbu x13, 0x4(x18); \ + ) + TEST_CASE(x8, x14, 0xb, x1, 16, \ + la x17, test_data; \ + lbu x14, -0x1(x17); \ + ) - # Store results - sw x30, 0(x8) - sw x31, 4(x8) - sw x1, 8(x8) - sw x2, 12(x8) - RVTEST_IO_ASSERT_GPR_EQ(x8, x30, 0x00000066) - RVTEST_IO_ASSERT_GPR_EQ(x8, x31, 0x000000F6) - RVTEST_IO_ASSERT_GPR_EQ(x8, x1, 0x000000F5) - RVTEST_IO_ASSERT_GPR_EQ(x8, x2, 0x00000055) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - test base address - 2048\n"); # Addresses for test data and results - la x10, test_A4_data + 2048 - la x11, test_A4_res + la x2, test_4_res - # Test - lbu x12, 0xFFFFF800(x10) - lbu x13, 0xFFFFF801(x10) - lbu x14, 0xFFFFF802(x10) - lbu x15, 0xFFFFF803(x10) + TEST_CASE(x4, x15, 0xe, x2, 0, \ + la x16, test_data; \ + lbu x15, 0x1(x16); \ + ) + TEST_CASE(x4, x16, 0xee, x2, 4, \ + la x15, test_data; \ + lbu x16, 0x0(x15); \ + ) + TEST_CASE(x4, x17, 0xbb, x2, 8, \ + la x14, test_data; \ + lbu x17, -0x2(x14); \ + ) + TEST_CASE(x4, x18, 0xdd, x2, 12, \ + la x13, test_data; \ + lbu x18, 0x3(x13); \ + ) + TEST_CASE(x4, x19, 0xc, x2, 16, \ + la x12, test_data; \ + lbu x19, -0x4(x12); \ + ) - # Store results - sw x12, 0(x11) - sw x13, 4(x11) - sw x14, 8(x11) - sw x15, 12(x11) - RVTEST_IO_ASSERT_GPR_EQ(x11, x12, 0x000000F8) - RVTEST_IO_ASSERT_GPR_EQ(x11, x13, 0x00000088) - RVTEST_IO_ASSERT_GPR_EQ(x11, x14, 0x00000077) - RVTEST_IO_ASSERT_GPR_EQ(x11, x15, 0x000000F7) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - test base address + 2047\n"); # Addresses for test data and results - la x13, test_A5_data - 2044 - la x14, test_A5_res + la x1, test_5_res - # Test - lbu x15, 0x7FC(x13) - lbu x16, 0x7FD(x13) - lbu x17, 0x7FE(x13) - lbu x18, 0x7FF(x13) + TEST_CASE(x3, x20, 0xd, x1, 0, \ + la x11, test_data; \ + lbu x20, 0x2(x11); \ + ) + TEST_CASE(x3, x21, 0xf0, x1, 4, \ + la x10, test_data; \ + lbu x21, 0x4(x10); \ + ) + TEST_CASE(x3, x22, 0xb, x1, 8, \ + la x9, test_data; \ + lbu x22, -0x1(x9); \ + ) + TEST_CASE(x3, x23, 0xe, x1, 12, \ + la x8, test_data; \ + lbu x23, 0x1(x8); \ + ) + TEST_CASE(x3, x24, 0xee, x1, 16, \ + la x7, test_data; \ + lbu x24, 0x0(x7); \ + ) - # Store results - sw x15, 0(x14) - sw x16, 4(x14) - sw x17, 8(x14) - sw x18, 12(x14) - RVTEST_IO_ASSERT_GPR_EQ(x14, x15, 0x000000AA) - RVTEST_IO_ASSERT_GPR_EQ(x14, x16, 0x0000000A) - RVTEST_IO_ASSERT_GPR_EQ(x14, x17, 0x00000009) - RVTEST_IO_ASSERT_GPR_EQ(x14, x18, 0x00000099) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test base address + -4,-1, ..., 6, 7\n"); # Addresses for test data and results - la x16, test_B_data - la x17, test_B_res + la x1, test_6_res - # Test - lbu x18, -4(x16) - lbu x19, -3(x16) - lbu x20, -2(x16) - lbu x21, -1(x16) - lbu x22, 0(x16) - lbu x23, 1(x16) - lbu x24, 2(x16) - lbu x25, 3(x16) - lbu x26, 4(x16) - lbu x27, 5(x16) - lbu x28, 6(x16) - lbu x29, 7(x16) + TEST_CASE(x8, x25, 0xbb, x1, 0, \ + la x6, test_data; \ + lbu x25, -0x2(x6); \ + ) + TEST_CASE(x8, x26, 0xdd, x1, 4, \ + la x5, test_data; \ + lbu x26, 0x3(x5); \ + ) + TEST_CASE(x8, x27, 0xc, x1, 8, \ + la x4, test_data; \ + lbu x27, -0x4(x4); \ + ) + TEST_CASE(x8, x28, 0xd, x1, 12, \ + la x3, test_data; \ + lbu x28, 0x2(x3); \ + ) + TEST_CASE(x8, x29, 0xf0, x1, 16, \ + la x2, test_data; \ + lbu x29, 0x4(x2); \ + ) - # Store results - sw x18, 0(x17) - sw x19, 4(x17) - sw x20, 8(x17) - sw x21, 12(x17) - sw x22, 16(x17) - sw x23, 20(x17) - sw x24, 24(x17) - sw x25, 28(x17) - sw x26, 32(x17) - sw x27, 36(x17) - sw x28, 40(x17) - sw x29, 44(x17) - RVTEST_IO_ASSERT_GPR_EQ(x17, x18, 0x0000000C) - RVTEST_IO_ASSERT_GPR_EQ(x17, x19, 0x000000CC) - RVTEST_IO_ASSERT_GPR_EQ(x17, x20, 0x000000BB) - RVTEST_IO_ASSERT_GPR_EQ(x17, x21, 0x0000000B) - RVTEST_IO_ASSERT_GPR_EQ(x17, x22, 0x000000EE) - RVTEST_IO_ASSERT_GPR_EQ(x17, x23, 0x0000000E) - RVTEST_IO_ASSERT_GPR_EQ(x17, x24, 0x0000000D) - RVTEST_IO_ASSERT_GPR_EQ(x17, x25, 0x000000DD) - RVTEST_IO_ASSERT_GPR_EQ(x17, x26, 0x000000F0) - RVTEST_IO_ASSERT_GPR_EQ(x17, x27, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x17, x28, 0x000000FF) - RVTEST_IO_ASSERT_GPR_EQ(x17, x29, 0x0000000F) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test load to x0\n"); # Addresses for test data and results - la x21, test_C_data - la x22, test_C_res + la x2, test_7_res - # Test - lbu x0, 0(x21) + TEST_CASE(x4, x30, 0xb, x2, 0, \ + la x1, test_data; \ + lbu x30, -0x1(x1); \ + ) + TEST_CASE(x4, x31, 0xe, x2, 4, \ + la x1, test_data; \ + lbu x31, 0x1(x1); \ + ) - # Store results - sw x0, 0(x22) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - test for forwarding\n"); - - # Addresses for test data and results - la x21, test_D_data - la x22, test_D_res - - # Test - lw x23, 0(x21) - lbu x24, 0(x23) - mv x25, x24 - - # Store results - sw x25, 0(x22) - - RVTEST_IO_ASSERT_GPR_EQ(x22, x25, 0x000000F0) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E1 - test store with same base and destination address\n"); - - # Addresses for test data and results - la x25, test_E1_data - la x26, test_E1_res - - # Test - lbu x25, 0(x25) - - # Store results - sw x25, 0(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x25, 0x00000010) - - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E2 - test store with same base and destination address, base with offset\n"); - - # Addresses for test data and results - la x27, test_E2_data + 1 - la x28, test_E2_res - - # Test - lbu x27, -1(x27) - - # Store results - sw x27, 0(x28) - - RVTEST_IO_ASSERT_GPR_EQ(x28, x27, 0x00000098) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 + .data + .align 4 +test_data_start: -test_A1_data: - .word 0x11F1F222 -test_A2_data: - .word 0xF33344F4 -test_A3_data: - .word 0x55F5F666 -test_A4_data: - .word 0xF77788F8 -test_A5_data: - .word 0x99090AAA - .word 0x0BBBCC0C -test_B_data: - .word 0xDD0D0EEE - .word 0x0FFF00F0 -test_C_data: - .word 0x12345678 -test_D_data: - .word test_D_data2_label -test_D_data2_label: - .word 0x9ABCDEF0 -test_E1_data: - .word 0x76543210 -test_E2_data: - .word 0xFEDCBA98 - + .word 0x11f1f222 + .word 0xf33344f4 + .word 0x55f5f666 + .word 0xf77788f8 + .word 0x99090aaa + .word 0xbbbcc0c +test_data: + .word 0xdd0d0eee + .word 0xfff00f0 + .word 0x12345678 + .word 0x9abcdef0 + .word 0x76543210 + .word 0xfedcba98 # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 4, 4, -1 -test_A2_res: - .fill 4, 4, -1 -test_A3_res: - .fill 4, 4, -1 -test_A4_res: - .fill 4, 4, -1 -test_A5_res: - .fill 4, 4, -1 -test_B_res: - .fill 12, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 1, 4, -1 -test_E1_res: - .fill 1, 4, -1 -test_E2_res: - .fill 1, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LH-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LH-01.S index e3b88b6..caa25cf 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LH-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LH-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-LH-01 +# RISC-V Compliance Test LH-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,306 +10,275 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction LH. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'LH'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test base address + 0\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") + # Addresses for test data and results - la x31, test_A1_data - la x2, test_A1_res + la x5, test_1_res - # Test - lh x3, 0(x31) - lh x4, 2(x31) + TEST_CASE(x7, x0, 0x0, x5, 0, \ + la x31, test_data; \ + lh x0, 0x0(x31); \ + ) + TEST_CASE(x7, x1, 0xbbb, x5, 4, \ + la x30, test_data; \ + lh x1, -0x2(x30); \ + ) + TEST_CASE(x7, x2, 0xffffdd0d, x5, 8, \ + la x29, test_data; \ + lh x2, 0x2(x29); \ + ) + TEST_CASE(x7, x3, 0xffffcc0c, x5, 12, \ + la x28, test_data; \ + lh x3, -0x4(x28); \ + ) + TEST_CASE(x7, x4, 0xffffdd0d, x5, 16, \ + la x27, test_data; \ + lh x4, 0x2(x27); \ + ) - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0xFFFFF222) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x000011F1) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test base address - 1\n"); # Addresses for test data and results - la x24, test_A2_data + 1 - la x5, test_A2_res + la x1, test_2_res - # Test - lh x25, -1(x24) - lh x26, +1(x24) + TEST_CASE(x3, x5, 0xf0, x1, 0, \ + la x26, test_data; \ + lh x5, 0x4(x26); \ + ) + TEST_CASE(x3, x6, 0xeee, x1, 4, \ + la x25, test_data; \ + lh x6, 0x0(x25); \ + ) + TEST_CASE(x3, x7, 0xeee, x1, 8, \ + la x24, test_data; \ + lh x7, 0x0(x24); \ + ) + TEST_CASE(x3, x8, 0xeee, x1, 12, \ + la x23, test_data; \ + lh x8, 0x0(x23); \ + ) + TEST_CASE(x3, x9, 0xbbb, x1, 16, \ + la x22, test_data; \ + lh x9, -0x2(x22); \ + ) - # Store results - sw x25, 0(x5) - sw x26, 4(x5) - RVTEST_IO_ASSERT_GPR_EQ(x5, x25, 0x000044F4) - RVTEST_IO_ASSERT_GPR_EQ(x5, x26, 0xFFFFF333) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test base address + 1\n"); # Addresses for test data and results - la x7, test_A3_data - 1 - la x8, test_A3_res + la x1, test_3_res - # Test - lh x30, 1(x7) - lh x31, 3(x7) + TEST_CASE(x8, x10, 0xffffdd0d, x1, 0, \ + la x21, test_data; \ + lh x10, 0x2(x21); \ + ) + TEST_CASE(x8, x11, 0xffffcc0c, x1, 4, \ + la x20, test_data; \ + lh x11, -0x4(x20); \ + ) + TEST_CASE(x8, x12, 0xffffdd0d, x1, 8, \ + la x19, test_data; \ + lh x12, 0x2(x19); \ + ) + TEST_CASE(x8, x13, 0xf0, x1, 12, \ + la x18, test_data; \ + lh x13, 0x4(x18); \ + ) + TEST_CASE(x8, x14, 0xeee, x1, 16, \ + la x17, test_data; \ + lh x14, 0x0(x17); \ + ) - # Store results - sw x30, 0(x8) - sw x31, 4(x8) - RVTEST_IO_ASSERT_GPR_EQ(x8, x30, 0xFFFFF666) - RVTEST_IO_ASSERT_GPR_EQ(x8, x31, 0x000055F5) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - test base address - 2048\n"); # Addresses for test data and results - la x10, test_A4_data + 2048 - la x11, test_A4_res + la x2, test_4_res - # Test - lh x12, 0xFFFFF800(x10) - lh x13, 0xFFFFF802(x10) + TEST_CASE(x4, x15, 0xeee, x2, 0, \ + la x16, test_data; \ + lh x15, 0x0(x16); \ + ) + TEST_CASE(x4, x16, 0xeee, x2, 4, \ + la x15, test_data; \ + lh x16, 0x0(x15); \ + ) + TEST_CASE(x4, x17, 0xbbb, x2, 8, \ + la x14, test_data; \ + lh x17, -0x2(x14); \ + ) + TEST_CASE(x4, x18, 0xffffdd0d, x2, 12, \ + la x13, test_data; \ + lh x18, 0x2(x13); \ + ) + TEST_CASE(x4, x19, 0xffffcc0c, x2, 16, \ + la x12, test_data; \ + lh x19, -0x4(x12); \ + ) - # Store results - sw x12, 0(x11) - sw x13, 4(x11) - RVTEST_IO_ASSERT_GPR_EQ(x11, x12, 0xFFFF88F8) - RVTEST_IO_ASSERT_GPR_EQ(x11, x13, 0xFFFFF777) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - test base address + 2047\n"); # Addresses for test data and results - la x13, test_A5_data - 2045 - la x14, test_A5_res + la x1, test_5_res - # Test - lh x15, 0x7FD(x13) - lh x16, 0x7FF(x13) + TEST_CASE(x3, x20, 0xffffdd0d, x1, 0, \ + la x11, test_data; \ + lh x20, 0x2(x11); \ + ) + TEST_CASE(x3, x21, 0xf0, x1, 4, \ + la x10, test_data; \ + lh x21, 0x4(x10); \ + ) + TEST_CASE(x3, x22, 0xeee, x1, 8, \ + la x9, test_data; \ + lh x22, 0x0(x9); \ + ) + TEST_CASE(x3, x23, 0xeee, x1, 12, \ + la x8, test_data; \ + lh x23, 0x0(x8); \ + ) + TEST_CASE(x3, x24, 0xeee, x1, 16, \ + la x7, test_data; \ + lh x24, 0x0(x7); \ + ) - # Store results - sw x15, 0(x14) - sw x16, 4(x14) - RVTEST_IO_ASSERT_GPR_EQ(x14, x15, 0x00000AAA) - RVTEST_IO_ASSERT_GPR_EQ(x14, x16, 0xFFFF9909) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test base address + -4,-2, 0, 2, 4, 6\n"); # Addresses for test data and results - la x16, test_B_data - la x17, test_B_res + la x1, test_6_res - # Test - lh x18, -4(x16) - lh x19, -2(x16) - lh x20, 0(x16) - lh x21, 2(x16) - lh x22, 4(x16) - lh x23, 6(x16) + TEST_CASE(x8, x25, 0xbbb, x1, 0, \ + la x6, test_data; \ + lh x25, -0x2(x6); \ + ) + TEST_CASE(x8, x26, 0xffffdd0d, x1, 4, \ + la x5, test_data; \ + lh x26, 0x2(x5); \ + ) + TEST_CASE(x8, x27, 0xffffcc0c, x1, 8, \ + la x4, test_data; \ + lh x27, -0x4(x4); \ + ) + TEST_CASE(x8, x28, 0xffffdd0d, x1, 12, \ + la x3, test_data; \ + lh x28, 0x2(x3); \ + ) + TEST_CASE(x8, x29, 0xf0, x1, 16, \ + la x2, test_data; \ + lh x29, 0x4(x2); \ + ) - # Store results - sw x18, 0(x17) - sw x19, 4(x17) - sw x20, 8(x17) - sw x21, 12(x17) - sw x22, 16(x17) - sw x23, 20(x17) - RVTEST_IO_ASSERT_GPR_EQ(x17, x18, 0xFFFFCC0C) - RVTEST_IO_ASSERT_GPR_EQ(x17, x19, 0x00000BBB) - RVTEST_IO_ASSERT_GPR_EQ(x17, x20, 0x00000EEE) - RVTEST_IO_ASSERT_GPR_EQ(x17, x21, 0xFFFFDD0D) - RVTEST_IO_ASSERT_GPR_EQ(x17, x22, 0x000000F0) - RVTEST_IO_ASSERT_GPR_EQ(x17, x23, 0x00000FFF) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test load to x0\n"); # Addresses for test data and results - la x21, test_C_data - la x22, test_C_res + la x2, test_7_res - # Test - lh x0, 0(x21) + TEST_CASE(x4, x30, 0xeee, x2, 0, \ + la x1, test_data; \ + lh x30, 0x0(x1); \ + ) + TEST_CASE(x4, x31, 0xeee, x2, 4, \ + la x1, test_data; \ + lh x31, 0x0(x1); \ + ) - # Store results - sw x0, 0(x22) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - test for forwarding\n"); - - # Addresses for test data and results - la x21, test_D_data - la x22, test_D_res - - # Test - lw x23, 0(x21) - lh x24, 0(x23) - mv x25, x24 - - # Store results - sw x25, 0(x22) - - RVTEST_IO_ASSERT_GPR_EQ(x22, x25, 0xFFFFDEF0) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E1 - test store with same base and destination address\n"); - - # Addresses for test data and results - la x25, test_E1_data - la x26, test_E1_res - - # Test - lh x25, 0(x25) - - # Store results - sw x25, 0(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x25, 0x00003210) - - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E2 - test store with same base and destination address, base with offset\n"); - - # Addresses for test data and results - la x27, test_E2_data + 1 - la x28, test_E2_res - - # Test - lh x27, -1(x27) - - # Store results - sw x27, 0(x28) - - RVTEST_IO_ASSERT_GPR_EQ(x28, x27, 0xFFFFBA98) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 + .data + .align 4 +test_data_start: -test_A1_data: - .word 0x11F1F222 -test_A2_data: - .word 0xF33344F4 -test_A3_data: - .word 0x55F5F666 -test_A4_data: - .word 0xF77788F8 -test_A5_data: - .word 0x99090AAA - .word 0x0BBBCC0C -test_B_data: - .word 0xDD0D0EEE - .word 0x0FFF00F0 -test_C_data: - .word 0x12345678 -test_D_data: - .word test_D_data2_label -test_D_data2_label: - .word 0x9ABCDEF0 - -test_E1_data: - .word 0x76543210 -test_E2_data: - .word 0xFEDCBA98 - + .word 0x11f1f222 + .word 0xf33344f4 + .word 0x55f5f666 + .word 0xf77788f8 + .word 0x99090aaa + .word 0xbbbcc0c +test_data: + .word 0xdd0d0eee + .word 0xfff00f0 + .word 0x12345678 + .word 0x9abcdef0 + .word 0x76543210 + .word 0xfedcba98 # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 2, 4, -1 -test_A2_res: - .fill 2, 4, -1 -test_A3_res: - .fill 2, 4, -1 -test_A4_res: - .fill 2, 4, -1 -test_A5_res: - .fill 2, 4, -1 -test_B_res: - .fill 6, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 1, 4, -1 -test_E1_res: - .fill 1, 4, -1 -test_E2_res: - .fill 1, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LHU-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LHU-01.S index 05b6e4a..4abffc7 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LHU-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LHU-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-LHU-01 +# RISC-V Compliance Test LHU-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,305 +10,275 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction LHU. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'LHU'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test base address + 0\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") + # Addresses for test data and results - la x31, test_A1_data - la x2, test_A1_res + la x5, test_1_res - # Test - lhu x3, 0(x31) - lhu x4, 2(x31) + TEST_CASE(x7, x0, 0x0, x5, 0, \ + la x31, test_data; \ + lhu x0, 0x0(x31); \ + ) + TEST_CASE(x7, x1, 0xbbb, x5, 4, \ + la x30, test_data; \ + lhu x1, -0x2(x30); \ + ) + TEST_CASE(x7, x2, 0xdd0d, x5, 8, \ + la x29, test_data; \ + lhu x2, 0x2(x29); \ + ) + TEST_CASE(x7, x3, 0xcc0c, x5, 12, \ + la x28, test_data; \ + lhu x3, -0x4(x28); \ + ) + TEST_CASE(x7, x4, 0xdd0d, x5, 16, \ + la x27, test_data; \ + lhu x4, 0x2(x27); \ + ) - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x0000F222) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x000011F1) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test base address - 1\n"); # Addresses for test data and results - la x24, test_A2_data + 1 - la x5, test_A2_res + la x1, test_2_res - # Test - lhu x25, -1(x24) - lhu x26, +1(x24) + TEST_CASE(x3, x5, 0xf0, x1, 0, \ + la x26, test_data; \ + lhu x5, 0x4(x26); \ + ) + TEST_CASE(x3, x6, 0xeee, x1, 4, \ + la x25, test_data; \ + lhu x6, 0x0(x25); \ + ) + TEST_CASE(x3, x7, 0xeee, x1, 8, \ + la x24, test_data; \ + lhu x7, 0x0(x24); \ + ) + TEST_CASE(x3, x8, 0xeee, x1, 12, \ + la x23, test_data; \ + lhu x8, 0x0(x23); \ + ) + TEST_CASE(x3, x9, 0xbbb, x1, 16, \ + la x22, test_data; \ + lhu x9, -0x2(x22); \ + ) - # Store results - sw x25, 0(x5) - sw x26, 4(x5) - RVTEST_IO_ASSERT_GPR_EQ(x5, x25, 0x000044F4) - RVTEST_IO_ASSERT_GPR_EQ(x5, x26, 0x0000F333) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test base address + 1\n"); # Addresses for test data and results - la x7, test_A3_data - 1 - la x8, test_A3_res + la x1, test_3_res - # Test - lhu x30, 1(x7) - lhu x31, 3(x7) + TEST_CASE(x8, x10, 0xdd0d, x1, 0, \ + la x21, test_data; \ + lhu x10, 0x2(x21); \ + ) + TEST_CASE(x8, x11, 0xcc0c, x1, 4, \ + la x20, test_data; \ + lhu x11, -0x4(x20); \ + ) + TEST_CASE(x8, x12, 0xdd0d, x1, 8, \ + la x19, test_data; \ + lhu x12, 0x2(x19); \ + ) + TEST_CASE(x8, x13, 0xf0, x1, 12, \ + la x18, test_data; \ + lhu x13, 0x4(x18); \ + ) + TEST_CASE(x8, x14, 0xeee, x1, 16, \ + la x17, test_data; \ + lhu x14, 0x0(x17); \ + ) - # Store results - sw x30, 0(x8) - sw x31, 4(x8) - RVTEST_IO_ASSERT_GPR_EQ(x8, x30, 0x0000F666) - RVTEST_IO_ASSERT_GPR_EQ(x8, x31, 0x000055F5) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - test base address - 2048\n"); # Addresses for test data and results - la x10, test_A4_data + 2048 - la x11, test_A4_res + la x2, test_4_res - # Test - lhu x12, 0xFFFFF800(x10) - lhu x13, 0xFFFFF802(x10) + TEST_CASE(x4, x15, 0xeee, x2, 0, \ + la x16, test_data; \ + lhu x15, 0x0(x16); \ + ) + TEST_CASE(x4, x16, 0xeee, x2, 4, \ + la x15, test_data; \ + lhu x16, 0x0(x15); \ + ) + TEST_CASE(x4, x17, 0xbbb, x2, 8, \ + la x14, test_data; \ + lhu x17, -0x2(x14); \ + ) + TEST_CASE(x4, x18, 0xdd0d, x2, 12, \ + la x13, test_data; \ + lhu x18, 0x2(x13); \ + ) + TEST_CASE(x4, x19, 0xcc0c, x2, 16, \ + la x12, test_data; \ + lhu x19, -0x4(x12); \ + ) - # Store results - sw x12, 0(x11) - sw x13, 4(x11) - RVTEST_IO_ASSERT_GPR_EQ(x11, x12, 0x000088F8) - RVTEST_IO_ASSERT_GPR_EQ(x11, x13, 0x0000F777) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - test base address + 2047\n"); # Addresses for test data and results - la x13, test_A5_data - 2045 - la x14, test_A5_res + la x1, test_5_res - # Test - lhu x15, 0x7FD(x13) - lhu x16, 0x7FF(x13) + TEST_CASE(x3, x20, 0xdd0d, x1, 0, \ + la x11, test_data; \ + lhu x20, 0x2(x11); \ + ) + TEST_CASE(x3, x21, 0xf0, x1, 4, \ + la x10, test_data; \ + lhu x21, 0x4(x10); \ + ) + TEST_CASE(x3, x22, 0xeee, x1, 8, \ + la x9, test_data; \ + lhu x22, 0x0(x9); \ + ) + TEST_CASE(x3, x23, 0xeee, x1, 12, \ + la x8, test_data; \ + lhu x23, 0x0(x8); \ + ) + TEST_CASE(x3, x24, 0xeee, x1, 16, \ + la x7, test_data; \ + lhu x24, 0x0(x7); \ + ) - # Store results - sw x15, 0(x14) - sw x16, 4(x14) - RVTEST_IO_ASSERT_GPR_EQ(x14, x15, 0x00000AAA) - RVTEST_IO_ASSERT_GPR_EQ(x14, x16, 0x00009909) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test base address + -4,-2, 0, 2, 4, 6\n"); # Addresses for test data and results - la x16, test_B_data - la x17, test_B_res + la x1, test_6_res - # Test - lhu x18, -4(x16) - lhu x19, -2(x16) - lhu x20, 0(x16) - lhu x21, 2(x16) - lhu x22, 4(x16) - lhu x23, 6(x16) + TEST_CASE(x8, x25, 0xbbb, x1, 0, \ + la x6, test_data; \ + lhu x25, -0x2(x6); \ + ) + TEST_CASE(x8, x26, 0xdd0d, x1, 4, \ + la x5, test_data; \ + lhu x26, 0x2(x5); \ + ) + TEST_CASE(x8, x27, 0xcc0c, x1, 8, \ + la x4, test_data; \ + lhu x27, -0x4(x4); \ + ) + TEST_CASE(x8, x28, 0xdd0d, x1, 12, \ + la x3, test_data; \ + lhu x28, 0x2(x3); \ + ) + TEST_CASE(x8, x29, 0xf0, x1, 16, \ + la x2, test_data; \ + lhu x29, 0x4(x2); \ + ) - # Store results - sw x18, 0(x17) - sw x19, 4(x17) - sw x20, 8(x17) - sw x21, 12(x17) - sw x22, 16(x17) - sw x23, 20(x17) - RVTEST_IO_ASSERT_GPR_EQ(x17, x18, 0x0000CC0C) - RVTEST_IO_ASSERT_GPR_EQ(x17, x19, 0x00000BBB) - RVTEST_IO_ASSERT_GPR_EQ(x17, x20, 0x00000EEE) - RVTEST_IO_ASSERT_GPR_EQ(x17, x21, 0x0000DD0D) - RVTEST_IO_ASSERT_GPR_EQ(x17, x22, 0x000000F0) - RVTEST_IO_ASSERT_GPR_EQ(x17, x23, 0x00000FFF) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test load to x0\n"); # Addresses for test data and results - la x21, test_C_data - la x22, test_C_res + la x2, test_7_res - # Test - lhu x0, 0(x21) + TEST_CASE(x4, x30, 0xeee, x2, 0, \ + la x1, test_data; \ + lhu x30, 0x0(x1); \ + ) + TEST_CASE(x4, x31, 0xeee, x2, 4, \ + la x1, test_data; \ + lhu x31, 0x0(x1); \ + ) - # Store results - sw x0, 0(x22) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - test for forwarding\n"); - - # Addresses for test data and results - la x21, test_D_data - la x22, test_D_res - - # Test - lw x23, 0(x21) - lhu x24, 0(x23) - mv x25, x24 - - # Store results - sw x25, 0(x22) - - RVTEST_IO_ASSERT_GPR_EQ(x22, x25, 0x0000DEF0) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E1 - test store with same base and destination address\n"); - - # Addresses for test data and results - la x25, test_E1_data - la x26, test_E1_res - - # Test - lhu x25, 0(x25) - - # Store results - sw x25, 0(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x25, 0x00003210) - - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E2 - test store with same base and destination address, base with offset\n"); - - # Addresses for test data and results - la x27, test_E2_data + 1 - la x28, test_E2_res - - # Test - lhu x27, -1(x27) - - # Store results - sw x27, 0(x28) - - RVTEST_IO_ASSERT_GPR_EQ(x28, x27, 0x0000BA98) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 + .data + .align 4 +test_data_start: -test_A1_data: - .word 0x11F1F222 -test_A2_data: - .word 0xF33344F4 -test_A3_data: - .word 0x55F5F666 -test_A4_data: - .word 0xF77788F8 -test_A5_data: - .word 0x99090AAA - .word 0x0BBBCC0C -test_B_data: - .word 0xDD0D0EEE - .word 0x0FFF00F0 -test_C_data: - .word 0x12345678 -test_D_data: - .word test_D_data2_label -test_D_data2_label: - .word 0x9ABCDEF0 -test_E1_data: - .word 0x76543210 -test_E2_data: - .word 0xFEDCBA98 - + .word 0x11f1f222 + .word 0xf33344f4 + .word 0x55f5f666 + .word 0xf77788f8 + .word 0x99090aaa + .word 0xbbbcc0c +test_data: + .word 0xdd0d0eee + .word 0xfff00f0 + .word 0x12345678 + .word 0x9abcdef0 + .word 0x76543210 + .word 0xfedcba98 # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 2, 4, -1 -test_A2_res: - .fill 2, 4, -1 -test_A3_res: - .fill 2, 4, -1 -test_A4_res: - .fill 2, 4, -1 -test_A5_res: - .fill 2, 4, -1 -test_B_res: - .fill 6, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 1, 4, -1 -test_E1_res: - .fill 1, 4, -1 -test_E2_res: - .fill 1, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LUI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LUI-01.S index 3bdcc07..dcf4f3a 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LUI-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LUI-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-LUI-01 +# RISC-V Compliance Test LUI-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,166 +10,227 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction LUI. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'LUI'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A - general test of LUI\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Address for test results - la x15, test_A_res + # --------------------------------------------------------------------------------------------- - # Test - lui x1, 0x0 - lui x3, 0x1 - lui x5, 0xFFFFF - lui x29, 0x7FFFF - lui x31, 0x80000 + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Store results - sw x1, 0(x15) - sw x3, 4(x15) - sw x5, 8(x15) - sw x29, 12(x15) - sw x31, 16(x15) - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x15, x1, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x15, x3, 0x00001000) - RVTEST_IO_ASSERT_GPR_EQ(x15, x5, 0xFFFFF000) - RVTEST_IO_ASSERT_GPR_EQ(x15, x29, 0x7FFFF000) - RVTEST_IO_ASSERT_GPR_EQ(x15, x31, 0x80000000) + # address for test results + la x5, test_1_res - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + TEST_CASE(x6, x0, 0x0, x5, 0, \ + lui x0, 0x0; \ + ) + TEST_CASE(x6, x1, 0x0, x5, 4, \ + lui x1, 0x0; \ + ) + TEST_CASE(x6, x2, 0x7ff000, x5, 8, \ + lui x2, 0x7ff; \ + ) + TEST_CASE(x6, x3, 0x1000, x5, 12, \ + lui x3, 0x1; \ + ) + TEST_CASE(x6, x4, 0x1234000, x5, 16, \ + lui x4, 0x1234; \ + ) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test LUI overwrites low bits\n"); - # Addresses for test data and results - la x15, test_B_data - la x16, test_B_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Load testdata - lw x2, 0(x15) - lw x4, 0(x15) - lw x6, 0(x15) - lw x28, 0(x15) - lw x30, 0(x15) - # Test - lui x2, 0x80000 - lui x4, 0x7FFFF - lui x6, 0 - lui x28, 1 - lui x30, 0xFFFFF + # address for test results + la x1, test_2_res - # Store results - sw x2, 0(x16) - sw x4, 4(x16) - sw x6, 8(x16) - sw x28, 12(x16) - sw x30, 16(x16) + TEST_CASE(x2, x5, 0x80000000, x1, 0, \ + lui x5, 0x80000; \ + ) + TEST_CASE(x2, x6, 0x1234000, x1, 4, \ + lui x6, 0x1234; \ + ) + TEST_CASE(x2, x7, 0xfffff000, x1, 8, \ + lui x7, 0xfffff; \ + ) + TEST_CASE(x2, x8, 0x1000, x1, 12, \ + lui x8, 0x1; \ + ) + TEST_CASE(x2, x9, 0x7ffff000, x1, 16, \ + lui x9, 0x7ffff; \ + ) - RVTEST_IO_ASSERT_GPR_EQ(x16, x2, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x16, x4, 0x7FFFF000) - RVTEST_IO_ASSERT_GPR_EQ(x16, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x16, x28, 0x00001000) - RVTEST_IO_ASSERT_GPR_EQ(x16, x30, 0xFFFFF000) - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test loading immediate using lui + addi or li alias\n"); - # Address for results - la x17, test_C_res + # address for test results + la x1, test_3_res - # Test - li x1, 0x42726E6F - li x15, 0x12345678 - li x30, 0x9ABCDEF0 + TEST_CASE(x7, x10, 0x54321000, x1, 0, \ + lui x10, 0x54321; \ + ) + TEST_CASE(x7, x11, 0x800000, x1, 4, \ + lui x11, 0x800; \ + ) + TEST_CASE(x7, x12, 0x0, x1, 8, \ + lui x12, 0x0; \ + ) + TEST_CASE(x7, x13, 0x7ff000, x1, 12, \ + lui x13, 0x7ff; \ + ) + TEST_CASE(x7, x14, 0x0, x1, 16, \ + lui x14, 0x0; \ + ) - lui x2, 0x42727 - addi x2, x2, 0xFFFFFE6F - lui x16, 0x12345 - addi x16, x16, 0x678 - lui x31, 0x9ABCE - addi x31, x31, 0xFFFFFEF0 - # Store results - sw x1, 0(x17) - sw x15, 4(x17) - sw x30, 8(x17) - sw x2, 12(x17) - sw x16, 16(x17) - sw x31, 20(x17) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - RVTEST_IO_ASSERT_GPR_EQ(x17, x1, 0x42726E6F) - RVTEST_IO_ASSERT_GPR_EQ(x17, x15, 0x12345678) - RVTEST_IO_ASSERT_GPR_EQ(x17, x30, 0x9ABCDEF0) - RVTEST_IO_ASSERT_GPR_EQ(x17, x2, 0x42726E6F) - RVTEST_IO_ASSERT_GPR_EQ(x17, x16, 0x12345678) - RVTEST_IO_ASSERT_GPR_EQ(x17, x31, 0x9ABCDEF0) - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + # address for test results + la x2, test_4_res - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + TEST_CASE(x3, x15, 0x1000, x2, 0, \ + lui x15, 0x1; \ + ) + TEST_CASE(x3, x16, 0x0, x2, 4, \ + lui x16, 0x0; \ + ) + TEST_CASE(x3, x17, 0x0, x2, 8, \ + lui x17, 0x0; \ + ) + TEST_CASE(x3, x18, 0x7ff000, x2, 12, \ + lui x18, 0x7ff; \ + ) + TEST_CASE(x3, x19, 0x1000, x2, 16, \ + lui x19, 0x1; \ + ) - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x1, test_5_res + + TEST_CASE(x2, x20, 0x1234000, x1, 0, \ + lui x20, 0x1234; \ + ) + TEST_CASE(x2, x21, 0x80000000, x1, 4, \ + lui x21, 0x80000; \ + ) + TEST_CASE(x2, x22, 0x1234000, x1, 8, \ + lui x22, 0x1234; \ + ) + TEST_CASE(x2, x23, 0xfffff000, x1, 12, \ + lui x23, 0xfffff; \ + ) + TEST_CASE(x2, x24, 0x1000, x1, 16, \ + lui x24, 0x1; \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x1, test_6_res + + TEST_CASE(x7, x25, 0x7ffff000, x1, 0, \ + lui x25, 0x7ffff; \ + ) + TEST_CASE(x7, x26, 0x54321000, x1, 4, \ + lui x26, 0x54321; \ + ) + TEST_CASE(x7, x27, 0x800000, x1, 8, \ + lui x27, 0x800; \ + ) + TEST_CASE(x7, x28, 0x0, x1, 12, \ + lui x28, 0x0; \ + ) + TEST_CASE(x7, x29, 0x7ff000, x1, 16, \ + lui x29, 0x7ff; \ + ) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x2, test_7_res + + TEST_CASE(x3, x30, 0x0, x2, 0, \ + lui x30, 0x0; \ + ) + TEST_CASE(x3, x31, 0x1000, x2, 4, \ + lui x31, 0x1; \ + ) + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_B_data: - .word 0x11111111 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A_res: - .fill 5, 4, -1 -test_B_res: - .fill 5, 4, -1 -test_C_res: - .fill 6, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LW-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LW-01.S index d07ccf2..dff1b6f 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LW-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-LW-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-LW-01 +# RISC-V Compliance Test LW-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,280 +10,275 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction LW. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'LW'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test base address + 0\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") + # Addresses for test data and results - la x31, test_A1_data - la x2, test_A1_res + la x5, test_1_res - # Test - lw x3, 0(x31) + TEST_CASE(x7, x0, 0x0, x5, 0, \ + la x31, test_data; \ + lw x0, 0x0(x31); \ + ) + TEST_CASE(x7, x1, 0xdd0d0eee, x5, 4, \ + la x30, test_data; \ + lw x1, 0x0(x30); \ + ) + TEST_CASE(x7, x2, 0xdd0d0eee, x5, 8, \ + la x29, test_data; \ + lw x2, 0x0(x29); \ + ) + TEST_CASE(x7, x3, 0xbbbcc0c, x5, 12, \ + la x28, test_data; \ + lw x3, -0x4(x28); \ + ) + TEST_CASE(x7, x4, 0xdd0d0eee, x5, 16, \ + la x27, test_data; \ + lw x4, 0x0(x27); \ + ) - # Store results - sw x3, 0(x2) - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x11F1F222) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test base address - 1\n"); # Addresses for test data and results - la x24, test_A2_data + 1 - la x5, test_A2_res + la x1, test_2_res - # Test - lw x25, -1(x24) + TEST_CASE(x3, x5, 0xfff00f0, x1, 0, \ + la x26, test_data; \ + lw x5, 0x4(x26); \ + ) + TEST_CASE(x3, x6, 0xdd0d0eee, x1, 4, \ + la x25, test_data; \ + lw x6, 0x0(x25); \ + ) + TEST_CASE(x3, x7, 0xdd0d0eee, x1, 8, \ + la x24, test_data; \ + lw x7, 0x0(x24); \ + ) + TEST_CASE(x3, x8, 0xdd0d0eee, x1, 12, \ + la x23, test_data; \ + lw x8, 0x0(x23); \ + ) + TEST_CASE(x3, x9, 0xdd0d0eee, x1, 16, \ + la x22, test_data; \ + lw x9, 0x0(x22); \ + ) - # Store results - sw x25, 0(x5) - RVTEST_IO_ASSERT_GPR_EQ(x5, x25, 0xF33344F4) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test base address + 1\n"); # Addresses for test data and results - la x7, test_A3_data - 1 - la x8, test_A3_res + la x1, test_3_res - # Test - lw x31, 1(x7) + TEST_CASE(x8, x10, 0xdd0d0eee, x1, 0, \ + la x21, test_data; \ + lw x10, 0x0(x21); \ + ) + TEST_CASE(x8, x11, 0xbbbcc0c, x1, 4, \ + la x20, test_data; \ + lw x11, -0x4(x20); \ + ) + TEST_CASE(x8, x12, 0xdd0d0eee, x1, 8, \ + la x19, test_data; \ + lw x12, 0x0(x19); \ + ) + TEST_CASE(x8, x13, 0xfff00f0, x1, 12, \ + la x18, test_data; \ + lw x13, 0x4(x18); \ + ) + TEST_CASE(x8, x14, 0xdd0d0eee, x1, 16, \ + la x17, test_data; \ + lw x14, 0x0(x17); \ + ) - # Store results - sw x31, 0(x8) - RVTEST_IO_ASSERT_GPR_EQ(x8, x31, 0x55F5F666) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - test base address - 2048\n"); # Addresses for test data and results - la x10, test_A4_data + 2048 - la x11, test_A4_res + la x2, test_4_res - # Test - lw x12, 0xFFFFF800(x10) + TEST_CASE(x4, x15, 0xdd0d0eee, x2, 0, \ + la x16, test_data; \ + lw x15, 0x0(x16); \ + ) + TEST_CASE(x4, x16, 0xdd0d0eee, x2, 4, \ + la x15, test_data; \ + lw x16, 0x0(x15); \ + ) + TEST_CASE(x4, x17, 0xdd0d0eee, x2, 8, \ + la x14, test_data; \ + lw x17, 0x0(x14); \ + ) + TEST_CASE(x4, x18, 0xdd0d0eee, x2, 12, \ + la x13, test_data; \ + lw x18, 0x0(x13); \ + ) + TEST_CASE(x4, x19, 0xbbbcc0c, x2, 16, \ + la x12, test_data; \ + lw x19, -0x4(x12); \ + ) - # Store results - sw x12, 0(x11) - RVTEST_IO_ASSERT_GPR_EQ(x11, x12, 0xF77788F8) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - test base address + 2047\n"); # Addresses for test data and results - la x13, test_A5_data - 2047 - la x14, test_A5_res + la x1, test_5_res - # Test - lw x15, 0x7FF(x13) + TEST_CASE(x3, x20, 0xdd0d0eee, x1, 0, \ + la x11, test_data; \ + lw x20, 0x0(x11); \ + ) + TEST_CASE(x3, x21, 0xfff00f0, x1, 4, \ + la x10, test_data; \ + lw x21, 0x4(x10); \ + ) + TEST_CASE(x3, x22, 0xdd0d0eee, x1, 8, \ + la x9, test_data; \ + lw x22, 0x0(x9); \ + ) + TEST_CASE(x3, x23, 0xdd0d0eee, x1, 12, \ + la x8, test_data; \ + lw x23, 0x0(x8); \ + ) + TEST_CASE(x3, x24, 0xdd0d0eee, x1, 16, \ + la x7, test_data; \ + lw x24, 0x0(x7); \ + ) - # Store results - sw x15, 0(x14) - RVTEST_IO_ASSERT_GPR_EQ(x14, x15, 0x99090AAA) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test base address + -4, 0, 4\n"); # Addresses for test data and results - la x16, test_B_data - la x17, test_B_res + la x1, test_6_res - # Test - lw x18, -4(x16) - lw x19, 0(x16) - lw x20, 4(x16) + TEST_CASE(x8, x25, 0xdd0d0eee, x1, 0, \ + la x6, test_data; \ + lw x25, 0x0(x6); \ + ) + TEST_CASE(x8, x26, 0xdd0d0eee, x1, 4, \ + la x5, test_data; \ + lw x26, 0x0(x5); \ + ) + TEST_CASE(x8, x27, 0xbbbcc0c, x1, 8, \ + la x4, test_data; \ + lw x27, -0x4(x4); \ + ) + TEST_CASE(x8, x28, 0xdd0d0eee, x1, 12, \ + la x3, test_data; \ + lw x28, 0x0(x3); \ + ) + TEST_CASE(x8, x29, 0xfff00f0, x1, 16, \ + la x2, test_data; \ + lw x29, 0x4(x2); \ + ) - # Store results - sw x18, 0(x17) - sw x19, 4(x17) - sw x20, 8(x17) - RVTEST_IO_ASSERT_GPR_EQ(x17, x18, 0x0BBBCC0C) - RVTEST_IO_ASSERT_GPR_EQ(x17, x19, 0xDD0D0EEE) - RVTEST_IO_ASSERT_GPR_EQ(x17, x20, 0x0FFF00F0) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test load to x0\n"); # Addresses for test data and results - la x21, test_C_data - la x22, test_C_res + la x2, test_7_res - # Test - lw x0, 0(x21) + TEST_CASE(x4, x30, 0xdd0d0eee, x2, 0, \ + la x1, test_data; \ + lw x30, 0x0(x1); \ + ) + TEST_CASE(x4, x31, 0xdd0d0eee, x2, 4, \ + la x1, test_data; \ + lw x31, 0x0(x1); \ + ) - # Store results - sw x0, 0(x22) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - test for forwarding\n"); - - # Addresses for test data and results - la x21, test_D_data - la x22, test_D_res - - # Test - lw x23, 0(x21) - lw x24, 0(x23) - mv x25, x24 - - # Store results - sw x25, 0(x22) - - RVTEST_IO_ASSERT_GPR_EQ(x22, x25, 0x9ABCDEF0) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E1 - test store with same base and destination address\n"); - - # Addresses for test data and results - la x25, test_E1_data - la x26, test_E1_res - - # Test - lw x25, 0(x25) - - # Store results - sw x25, 0(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x25, 0x76543210) - - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E2 - test store with same base and destination address, base with offset\n"); - - # Addresses for test data and results - la x27, test_E2_data + 1 - la x28, test_E2_res - - # Test - lw x27, -1(x27) - - # Store results - sw x27, 0(x28) - - RVTEST_IO_ASSERT_GPR_EQ(x28, x27, 0xFEDCBA98) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 + .data + .align 4 +test_data_start: -test_A1_data: - .word 0x11F1F222 -test_A2_data: - .word 0xF33344F4 -test_A3_data: - .word 0x55F5F666 -test_A4_data: - .word 0xF77788F8 -test_A5_data: - .word 0x99090AAA - .word 0x0BBBCC0C -test_B_data: - .word 0xDD0D0EEE - .word 0x0FFF00F0 -test_C_data: - .word 0x12345678 -test_D_data: - .word test_D_data2_label -test_D_data2_label: - .word 0x9ABCDEF0 -test_E1_data: - .word 0x76543210 -test_E2_data: - .word 0xFEDCBA98 + .word 0x11f1f222 + .word 0xf33344f4 + .word 0x55f5f666 + .word 0xf77788f8 + .word 0x99090aaa + .word 0xbbbcc0c +test_data: + .word 0xdd0d0eee + .word 0xfff00f0 + .word 0x12345678 + .word 0x9abcdef0 + .word 0x76543210 + .word 0xfedcba98 # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 1, 4, -1 -test_A2_res: - .fill 1, 4, -1 -test_A3_res: - .fill 1, 4, -1 -test_A4_res: - .fill 1, 4, -1 -test_A5_res: - .fill 1, 4, -1 -test_B_res: - .fill 3, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 1, 4, -1 -test_E1_res: - .fill 1, 4, -1 -test_E2_res: - .fill 1, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S index 4de65f9..0dc6869 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S
@@ -283,7 +283,7 @@ addi x30, x30, -2 csrw mepc, x30 - # store low bits of mbadaddr + # store low bits of mtval csrr x30, mtval andi x30, x30, 3 sw x30, 0(x1)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S index 5a20187..8fba0c5 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S
@@ -194,8 +194,8 @@ addi x30, x30, 4 csrw mepc, x30 - # store low bits of mbadaddr - csrr x30, mbadaddr + # store low bits of mtval + csrr x30, mtval andi x30, x30, 3 sw x30, 0(x1)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-OR-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-OR-01.S index 03a6729..0740530 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-OR-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-OR-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-OR-01 +# RISC-V Compliance Test OR-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,428 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction OR. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'OR'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region. RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - # Test - or x4, x3, x4 - or x5, x3, x5 - or x6, x3, x6 - or x7, x3, x7 - or x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(or, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(or, x1, x30, x15, 0xfffff801, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_RR_OP(or, x2, x29, x14, 0xffffffff, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(or, x3, x28, x13, 0xffffefff, 0x7ff, -0x1234, x5, 12, x6) # Testcase 3 + TEST_RR_OP(or, x4, x27, x12, 0x80000000, 0x0, 0x80000000, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(or, x5, x26, x11, 0x1a34, 0x800, 0x1234, x1, 0, x2) # Testcase 5 + TEST_RR_OP(or, x6, x25, x10, 0xffffffff, 0x7654321, 0xffffffff, x1, 4, x2) # Testcase 6 + TEST_RR_OP(or, x7, x24, x9, 0x7fffffff, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(or, x8, x23, x8, 0x7fffffff, 0x1, 0x7fffffff, x1, 12, x2) # Testcase 8 + TEST_RR_OP(or, x9, x22, x7, 0xffffffff, 0xffffffff, 0x7654321, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 0 - li x10, 1 - li x11, -1 - li x12, 0x7FFFFFFF - li x13, 0x80000000 - # Test - or x9, x8, x9 - or x10, x8, x10 - or x11, x8, x11 - or x12, x8, x12 - or x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x80000001) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(or, x10, x21, x6, 0x1a34, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_RR_OP(or, x11, x20, x5, 0x80000000, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_RR_OP(or, x12, x19, x4, 0xffffefff, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_RR_OP(or, x13, x18, x3, 0xffffffff, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_RR_OP(or, x14, x17, x2, 0xfffff801, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 0 - li x15, 1 - li x16, -1 - li x17, 0x7FFFFFFF - li x18, 0x80000000 + # address for test results + la x2, test_4_res - # Test - or x14, x13, x14 - or x15, x13, x15 - or x16, x13, x16 - or x17, x13, x17 - or x18, x13, x18 + TEST_RR_OP(or, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_RR_OP(or, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(or, x17, x14, x31, 0xfffff801, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_RR_OP(or, x18, x13, x30, 0xffffffff, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(or, x19, x12, x29, 0xffffefff, 0x7ff, -0x1234, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0xFFFFFFFF) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + TEST_RR_OP(or, x20, x11, x28, 0x80000000, 0x0, 0x80000000, x1, 0, x2) # Testcase 20 + TEST_RR_OP(or, x21, x10, x27, 0x1a34, 0x800, 0x1234, x1, 4, x2) # Testcase 21 + TEST_RR_OP(or, x22, x9, x26, 0xffffffff, 0x7654321, 0xffffffff, x1, 8, x2) # Testcase 22 + TEST_RR_OP(or, x23, x8, x25, 0x7fffffff, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(or, x24, x7, x24, 0x7fffffff, 0x1, 0x7fffffff, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x1) - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test execution - or x19, x18, x19 - or x20, x18, x20 - or x21, x18, x21 - or x22, x18, x22 - or x23, x18, x23 - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0xFFFFFFFF) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Register initialization - li x24, 0 - li x25, 1 - li x26, -1 - li x27, 0x7FFFFFFF - li x28, 0x80000000 - - # Test - or x24, x23, x24 - or x25, x23, x25 - or x26, x23, x26 - or x27, x23, x27 - or x28, x23, x28 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x80000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x80000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x25, test_B_data - la x26, test_B_res - - # Load testdata - lw x28, 0(x25) - - # Register initialization - li x4, 0x10 - li x5, 0x20 - li x6, 0x40 - li x7, 0x80 - li x8, 0x100 - li x9, 0xFFFFF800 - - # Test - or x29, x28, x4 - or x30, x29, x5 - or x31, x30, x6 - or x1, x31, x7 - or x2, x1, x8 - or x3, x2, x9 - - # store results - sw x4, 0(x26) - sw x28, 4(x26) - sw x29, 8(x26) - sw x30, 12(x26) - sw x31, 16(x26) - sw x1, 20(x26) - sw x2, 24(x26) - sw x3, 28(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x4, 0x00000010) - RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0x0000000D) - RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0x0000001D) - RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0x0000003D) - RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0x0000007D) - RVTEST_IO_ASSERT_GPR_EQ(x26, x1, 0x000000FD) - RVTEST_IO_ASSERT_GPR_EQ(x26, x2, 0x000001FD) - RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0xFFFFF9FD) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - or x0, x28, x27 - - # store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - or x0, x28, x27 - or x5, x0, x0 - - # store results - sw x0, 0(x2) - sw x5, 4(x2) - - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + TEST_RR_OP(or, x25, x6, x23, 0xffffffff, 0xffffffff, 0x7654321, x1, 0, x7) # Testcase 25 + TEST_RR_OP(or, x26, x5, x22, 0x1a34, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_RR_OP(or, x27, x4, x21, 0x80000000, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_RR_OP(or, x28, x3, x20, 0xffffefff, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_RR_OP(or, x29, x2, x19, 0xffffffff, -0x1, -0x1, x1, 16, x7) # Testcase 29 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving (or with x0)\n"); - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Load testdata - lw x3, 0(x1) - # Test - or x4, x3, x0 - or x5, x4, x0 - or x6, x0, x5 - or x14, x6, x0 - or x15, x14, x0 - or x16, x15, x0 - or x25, x0, x16 - or x26, x0, x25 - or x27, x26, x0 + # address for test results + la x2, test_7_res - # Store results - sw x4, 0(x2) - sw x26, 4(x2) - sw x27, 8(x2) + TEST_RR_OP(or, x30, x1, x18, 0xfffff801, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_RR_OP(or, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0x0000000D -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x36925814 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 8, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 3, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 -RV_COMPLIANCE_DATA_END # End of test output data region. +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ORI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ORI-01.S index b202e82..d6ceb8c 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ORI-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-ORI-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-ORI-01 +# RISC-V Compliance Test ORI-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,380 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction ORI. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'ORI'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - ori x4, x3, 1 - ori x5, x3, 0x7FF - ori x6, x3, 0xFFFFFFFF - ori x7, x3, 0 - ori x8, x3, 0xFFFFF800 - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + # address for test results + la x5, test_1_res - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x000007FF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0xFFFFF800) + TEST_IMM_OP(ori, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_IMM_OP(ori, x1, x30, 0xfffff801, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_IMM_OP(ori, x2, x29, 0xffffffff, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_IMM_OP(ori, x3, x28, 0xffffffff, 0x7ff, -0x800, x5, 12, x6) # Testcase 3 + TEST_IMM_OP(ori, x4, x27, 0xfffff800, 0x0, 0x800, x5, 16, x6) # Testcase 4 - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX immediate values\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - # Load testdata - lw x8, 0(x1) + # address for test results + la x1, test_2_res - # Test - ori x9, x8, 1 - ori x10, x8, 0x7FF - ori x11, x8, 0xFFFFFFFF - ori x12, x8, 0 - ori x13, x8, 0xFFFFF800 + TEST_IMM_OP(ori, x5, x26, 0xfffff800, 0x800, 0x800, x1, 0, x2) # Testcase 5 + TEST_IMM_OP(ori, x6, x25, 0xfffffb21, 0x7654321, 0x800, x1, 4, x2) # Testcase 6 + TEST_IMM_OP(ori, x7, x24, 0x7fffffff, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_IMM_OP(ori, x8, x23, 0xfffff801, 0x1, 0x800, x1, 12, x2) # Testcase 8 + TEST_IMM_OP(ori, x9, x22, 0xffffffff, 0xffffffff, 0x800, x1, 16, x2) # Testcase 9 - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x000007FF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFF801) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX immediate values\n"); + # address for test results + la x1, test_3_res - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + TEST_IMM_OP(ori, x10, x21, 0xfffffa34, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_IMM_OP(ori, x11, x20, 0x80000000, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_IMM_OP(ori, x12, x19, 0xffffefff, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_IMM_OP(ori, x13, x18, 0xffffffff, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_IMM_OP(ori, x14, x17, 0xfffff801, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # Load testdata - lw x13, 0(x1) - # Test - ori x14, x13, 1 - ori x15, x13, 0x7FF - ori x16, x13, 0xFFFFFFFF - ori x17, x13, 0 - ori x18, x13, 0xFFFFF800 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0xFFFFFFFF) + # address for test results + la x2, test_4_res - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + TEST_IMM_OP(ori, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_IMM_OP(ori, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_IMM_OP(ori, x17, x14, 0xfffff801, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_IMM_OP(ori, x18, x13, 0xffffffff, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_IMM_OP(ori, x19, x12, 0xffffffff, 0x7ff, -0x800, x2, 16, x3) # Testcase 19 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - # Load testdata - lw x18, 0(x1) - # Test - ori x19, x18, 1 - ori x20, x18, 0x7FF - ori x21, x18, 0xFFFFFFFF - ori x22, x18, 0 - ori x23, x18, 0xFFFFF800 + # address for test results + la x1, test_5_res - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + TEST_IMM_OP(ori, x20, x11, 0xfffff800, 0x0, 0x800, x1, 0, x2) # Testcase 20 + TEST_IMM_OP(ori, x21, x10, 0xfffff800, 0x800, 0x800, x1, 4, x2) # Testcase 21 + TEST_IMM_OP(ori, x22, x9, 0xfffffb21, 0x7654321, 0x800, x1, 8, x2) # Testcase 22 + TEST_IMM_OP(ori, x23, x8, 0x7fffffff, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_IMM_OP(ori, x24, x7, 0xfffff801, 0x1, 0x800, x1, 16, x2) # Testcase 24 - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0xFFFFFFFF) - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Test - ori x24, x23, 1 - ori x25, x23, 0x7FF - ori x26, x23, 0xFFFFFFFF - ori x27, x23, 0 - ori x28, x23, 0xFFFFF800 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x800007FF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0xFFFFF800) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - - # Load testdata - lw x28, 0(x26) - - # Test - ori x29, x28, 0x10 - ori x30, x29, 0x20 - ori x31, x30, 0x40 - ori x1, x31, 0x80 - ori x2, x1, 0x100 - ori x3, x2, 0xFFFFF800 - - # Store results - sw x28, 0(x27) - sw x29, 4(x27) - sw x30, 8(x27) - sw x31, 12(x27) - sw x1, 16(x27) - sw x2, 20(x27) - sw x3, 24(x27) - - - RVTEST_IO_ASSERT_GPR_EQ(x27, x28, 0x0000000D) - RVTEST_IO_ASSERT_GPR_EQ(x27, x29, 0x0000001D) - RVTEST_IO_ASSERT_GPR_EQ(x27, x30, 0x0000003D) - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x0000007D) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0x000000FD) - RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0x000001FD) - RVTEST_IO_ASSERT_GPR_EQ(x27, x3, 0xFFFFF9FD) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Test - ori x0, x5, 1 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Test - ori x0, x5, 1 - ori x5, x0, 1 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) + # address for test results + la x1, test_6_res - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + TEST_IMM_OP(ori, x25, x6, 0xffffffff, 0xffffffff, 0x800, x1, 0, x7) # Testcase 25 + TEST_IMM_OP(ori, x26, x5, 0xfffffa34, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_IMM_OP(ori, x27, x4, 0x80000000, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_IMM_OP(ori, x28, x3, 0xffffefff, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_IMM_OP(ori, x29, x2, 0xffffffff, -0x1, -0x1, x1, 16, x7) # Testcase 29 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving (ori with 0)\n"); - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Load testdata - lw x3, 0(x1) - # Test - ori x4, x3, 0 - ori x5, x4, 0 - ori x6, x5, 0 - ori x14, x6, 0 - ori x15, x14, 0 - ori x16, x15, 0 - ori x25, x16, 0 - ori x26, x25, 0 - ori x27, x26, 0 + # address for test results + la x2, test_7_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) + TEST_IMM_OP(ori, x30, x1, 0xfffff801, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_IMM_OP(ori, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0x0000000D -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x36925814 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SB-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SB-01.S index d2bbc05..3ee2909 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SB-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SB-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SB-01 +# RISC-V Compliance Test SB-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,363 +10,419 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SB. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SB'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test base address + 0\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Address for test results - la x1, test_A1_res + # --------------------------------------------------------------------------------------------- - # Set memory - li x31, 0xAAAABBBB - sw x31, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - li x2, 0x11F1F222 - sb x2, 0(x1) - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x11F1F222) - RVTEST_IO_ASSERT_GPR_EQ(x1, x31, 0xAAAABBBB) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test base address - 1\n"); - - # Address for test results - la x5, test_A2_res + 1 + # Addresses for test results + la x5, test_1_res # Clear memory - sw x0, -1(x5) - + sb x0, 0x0(x5) # Test - li x25, 0xF33344F4 - sb x25, 0xFFFFFFFF(x5) + li x16, -0x1 + addi x31, x5, 0 + sb x16, 0x0(x31) - RVTEST_IO_ASSERT_GPR_EQ(x5, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x5, x25, 0xF33344F4) + #RVTEST_IO_ASSERT_GPR_EQ(x6, x31, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x16, -0x1) + # Clear memory + sb x0, -0x2(x5) + # Test + li x15, 0x1 + addi x30, x5, 0 + sb x15, -0x2(x30) - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x6, x30, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x15, 0x1) + # Clear memory + sb x0, 0x3(x5) + # Test + li x14, 0x0 + addi x29, x5, 0 + sb x14, 0x3(x29) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test base address + 1\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x6, x29, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x14, 0x0) + # Clear memory + sb x0, -0x4(x5) + # Test + li x13, 0x7ff + addi x28, x5, 0 + sb x13, -0x4(x28) - # Address for test results - la x8, test_A3_res - 1 + #RVTEST_IO_ASSERT_GPR_EQ(x6, x28, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x13, 0x7ff) + # Clear memory + sb x0, 0x2(x5) + # Test + li x12, 0x0 + addi x27, x5, 0 + sb x12, 0x2(x27) + + #RVTEST_IO_ASSERT_GPR_EQ(x6, x27, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x12, 0x0) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") + + + # Addresses for test results + la x1, test_2_res # Clear memory - sw x0, 1(x8) - + sb x0, 0x4(x1) # Test - li x31, 0x55F5F666 - sb x31, +1(x8) + li x11, 0x800 + addi x26, x1, 0 + sb x11, 0x4(x26) - RVTEST_IO_ASSERT_GPR_EQ(x8, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x8, x31, 0x55F5F666) + #RVTEST_IO_ASSERT_GPR_EQ(x2, x26, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x800) + # Clear memory + sb x0, -0x1(x1) + # Test + li x10, 0x7654321 + addi x25, x1, 0 + sb x10, -0x1(x25) - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x2, x25, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7654321) + # Clear memory + sb x0, 0x1(x1) + # Test + li x9, 0x7fffffff + addi x24, x1, 0 + sb x9, 0x1(x24) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - test base address - 2048\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x2, x24, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x7fffffff) + # Clear memory + sb x0, 0x0(x1) + # Test + li x8, 0x1 + addi x23, x1, 0 + sb x8, 0x0(x23) - # Address for test results - la x11, test_A4_res + 2048 + #RVTEST_IO_ASSERT_GPR_EQ(x2, x23, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x1) + # Clear memory + sb x0, -0x2(x1) + # Test + li x7, 0xffffffff + addi x22, x1, 0 + sb x7, -0x2(x22) + + #RVTEST_IO_ASSERT_GPR_EQ(x2, x22, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0xffffffff) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") + + + # Addresses for test results + la x1, test_3_res # Clear memory - sw x0, -2048(x11) - + sb x0, 0x3(x1) # Test - li x12, 0xF77788F8 - sb x12, 0xFFFFF800(x11) + li x6, 0x1234 + addi x21, x1, 0 + sb x6, 0x3(x21) - RVTEST_IO_ASSERT_GPR_EQ(x11, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x11, x12, 0xF77788F8) + #RVTEST_IO_ASSERT_GPR_EQ(x7, x21, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x6, 0x1234) + # Clear memory + sb x0, -0x4(x1) + # Test + li x5, 0x80000000 + addi x20, x1, 0 + sb x5, -0x4(x20) - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x7, x20, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x5, 0x80000000) + # Clear memory + sb x0, 0x2(x1) + # Test + li x4, -0x1234 + addi x19, x1, 0 + sb x4, 0x2(x19) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - test base address + 2047\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x7, x19, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x4, -0x1234) + # Clear memory + sb x0, 0x4(x1) + # Test + li x3, -0x1 + addi x18, x1, 0 + sb x3, 0x4(x18) - # Address for test results - la x14, test_A5_res - 2047 + #RVTEST_IO_ASSERT_GPR_EQ(x7, x18, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x3, -0x1) + # Clear memory + sb x0, -0x1(x1) + # Test + li x2, -0x7ff + addi x17, x1, 0 + sb x2, -0x1(x17) + + #RVTEST_IO_ASSERT_GPR_EQ(x7, x17, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x2, -0x7ff) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # Addresses for test results + la x2, test_4_res # Clear memory - sw x0, 2047(x14) - + sb x0, 0x1(x2) # Test - li x15, 0x99090AAA - sb x15, 0x7FF(x14) + li x1, 0x0 + addi x16, x2, 0 + sb x1, 0x1(x16) - RVTEST_IO_ASSERT_GPR_EQ(x14, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x14, x15, 0x99090AAA) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test base address + -4, -3, ... , 7\n"); - - # Address for test results - la x17, test_B_res - + #RVTEST_IO_ASSERT_GPR_EQ(x3, x16, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x1, 0x0) + # Clear memory + sb x0, 0x0(x2) # Test - li x18, 0x1111110C - li x19, 0x222222CC - li x20, 0x333333BB - li x21, 0x4444440B - li x22, 0x555555EE - li x23, 0x6666660E - li x24, 0x7777770D - li x25, 0x888888DD - li x26, 0x999999F0 - li x27, 0xAAAAAA00 - li x28, 0xBBBBBBFF - li x29, 0xCCCCCC0F + li x0, -0x1 + addi x15, x2, 0 + sb x0, 0x0(x15) - # Store results - sb x18, -4(x17) - sb x19, -3(x17) - sb x20, -2(x17) - sb x21, -1(x17) - sb x22, 0(x17) - sb x23, 1(x17) - sb x24, 2(x17) - sb x25, 3(x17) - sb x26, 4(x17) - sb x27, 5(x17) - sb x28, 6(x17) - sb x29, 7(x17) - - RVTEST_IO_ASSERT_GPR_EQ(x17, x18, 0x1111110C) - RVTEST_IO_ASSERT_GPR_EQ(x17, x19, 0x222222CC) - RVTEST_IO_ASSERT_GPR_EQ(x17, x20, 0x333333BB) - RVTEST_IO_ASSERT_GPR_EQ(x17, x21, 0x4444440B) - RVTEST_IO_ASSERT_GPR_EQ(x17, x22, 0x555555EE) - RVTEST_IO_ASSERT_GPR_EQ(x17, x23, 0x6666660E) - RVTEST_IO_ASSERT_GPR_EQ(x17, x24, 0x7777770D) - RVTEST_IO_ASSERT_GPR_EQ(x17, x25, 0x888888DD) - RVTEST_IO_ASSERT_GPR_EQ(x17, x26, 0x999999F0) - RVTEST_IO_ASSERT_GPR_EQ(x17, x27, 0xAAAAAA00) - RVTEST_IO_ASSERT_GPR_EQ(x17, x28, 0xBBBBBBFF) - RVTEST_IO_ASSERT_GPR_EQ(x17, x29, 0xCCCCCC0F) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test store x0\n"); - - # Address for test results - la x22, test_C_res - - # Set memory - li x1, 0x87654321 - sw x1, 0(x22) - + #RVTEST_IO_ASSERT_GPR_EQ(x3, x15, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x0, 0) + # Clear memory + sb x0, -0x2(x2) # Test - li x0, 0x12345678 - sb x0, 0(x22) + li x31, 0x1 + addi x14, x2, 0 + sb x31, -0x2(x14) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x22, x1, 0x87654321) + #RVTEST_IO_ASSERT_GPR_EQ(x3, x14, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x31, 0x1) + # Clear memory + sb x0, 0x3(x2) + # Test + li x30, 0x0 + addi x13, x2, 0 + sb x30, 0x3(x13) - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x3, x13, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x30, 0x0) + # Clear memory + sb x0, -0x4(x2) + # Test + li x29, 0x7ff + addi x12, x2, 0 + sb x29, -0x4(x12) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D1 - test for forwarding (to address register)\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x3, x12, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x29, 0x7ff) - # Address for test data - la x21, test_D1_data + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # Addresses for test results + la x1, test_5_res # Clear memory - lw x1, 0(x21) - sw x0, 0(x1) - + sb x0, 0x2(x1) # Test - li x19, 0x11223344 - lw x23, 0(x21) - sb x19, 0(x23) + li x28, 0x0 + addi x11, x1, 0 + sb x28, 0x2(x11) - RVTEST_IO_ASSERT_GPR_EQ(x23, x19, 0x11223344) + #RVTEST_IO_ASSERT_GPR_EQ(x2, x11, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x0) + # Clear memory + sb x0, 0x4(x1) + # Test + li x27, 0x800 + addi x10, x1, 0 + sb x27, 0x4(x10) - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x2, x10, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x800) + # Clear memory + sb x0, -0x1(x1) + # Test + li x26, 0x7654321 + addi x9, x1, 0 + sb x26, -0x1(x9) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D2 - test for forwarding (to data register)\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x2, x9, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7654321) + # Clear memory + sb x0, 0x1(x1) + # Test + li x25, 0x7fffffff + addi x8, x1, 0 + sb x25, 0x1(x8) - # Address for test data - la x23, test_D2_data - la x24, test_D2_res + #RVTEST_IO_ASSERT_GPR_EQ(x2, x8, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x7fffffff) + # Clear memory + sb x0, 0x0(x1) + # Test + li x24, 0x1 + addi x7, x1, 0 + sb x24, 0x0(x7) + + #RVTEST_IO_ASSERT_GPR_EQ(x2, x7, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x1) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # Addresses for test results + la x1, test_6_res # Clear memory - sw x0, 0(x24) - + sb x0, -0x2(x1) # Test - lw x25, 0(x23) - sb x25, 0(x24) + li x23, 0xffffffff + addi x6, x1, 0 + sb x23, -0x2(x6) - RVTEST_IO_ASSERT_GPR_EQ(x24, x25, 0x9ABCDEF0) + #RVTEST_IO_ASSERT_GPR_EQ(x7, x6, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x23, 0xffffffff) + # Clear memory + sb x0, 0x3(x1) + # Test + li x22, 0x1234 + addi x5, x1, 0 + sb x22, 0x3(x5) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x7, x5, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x22, 0x1234) + # Clear memory + sb x0, -0x4(x1) + # Test + li x21, 0x80000000 + addi x4, x1, 0 + sb x21, -0x4(x4) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E1 - test war hazard (data register)\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x7, x4, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x21, 0x80000000) + # Clear memory + sb x0, 0x2(x1) + # Test + li x20, -0x1234 + addi x3, x1, 0 + sb x20, 0x2(x3) - # Address for test results - la x26, test_E1_res + #RVTEST_IO_ASSERT_GPR_EQ(x7, x3, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x20, -0x1234) + # Clear memory + sb x0, 0x4(x1) + # Test + li x19, -0x1 + addi x2, x1, 0 + sb x19, 0x4(x2) + + #RVTEST_IO_ASSERT_GPR_EQ(x7, x2, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x19, -0x1) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # Addresses for test results + la x2, test_7_res # Clear memory - sw x0, 0(x26) - + sb x0, -0x1(x2) # Test - li x25, 0x76543210 - sb x25, 0(x26) - mv x25, x0 + li x18, -0x7ff + addi x1, x2, 0 + sb x18, -0x1(x1) - RVTEST_IO_ASSERT_GPR_EQ(x26, x25, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E2 - test war hazard (address register)\n"); - - # Address for test results - la x28, test_E2_res - + #RVTEST_IO_ASSERT_GPR_EQ(x3, x1, test_7_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x18, -0x7ff) # Clear memory - sw x0, 0(x28) - + sb x0, 0x1(x2) # Test - li x27, 0x89ABCDEF - sb x27, 0(x28) - addi x28, x28, -4 + li x17, 0x0 + addi x1, x2, 0 + sb x17, 0x1(x1) - RVTEST_IO_ASSERT_GPR_EQ(x28, x27, 0x89ABCDEF) + #RVTEST_IO_ASSERT_GPR_EQ(x3, x1, test_7_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x17, 0x0) - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part F - test raw hazard in memory\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - # Address for test results - la x29, test_F_res + # --------------------------------------------------------------------------------------------- - # Clear memory - sw x0, 0(x29) - sw x0, 4(x29) - - # Test - li x27, 0x14725836 - sb x27, 0(x29) - lw x30, 0(x29) - sb x30, 4(x29) - - RVTEST_IO_ASSERT_GPR_EQ(x29, x27, 0x14725836) - RVTEST_IO_ASSERT_GPR_EQ(x29, x30, 0x00000036) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part G - test waw hazard in memory\n"); - - # Address for test results - la x1, test_G_res - - # Clear memory - sw x0, 0(x1) - - # Test - li x2, 0x96385201 - li x3, 0x25814963 - sb x2, 0(x1) - sb x3, 0(x1) - - RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x96385201) - RVTEST_IO_ASSERT_GPR_EQ(x1, x3, 0x25814963) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_D1_data: - .word test_D1_res -test_D2_data: - .word 0x9ABCDEF0 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 1, 4, -1 -test_A2_res: - .fill 1, 4, -1 -test_A3_res: - .fill 1, 4, -1 -test_A4_res: - .fill 1, 4, -1 -test_A5_res: - .fill 1, 4, -1 - .fill 1, 4, -1 -test_B_res: - .fill 2, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D1_res: - .fill 1, 4, -1 -test_D2_res: - .fill 1, 4, -1 -test_E1_res: - .fill 1, 4, -1 -test_E2_res: - .fill 1, 4, -1 -test_F_res: - .fill 2, 4, -1 -test_G_res: - .fill 1, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SH-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SH-01.S index 3719102..4363caa 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SH-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SH-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SH-01 +# RISC-V Compliance Test SH-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,345 +10,419 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SH. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SH'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test base address + 0\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Address for test results - la x1, test_A1_res + # --------------------------------------------------------------------------------------------- - # Set memory - li x31, 0xAAAABBBB - sw x31, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - li x2, 0x11F1F222 - sh x2, 0(x1) - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x11F1F222) - RVTEST_IO_ASSERT_GPR_EQ(x1, x31, 0xAAAABBBB) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test base address - 1\n"); - - # Address for test results - la x5, test_A2_res + 1 + # Addresses for test results + la x5, test_1_res # Clear memory - sw x0, -1(x5) - + sh x0, 0x0(x5) # Test - li x25, 0xF33344F4 - sh x25, 0xFFFFFFFF(x5) + li x16, -0x1 + addi x31, x5, 0 + sh x16, 0x0(x31) - RVTEST_IO_ASSERT_GPR_EQ(x5, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x5, x25, 0xF33344F4) + #RVTEST_IO_ASSERT_GPR_EQ(x6, x31, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x16, -0x1) + # Clear memory + sh x0, -0x2(x5) + # Test + li x15, 0x1 + addi x30, x5, 0 + sh x15, -0x2(x30) - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x6, x30, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x15, 0x1) + # Clear memory + sh x0, 0x2(x5) + # Test + li x14, 0x0 + addi x29, x5, 0 + sh x14, 0x2(x29) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test base address + 1\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x6, x29, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x14, 0x0) + # Clear memory + sh x0, -0x4(x5) + # Test + li x13, 0x7ff + addi x28, x5, 0 + sh x13, -0x4(x28) - # Address for test results - la x8, test_A3_res - 1 + #RVTEST_IO_ASSERT_GPR_EQ(x6, x28, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x13, 0x7ff) + # Clear memory + sh x0, 0x2(x5) + # Test + li x12, 0x0 + addi x27, x5, 0 + sh x12, 0x2(x27) + + #RVTEST_IO_ASSERT_GPR_EQ(x6, x27, test_1_res) + RVTEST_IO_ASSERT_GPR_EQ(x6, x12, 0x0) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") + + + # Addresses for test results + la x1, test_2_res # Clear memory - sw x0, 1(x8) - + sh x0, 0x4(x1) # Test - li x31, 0x55F5F666 - sh x31, +1(x8) + li x11, 0x800 + addi x26, x1, 0 + sh x11, 0x4(x26) - RVTEST_IO_ASSERT_GPR_EQ(x8, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x8, x31, 0x55F5F666) + #RVTEST_IO_ASSERT_GPR_EQ(x2, x26, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x800) + # Clear memory + sh x0, 0x0(x1) + # Test + li x10, 0x7654321 + addi x25, x1, 0 + sh x10, 0x0(x25) - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x2, x25, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x7654321) + # Clear memory + sh x0, 0x0(x1) + # Test + li x9, 0x7fffffff + addi x24, x1, 0 + sh x9, 0x0(x24) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - test base address - 2048\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x2, x24, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x7fffffff) + # Clear memory + sh x0, 0x0(x1) + # Test + li x8, 0x1 + addi x23, x1, 0 + sh x8, 0x0(x23) - # Address for test results - la x11, test_A4_res + 2048 + #RVTEST_IO_ASSERT_GPR_EQ(x2, x23, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x1) + # Clear memory + sh x0, -0x2(x1) + # Test + li x7, 0xffffffff + addi x22, x1, 0 + sh x7, -0x2(x22) + + #RVTEST_IO_ASSERT_GPR_EQ(x2, x22, test_2_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0xffffffff) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") + + + # Addresses for test results + la x1, test_3_res # Clear memory - sw x0, -2048(x11) - + sh x0, 0x2(x1) # Test - li x12, 0xF77788F8 - sh x12, 0xFFFFF800(x11) + li x6, 0x1234 + addi x21, x1, 0 + sh x6, 0x2(x21) - RVTEST_IO_ASSERT_GPR_EQ(x11, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x11, x12, 0xF77788F8) + #RVTEST_IO_ASSERT_GPR_EQ(x7, x21, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x6, 0x1234) + # Clear memory + sh x0, -0x4(x1) + # Test + li x5, 0x80000000 + addi x20, x1, 0 + sh x5, -0x4(x20) - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x7, x20, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x5, 0x80000000) + # Clear memory + sh x0, 0x2(x1) + # Test + li x4, -0x1234 + addi x19, x1, 0 + sh x4, 0x2(x19) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - test base address + 2047\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x7, x19, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x4, -0x1234) + # Clear memory + sh x0, 0x4(x1) + # Test + li x3, -0x1 + addi x18, x1, 0 + sh x3, 0x4(x18) - # Address for test results - la x14, test_A5_res - 2047 + #RVTEST_IO_ASSERT_GPR_EQ(x7, x18, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x3, -0x1) + # Clear memory + sh x0, 0x0(x1) + # Test + li x2, -0x7ff + addi x17, x1, 0 + sh x2, 0x0(x17) + + #RVTEST_IO_ASSERT_GPR_EQ(x7, x17, test_3_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x2, -0x7ff) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") + + + # Addresses for test results + la x2, test_4_res # Clear memory - sw x0, 2047(x14) - + sh x0, 0x0(x2) # Test - li x15, 0x99090AAA - sh x15, 0x7FF(x14) + li x1, 0x0 + addi x16, x2, 0 + sh x1, 0x0(x16) - RVTEST_IO_ASSERT_GPR_EQ(x14, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x14, x15, 0x99090AAA) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test base address + -4, -2, ... , 6\n"); - - # Address for test results - la x17, test_B_res - + #RVTEST_IO_ASSERT_GPR_EQ(x3, x16, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x1, 0x0) + # Clear memory + sh x0, 0x0(x2) # Test - li x18, 0x1111CC0C - li x19, 0x22220BBB - li x20, 0x33330EEE - li x21, 0x4444DD0D - li x22, 0x777700F0 - li x23, 0x66660FFF + li x0, -0x1 + addi x15, x2, 0 + sh x0, 0x0(x15) - # Store results - sh x18, -4(x17) - sh x19, -2(x17) - sh x20, 0(x17) - sh x21, 2(x17) - sh x22, 4(x17) - sh x23, 6(x17) - - RVTEST_IO_ASSERT_GPR_EQ(x17, x18, 0x1111CC0C) - RVTEST_IO_ASSERT_GPR_EQ(x17, x19, 0x22220BBB) - RVTEST_IO_ASSERT_GPR_EQ(x17, x20, 0x33330EEE) - RVTEST_IO_ASSERT_GPR_EQ(x17, x21, 0x4444DD0D) - RVTEST_IO_ASSERT_GPR_EQ(x17, x22, 0x777700F0) - RVTEST_IO_ASSERT_GPR_EQ(x17, x23, 0x66660FFF) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test store x0\n"); - - # Address for test results - la x22, test_C_res - - # Set memory - li x1, 0x87654321 - sw x1, 0(x22) - + #RVTEST_IO_ASSERT_GPR_EQ(x3, x15, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x0, 0) + # Clear memory + sh x0, -0x2(x2) # Test - li x0, 0x12345678 - sh x0, 0(x22) + li x31, 0x1 + addi x14, x2, 0 + sh x31, -0x2(x14) - RVTEST_IO_ASSERT_GPR_EQ(x22, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x22, x1, 0x87654321) + #RVTEST_IO_ASSERT_GPR_EQ(x3, x14, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x31, 0x1) + # Clear memory + sh x0, 0x2(x2) + # Test + li x30, 0x0 + addi x13, x2, 0 + sh x30, 0x2(x13) - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x3, x13, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x30, 0x0) + # Clear memory + sh x0, -0x4(x2) + # Test + li x29, 0x7ff + addi x12, x2, 0 + sh x29, -0x4(x12) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D1 - test for forwarding (to address register)\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x3, x12, test_4_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x29, 0x7ff) - # Address for test data - la x21, test_D1_data + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # Addresses for test results + la x1, test_5_res # Clear memory - lw x1, 0(x21) - sw x0, 0(x1) - + sh x0, 0x2(x1) # Test - li x19, 0x11223344 - lw x23, 0(x21) - sh x19, 0(x23) + li x28, 0x0 + addi x11, x1, 0 + sh x28, 0x2(x11) - RVTEST_IO_ASSERT_GPR_EQ(x23, x19, 0x11223344) + #RVTEST_IO_ASSERT_GPR_EQ(x2, x11, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x0) + # Clear memory + sh x0, 0x4(x1) + # Test + li x27, 0x800 + addi x10, x1, 0 + sh x27, 0x4(x10) - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x2, x10, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x800) + # Clear memory + sh x0, 0x0(x1) + # Test + li x26, 0x7654321 + addi x9, x1, 0 + sh x26, 0x0(x9) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D2 - test for forwarding (to data register)\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x2, x9, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7654321) + # Clear memory + sh x0, 0x0(x1) + # Test + li x25, 0x7fffffff + addi x8, x1, 0 + sh x25, 0x0(x8) - # Address for test data - la x23, test_D2_data - la x24, test_D2_res + #RVTEST_IO_ASSERT_GPR_EQ(x2, x8, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x7fffffff) + # Clear memory + sh x0, 0x0(x1) + # Test + li x24, 0x1 + addi x7, x1, 0 + sh x24, 0x0(x7) + + #RVTEST_IO_ASSERT_GPR_EQ(x2, x7, test_5_res) + RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x1) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # Addresses for test results + la x1, test_6_res # Clear memory - sw x0, 0(x24) - + sh x0, -0x2(x1) # Test - lw x25, 0(x23) - sh x25, 0(x24) + li x23, 0xffffffff + addi x6, x1, 0 + sh x23, -0x2(x6) - RVTEST_IO_ASSERT_GPR_EQ(x24, x25, 0x9ABCDEF0) + #RVTEST_IO_ASSERT_GPR_EQ(x7, x6, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x23, 0xffffffff) + # Clear memory + sh x0, 0x2(x1) + # Test + li x22, 0x1234 + addi x5, x1, 0 + sh x22, 0x2(x5) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x7, x5, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x22, 0x1234) + # Clear memory + sh x0, -0x4(x1) + # Test + li x21, 0x80000000 + addi x4, x1, 0 + sh x21, -0x4(x4) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E1 - test war hazard (data register)\n"); + #RVTEST_IO_ASSERT_GPR_EQ(x7, x4, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x21, 0x80000000) + # Clear memory + sh x0, 0x2(x1) + # Test + li x20, -0x1234 + addi x3, x1, 0 + sh x20, 0x2(x3) - # Address for test results - la x26, test_E1_res + #RVTEST_IO_ASSERT_GPR_EQ(x7, x3, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x20, -0x1234) + # Clear memory + sh x0, 0x4(x1) + # Test + li x19, -0x1 + addi x2, x1, 0 + sh x19, 0x4(x2) + + #RVTEST_IO_ASSERT_GPR_EQ(x7, x2, test_6_res) + RVTEST_IO_ASSERT_GPR_EQ(x7, x19, -0x1) + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # Addresses for test results + la x2, test_7_res # Clear memory - sw x0, 0(x26) - + sh x0, 0x0(x2) # Test - li x25, 0x76543210 - sh x25, 0(x26) - mv x25, x0 + li x18, -0x7ff + addi x1, x2, 0 + sh x18, 0x0(x1) - RVTEST_IO_ASSERT_GPR_EQ(x26, x25, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E2 - test war hazard (address register)\n"); - - # Address for test results - la x28, test_E2_res - + #RVTEST_IO_ASSERT_GPR_EQ(x3, x1, test_7_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x18, -0x7ff) # Clear memory - sw x0, 0(x28) - + sh x0, 0x0(x2) # Test - li x27, 0x89ABCDEF - sh x27, 0(x28) - addi x28, x28, -4 + li x17, 0x0 + addi x1, x2, 0 + sh x17, 0x0(x1) - RVTEST_IO_ASSERT_GPR_EQ(x28, x27, 0x89ABCDEF) + #RVTEST_IO_ASSERT_GPR_EQ(x3, x1, test_7_res) + RVTEST_IO_ASSERT_GPR_EQ(x3, x17, 0x0) - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part F - test raw hazard in memory\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - # Address for test results - la x29, test_F_res + # --------------------------------------------------------------------------------------------- - # Clear memory - sw x0, 0(x29) - sw x0, 4(x29) - - # Test - li x27, 0x14725836 - sh x27, 0(x29) - lw x30, 0(x29) - sh x30, 4(x29) - - RVTEST_IO_ASSERT_GPR_EQ(x29, x27, 0x14725836) - RVTEST_IO_ASSERT_GPR_EQ(x29, x30, 0x00005836) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part G - test waw hazard in memory\n"); - - # Address for test results - la x1, test_G_res - - # Clear memory - sw x0, 0(x1) - - # Test - li x2, 0x96385201 - li x3, 0x25814963 - sh x2, 0(x1) - sh x3, 0(x1) - - RVTEST_IO_ASSERT_GPR_EQ(x1, x2, 0x96385201) - RVTEST_IO_ASSERT_GPR_EQ(x1, x3, 0x25814963) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_D1_data: - .word test_D1_res -test_D2_data: - .word 0x9ABCDEF0 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 1, 4, -1 -test_A2_res: - .fill 1, 4, -1 -test_A3_res: - .fill 1, 4, -1 -test_A4_res: - .fill 1, 4, -1 -test_A5_res: - .fill 1, 4, -1 - .fill 1, 4, -1 -test_B_res: - .fill 2, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D1_res: - .fill 1, 4, -1 -test_D2_res: - .fill 1, 4, -1 -test_E1_res: - .fill 1, 4, -1 -test_E2_res: - .fill 1, 4, -1 -test_F_res: - .fill 2, 4, -1 -test_G_res: - .fill 1, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLL-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLL-01.S index a623b6f..ab88d62 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLL-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLL-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SLL-01 +# RISC-V Compliance Test SLL-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,422 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SLL. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SLL'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX (5bit) register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 1 - li x5, 0xF - li x6, 0x1F - li x7, 0 - li x8, 0x10 - # Test - sll x4, x3, x4 - sll x5, x3, x5 - sll x6, x3, x6 - sll x7, x3, x7 - sll x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(sll, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(sll, x1, x30, x15, 0x1, 0x1, 0x0, x5, 4, x6) # Testcase 1 + TEST_RR_OP(sll, x2, x29, x14, 0x0, 0x0, 0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(sll, x3, x28, x13, 0x7ff0, 0x7ff, 0x4, x5, 12, x6) # Testcase 3 + TEST_RR_OP(sll, x4, x27, x12, 0x0, 0x0, 0x8, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX (5bit) register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(sll, x5, x26, x11, 0x0, 0x800, 0x1f, x1, 0, x2) # Testcase 5 + TEST_RR_OP(sll, x6, x25, x10, 0x43210000, 0x7654321, 0x10, x1, 4, x2) # Testcase 6 + TEST_RR_OP(sll, x7, x24, x9, 0xfffffffe, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(sll, x8, x23, x8, 0x1, 0x1, 0x0, x1, 12, x2) # Testcase 8 + TEST_RR_OP(sll, x9, x22, x7, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 1 - li x10, 0xF - li x11, 0x1F - li x12, 0 - li x13, 0x10 - # Test - sll x9, x8, x9 - sll x10, x8, x10 - sll x11, x8, x11 - sll x12, x8, x12 - sll x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000002) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00008000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00010000) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(sll, x10, x21, x6, 0x2468, 0x1234, 0x1, x1, 0, x7) # Testcase 10 + TEST_RR_OP(sll, x11, x20, x5, 0x0, 0x80000000, 0x4, x1, 4, x7) # Testcase 11 + TEST_RR_OP(sll, x12, x19, x4, 0xffedcc00, -0x1234, 0x8, x1, 8, x7) # Testcase 12 + TEST_RR_OP(sll, x13, x18, x3, 0x80000000, -0x1, 0x1f, x1, 12, x7) # Testcase 13 + TEST_RR_OP(sll, x14, x17, x2, 0xf8010000, -0x7ff, 0x10, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX (5bit) register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 1 - li x15, 0xF - li x16, 0x1F - li x17, 0 - li x18, 0x10 + # address for test results + la x2, test_4_res - # Test - sll x14, x13, x14 - sll x15, x13, x15 - sll x16, x13, x16 - sll x17, x13, x17 - sll x18, x13, x18 + TEST_RR_OP(sll, x15, x16, x1, 0x0, 0x0, 0x1, x2, 0, x3) # Testcase 15 + TEST_RR_OP(sll, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(sll, x17, x14, x31, 0x1, 0x1, 0x0, x2, 8, x3) # Testcase 17 + TEST_RR_OP(sll, x18, x13, x30, 0x0, 0x0, 0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(sll, x19, x12, x29, 0x7ff0, 0x7ff, 0x4, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFF8000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0xFFFF0000) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX (5bit) register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x12, test_A4_data - la x13, test_A4_res + TEST_RR_OP(sll, x20, x11, x28, 0x0, 0x0, 0x8, x1, 0, x2) # Testcase 20 + TEST_RR_OP(sll, x21, x10, x27, 0x0, 0x800, 0x1f, x1, 4, x2) # Testcase 21 + TEST_RR_OP(sll, x22, x9, x26, 0x43210000, 0x7654321, 0x10, x1, 8, x2) # Testcase 22 + TEST_RR_OP(sll, x23, x8, x25, 0xfffffffe, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(sll, x24, x7, x24, 0x1, 0x1, 0x0, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x12) - # Register initialization - li x19, 1 - li x20, 0xF - li x21, 0x1F - li x22, 0 - li x23, 0x10 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test - sll x19, x18, x19 - sll x20, x18, x20 - sll x21, x18, x21 - sll x22, x18, x22 - sll x23, x18, x23 - # Store results - sw x18, 0(x13) - sw x19, 4(x13) - sw x20, 8(x13) - sw x21, 12(x13) - sw x22, 16(x13) - sw x23, 20(x13) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x13, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x19, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x13, x20, 0xFFFF8000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x21, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0xFFFF0000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX (5bit) register values\n"); - - # Addresses for test data and results - la x12, test_A5_data - la x13, test_A5_res - - # Load testdata - lw x23, 0(x12) - - # Register initialization - li x24, 1 - li x25, 0xF - li x26, 0x1F - li x27, 0 - li x28, 0x10 - - # Test - sll x24, x23, x24 - sll x25, x23, x25 - sll x26, x23, x26 - sll x27, x23, x27 - sll x28, x23, x28 - - # Store results - sw x23, 0(x13) - sw x24, 4(x13) - sw x25, 8(x13) - sw x26, 12(x13) - sw x27, 16(x13) - sw x28, 20(x13) - - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x24, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x26, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x27, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x28, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x25, test_B_data - la x26, test_B_res - - # Load testdata - lw x28, 0(x25) - - # Register initialization - li x27, 0x1 - - # Test - sll x29, x28, x27 - sll x30, x29, x27 - sll x31, x30, x27 - sll x1, x31, x27 - sll x2, x1, x27 - sll x3, x2, x27 - - # Store results - sw x28, 0(x26) - sw x29, 4(x26) - sw x30, 8(x26) - sw x31, 12(x26) - sw x1, 16(x26) - sw x2, 20(x26) - sw x3, 24(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0xABCDEF10) - RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0x579BDE20) - RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0xAF37BC40) - RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0x5E6F7880) - RVTEST_IO_ASSERT_GPR_EQ(x26, x1, 0xBCDEF100) - RVTEST_IO_ASSERT_GPR_EQ(x26, x2, 0x79BDE200) - RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0xF37BC400) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Register initialization - li x27, 1 - - # Test - sll x0, x5, x27 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Register initialization - li x27, 1 - - # Test - sll x0, x5, x27 - sll x5, x0, x27 - - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing shift by value greater than 31\n"); + TEST_RR_OP(sll, x25, x6, x23, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7) # Testcase 25 + TEST_RR_OP(sll, x26, x5, x22, 0x2468, 0x1234, 0x1, x1, 4, x7) # Testcase 26 + TEST_RR_OP(sll, x27, x4, x21, 0x0, 0x80000000, 0x4, x1, 8, x7) # Testcase 27 + TEST_RR_OP(sll, x28, x3, x20, 0xffedcc00, -0x1234, 0x8, x1, 12, x7) # Testcase 28 + TEST_RR_OP(sll, x29, x2, x19, 0x80000000, -0x1, 0x1f, x1, 16, x7) # Testcase 29 - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res - # Load testdata - lw x3, 0(x1) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Register initialization - li x4, 0xFFFFFE0 - li x5, 0xFFFFFE1 - li x6, 0xFFFFFEF - li x7, 0xFFFFFFF - # Test - sll x4, x3, x4 - sll x5, x3, x5 - sll x6, x3, x6 - sll x7, x3, x7 + # address for test results + la x2, test_7_res - # Store results - sw x4, 0(x2) - sw x5, 4(x2) - sw x6, 8(x2) - sw x7, 12(x2) + TEST_RR_OP(sll, x30, x1, x18, 0xf8010000, -0x7ff, 0x10, x2, 0, x3) # Testcase 30 + TEST_RR_OP(sll, x31, x0, x17, 0x0, 0x0, 0x1, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x0ECA8642) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xA1908000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x80000000) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDEF10 -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x87654321 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S index f87e8ed..75128a5 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLLI-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SLLI-01 +# RISC-V Compliance Test SLLI-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,341 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SLLI. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SLLI'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - slli x4, x3, 1 - slli x5, x3, 0xF - slli x6, x3, 0x1F - slli x7, x3, 0 - slli x8, x3, 0x10 - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + # address for test results + la x5, test_1_res - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) + TEST_IMM_OP(slli, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_IMM_OP(slli, x1, x30, 0x1, 0x1, 0x0, x5, 4, x6) # Testcase 1 + TEST_IMM_OP(slli, x2, x29, 0x0, 0x0, 0x1, x5, 8, x6) # Testcase 2 + TEST_IMM_OP(slli, x3, x28, 0x7ff0, 0x7ff, 0x4, x5, 12, x6) # Testcase 3 + TEST_IMM_OP(slli, x4, x27, 0x0, 0x0, 0x8, x5, 16, x6) # Testcase 4 - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX immediate values\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - # Load testdata - lw x8, 0(x1) + # address for test results + la x1, test_2_res - # Test - slli x9, x8, 1 - slli x10, x8, 0xF - slli x11, x8, 0x1F - slli x12, x8, 0 - slli x13, x8, 0x10 + TEST_IMM_OP(slli, x5, x26, 0x0, 0x800, 0x1f, x1, 0, x2) # Testcase 5 + TEST_IMM_OP(slli, x6, x25, 0x43210000, 0x7654321, 0x10, x1, 4, x2) # Testcase 6 + TEST_IMM_OP(slli, x7, x24, 0xfffffffe, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_IMM_OP(slli, x8, x23, 0x1, 0x1, 0x0, x1, 12, x2) # Testcase 8 + TEST_IMM_OP(slli, x9, x22, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2) # Testcase 9 - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000002) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00008000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00010000) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX immediate values\n"); + # address for test results + la x1, test_3_res - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + TEST_IMM_OP(slli, x10, x21, 0x2468, 0x1234, 0x1, x1, 0, x7) # Testcase 10 + TEST_IMM_OP(slli, x11, x20, 0x0, 0x80000000, 0x4, x1, 4, x7) # Testcase 11 + TEST_IMM_OP(slli, x12, x19, 0xffedcc00, -0x1234, 0x8, x1, 8, x7) # Testcase 12 + TEST_IMM_OP(slli, x13, x18, 0x80000000, -0x1, 0x1f, x1, 12, x7) # Testcase 13 + TEST_IMM_OP(slli, x14, x17, 0xf8010000, -0x7ff, 0x10, x1, 16, x7) # Testcase 14 - # Load testdata - lw x13, 0(x1) - # Test - slli x14, x13, 1 - slli x15, x13, 0xF - slli x16, x13, 0x1F - slli x17, x13, 0 - slli x18, x13, 0x10 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFF8000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0xFFFF0000) + # address for test results + la x2, test_4_res - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + TEST_IMM_OP(slli, x15, x16, 0x0, 0x0, 0x1, x2, 0, x3) # Testcase 15 + TEST_IMM_OP(slli, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_IMM_OP(slli, x17, x14, 0x1, 0x1, 0x0, x2, 8, x3) # Testcase 17 + TEST_IMM_OP(slli, x18, x13, 0x0, 0x0, 0x1, x2, 12, x3) # Testcase 18 + TEST_IMM_OP(slli, x19, x12, 0x7ff0, 0x7ff, 0x4, x2, 16, x3) # Testcase 19 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x12, test_A4_data - la x13, test_A4_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - # Load testdata - lw x18, 0(x12) - # Test - slli x19, x18, 1 - slli x20, x18, 0xF - slli x21, x18, 0x1F - slli x22, x18, 0 - slli x23, x18, 0x10 + # address for test results + la x1, test_5_res - # Store results - sw x18, 0(x13) - sw x19, 4(x13) - sw x20, 8(x13) - sw x21, 12(x13) - sw x22, 16(x13) - sw x23, 20(x13) + TEST_IMM_OP(slli, x20, x11, 0x0, 0x0, 0x8, x1, 0, x2) # Testcase 20 + TEST_IMM_OP(slli, x21, x10, 0x0, 0x800, 0x1f, x1, 4, x2) # Testcase 21 + TEST_IMM_OP(slli, x22, x9, 0x43210000, 0x7654321, 0x10, x1, 8, x2) # Testcase 22 + TEST_IMM_OP(slli, x23, x8, 0xfffffffe, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_IMM_OP(slli, x24, x7, 0x1, 0x1, 0x0, x1, 16, x2) # Testcase 24 - RVTEST_IO_ASSERT_GPR_EQ(x13, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x19, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x13, x20, 0xFFFF8000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x21, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0xFFFF0000) - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x12, test_A5_data - la x13, test_A5_res + # address for test results + la x1, test_6_res - # Load testdata - lw x23, 0(x12) + TEST_IMM_OP(slli, x25, x6, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7) # Testcase 25 + TEST_IMM_OP(slli, x26, x5, 0x2468, 0x1234, 0x1, x1, 4, x7) # Testcase 26 + TEST_IMM_OP(slli, x27, x4, 0x0, 0x80000000, 0x4, x1, 8, x7) # Testcase 27 + TEST_IMM_OP(slli, x28, x3, 0xffedcc00, -0x1234, 0x8, x1, 12, x7) # Testcase 28 + TEST_IMM_OP(slli, x29, x2, 0x80000000, -0x1, 0x1f, x1, 16, x7) # Testcase 29 - # Test - slli x24, x23, 1 - slli x25, x23, 0xF - slli x26, x23, 0x1F - slli x27, x23, 0 - slli x28, x23, 0x10 - # Store results - sw x23, 0(x13) - sw x24, 4(x13) - sw x25, 8(x13) - sw x26, 12(x13) - sw x27, 16(x13) - sw x28, 20(x13) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x24, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x26, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x27, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x28, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); + # address for test results + la x2, test_7_res - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); + TEST_IMM_OP(slli, x30, x1, 0xf8010000, -0x7ff, 0x10, x2, 0, x3) # Testcase 30 + TEST_IMM_OP(slli, x31, x0, 0x0, 0x0, 0x1, x2, 4, x3) # Testcase 31 - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - # Load testdata - lw x28, 0(x26) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - # Test - slli x29, x28, 1 - slli x30, x29, 1 - slli x31, x30, 1 - slli x1, x31, 1 - slli x2, x1, 1 - slli x3, x2, 1 + # --------------------------------------------------------------------------------------------- - # Store results - sw x28, 0(x27) - sw x29, 4(x27) - sw x30, 8(x27) - sw x31, 12(x27) - sw x1, 16(x27) - sw x2, 20(x27) - sw x3, 24(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x28, 0xABCDEF10) - RVTEST_IO_ASSERT_GPR_EQ(x27, x29, 0x579BDE20) - RVTEST_IO_ASSERT_GPR_EQ(x27, x30, 0xAF37BC40) - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x5E6F7880) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0xBCDEF100) - RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0x79BDE200) - RVTEST_IO_ASSERT_GPR_EQ(x27, x3, 0xF37BC400) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Test - slli x0, x5, 1 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Test - slli x0, x5, 1 - slli x5, x0, 1 - - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDEF10 -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLT-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLT-01.S index ae84063..e76faff 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLT-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLT-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SLT-01 +# RISC-V Compliance Test SLT-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,401 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.SE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SLT. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SLT'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 1 - li x5, 0x7FFFFFFF - li x6, 0xFFFFFFFF - li x7, 0 - li x8, 0x80000000 - # Test - slt x4, x3, x4 - slt x5, x3, x5 - slt x6, x3, x6 - slt x7, x3, x7 - slt x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(slt, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(slt, x1, x30, x15, 0x0, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_RR_OP(slt, x2, x29, x14, 0x0, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(slt, x3, x28, x13, 0x0, 0x7ff, -0x1234, x5, 12, x6) # Testcase 3 + TEST_RR_OP(slt, x4, x27, x12, 0x0, 0x0, 0x80000000, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(slt, x5, x26, x11, 0x1, 0x800, 0x1234, x1, 0, x2) # Testcase 5 + TEST_RR_OP(slt, x6, x25, x10, 0x0, 0x7654321, 0xffffffff, x1, 4, x2) # Testcase 6 + TEST_RR_OP(slt, x7, x24, x9, 0x0, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(slt, x8, x23, x8, 0x1, 0x1, 0x7fffffff, x1, 12, x2) # Testcase 8 + TEST_RR_OP(slt, x9, x22, x7, 0x1, 0xffffffff, 0x7654321, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 1 - li x10, 0x7FFFFFFF - li x11, 0xFFFFFFFF - li x12, 0 - li x13, 0x80000000 - # Test - slt x9, x8, x9 - slt x10, x8, x10 - slt x11, x8, x11 - slt x12, x8, x12 - slt x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(slt, x10, x21, x6, 0x0, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_RR_OP(slt, x11, x20, x5, 0x1, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_RR_OP(slt, x12, x19, x4, 0x1, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_RR_OP(slt, x13, x18, x3, 0x0, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_RR_OP(slt, x14, x17, x2, 0x1, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 1 - li x15, 0x7FFFFFFF - li x16, 0xFFFFFFFF - li x17, 0 - li x18, 0x80000000 + # address for test results + la x2, test_4_res - # Test - slt x14, x13, x14 - slt x15, x13, x15 - slt x16, x13, x16 - slt x17, x13, x17 - slt x18, x13, x18 + TEST_RR_OP(slt, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_RR_OP(slt, x16, x15, x0, 0x1, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(slt, x17, x14, x31, 0x0, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_RR_OP(slt, x18, x13, x30, 0x0, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(slt, x19, x12, x29, 0x0, 0x7ff, -0x1234, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x00000000) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + TEST_RR_OP(slt, x20, x11, x28, 0x0, 0x0, 0x80000000, x1, 0, x2) # Testcase 20 + TEST_RR_OP(slt, x21, x10, x27, 0x1, 0x800, 0x1234, x1, 4, x2) # Testcase 21 + TEST_RR_OP(slt, x22, x9, x26, 0x0, 0x7654321, 0xffffffff, x1, 8, x2) # Testcase 22 + TEST_RR_OP(slt, x23, x8, x25, 0x0, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(slt, x24, x7, x24, 0x1, 0x1, 0x7fffffff, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x1) - # Register initialization - li x19, 1 - li x20, 0x7FFFFFFF - li x21, 0xFFFFFFFF - li x22, 0 - li x23, 0x80000000 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test - slt x19, x18, x19 - slt x20, x18, x20 - slt x21, x18, x21 - slt x22, x18, x22 - slt x23, x18, x23 - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x00000000) + TEST_RR_OP(slt, x25, x6, x23, 0x1, 0xffffffff, 0x7654321, x1, 0, x7) # Testcase 25 + TEST_RR_OP(slt, x26, x5, x22, 0x0, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_RR_OP(slt, x27, x4, x21, 0x1, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_RR_OP(slt, x28, x3, x20, 0x1, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_RR_OP(slt, x29, x2, x19, 0x0, -0x1, -0x1, x1, 16, x7) # Testcase 29 - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - # Load testdata - lw x23, 0(x1) + # address for test results + la x2, test_7_res - # Register initialization - li x24, 1 - li x25, 0x7FFFFFFF - li x26, 0xFFFFFFFF - li x27, 0 - li x28, 0x80000000 + TEST_RR_OP(slt, x30, x1, x18, 0x1, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_RR_OP(slt, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - # Test - slt x24, x23, x24 - slt x25, x23, x25 - slt x26, x23, x26 - slt x27, x23, x27 - slt x28, x23, x28 - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x00000000) + # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing writing to x0\n"); - - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - - # Load testdata - lw x1, 0(x26) - - # Register initialization - li x2, 1 - - # Test - slt x0, x1, x2 - - # Store results - sw x0, 0(x27) - sw x1, 4(x27) - sw x2, 8(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing compare x0\n"); - - # Addresses for test data and results - la x31, test_C_res - - # Register initialization - li x1, 1 - li x2, 0x7FF - li x3, 0xFFFFFFFF - li x4, 0 - li x5, 0xFFFFF800 - - # Test - slt x6, x0, x1 - slt x7, x0, x2 - slt x8, x0, x3 - slt x9, x0, x4 - slt x10, x0, x5 - slt x11, x1, x0 - slt x12, x2, x0 - slt x13, x3, x0 - slt x14, x4, x0 - slt x15, x5, x0 - - # Store results - sw x6, 0(x31) - sw x7, 4(x31) - sw x8, 8(x31) - sw x9, 12(x31) - sw x10, 16(x31) - sw x11, 20(x31) - sw x12, 24(x31) - sw x13, 28(x31) - sw x14, 32(x31) - sw x15, 36(x31) - - RVTEST_IO_ASSERT_GPR_EQ(x31, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x7, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x8, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x10, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x12, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x13, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x14, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x15, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x31, test_D_res - - # Register initialization - li x3, 0x1 - - # Test - slt x1, x0, x3 - slt x2, x1, x3 - slt x28, x2, x3 - slt x29, x28, x3 - slt x30, x29, x3 - - # Store results - sw x1, 0(x31) - sw x2, 4(x31) - sw x28, 8(x31) - sw x29, 12(x31) - sw x30, 16(x31) - - RVTEST_IO_ASSERT_GPR_EQ(x31, x1, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x2, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x28, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x29, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x30, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xFFFFFFFF + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 3, 4, -1 -test_C_res: - .fill 10, 4, -1 -test_D_res: - .fill 5, 4, -1 - +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S index 32efea5..67740af 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTI-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SLTI-01 +# RISC-V Compliance Test SLTI-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,340 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SLTI. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SLTI'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) - - # Test - slti x4, x3, 1 - slti x5, x3, 0x7FF - slti x6, x3, 0xFFFFFFFF - slti x7, x3, 0 - slti x8, x3, 0xFFFFF800 - - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - - # Load testdata - lw x8, 0(x1) - - # Test - slti x9, x8, 1 - slti x10, x8, 0x7FF - slti x11, x8, 0xFFFFFFFF - slti x12, x8, 0 - slti x13, x8, 0xFFFFF800 - - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res - - # Load testdata - lw x13, 0(x1) - - # Test - slti x14, x13, 1 - slti x15, x13, 0x7FF - slti x16, x13, 0xFFFFFFFF - slti x17, x13, 0 - slti x18, x13, 0xFFFFF800 - - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res - - # Load testdata - lw x18, 0(x1) - - # Test - slti x19, x18, 1 - slti x20, x18, 0x7FF - slti x21, x18, 0xFFFFFFFF - slti x22, x18, 0 - slti x23, x18, 0xFFFFF800 - - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Test - slti x24, x23, 1 - slti x25, x23, 0x7FF - slti x26, x23, 0xFFFFFFFF - slti x27, x23, 0 - slti x28, x23, 0xFFFFF800 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing writing to x0\n"); - - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - - # Load testdata - lw x1, 0(x26) - - # Test - slti x0, x1, 1 - - # Store results - sw x1, 0(x27) - sw x0, 4(x27) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - RVTEST_IO_ASSERT_GPR_EQ(x27, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0xFFFFFFFF) + # address for test results + la x5, test_1_res - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); + TEST_IMM_OP(slti, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_IMM_OP(slti, x1, x30, 0x0, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_IMM_OP(slti, x2, x29, 0x0, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_IMM_OP(slti, x3, x28, 0x0, 0x7ff, -0x800, x5, 12, x6) # Testcase 3 + TEST_IMM_OP(slti, x4, x27, 0x0, 0x0, 0x800, x5, 16, x6) # Testcase 4 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing compare x0\n"); - # Addresses for test data and results - la x31, test_C_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Test - slti x1, x0, 1 - slti x2, x0, 0x7FF - slti x3, x0, 0xFFFFFFFF - slti x4, x0, 0 - slti x5, x0, 0xFFFFF800 - # Store results - sw x0, 0(x31) - sw x1, 4(x31) - sw x2, 8(x31) - sw x3, 12(x31) - sw x4, 16(x31) - sw x5, 20(x31) + # address for test results + la x1, test_2_res - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x1, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x2, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x5, 0x00000000) + TEST_IMM_OP(slti, x5, x26, 0x0, 0x800, 0x800, x1, 0, x2) # Testcase 5 + TEST_IMM_OP(slti, x6, x25, 0x0, 0x7654321, 0x800, x1, 4, x2) # Testcase 6 + TEST_IMM_OP(slti, x7, x24, 0x0, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_IMM_OP(slti, x8, x23, 0x0, 0x1, 0x800, x1, 12, x2) # Testcase 8 + TEST_IMM_OP(slti, x9, x22, 0x0, 0xffffffff, 0x800, x1, 16, x2) # Testcase 9 - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding between instructions\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Addresses for test data and results - la x31, test_D_res - # Test - slti x1, x0, 1 - slti x2, x1, 1 - slti x28, x2, 1 - slti x29, x28, 1 - slti x30, x29, 1 + # address for test results + la x1, test_3_res - # Store results - sw x0, 0(x31) - sw x1, 4(x31) - sw x2, 8(x31) - sw x28, 12(x31) - sw x29, 16(x31) - sw x30, 20(x31) + TEST_IMM_OP(slti, x10, x21, 0x0, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_IMM_OP(slti, x11, x20, 0x1, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_IMM_OP(slti, x12, x19, 0x1, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_IMM_OP(slti, x13, x18, 0x0, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_IMM_OP(slti, x14, x17, 0x1, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x1, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x2, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x28, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x29, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x30, 0x00000001) - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + # address for test results + la x2, test_4_res + + TEST_IMM_OP(slti, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_IMM_OP(slti, x16, x15, 0x1, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_IMM_OP(slti, x17, x14, 0x0, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_IMM_OP(slti, x18, x13, 0x0, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_IMM_OP(slti, x19, x12, 0x0, 0x7ff, -0x800, x2, 16, x3) # Testcase 19 + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x1, test_5_res + + TEST_IMM_OP(slti, x20, x11, 0x0, 0x0, 0x800, x1, 0, x2) # Testcase 20 + TEST_IMM_OP(slti, x21, x10, 0x0, 0x800, 0x800, x1, 4, x2) # Testcase 21 + TEST_IMM_OP(slti, x22, x9, 0x0, 0x7654321, 0x800, x1, 8, x2) # Testcase 22 + TEST_IMM_OP(slti, x23, x8, 0x0, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_IMM_OP(slti, x24, x7, 0x0, 0x1, 0x800, x1, 16, x2) # Testcase 24 + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x1, test_6_res + + TEST_IMM_OP(slti, x25, x6, 0x0, 0xffffffff, 0x800, x1, 0, x7) # Testcase 25 + TEST_IMM_OP(slti, x26, x5, 0x0, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_IMM_OP(slti, x27, x4, 0x1, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_IMM_OP(slti, x28, x3, 0x1, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_IMM_OP(slti, x29, x2, 0x0, -0x1, -0x1, x1, 16, x7) # Testcase 29 + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x2, test_7_res + + TEST_IMM_OP(slti, x30, x1, 0x1, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_IMM_OP(slti, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xFFFFFFFF + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 2, 4, -1 -test_C_res: - .fill 6, 4, -1 -test_D_res: - .fill 6, 4, -1 - +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S index 6cb0eed..e55c176 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTIU-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SLTIU-01 +# RISC-V Compliance Test SLTIU-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,340 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SLTIU. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SLTIU'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) - - # Test - sltiu x4, x3, 1 - sltiu x5, x3, 0x7FF - sltiu x6, x3, 0xFFFFFFFF - sltiu x7, x3, 0 - sltiu x8, x3, 0xFFFFF800 - - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) - - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - - # Load testdata - lw x8, 0(x1) - - # Test - sltiu x9, x8, 1 - sltiu x10, x8, 0x7FF - sltiu x11, x8, 0xFFFFFFFF - sltiu x12, x8, 0 - sltiu x13, x8, 0xFFFFF800 - - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res - - # Load testdata - lw x13, 0(x1) - - # Test - sltiu x14, x13, 1 - sltiu x15, x13, 0x7FF - sltiu x16, x13, 0xFFFFFFFF - sltiu x17, x13, 0 - sltiu x18, x13, 0xFFFFF800 - - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res - - # Load testdata - lw x18, 0(x1) - - # Test - sltiu x19, x18, 1 - sltiu x20, x18, 0x7FF - sltiu x21, x18, 0xFFFFFFFF - sltiu x22, x18, 0 - sltiu x23, x18, 0xFFFFF800 - - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Test - sltiu x24, x23, 1 - sltiu x25, x23, 0x7FF - sltiu x26, x23, 0xFFFFFFFF - sltiu x27, x23, 0 - sltiu x28, x23, 0xFFFFF800 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing writing to x0\n"); - - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - - # Load testdata - lw x1, 0(x26) - - # Test - sltiu x0, x1, 0xFFFFFFFF - - # Store results - sw x1, 0(x27) - sw x0, 4(x27) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x27, x0, 0x00000000) + # address for test results + la x5, test_1_res - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); + TEST_IMM_OP(sltiu, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_IMM_OP(sltiu, x1, x30, 0x1, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_IMM_OP(sltiu, x2, x29, 0x1, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_IMM_OP(sltiu, x3, x28, 0x1, 0x7ff, -0x800, x5, 12, x6) # Testcase 3 + TEST_IMM_OP(sltiu, x4, x27, 0x1, 0x0, 0x800, x5, 16, x6) # Testcase 4 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing compare x0\n"); - # Addresses for test data and results - la x31, test_C_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Test - sltiu x1, x0, 1 - sltiu x2, x0, 0x7FF - sltiu x3, x0, 0xFFFFFFFF - sltiu x4, x0, 0 - sltiu x5, x0, 0xFFFFF800 - # Store results - sw x0, 0(x31) - sw x1, 4(x31) - sw x2, 8(x31) - sw x3, 12(x31) - sw x4, 16(x31) - sw x5, 20(x31) + # address for test results + la x1, test_2_res - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x1, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x2, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x3, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x5, 0x00000001) + TEST_IMM_OP(sltiu, x5, x26, 0x1, 0x800, 0x800, x1, 0, x2) # Testcase 5 + TEST_IMM_OP(sltiu, x6, x25, 0x1, 0x7654321, 0x800, x1, 4, x2) # Testcase 6 + TEST_IMM_OP(sltiu, x7, x24, 0x0, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_IMM_OP(sltiu, x8, x23, 0x1, 0x1, 0x800, x1, 12, x2) # Testcase 8 + TEST_IMM_OP(sltiu, x9, x22, 0x0, 0xffffffff, 0x800, x1, 16, x2) # Testcase 9 - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding between instructions\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Addresses for test data and results - la x31, test_D_res - # Test - sltiu x1, x0, 1 - sltiu x2, x1, 1 - sltiu x28, x2, 1 - sltiu x29, x28, 1 - sltiu x30, x29, 1 + # address for test results + la x1, test_3_res - # Store results - sw x0, 0(x31) - sw x1, 4(x31) - sw x2, 8(x31) - sw x28, 12(x31) - sw x29, 16(x31) - sw x30, 20(x31) + TEST_IMM_OP(sltiu, x10, x21, 0x1, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_IMM_OP(sltiu, x11, x20, 0x0, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_IMM_OP(sltiu, x12, x19, 0x0, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_IMM_OP(sltiu, x13, x18, 0x0, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_IMM_OP(sltiu, x14, x17, 0x0, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x1, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x2, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x28, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x29, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x30, 0x00000001) - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + # address for test results + la x2, test_4_res + + TEST_IMM_OP(sltiu, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_IMM_OP(sltiu, x16, x15, 0x0, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_IMM_OP(sltiu, x17, x14, 0x1, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_IMM_OP(sltiu, x18, x13, 0x1, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_IMM_OP(sltiu, x19, x12, 0x1, 0x7ff, -0x800, x2, 16, x3) # Testcase 19 + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") + + + # address for test results + la x1, test_5_res + + TEST_IMM_OP(sltiu, x20, x11, 0x1, 0x0, 0x800, x1, 0, x2) # Testcase 20 + TEST_IMM_OP(sltiu, x21, x10, 0x1, 0x800, 0x800, x1, 4, x2) # Testcase 21 + TEST_IMM_OP(sltiu, x22, x9, 0x1, 0x7654321, 0x800, x1, 8, x2) # Testcase 22 + TEST_IMM_OP(sltiu, x23, x8, 0x0, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_IMM_OP(sltiu, x24, x7, 0x1, 0x1, 0x800, x1, 16, x2) # Testcase 24 + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") + + + # address for test results + la x1, test_6_res + + TEST_IMM_OP(sltiu, x25, x6, 0x0, 0xffffffff, 0x800, x1, 0, x7) # Testcase 25 + TEST_IMM_OP(sltiu, x26, x5, 0x1, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_IMM_OP(sltiu, x27, x4, 0x0, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_IMM_OP(sltiu, x28, x3, 0x0, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_IMM_OP(sltiu, x29, x2, 0x0, -0x1, -0x1, x1, 16, x7) # Testcase 29 + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # address for test results + la x2, test_7_res + + TEST_IMM_OP(sltiu, x30, x1, 0x0, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_IMM_OP(sltiu, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 1 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 2, 4, -1 -test_C_res: - .fill 6, 4, -1 -test_D_res: - .fill 6, 4, -1 - +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S index 1cdc5f5..b57a894 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SLTU-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SLTU-01 +# RISC-V Compliance Test SLTU-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,399 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SLTU. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SLTU'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 1 - li x5, 0x7FFFFFFF - li x6, 0xFFFFFFFF - li x7, 0 - li x8, 0x80000000 - # Test - sltu x4, x3, x4 - sltu x5, x3, x5 - sltu x6, x3, x6 - sltu x7, x3, x7 - sltu x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(sltu, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(sltu, x1, x30, x15, 0x1, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_RR_OP(sltu, x2, x29, x14, 0x1, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(sltu, x3, x28, x13, 0x1, 0x7ff, -0x1234, x5, 12, x6) # Testcase 3 + TEST_RR_OP(sltu, x4, x27, x12, 0x1, 0x0, 0x80000000, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(sltu, x5, x26, x11, 0x1, 0x800, 0x1234, x1, 0, x2) # Testcase 5 + TEST_RR_OP(sltu, x6, x25, x10, 0x1, 0x7654321, 0xffffffff, x1, 4, x2) # Testcase 6 + TEST_RR_OP(sltu, x7, x24, x9, 0x0, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(sltu, x8, x23, x8, 0x1, 0x1, 0x7fffffff, x1, 12, x2) # Testcase 8 + TEST_RR_OP(sltu, x9, x22, x7, 0x0, 0xffffffff, 0x7654321, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 1 - li x10, 0x7FFFFFFF - li x11, 0xFFFFFFFF - li x12, 0 - li x13, 0x80000000 - # Test - sltu x9, x8, x9 - sltu x10, x8, x10 - sltu x11, x8, x11 - sltu x12, x8, x12 - sltu x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000001) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(sltu, x10, x21, x6, 0x0, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_RR_OP(sltu, x11, x20, x5, 0x0, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_RR_OP(sltu, x12, x19, x4, 0x0, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_RR_OP(sltu, x13, x18, x3, 0x0, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_RR_OP(sltu, x14, x17, x2, 0x0, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 1 - li x15, 0x7FFFFFFF - li x16, 0xFFFFFFFF - li x17, 0 - li x18, 0x80000000 + # address for test results + la x2, test_4_res - # Test - sltu x14, x13, x14 - sltu x15, x13, x15 - sltu x16, x13, x16 - sltu x17, x13, x17 - sltu x18, x13, x18 + TEST_RR_OP(sltu, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_RR_OP(sltu, x16, x15, x0, 0x0, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(sltu, x17, x14, x31, 0x1, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_RR_OP(sltu, x18, x13, x30, 0x1, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(sltu, x19, x12, x29, 0x1, 0x7ff, -0x1234, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x00000000) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + TEST_RR_OP(sltu, x20, x11, x28, 0x1, 0x0, 0x80000000, x1, 0, x2) # Testcase 20 + TEST_RR_OP(sltu, x21, x10, x27, 0x1, 0x800, 0x1234, x1, 4, x2) # Testcase 21 + TEST_RR_OP(sltu, x22, x9, x26, 0x1, 0x7654321, 0xffffffff, x1, 8, x2) # Testcase 22 + TEST_RR_OP(sltu, x23, x8, x25, 0x0, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(sltu, x24, x7, x24, 0x1, 0x1, 0x7fffffff, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x1) - # Register initialization - li x19, 1 - li x20, 0x7FFFFFFF - li x21, 0xFFFFFFFF - li x22, 0 - li x23, 0x80000000 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test - sltu x19, x18, x19 - sltu x20, x18, x20 - sltu x21, x18, x21 - sltu x22, x18, x22 - sltu x23, x18, x23 - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x00000001) + TEST_RR_OP(sltu, x25, x6, x23, 0x0, 0xffffffff, 0x7654321, x1, 0, x7) # Testcase 25 + TEST_RR_OP(sltu, x26, x5, x22, 0x0, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_RR_OP(sltu, x27, x4, x21, 0x0, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_RR_OP(sltu, x28, x3, x20, 0x0, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_RR_OP(sltu, x29, x2, x19, 0x0, -0x1, -0x1, x1, 16, x7) # Testcase 29 - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - # Load testdata - lw x23, 0(x1) + # address for test results + la x2, test_7_res - # Register initialization - li x24, 1 - li x25, 0x7FFFFFFF - li x26, 0xFFFFFFFF - li x27, 0 - li x28, 0x80000000 + TEST_RR_OP(sltu, x30, x1, x18, 0x0, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_RR_OP(sltu, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - # Test - sltu x24, x23, x24 - sltu x25, x23, x25 - sltu x26, x23, x26 - sltu x27, x23, x27 - sltu x28, x23, x28 - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x00000000) + # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing writing to x0\n"); - - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - - # Load testdata - lw x1, 0(x26) - - # Register initialization - li x2, 0xFFFFFFFF - - # Test - sltu x0, x1, x2 - - # Store results - sw x0, 0(x27) - sw x1, 4(x27) - sw x2, 8(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0xFFFFFFFF) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing compare x0\n"); - - # Addresses for test data and results - la x31, test_C_res - - # Register initialization - li x1, 1 - li x2, 0x7FF - li x3, 0xFFFFFFFF - li x4, 0 - li x5, 0xFFFFF800 - - # Test - sltu x6, x0, x1 - sltu x7, x0, x2 - sltu x8, x0, x3 - sltu x9, x0, x4 - sltu x10, x0, x5 - sltu x11, x1, x0 - sltu x12, x2, x0 - sltu x13, x3, x0 - sltu x14, x4, x0 - sltu x15, x5, x0 - - # Store results - sw x6, 0(x31) - sw x7, 4(x31) - sw x8, 8(x31) - sw x9, 12(x31) - sw x10, 16(x31) - sw x11, 20(x31) - sw x12, 24(x31) - sw x13, 28(x31) - sw x14, 32(x31) - sw x15, 36(x31) - - RVTEST_IO_ASSERT_GPR_EQ(x31, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x7, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x10, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x12, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x13, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x14, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x15, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x31, test_D_res - - # Register initialization - li x3, 0x1 - - # Test - sltu x1, x0, x3 - sltu x2, x1, x3 - sltu x28, x2, x3 - sltu x29, x28, x3 - sltu x30, x29, x3 - - # Store results - sw x1, 0(x31) - sw x2, 4(x31) - sw x28, 8(x31) - sw x29, 12(x31) - sw x30, 16(x31) - - RVTEST_IO_ASSERT_GPR_EQ(x31, x1, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x2, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x28, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x31, x29, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x31, x30, 0x00000001) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 1 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 3, 4, -1 -test_C_res: - .fill 10, 4, -1 -test_D_res: - .fill 5, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRA-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRA-01.S index 415872a..30f6ae0 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRA-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRA-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SRA-01 +# RISC-V Compliance Test SRA-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,422 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SRA. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SRA'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX (5bit) register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 1 - li x5, 0xF - li x6, 0x1F - li x7, 0 - li x8, 0x10 - # Test - sra x4, x3, x4 - sra x5, x3, x5 - sra x6, x3, x6 - sra x7, x3, x7 - sra x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(sra, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(sra, x1, x30, x15, 0x1, 0x1, 0x0, x5, 4, x6) # Testcase 1 + TEST_RR_OP(sra, x2, x29, x14, 0x0, 0x0, 0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(sra, x3, x28, x13, 0x7f, 0x7ff, 0x4, x5, 12, x6) # Testcase 3 + TEST_RR_OP(sra, x4, x27, x12, 0x0, 0x0, 0x8, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX (5bit) register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(sra, x5, x26, x11, 0x0, 0x800, 0x1f, x1, 0, x2) # Testcase 5 + TEST_RR_OP(sra, x6, x25, x10, 0x765, 0x7654321, 0x10, x1, 4, x2) # Testcase 6 + TEST_RR_OP(sra, x7, x24, x9, 0x3fffffff, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(sra, x8, x23, x8, 0x1, 0x1, 0x0, x1, 12, x2) # Testcase 8 + TEST_RR_OP(sra, x9, x22, x7, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 1 - li x10, 0xF - li x11, 0x1F - li x12, 0 - li x13, 0x10 - # Test - sra x9, x8, x9 - sra x10, x8, x10 - sra x11, x8, x11 - sra x12, x8, x12 - sra x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(sra, x10, x21, x6, 0x91a, 0x1234, 0x1, x1, 0, x7) # Testcase 10 + TEST_RR_OP(sra, x11, x20, x5, 0xf8000000, 0x80000000, 0x4, x1, 4, x7) # Testcase 11 + TEST_RR_OP(sra, x12, x19, x4, 0xffffffed, -0x1234, 0x8, x1, 8, x7) # Testcase 12 + TEST_RR_OP(sra, x13, x18, x3, 0xffffffff, -0x1, 0x1f, x1, 12, x7) # Testcase 13 + TEST_RR_OP(sra, x14, x17, x2, 0xffffffff, -0x7ff, 0x10, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX (5bit) register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 1 - li x15, 0xF - li x16, 0x1F - li x17, 0 - li x18, 0x10 + # address for test results + la x2, test_4_res - # Test - sra x14, x13, x14 - sra x15, x13, x15 - sra x16, x13, x16 - sra x17, x13, x17 - sra x18, x13, x18 + TEST_RR_OP(sra, x15, x16, x1, 0x0, 0x0, 0x1, x2, 0, x3) # Testcase 15 + TEST_RR_OP(sra, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(sra, x17, x14, x31, 0x1, 0x1, 0x0, x2, 8, x3) # Testcase 17 + TEST_RR_OP(sra, x18, x13, x30, 0x0, 0x0, 0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(sra, x19, x12, x29, 0x7f, 0x7ff, 0x4, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0xFFFFFFFF) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX (5bit) register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x12, test_A4_data - la x13, test_A4_res + TEST_RR_OP(sra, x20, x11, x28, 0x0, 0x0, 0x8, x1, 0, x2) # Testcase 20 + TEST_RR_OP(sra, x21, x10, x27, 0x0, 0x800, 0x1f, x1, 4, x2) # Testcase 21 + TEST_RR_OP(sra, x22, x9, x26, 0x765, 0x7654321, 0x10, x1, 8, x2) # Testcase 22 + TEST_RR_OP(sra, x23, x8, x25, 0x3fffffff, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(sra, x24, x7, x24, 0x1, 0x1, 0x0, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x12) - # Register initialization - li x19, 1 - li x20, 0xF - li x21, 0x1F - li x22, 0 - li x23, 0x10 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test - sra x19, x18, x19 - sra x20, x18, x20 - sra x21, x18, x21 - sra x22, x18, x22 - sra x23, x18, x23 - # Store results - sw x18, 0(x13) - sw x19, 4(x13) - sw x20, 8(x13) - sw x21, 12(x13) - sw x22, 16(x13) - sw x23, 20(x13) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x13, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x19, 0x3FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x20, 0x0000FFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x21, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x00007FFF) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX (5bit) register values\n"); - - # Addresses for test data and results - la x12, test_A5_data - la x13, test_A5_res - - # Load testdata - lw x23, 0(x12) - - # Register initialization - li x24, 1 - li x25, 0xF - li x26, 0x1F - li x27, 0 - li x28, 0x10 - - # Test - sra x24, x23, x24 - sra x25, x23, x25 - sra x26, x23, x26 - sra x27, x23, x27 - sra x28, x23, x28 - - # Store results - sw x23, 0(x13) - sw x24, 4(x13) - sw x25, 8(x13) - sw x26, 12(x13) - sw x27, 16(x13) - sw x28, 20(x13) - - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x24, 0xC0000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x25, 0xFFFF0000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x26, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x27, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x28, 0xFFFF8000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x25, test_B_data - la x26, test_B_res - - # Load testdata - lw x28, 0(x25) - - # Register initialization - li x27, 0x1 - - # Test - sra x29, x28, x27 - sra x30, x29, x27 - sra x31, x30, x27 - sra x1, x31, x27 - sra x2, x1, x27 - sra x3, x2, x27 - - # Store results - sw x28, 0(x26) - sw x29, 4(x26) - sw x30, 8(x26) - sw x31, 12(x26) - sw x1, 16(x26) - sw x2, 20(x26) - sw x3, 24(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0xABCDEF10) - RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0xD5E6F788) - RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0xEAF37BC4) - RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0xF579BDE2) - RVTEST_IO_ASSERT_GPR_EQ(x26, x1, 0xFABCDEF1) - RVTEST_IO_ASSERT_GPR_EQ(x26, x2, 0xFD5E6F78) - RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0xFEAF37BC) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Register initialization - li x27, 1 - - # Test - sra x0, x5, x27 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Register initialization - li x27, 1 - - # Test - sra x0, x5, x27 - sra x5, x0, x27 - - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing shift by value greater than 31\n"); + TEST_RR_OP(sra, x25, x6, x23, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7) # Testcase 25 + TEST_RR_OP(sra, x26, x5, x22, 0x91a, 0x1234, 0x1, x1, 4, x7) # Testcase 26 + TEST_RR_OP(sra, x27, x4, x21, 0xf8000000, 0x80000000, 0x4, x1, 8, x7) # Testcase 27 + TEST_RR_OP(sra, x28, x3, x20, 0xffffffed, -0x1234, 0x8, x1, 12, x7) # Testcase 28 + TEST_RR_OP(sra, x29, x2, x19, 0xffffffff, -0x1, 0x1f, x1, 16, x7) # Testcase 29 - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res - # Load testdata - lw x3, 0(x1) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Register initialization - li x4, 0xFFFFFE0 - li x5, 0xFFFFFE1 - li x6, 0xFFFFFEF - li x7, 0xFFFFFFF - # Test - sra x4, x3, x4 - sra x5, x3, x5 - sra x6, x3, x6 - sra x7, x3, x7 + # address for test results + la x2, test_7_res - # Store results - sw x4, 0(x2) - sw x5, 4(x2) - sw x6, 8(x2) - sw x7, 12(x2) + TEST_RR_OP(sra, x30, x1, x18, 0xffffffff, -0x7ff, 0x10, x2, 0, x3) # Testcase 30 + TEST_RR_OP(sra, x31, x0, x17, 0x0, 0x0, 0x1, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0xC3B2A190) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFF0ECA) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0xFFFFFFFF) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDEF10 -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x87654321 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S index b5266cc..d83222b 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRAI-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SRAI-01 +# RISC-V Compliance Test SRAI-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,341 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SRAI. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SRAI'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - srai x4, x3, 1 - srai x5, x3, 0xF - srai x6, x3, 0x1F - srai x7, x3, 0 - srai x8, x3, 0x10 - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + # address for test results + la x5, test_1_res - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) + TEST_IMM_OP(srai, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_IMM_OP(srai, x1, x30, 0x1, 0x1, 0x0, x5, 4, x6) # Testcase 1 + TEST_IMM_OP(srai, x2, x29, 0x0, 0x0, 0x1, x5, 8, x6) # Testcase 2 + TEST_IMM_OP(srai, x3, x28, 0x7f, 0x7ff, 0x4, x5, 12, x6) # Testcase 3 + TEST_IMM_OP(srai, x4, x27, 0x0, 0x0, 0x8, x5, 16, x6) # Testcase 4 - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX immediate values\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - # Load testdata - lw x8, 0(x1) + # address for test results + la x1, test_2_res - # Test - srai x9, x8, 1 - srai x10, x8, 0xF - srai x11, x8, 0x1F - srai x12, x8, 0 - srai x13, x8, 0x10 + TEST_IMM_OP(srai, x5, x26, 0x0, 0x800, 0x1f, x1, 0, x2) # Testcase 5 + TEST_IMM_OP(srai, x6, x25, 0x765, 0x7654321, 0x10, x1, 4, x2) # Testcase 6 + TEST_IMM_OP(srai, x7, x24, 0x3fffffff, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_IMM_OP(srai, x8, x23, 0x1, 0x1, 0x0, x1, 12, x2) # Testcase 8 + TEST_IMM_OP(srai, x9, x22, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2) # Testcase 9 - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX immediate values\n"); + # address for test results + la x1, test_3_res - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + TEST_IMM_OP(srai, x10, x21, 0x91a, 0x1234, 0x1, x1, 0, x7) # Testcase 10 + TEST_IMM_OP(srai, x11, x20, 0xf8000000, 0x80000000, 0x4, x1, 4, x7) # Testcase 11 + TEST_IMM_OP(srai, x12, x19, 0xffffffed, -0x1234, 0x8, x1, 8, x7) # Testcase 12 + TEST_IMM_OP(srai, x13, x18, 0xffffffff, -0x1, 0x1f, x1, 12, x7) # Testcase 13 + TEST_IMM_OP(srai, x14, x17, 0xffffffff, -0x7ff, 0x10, x1, 16, x7) # Testcase 14 - # Load testdata - lw x13, 0(x1) - # Test - srai x14, x13, 1 - srai x15, x13, 0xF - srai x16, x13, 0x1F - srai x17, x13, 0 - srai x18, x13, 0x10 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0xFFFFFFFF) + # address for test results + la x2, test_4_res - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + TEST_IMM_OP(srai, x15, x16, 0x0, 0x0, 0x1, x2, 0, x3) # Testcase 15 + TEST_IMM_OP(srai, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_IMM_OP(srai, x17, x14, 0x1, 0x1, 0x0, x2, 8, x3) # Testcase 17 + TEST_IMM_OP(srai, x18, x13, 0x0, 0x0, 0x1, x2, 12, x3) # Testcase 18 + TEST_IMM_OP(srai, x19, x12, 0x7f, 0x7ff, 0x4, x2, 16, x3) # Testcase 19 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x12, test_A4_data - la x13, test_A4_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - # Load testdata - lw x18, 0(x12) - # Test - srai x19, x18, 1 - srai x20, x18, 0xF - srai x21, x18, 0x1F - srai x22, x18, 0 - srai x23, x18, 0x10 + # address for test results + la x1, test_5_res - # Store results - sw x18, 0(x13) - sw x19, 4(x13) - sw x20, 8(x13) - sw x21, 12(x13) - sw x22, 16(x13) - sw x23, 20(x13) + TEST_IMM_OP(srai, x20, x11, 0x0, 0x0, 0x8, x1, 0, x2) # Testcase 20 + TEST_IMM_OP(srai, x21, x10, 0x0, 0x800, 0x1f, x1, 4, x2) # Testcase 21 + TEST_IMM_OP(srai, x22, x9, 0x765, 0x7654321, 0x10, x1, 8, x2) # Testcase 22 + TEST_IMM_OP(srai, x23, x8, 0x3fffffff, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_IMM_OP(srai, x24, x7, 0x1, 0x1, 0x0, x1, 16, x2) # Testcase 24 - RVTEST_IO_ASSERT_GPR_EQ(x13, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x19, 0x3FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x20, 0x0000FFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x21, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x00007FFF) - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x12, test_A5_data - la x13, test_A5_res + # address for test results + la x1, test_6_res - # Load testdata - lw x23, 0(x12) + TEST_IMM_OP(srai, x25, x6, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7) # Testcase 25 + TEST_IMM_OP(srai, x26, x5, 0x91a, 0x1234, 0x1, x1, 4, x7) # Testcase 26 + TEST_IMM_OP(srai, x27, x4, 0xf8000000, 0x80000000, 0x4, x1, 8, x7) # Testcase 27 + TEST_IMM_OP(srai, x28, x3, 0xffffffed, -0x1234, 0x8, x1, 12, x7) # Testcase 28 + TEST_IMM_OP(srai, x29, x2, 0xffffffff, -0x1, 0x1f, x1, 16, x7) # Testcase 29 - # Test - srai x24, x23, 1 - srai x25, x23, 0xF - srai x26, x23, 0x1F - srai x27, x23, 0 - srai x28, x23, 0x10 - # Store results - sw x23, 0(x13) - sw x24, 4(x13) - sw x25, 8(x13) - sw x26, 12(x13) - sw x27, 16(x13) - sw x28, 20(x13) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x24, 0xC0000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x25, 0xFFFF0000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x26, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x27, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x28, 0xFFFF8000) - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); + # address for test results + la x2, test_7_res - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); + TEST_IMM_OP(srai, x30, x1, 0xffffffff, -0x7ff, 0x10, x2, 0, x3) # Testcase 30 + TEST_IMM_OP(srai, x31, x0, 0x0, 0x0, 0x1, x2, 4, x3) # Testcase 31 - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - # Load testdata - lw x28, 0(x26) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - # Test - srai x29, x28, 1 - srai x30, x29, 1 - srai x31, x30, 1 - srai x1, x31, 1 - srai x2, x1, 1 - srai x3, x2, 1 + # --------------------------------------------------------------------------------------------- - # Store results - sw x28, 0(x27) - sw x29, 4(x27) - sw x30, 8(x27) - sw x31, 12(x27) - sw x1, 16(x27) - sw x2, 20(x27) - sw x3, 24(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x28, 0xABCDEF10) - RVTEST_IO_ASSERT_GPR_EQ(x27, x29, 0xD5E6F788) - RVTEST_IO_ASSERT_GPR_EQ(x27, x30, 0xEAF37BC4) - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0xF579BDE2) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0xFABCDEF1) - RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0xFD5E6F78) - RVTEST_IO_ASSERT_GPR_EQ(x27, x3, 0xFEAF37BC) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Test - srai x0, x5, 1 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Test - srai x0, x5, 1 - srai x5, x0, 1 - - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDEF10 -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRL-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRL-01.S index d7277f1..9cd51ae 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRL-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRL-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SRL-01 +# RISC-V Compliance Test SRL-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,422 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SRL. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SRL'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX (5bit) register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 1 - li x5, 0xF - li x6, 0x1F - li x7, 0 - li x8, 0x10 - # Test - srl x4, x3, x4 - srl x5, x3, x5 - srl x6, x3, x6 - srl x7, x3, x7 - srl x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(srl, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(srl, x1, x30, x15, 0x1, 0x1, 0x0, x5, 4, x6) # Testcase 1 + TEST_RR_OP(srl, x2, x29, x14, 0x0, 0x0, 0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(srl, x3, x28, x13, 0x7f, 0x7ff, 0x4, x5, 12, x6) # Testcase 3 + TEST_RR_OP(srl, x4, x27, x12, 0x0, 0x0, 0x8, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX (5bit) register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(srl, x5, x26, x11, 0x0, 0x800, 0x1f, x1, 0, x2) # Testcase 5 + TEST_RR_OP(srl, x6, x25, x10, 0x765, 0x7654321, 0x10, x1, 4, x2) # Testcase 6 + TEST_RR_OP(srl, x7, x24, x9, 0x3fffffff, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(srl, x8, x23, x8, 0x1, 0x1, 0x0, x1, 12, x2) # Testcase 8 + TEST_RR_OP(srl, x9, x22, x7, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 1 - li x10, 0xF - li x11, 0x1F - li x12, 0 - li x13, 0x10 - # Test - srl x9, x8, x9 - srl x10, x8, x10 - srl x11, x8, x11 - srl x12, x8, x12 - srl x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(srl, x10, x21, x6, 0x91a, 0x1234, 0x1, x1, 0, x7) # Testcase 10 + TEST_RR_OP(srl, x11, x20, x5, 0x8000000, 0x80000000, 0x4, x1, 4, x7) # Testcase 11 + TEST_RR_OP(srl, x12, x19, x4, 0xffffed, -0x1234, 0x8, x1, 8, x7) # Testcase 12 + TEST_RR_OP(srl, x13, x18, x3, 0x1, -0x1, 0x1f, x1, 12, x7) # Testcase 13 + TEST_RR_OP(srl, x14, x17, x2, 0xffff, -0x7ff, 0x10, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX (5bit) register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 1 - li x15, 0xF - li x16, 0x1F - li x17, 0 - li x18, 0x10 + # address for test results + la x2, test_4_res - # Test - srl x14, x13, x14 - srl x15, x13, x15 - srl x16, x13, x16 - srl x17, x13, x17 - srl x18, x13, x18 + TEST_RR_OP(srl, x15, x16, x1, 0x0, 0x0, 0x1, x2, 0, x3) # Testcase 15 + TEST_RR_OP(srl, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(srl, x17, x14, x31, 0x1, 0x1, 0x0, x2, 8, x3) # Testcase 17 + TEST_RR_OP(srl, x18, x13, x30, 0x0, 0x0, 0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(srl, x19, x12, x29, 0x7f, 0x7ff, 0x4, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x0001FFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x0000FFFF) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX (5bit) register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x12, test_A4_data - la x13, test_A4_res + TEST_RR_OP(srl, x20, x11, x28, 0x0, 0x0, 0x8, x1, 0, x2) # Testcase 20 + TEST_RR_OP(srl, x21, x10, x27, 0x0, 0x800, 0x1f, x1, 4, x2) # Testcase 21 + TEST_RR_OP(srl, x22, x9, x26, 0x765, 0x7654321, 0x10, x1, 8, x2) # Testcase 22 + TEST_RR_OP(srl, x23, x8, x25, 0x3fffffff, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(srl, x24, x7, x24, 0x1, 0x1, 0x0, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x12) - # Register initialization - li x19, 1 - li x20, 0xF - li x21, 0x1F - li x22, 0 - li x23, 0x10 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test - srl x19, x18, x19 - srl x20, x18, x20 - srl x21, x18, x21 - srl x22, x18, x22 - srl x23, x18, x23 - # Store results - sw x18, 0(x13) - sw x19, 4(x13) - sw x20, 8(x13) - sw x21, 12(x13) - sw x22, 16(x13) - sw x23, 20(x13) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x13, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x19, 0x3FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x20, 0x0000FFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x21, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x00007FFF) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX (5bit) register values\n"); - - # Addresses for test data and results - la x12, test_A5_data - la x13, test_A5_res - - # Load testdata - lw x23, 0(x12) - - # Register initialization - li x24, 1 - li x25, 0xF - li x26, 0x1F - li x27, 0 - li x28, 0x10 - - # Test - srl x24, x23, x24 - srl x25, x23, x25 - srl x26, x23, x26 - srl x27, x23, x27 - srl x28, x23, x28 - - # Store results - sw x23, 0(x13) - sw x24, 4(x13) - sw x25, 8(x13) - sw x26, 12(x13) - sw x27, 16(x13) - sw x28, 20(x13) - - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x24, 0x40000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x25, 0x00010000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x13, x27, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x28, 0x00008000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x25, test_B_data - la x26, test_B_res - - # Load testdata - lw x28, 0(x25) - - # Register initialization - li x27, 0x1 - - # Test - srl x29, x28, x27 - srl x30, x29, x27 - srl x31, x30, x27 - srl x1, x31, x27 - srl x2, x1, x27 - srl x3, x2, x27 - - # Store results - sw x28, 0(x26) - sw x29, 4(x26) - sw x30, 8(x26) - sw x31, 12(x26) - sw x1, 16(x26) - sw x2, 20(x26) - sw x3, 24(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0xABCDEF10) - RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0x55E6F788) - RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0x2AF37BC4) - RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0x1579BDE2) - RVTEST_IO_ASSERT_GPR_EQ(x26, x1, 0x0ABCDEF1) - RVTEST_IO_ASSERT_GPR_EQ(x26, x2, 0x055E6F78) - RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0x02AF37BC) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Register initialization - li x27, 1 - - # Test - srl x0, x5, x27 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Register initialization - li x27, 1 - - # Test - srl x0, x5, x27 - srl x5, x0, x27 - - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing shift by value greater than 31\n"); + TEST_RR_OP(srl, x25, x6, x23, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7) # Testcase 25 + TEST_RR_OP(srl, x26, x5, x22, 0x91a, 0x1234, 0x1, x1, 4, x7) # Testcase 26 + TEST_RR_OP(srl, x27, x4, x21, 0x8000000, 0x80000000, 0x4, x1, 8, x7) # Testcase 27 + TEST_RR_OP(srl, x28, x3, x20, 0xffffed, -0x1234, 0x8, x1, 12, x7) # Testcase 28 + TEST_RR_OP(srl, x29, x2, x19, 0x1, -0x1, 0x1f, x1, 16, x7) # Testcase 29 - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res - # Load testdata - lw x3, 0(x1) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Register initialization - li x4, 0xFFFFFE0 - li x5, 0xFFFFFE1 - li x6, 0xFFFFFEF - li x7, 0xFFFFFFF - # Test - srl x4, x3, x4 - srl x5, x3, x5 - srl x6, x3, x6 - srl x7, x3, x7 + # address for test results + la x2, test_7_res - # Store results - sw x4, 0(x2) - sw x5, 4(x2) - sw x6, 8(x2) - sw x7, 12(x2) + TEST_RR_OP(srl, x30, x1, x18, 0xffff, -0x7ff, 0x10, x2, 0, x3) # Testcase 30 + TEST_RR_OP(srl, x31, x0, x17, 0x0, 0x0, 0x1, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x87654321) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x43B2A190) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00010ECA) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000001) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDEF10 -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x87654321 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S index 6da7655..8012626 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SRLI-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SRLI-01 +# RISC-V Compliance Test SRLI-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,341 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SRLI. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SRLI'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - srli x4, x3, 1 - srli x5, x3, 0xF - srli x6, x3, 0x1F - srli x7, x3, 0 - srli x8, x3, 0x10 - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + # address for test results + la x5, test_1_res - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000000) + TEST_IMM_OP(srli, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_IMM_OP(srli, x1, x30, 0x1, 0x1, 0x0, x5, 4, x6) # Testcase 1 + TEST_IMM_OP(srli, x2, x29, 0x0, 0x0, 0x1, x5, 8, x6) # Testcase 2 + TEST_IMM_OP(srli, x3, x28, 0x7f, 0x7ff, 0x4, x5, 12, x6) # Testcase 3 + TEST_IMM_OP(srli, x4, x27, 0x0, 0x0, 0x8, x5, 16, x6) # Testcase 4 - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX immediate values\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - # Load testdata - lw x8, 0(x1) + # address for test results + la x1, test_2_res - # Test - srli x9, x8, 1 - srli x10, x8, 0xF - srli x11, x8, 0x1F - srli x12, x8, 0 - srli x13, x8, 0x10 + TEST_IMM_OP(srli, x5, x26, 0x0, 0x800, 0x1f, x1, 0, x2) # Testcase 5 + TEST_IMM_OP(srli, x6, x25, 0x765, 0x7654321, 0x10, x1, 4, x2) # Testcase 6 + TEST_IMM_OP(srli, x7, x24, 0x3fffffff, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_IMM_OP(srli, x8, x23, 0x1, 0x1, 0x0, x1, 12, x2) # Testcase 8 + TEST_IMM_OP(srli, x9, x22, 0xffffffff, 0xffffffff, 0x0, x1, 16, x2) # Testcase 9 - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x00000000) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX immediate values\n"); + # address for test results + la x1, test_3_res - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + TEST_IMM_OP(srli, x10, x21, 0x91a, 0x1234, 0x1, x1, 0, x7) # Testcase 10 + TEST_IMM_OP(srli, x11, x20, 0x8000000, 0x80000000, 0x4, x1, 4, x7) # Testcase 11 + TEST_IMM_OP(srli, x12, x19, 0xffffed, -0x1234, 0x8, x1, 8, x7) # Testcase 12 + TEST_IMM_OP(srli, x13, x18, 0x1, -0x1, 0x1f, x1, 12, x7) # Testcase 13 + TEST_IMM_OP(srli, x14, x17, 0xffff, -0x7ff, 0x10, x1, 16, x7) # Testcase 14 - # Load testdata - lw x13, 0(x1) - # Test - srli x14, x13, 1 - srli x15, x13, 0xF - srli x16, x13, 0x1F - srli x17, x13, 0 - srli x18, x13, 0x10 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0x0001FFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x0000FFFF) + # address for test results + la x2, test_4_res - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + TEST_IMM_OP(srli, x15, x16, 0x0, 0x0, 0x1, x2, 0, x3) # Testcase 15 + TEST_IMM_OP(srli, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_IMM_OP(srli, x17, x14, 0x1, 0x1, 0x0, x2, 8, x3) # Testcase 17 + TEST_IMM_OP(srli, x18, x13, 0x0, 0x0, 0x1, x2, 12, x3) # Testcase 18 + TEST_IMM_OP(srli, x19, x12, 0x7f, 0x7ff, 0x4, x2, 16, x3) # Testcase 19 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x12, test_A4_data - la x13, test_A4_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - # Load testdata - lw x18, 0(x12) - # Test - srli x19, x18, 1 - srli x20, x18, 0xF - srli x21, x18, 0x1F - srli x22, x18, 0 - srli x23, x18, 0x10 + # address for test results + la x1, test_5_res - # Store results - sw x18, 0(x13) - sw x19, 4(x13) - sw x20, 8(x13) - sw x21, 12(x13) - sw x22, 16(x13) - sw x23, 20(x13) + TEST_IMM_OP(srli, x20, x11, 0x0, 0x0, 0x8, x1, 0, x2) # Testcase 20 + TEST_IMM_OP(srli, x21, x10, 0x0, 0x800, 0x1f, x1, 4, x2) # Testcase 21 + TEST_IMM_OP(srli, x22, x9, 0x765, 0x7654321, 0x10, x1, 8, x2) # Testcase 22 + TEST_IMM_OP(srli, x23, x8, 0x3fffffff, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_IMM_OP(srli, x24, x7, 0x1, 0x1, 0x0, x1, 16, x2) # Testcase 24 - RVTEST_IO_ASSERT_GPR_EQ(x13, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x19, 0x3FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x20, 0x0000FFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x21, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x00007FFF) - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x12, test_A5_data - la x13, test_A5_res + # address for test results + la x1, test_6_res - # Load testdata - lw x23, 0(x12) + TEST_IMM_OP(srli, x25, x6, 0xffffffff, 0xffffffff, 0x0, x1, 0, x7) # Testcase 25 + TEST_IMM_OP(srli, x26, x5, 0x91a, 0x1234, 0x1, x1, 4, x7) # Testcase 26 + TEST_IMM_OP(srli, x27, x4, 0x8000000, 0x80000000, 0x4, x1, 8, x7) # Testcase 27 + TEST_IMM_OP(srli, x28, x3, 0xffffed, -0x1234, 0x8, x1, 12, x7) # Testcase 28 + TEST_IMM_OP(srli, x29, x2, 0x1, -0x1, 0x1f, x1, 16, x7) # Testcase 29 - # Test - srli x24, x23, 1 - srli x25, x23, 0xF - srli x26, x23, 0x1F - srli x27, x23, 0 - srli x28, x23, 0x10 - # Store results - sw x23, 0(x13) - sw x24, 4(x13) - sw x25, 8(x13) - sw x26, 12(x13) - sw x27, 16(x13) - sw x28, 20(x13) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - RVTEST_IO_ASSERT_GPR_EQ(x13, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x24, 0x40000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x25, 0x00010000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x26, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x13, x27, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x13, x28, 0x00008000) - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); + # address for test results + la x2, test_7_res - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); + TEST_IMM_OP(srli, x30, x1, 0xffff, -0x7ff, 0x10, x2, 0, x3) # Testcase 30 + TEST_IMM_OP(srli, x31, x0, 0x0, 0x0, 0x1, x2, 4, x3) # Testcase 31 - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - # Load testdata - lw x28, 0(x26) + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - # Test - srli x29, x28, 1 - srli x30, x29, 1 - srli x31, x30, 1 - srli x1, x31, 1 - srli x2, x1, 1 - srli x3, x2, 1 + # --------------------------------------------------------------------------------------------- - # Store results - sw x28, 0(x27) - sw x29, 4(x27) - sw x30, 8(x27) - sw x31, 12(x27) - sw x1, 16(x27) - sw x2, 20(x27) - sw x3, 24(x27) - - RVTEST_IO_ASSERT_GPR_EQ(x27, x28, 0xABCDEF10) - RVTEST_IO_ASSERT_GPR_EQ(x27, x29, 0x55E6F788) - RVTEST_IO_ASSERT_GPR_EQ(x27, x30, 0x2AF37BC4) - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0x1579BDE2) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0x0ABCDEF1) - RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0x055E6F78) - RVTEST_IO_ASSERT_GPR_EQ(x27, x3, 0x02AF37BC) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Test - srli x0, x5, 1 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Test - srli x0, x5, 1 - srli x5, x0, 1 - - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - - RVTEST_IO_WRITE_STR(x31, "# Test End\n") - - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDEF10 -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SUB-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SUB-01.S index 6fc9f0d..be59eb4 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SUB-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SUB-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-SUB-01 +# RISC-V Compliance Test SUB-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,423 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SUB. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SUB'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region. RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - # Test - sub x4, x3, x4 - sub x5, x3, x5 - sub x6, x3, x6 - sub x7, x3, x7 - sub x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(sub, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(sub, x1, x30, x15, 0x800, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_RR_OP(sub, x2, x29, x14, 0x1, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(sub, x3, x28, x13, 0x1a33, 0x7ff, -0x1234, x5, 12, x6) # Testcase 3 + TEST_RR_OP(sub, x4, x27, x12, 0x80000000, 0x0, 0x80000000, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x80000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(sub, x5, x26, x11, 0xfffff5cc, 0x800, 0x1234, x1, 0, x2) # Testcase 5 + TEST_RR_OP(sub, x6, x25, x10, 0x7654322, 0x7654321, 0xffffffff, x1, 4, x2) # Testcase 6 + TEST_RR_OP(sub, x7, x24, x9, 0x7ffffffe, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(sub, x8, x23, x8, 0x80000002, 0x1, 0x7fffffff, x1, 12, x2) # Testcase 8 + TEST_RR_OP(sub, x9, x22, x7, 0xf89abcde, 0xffffffff, 0x7654321, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 0 - li x10, 1 - li x11, -1 - li x12, 0x7FFFFFFF - li x13, 0x80000000 - # Test - sub x9, x8, x9 - sub x10, x8, x10 - sub x11, x8, x11 - sub x12, x8, x12 - sub x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0x00000002) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x80000002) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x80000001) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(sub, x10, x21, x6, 0xa34, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_RR_OP(sub, x11, x20, x5, 0x80000000, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_RR_OP(sub, x12, x19, x4, 0xffffe5cd, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_RR_OP(sub, x13, x18, x3, 0x0, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_RR_OP(sub, x14, x17, x2, 0xfffff800, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 0 - li x15, 1 - li x16, -1 - li x17, 0x7FFFFFFF - li x18, 0x80000000 + # address for test results + la x2, test_4_res - # Test - sub x14, x13, x14 - sub x15, x13, x15 - sub x16, x13, x16 - sub x17, x13, x17 - sub x18, x13, x18 + TEST_RR_OP(sub, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_RR_OP(sub, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(sub, x17, x14, x31, 0x800, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_RR_OP(sub, x18, x13, x30, 0x1, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(sub, x19, x12, x29, 0x1a33, 0x7ff, -0x1234, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + TEST_RR_OP(sub, x20, x11, x28, 0x80000000, 0x0, 0x80000000, x1, 0, x2) # Testcase 20 + TEST_RR_OP(sub, x21, x10, x27, 0xfffff5cc, 0x800, 0x1234, x1, 4, x2) # Testcase 21 + TEST_RR_OP(sub, x22, x9, x26, 0x7654322, 0x7654321, 0xffffffff, x1, 8, x2) # Testcase 22 + TEST_RR_OP(sub, x23, x8, x25, 0x7ffffffe, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(sub, x24, x7, x24, 0x80000002, 0x1, 0x7fffffff, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x1) - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test execution - sub x19, x18, x19 - sub x20, x18, x20 - sub x21, x18, x21 - sub x22, x18, x22 - sub x23, x18, x23 - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x7FFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0xFFFFFFFF) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Register initialization - li x24, 0 - li x25, 1 - li x26, -1 - li x27, 0x7FFFFFFF - li x28, 0x80000000 - - # Test - sub x24, x23, x24 - sub x25, x23, x25 - sub x26, x23, x26 - sub x27, x23, x27 - sub x28, x23, x28 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x80000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x25, test_B_data - la x26, test_B_res - - # Load testdata - lw x28, 0(x25) - - # Register initialization - li x27, 0x1 - - # Test - sub x29, x28, x27 - sub x30, x29, x27 - sub x31, x30, x27 - sub x1, x31, x27 - sub x2, x1, x27 - sub x3, x2, x27 - - # store results - sw x27, 0(x26) - sw x28, 4(x26) - sw x29, 8(x26) - sw x30, 12(x26) - sw x31, 16(x26) - sw x1, 20(x26) - sw x2, 24(x26) - sw x3, 28(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x27, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0x0000ABCD) - RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0x0000ABCC) - RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0x0000ABCB) - RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0x0000ABCA) - RVTEST_IO_ASSERT_GPR_EQ(x26, x1, 0x0000ABC9) - RVTEST_IO_ASSERT_GPR_EQ(x26, x2, 0x0000ABC8) - RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0x0000ABC7) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - sub x0, x28, x27 - - # store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - sub x0, x28, x27 - sub x5, x0, x0 - - # store results - sw x0, 0(x2) - sw x5, 4(x2) - - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + TEST_RR_OP(sub, x25, x6, x23, 0xf89abcde, 0xffffffff, 0x7654321, x1, 0, x7) # Testcase 25 + TEST_RR_OP(sub, x26, x5, x22, 0xa34, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_RR_OP(sub, x27, x4, x21, 0x80000000, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_RR_OP(sub, x28, x3, x20, 0xffffe5cd, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_RR_OP(sub, x29, x2, x19, 0x0, -0x1, -0x1, x1, 16, x7) # Testcase 29 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving and negation (sub with x0)\n"); - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Load testdata - lw x3, 0(x1) - # Test - sub x4, x3, x0 - sub x5, x4, x0 - sub x6, x0, x5 - sub x14, x6, x0 - sub x15, x14, x0 - sub x16, x15, x0 - sub x25, x0, x16 - sub x26, x0, x25 - sub x27, x26, x0 + # address for test results + la x2, test_7_res - # Store results - sw x4, 0(x2) - sw x26, 4(x2) - sw x27, 8(x2) + TEST_RR_OP(sub, x30, x1, x18, 0xfffff800, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_RR_OP(sub, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0xC96DA7EC) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xC96DA7EC) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0x0000ABCD -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x36925814 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 8, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 3, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 -RV_COMPLIANCE_DATA_END # End of test output data region. +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SW-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SW-01.S index 2c81fd0..afabbb7 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SW-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-SW-01.S
@@ -1,274 +1,519 @@ # RISC-V Compliance Test I-SW-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions -# All rights reserved. # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the -# names of its contributors may be used to endorse or promote products -# derived from this software without specific prior written permission. +# Copyright (c) 2019 Imperas Software Ltd., www.imperas.com # -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction SW. +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. +# +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +# +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'SW'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - test base address + 0\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Address for test results - la x1, test_A1_res + # --------------------------------------------------------------------------------------------- - # Test - li x2, 0x11F1F222 - sw x2, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - test base address - 1\n"); + # Addresses for test results + la x5, test_1_res - # Address for test results - la x5, test_A2_res + 1 + # Clear memory + sw x0, 0(x5) + # Load values and compute offsets + li x16, -0x1 + addi x31, x5,0 + addi x31, x31, 0x7d0 + # Test Instruction + sw x16, -0x7d0(x31) + # Check results: mem[test_1_res+0] = -0x1 + lw x7, 0(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x7, -0x1) - # Test - li x25, 0xF33344F4 - sw x25, 0xFFFFFFFF(x5) + # Clear memory + sw x0, 4(x5) + # Load values and compute offsets + li x15, 0x1 + addi x30, x5,4 + addi x30, x30, 0x0 + # Test Instruction + sw x15, 0x0(x30) + # Check results: mem[test_1_res+4] = 0x1 + lw x7, 4(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x7, 0x1) - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + # Clear memory + sw x0, 8(x5) + # Load values and compute offsets + li x14, 0x0 + addi x29, x5,8 + addi x29, x29, 0x1 + # Test Instruction + sw x14, -0x1(x29) + # Check results: mem[test_1_res+8] = 0x0 + lw x7, 8(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x7, 0x0) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - test base address + 1\n"); + # Clear memory + sw x0, 12(x5) + # Load values and compute offsets + li x13, 0x7ff + addi x28, x5,12 + addi x28, x28, 0x7d0 + # Test Instruction + sw x13, -0x7d0(x28) + # Check results: mem[test_1_res+12] = 0x7ff + lw x7, 12(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x7, 0x7ff) - # Address for test results - la x8, test_A3_res - 1 + # Clear memory + sw x0, 16(x5) + # Load values and compute offsets + li x12, 0x0 + addi x27, x5,16 + addi x27, x27, -0x7d0 + # Test Instruction + sw x12, 0x7d0(x27) + # Check results: mem[test_1_res+16] = 0x0 + lw x7, 16(x5) + RVTEST_IO_ASSERT_GPR_EQ(x6, x7, 0x0) - # Test - li x31, 0x55F5F666 - sw x31, +1(x8) - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - test base address - 2048\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Address for test results - la x11, test_A4_res + 2048 - # Test - li x12, 0xF77788F8 - sw x12, 0xFFFFF800(x11) + # Addresses for test results + la x1, test_2_res - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); + # Clear memory + sw x0, 0(x1) + # Load values and compute offsets + li x11, 0x800 + addi x26, x1,0 + addi x26, x26, -0x7d0 + # Test Instruction + sw x11, 0x7d0(x26) + # Check results: mem[test_2_res+0] = 0x800 + lw x3, 0(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x800) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - test base address + 2047\n"); + # Clear memory + sw x0, 4(x1) + # Load values and compute offsets + li x10, 0x7654321 + addi x25, x1,4 + addi x25, x25, -0x7d0 + # Test Instruction + sw x10, 0x7d0(x25) + # Check results: mem[test_2_res+4] = 0x7654321 + lw x3, 4(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x7654321) - # Address for test results - la x14, test_A5_res - 2047 + # Clear memory + sw x0, 8(x1) + # Load values and compute offsets + li x9, 0x7fffffff + addi x24, x1,8 + addi x24, x24, -0x1 + # Test Instruction + sw x9, 0x1(x24) + # Check results: mem[test_2_res+8] = 0x7fffffff + lw x3, 8(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x7fffffff) - # Test - li x15, 0x99090AAA - sw x15, 0x7FF(x14) + # Clear memory + sw x0, 12(x1) + # Load values and compute offsets + li x8, 0x1 + addi x23, x1,12 + addi x23, x23, -0x7d0 + # Test Instruction + sw x8, 0x7d0(x23) + # Check results: mem[test_2_res+12] = 0x1 + lw x3, 12(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x1) - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); + # Clear memory + sw x0, 16(x1) + # Load values and compute offsets + li x7, 0xffffffff + addi x22, x1,16 + addi x22, x22, -0x7d0 + # Test Instruction + sw x7, 0x7d0(x22) + # Check results: mem[test_2_res+16] = 0xffffffff + lw x3, 16(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0xffffffff) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - test base address + -4, 0, 4\n"); - # Address for test results - la x17, test_B_res - # Test - li x18, 0x0BBBCC0C - li x19, 0xDD0D0EEE - li x20, 0x0FFF00F0 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x18, -4(x17) - sw x19, 0(x17) - sw x20, 4(x17) - RVTEST_IO_ASSERT_GPR_EQ(x17, x18, 0x0BBBCC0C) - RVTEST_IO_ASSERT_GPR_EQ(x17, x19, 0xDD0D0EEE) - RVTEST_IO_ASSERT_GPR_EQ(x17, x20, 0x0FFF00F0) + # Addresses for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); + # Clear memory + sw x0, 0(x1) + # Load values and compute offsets + li x6, 0x1234 + addi x21, x1,0 + addi x21, x21, -0x7d0 + # Test Instruction + sw x6, 0x7d0(x21) + # Check results: mem[test_3_res+0] = 0x1234 + lw x8, 0(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0x1234) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - test store x0\n"); + # Clear memory + sw x0, 4(x1) + # Load values and compute offsets + li x5, 0x80000000 + addi x20, x1,4 + addi x20, x20, 0x0 + # Test Instruction + sw x5, 0x0(x20) + # Check results: mem[test_3_res+4] = 0x80000000 + lw x8, 4(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0x80000000) - # Address for test results - la x22, test_C_res + # Clear memory + sw x0, 8(x1) + # Load values and compute offsets + li x4, -0x1234 + addi x19, x1,8 + addi x19, x19, -0x7d0 + # Test Instruction + sw x4, 0x7d0(x19) + # Check results: mem[test_3_res+8] = -0x1234 + lw x8, 8(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x1234) - # Test - li x0, 0x12345678 - sw x0, 0(x22) + # Clear memory + sw x0, 12(x1) + # Load values and compute offsets + li x3, -0x1 + addi x18, x1,12 + addi x18, x18, 0x1 + # Test Instruction + sw x3, -0x1(x18) + # Check results: mem[test_3_res+12] = -0x1 + lw x8, 12(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x1) - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); + # Clear memory + sw x0, 16(x1) + # Load values and compute offsets + li x2, -0x7ff + addi x17, x1,16 + addi x17, x17, 0x0 + # Test Instruction + sw x2, 0x0(x17) + # Check results: mem[test_3_res+16] = -0x7ff + lw x8, 16(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x7ff) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D1 - test for forwarding (to address register)\n"); - # Address for test data - la x21, test_D1_data - # Test - li x19, 0x11223344 - lw x23, 0(x21) - sw x19, 0(x23) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D2 - test for forwarding (to data register)\n"); + # Addresses for test results + la x2, test_4_res - # Address for test data - la x23, test_D2_data - la x24, test_D2_res + # Clear memory + sw x0, 0(x2) + # Load values and compute offsets + li x1, -0x2 + addi x16, x2,0 + addi x16, x16, -0x1 + # Test Instruction + sw x1, 0x1(x16) + # Check results: mem[test_4_res+0] = -0x2 + lw x4, 0(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x4, -0x2) - # Test - lw x25, 0(x23) - sw x25, 0(x24) + # Clear memory + sw x0, 4(x2) + # Load values and compute offsets + li x0, -0x1 + addi x15, x2,4 + addi x15, x15, 0x7d0 + # Test Instruction + sw x0, -0x7d0(x15) + # Check results: mem[test_4_res+4] = 0 + lw x4, 4(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x4, 0) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # Clear memory + sw x0, 8(x2) + # Load values and compute offsets + li x31, 0x1 + addi x14, x2,8 + addi x14, x14, 0x0 + # Test Instruction + sw x31, 0x0(x14) + # Check results: mem[test_4_res+8] = 0x1 + lw x4, 8(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x4, 0x1) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E1 - test war hazard (data register)\n"); + # Clear memory + sw x0, 12(x2) + # Load values and compute offsets + li x30, 0x0 + addi x13, x2,12 + addi x13, x13, 0x1 + # Test Instruction + sw x30, -0x1(x13) + # Check results: mem[test_4_res+12] = 0x0 + lw x4, 12(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x4, 0x0) - # Address for test results - la x26, test_E1_res + # Clear memory + sw x0, 16(x2) + # Load values and compute offsets + li x29, 0x7ff + addi x12, x2,16 + addi x12, x12, 0x7d0 + # Test Instruction + sw x29, -0x7d0(x12) + # Check results: mem[test_4_res+16] = 0x7ff + lw x4, 16(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x4, 0x7ff) - # Test - li x25, 0x76543210 - sw x25, 0(x26) - mv x25, x0 - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E2 - test war hazard (address register)\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - # Address for test results - la x28, test_E2_res - # Test - li x27, 0x89ABCDEF - sw x27, 0(x28) - addi x28, x28, -4 + # Addresses for test results + la x1, test_5_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + # Clear memory + sw x0, 0(x1) + # Load values and compute offsets + li x28, 0x0 + addi x11, x1,0 + addi x11, x11, -0x7d0 + # Test Instruction + sw x28, 0x7d0(x11) + # Check results: mem[test_5_res+0] = 0x0 + lw x3, 0(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x0) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part F - test raw hazard in memory\n"); + # Clear memory + sw x0, 4(x1) + # Load values and compute offsets + li x27, 0x800 + addi x10, x1,4 + addi x10, x10, -0x7d0 + # Test Instruction + sw x27, 0x7d0(x10) + # Check results: mem[test_5_res+4] = 0x800 + lw x3, 4(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x800) - # Address for test results - la x29, test_F_res + # Clear memory + sw x0, 8(x1) + # Load values and compute offsets + li x26, 0x7654321 + addi x9, x1,8 + addi x9, x9, -0x7d0 + # Test Instruction + sw x26, 0x7d0(x9) + # Check results: mem[test_5_res+8] = 0x7654321 + lw x3, 8(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x7654321) - # Test - li x27, 0x14725836 - sw x27, 0(x29) - lw x30, 0(x29) - sw x30, 4(x29) + # Clear memory + sw x0, 12(x1) + # Load values and compute offsets + li x25, 0x7fffffff + addi x8, x1,12 + addi x8, x8, -0x1 + # Test Instruction + sw x25, 0x1(x8) + # Check results: mem[test_5_res+12] = 0x7fffffff + lw x3, 12(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x7fffffff) - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + # Clear memory + sw x0, 16(x1) + # Load values and compute offsets + li x24, 0x1 + addi x7, x1,16 + addi x7, x7, -0x7d0 + # Test Instruction + sw x24, 0x7d0(x7) + # Check results: mem[test_5_res+16] = 0x1 + lw x3, 16(x1) + RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x1) - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part G - test waw hazard in memory\n"); - # Address for test results - la x1, test_G_res - # Test - li x2, 0x96385201 - li x3, 0x25814963 - sw x2, 0(x1) - sw x3, 0(x1) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # Addresses for test results + la x1, test_6_res - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + # Clear memory + sw x0, 0(x1) + # Load values and compute offsets + li x23, 0xffffffff + addi x6, x1,0 + addi x6, x6, -0x7d0 + # Test Instruction + sw x23, 0x7d0(x6) + # Check results: mem[test_6_res+0] = 0xffffffff + lw x8, 0(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0xffffffff) + + # Clear memory + sw x0, 4(x1) + # Load values and compute offsets + li x22, 0x1234 + addi x5, x1,4 + addi x5, x5, -0x7d0 + # Test Instruction + sw x22, 0x7d0(x5) + # Check results: mem[test_6_res+4] = 0x1234 + lw x8, 4(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0x1234) + + # Clear memory + sw x0, 8(x1) + # Load values and compute offsets + li x21, 0x80000000 + addi x4, x1,8 + addi x4, x4, 0x0 + # Test Instruction + sw x21, 0x0(x4) + # Check results: mem[test_6_res+8] = 0x80000000 + lw x8, 8(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, 0x80000000) + + # Clear memory + sw x0, 12(x1) + # Load values and compute offsets + li x20, -0x1234 + addi x3, x1,12 + addi x3, x3, -0x7d0 + # Test Instruction + sw x20, 0x7d0(x3) + # Check results: mem[test_6_res+12] = -0x1234 + lw x8, 12(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x1234) + + # Clear memory + sw x0, 16(x1) + # Load values and compute offsets + li x19, -0x1 + addi x2, x1,16 + addi x2, x2, 0x1 + # Test Instruction + sw x19, -0x1(x2) + # Check results: mem[test_6_res+16] = -0x1 + lw x8, 16(x1) + RVTEST_IO_ASSERT_GPR_EQ(x7, x8, -0x1) + + + + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") + + + # Addresses for test results + la x2, test_7_res + + # Clear memory + sw x0, 0(x2) + # Load values and compute offsets + li x18, -0x7ff + addi x1, x2,0 + addi x1, x1, 0x0 + # Test Instruction + sw x18, 0x0(x1) + # Check results: mem[test_7_res+0] = -0x7ff + lw x4, 0(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x4, -0x7ff) + + # Clear memory + sw x0, 4(x2) + # Load values and compute offsets + li x17, -0x2 + addi x1, x2,4 + addi x1, x1, -0x1 + # Test Instruction + sw x17, 0x1(x1) + # Check results: mem[test_7_res+4] = -0x2 + lw x4, 4(x2) + RVTEST_IO_ASSERT_GPR_EQ(x3, x4, -0x2) + + + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_D1_data: - .word test_D1_res -test_D2_data: - .word 0x9ABCDEF0 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 1, 4, -1 -test_A2_res: - .fill 1, 4, -1 -test_A3_res: - .fill 1, 4, -1 -test_A4_res: - .fill 1, 4, -1 -test_A5_res: - .fill 1, 4, -1 - .fill 1, 4, -1 -test_B_res: - .fill 2, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D1_res: - .fill 1, 4, -1 -test_D2_res: - .fill 1, 4, -1 -test_E1_res: - .fill 1, 4, -1 -test_E2_res: - .fill 1, 4, -1 -test_F_res: - .fill 2, 4, -1 -test_G_res: - .fill 1, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-XOR-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-XOR-01.S index a8ca6a9..af35340 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-XOR-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-XOR-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-XOR-01 +# RISC-V Compliance Test XOR-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,428 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction XOR. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'XOR'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region. RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX register values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Register initialization - li x4, 0 - li x5, 1 - li x6, -1 - li x7, 0x7FFFFFFF - li x8, 0x80000000 - # Test - xor x4, x3, x4 - xor x5, x3, x5 - xor x6, x3, x6 - xor x7, x3, x7 - xor x8, x3, x8 + # address for test results + la x5, test_1_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + TEST_RR_OP(xor, x0, x31, x16, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_RR_OP(xor, x1, x30, x15, 0xfffff800, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_RR_OP(xor, x2, x29, x14, 0xffffffff, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_RR_OP(xor, x3, x28, x13, 0xffffea33, 0x7ff, -0x1234, x5, 12, x6) # Testcase 3 + TEST_RR_OP(xor, x4, x27, x12, 0x80000000, 0x0, 0x80000000, x5, 16, x6) # Testcase 4 - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x80000000) - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res + # address for test results + la x1, test_2_res - # Load testdata - lw x8, 0(x1) + TEST_RR_OP(xor, x5, x26, x11, 0x1a34, 0x800, 0x1234, x1, 0, x2) # Testcase 5 + TEST_RR_OP(xor, x6, x25, x10, 0xf89abcde, 0x7654321, 0xffffffff, x1, 4, x2) # Testcase 6 + TEST_RR_OP(xor, x7, x24, x9, 0x7ffffffe, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_RR_OP(xor, x8, x23, x8, 0x7ffffffe, 0x1, 0x7fffffff, x1, 12, x2) # Testcase 8 + TEST_RR_OP(xor, x9, x22, x7, 0xf89abcde, 0xffffffff, 0x7654321, x1, 16, x2) # Testcase 9 - # Register initialization - li x9, 0 - li x10, 1 - li x11, -1 - li x12, 0x7FFFFFFF - li x13, 0x80000000 - # Test - xor x9, x8, x9 - xor x10, x8, x10 - xor x11, x8, x11 - xor x12, x8, x12 - xor x13, x8, x13 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x7FFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0x80000001) + # address for test results + la x1, test_3_res - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); + TEST_RR_OP(xor, x10, x21, x6, 0x1a34, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_RR_OP(xor, x11, x20, x5, 0x80000000, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_RR_OP(xor, x12, x19, x4, 0xffffea33, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_RR_OP(xor, x13, x18, x3, 0x0, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_RR_OP(xor, x14, x17, x2, 0xfffff800, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX register values\n"); - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Load testdata - lw x13, 0(x1) - # Register initialization - li x14, 0 - li x15, 1 - li x16, -1 - li x17, 0x7FFFFFFF - li x18, 0x80000000 + # address for test results + la x2, test_4_res - # Test - xor x14, x13, x14 - xor x15, x13, x15 - xor x16, x13, x16 - xor x17, x13, x17 - xor x18, x13, x18 + TEST_RR_OP(xor, x15, x16, x1, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_RR_OP(xor, x16, x15, x0, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_RR_OP(xor, x17, x14, x31, 0xfffff800, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_RR_OP(xor, x18, x13, x30, 0xffffffff, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_RR_OP(xor, x19, x12, x29, 0xffffea33, 0x7ff, -0x1234, x2, 16, x3) # Testcase 19 - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX register values\n"); + # address for test results + la x1, test_5_res - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + TEST_RR_OP(xor, x20, x11, x28, 0x80000000, 0x0, 0x80000000, x1, 0, x2) # Testcase 20 + TEST_RR_OP(xor, x21, x10, x27, 0x1a34, 0x800, 0x1234, x1, 4, x2) # Testcase 21 + TEST_RR_OP(xor, x22, x9, x26, 0xf89abcde, 0x7654321, 0xffffffff, x1, 8, x2) # Testcase 22 + TEST_RR_OP(xor, x23, x8, x25, 0x7ffffffe, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_RR_OP(xor, x24, x7, x24, 0x7ffffffe, 0x1, 0x7fffffff, x1, 16, x2) # Testcase 24 - # Load testdata - lw x18, 0(x1) - # Register initialization - li x19, 0 - li x20, 1 - li x21, -1 - li x22, 0x7FFFFFFF - li x23, 0x80000000 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Test execution - xor x19, x18, x19 - xor x20, x18, x20 - xor x21, x18, x21 - xor x22, x18, x22 - xor x23, x18, x23 - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + # address for test results + la x1, test_6_res - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x7FFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0xFFFFFFFF) - - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX register values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Register initialization - li x24, 0 - li x25, 1 - li x26, -1 - li x27, 0x7FFFFFFF - li x28, 0x80000000 - - # Test - xor x24, x23, x24 - xor x25, x23, x25 - xor x26, x23, x26 - xor x27, x23, x27 - xor x28, x23, x28 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x80000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x25, test_B_data - la x26, test_B_res - - # Load testdata - lw x28, 0(x25) - - # Register initialization - li x4, 0x7F - li x5, 0x3F - li x6, 0x1F - li x7, 0x0F - li x8, 0x07 - li x9, 0x03 - - # Test - xor x29, x28, x4 - xor x30, x29, x5 - xor x31, x30, x6 - xor x1, x31, x7 - xor x2, x1, x8 - xor x3, x2, x9 - - # store results - sw x4, 0(x26) - sw x28, 4(x26) - sw x29, 8(x26) - sw x30, 12(x26) - sw x31, 16(x26) - sw x1, 20(x26) - sw x2, 24(x26) - sw x3, 28(x26) - - RVTEST_IO_ASSERT_GPR_EQ(x26, x4, 0x0000007F) - RVTEST_IO_ASSERT_GPR_EQ(x26, x28, 0xABCDFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x26, x29, 0xABCDFF80) - RVTEST_IO_ASSERT_GPR_EQ(x26, x30, 0xABCDFFBF) - RVTEST_IO_ASSERT_GPR_EQ(x26, x31, 0xABCDFFA0) - RVTEST_IO_ASSERT_GPR_EQ(x26, x1, 0xABCDFFAF) - RVTEST_IO_ASSERT_GPR_EQ(x26, x2, 0xABCDFFA8) - RVTEST_IO_ASSERT_GPR_EQ(x26, x3, 0xABCDFFAB) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - xor x0, x28, x27 - - # store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x28, 0(x1) - - # Register initialization - li x27, 0xF7FF8818 - - # Test - xor x0, x28, x27 - xor x5, x0, x0 - - # store results - sw x0, 0(x2) - sw x5, 4(x2) - - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + TEST_RR_OP(xor, x25, x6, x23, 0xf89abcde, 0xffffffff, 0x7654321, x1, 0, x7) # Testcase 25 + TEST_RR_OP(xor, x26, x5, x22, 0x1a34, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_RR_OP(xor, x27, x4, x21, 0x80000000, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_RR_OP(xor, x28, x3, x20, 0xffffea33, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_RR_OP(xor, x29, x2, x19, 0x0, -0x1, -0x1, x1, 16, x7) # Testcase 29 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving (xor with x0)\n"); - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Load testdata - lw x3, 0(x1) - # Test - xor x4, x3, x0 - xor x5, x4, x0 - xor x6, x0, x5 - xor x14, x6, x0 - xor x15, x14, x0 - xor x16, x15, x0 - xor x25, x0, x16 - xor x26, x0, x25 - xor x27, x26, x0 + # address for test results + la x2, test_7_res - # Store results - sw x4, 0(x2) - sw x26, 4(x2) - sw x27, 8(x2) + TEST_RR_OP(xor, x30, x1, x18, 0xfffff800, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_RR_OP(xor, x31, x0, x17, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDFFFF -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x36925814 + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 8, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 3, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 -RV_COMPLIANCE_DATA_END # End of test output data region. +RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-XORI-01.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-XORI-01.S index 5637a48..7137385 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-XORI-01.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/src/I-XORI-01.S
@@ -1,7 +1,6 @@ -# RISC-V Compliance Test I-XORI-01 +# RISC-V Compliance Test XORI-01 # -# Copyright (c) 2017, Codasip Ltd. -# Copyright (c) 2018, Imperas Software Ltd. Additions +# Copyright (c) 2019, Imperas Software Ltd. # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -11,380 +10,163 @@ # * Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# * Neither the name of the Codasip Ltd., Imperas Software Ltd. nor the +# * Neither the name of the Imperas Software Ltd. nor the # names of its contributors may be used to endorse or promote products # derived from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS # IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, # THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd., Imperas Software Ltd. -# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; # LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND # ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -# Specification: RV32I Base Integer Instruction Set, Version 2.0 -# Description: Testing instruction XORI. +# Specification: RV32I Base Integer Instruction Set, Version 2.1 +# Description: Testing instruction 'XORI'. +#include "riscv_test_macros.h" #include "compliance_test.h" #include "compliance_io.h" -#include "test_macros.h" -# Test Virtual Machine (TVM) used by program. RV_COMPLIANCE_RV32M -# Test code region RV_COMPLIANCE_CODE_BEGIN - RVTEST_IO_INIT - RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) - RVTEST_IO_WRITE_STR(x31, "# Test Begin\n") - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - general test of value 0 with 0, 1, -1, MIN, MAX immediate values\n"); + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin\n") - # Addresses for test data and results - la x1, test_A1_data - la x2, test_A1_res + # --------------------------------------------------------------------------------------------- - # Load testdata - lw x3, 0(x1) + RVTEST_IO_WRITE_STR(x31, "# Test number 1\n") - # Test - xori x4, x3, 1 - xori x5, x3, 0x7FF - xori x6, x3, 0xFFFFFFFF - xori x7, x3, 0 - xori x8, x3, 0xFFFFF800 - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x5, 8(x2) - sw x6, 12(x2) - sw x7, 16(x2) - sw x8, 20(x2) + # address for test results + la x5, test_1_res - // - // Assert - // - RVTEST_IO_CHECK() - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x000007FF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x6, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x7, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0xFFFFF800) + TEST_IMM_OP(xori, x0, x31, 0x0, -0x1, 0x0, x5, 0, x6) # Testcase 0 + TEST_IMM_OP(xori, x1, x30, 0xfffff800, 0x1, -0x7ff, x5, 4, x6) # Testcase 1 + TEST_IMM_OP(xori, x2, x29, 0xffffffff, 0x0, -0x1, x5, 8, x6) # Testcase 2 + TEST_IMM_OP(xori, x3, x28, 0xffffffff, 0x7ff, -0x800, x5, 12, x6) # Testcase 3 + TEST_IMM_OP(xori, x4, x27, 0xfffff800, 0x0, 0x800, x5, 16, x6) # Testcase 4 - RVTEST_IO_WRITE_STR(x31, "# Test part A1 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - general test of value 1 with 0, 1, -1, MIN, MAX immediate values\n"); + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 2\n") - # Addresses for test data and results - la x1, test_A2_data - la x2, test_A2_res - # Load testdata - lw x8, 0(x1) + # address for test results + la x1, test_2_res - # Test - xori x9, x8, 1 - xori x10, x8, 0x7FF - xori x11, x8, 0xFFFFFFFF - xori x12, x8, 0 - xori x13, x8, 0xFFFFF800 + TEST_IMM_OP(xori, x5, x26, 0xfffff000, 0x800, 0x800, x1, 0, x2) # Testcase 5 + TEST_IMM_OP(xori, x6, x25, 0xf89abb21, 0x7654321, 0x800, x1, 4, x2) # Testcase 6 + TEST_IMM_OP(xori, x7, x24, 0x7ffffffe, 0x7fffffff, 0x1, x1, 8, x2) # Testcase 7 + TEST_IMM_OP(xori, x8, x23, 0xfffff801, 0x1, 0x800, x1, 12, x2) # Testcase 8 + TEST_IMM_OP(xori, x9, x22, 0x7ff, 0xffffffff, 0x800, x1, 16, x2) # Testcase 9 - # Store results - sw x8, 0(x2) - sw x9, 4(x2) - sw x10, 8(x2) - sw x11, 12(x2) - sw x12, 16(x2) - sw x13, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x8, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x9, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x000007FE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x11, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x12, 0x00000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFF801) + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 3\n") - RVTEST_IO_WRITE_STR(x31, "# Test part A2 - Complete\n"); - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - general test of value -1 with 0, 1, -1, MIN, MAX immediate values\n"); + # address for test results + la x1, test_3_res - # Addresses for test data and results - la x1, test_A3_data - la x2, test_A3_res + TEST_IMM_OP(xori, x10, x21, 0xffffea34, 0x1234, 0x800, x1, 0, x7) # Testcase 10 + TEST_IMM_OP(xori, x11, x20, 0x80000000, 0x80000000, 0x0, x1, 4, x7) # Testcase 11 + TEST_IMM_OP(xori, x12, x19, 0xffffea33, -0x1234, 0x7ff, x1, 8, x7) # Testcase 12 + TEST_IMM_OP(xori, x13, x18, 0x0, -0x1, -0x1, x1, 12, x7) # Testcase 13 + TEST_IMM_OP(xori, x14, x17, 0xfffff800, -0x7ff, 0x1, x1, 16, x7) # Testcase 14 - # Load testdata - lw x13, 0(x1) - # Test - xori x14, x13, 1 - xori x15, x13, 0x7FF - xori x16, x13, 0xFFFFFFFF - xori x17, x13, 0 - xori x18, x13, 0xFFFFF800 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 4\n") - # Store results - sw x13, 0(x2) - sw x14, 4(x2) - sw x15, 8(x2) - sw x16, 12(x2) - sw x17, 16(x2) - sw x18, 20(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x13, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x14, 0xFFFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x15, 0xFFFFF800) - RVTEST_IO_ASSERT_GPR_EQ(x2, x16, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x17, 0xFFFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x000007FF) + # address for test results + la x2, test_4_res - RVTEST_IO_WRITE_STR(x31, "# Test part A3 - Complete\n"); + TEST_IMM_OP(xori, x15, x16, 0x0, 0x0, 0x0, x2, 0, x3) # Testcase 15 + TEST_IMM_OP(xori, x16, x15, 0xffffffff, -0x1, 0x0, x2, 4, x3) # Testcase 16 + TEST_IMM_OP(xori, x17, x14, 0xfffff800, 0x1, -0x7ff, x2, 8, x3) # Testcase 17 + TEST_IMM_OP(xori, x18, x13, 0xffffffff, 0x0, -0x1, x2, 12, x3) # Testcase 18 + TEST_IMM_OP(xori, x19, x12, 0xffffffff, 0x7ff, -0x800, x2, 16, x3) # Testcase 19 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - general test of value 0x7FFFFFFF with 0, 1, -1, MIN, MAX immediate values\n"); - # Addresses for test data and results - la x1, test_A4_data - la x2, test_A4_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 5\n") - # Load testdata - lw x18, 0(x1) - # Test - xori x19, x18, 1 - xori x20, x18, 0x7FF - xori x21, x18, 0xFFFFFFFF - xori x22, x18, 0 - xori x23, x18, 0xFFFFF800 + # address for test results + la x1, test_5_res - # Store results - sw x18, 0(x2) - sw x19, 4(x2) - sw x20, 8(x2) - sw x21, 12(x2) - sw x22, 16(x2) - sw x23, 20(x2) + TEST_IMM_OP(xori, x20, x11, 0xfffff800, 0x0, 0x800, x1, 0, x2) # Testcase 20 + TEST_IMM_OP(xori, x21, x10, 0xfffff000, 0x800, 0x800, x1, 4, x2) # Testcase 21 + TEST_IMM_OP(xori, x22, x9, 0xf89abb21, 0x7654321, 0x800, x1, 8, x2) # Testcase 22 + TEST_IMM_OP(xori, x23, x8, 0x7ffffffe, 0x7fffffff, 0x1, x1, 12, x2) # Testcase 23 + TEST_IMM_OP(xori, x24, x7, 0xfffff801, 0x1, 0x800, x1, 16, x2) # Testcase 24 - RVTEST_IO_ASSERT_GPR_EQ(x2, x18, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x19, 0x7FFFFFFE) - RVTEST_IO_ASSERT_GPR_EQ(x2, x20, 0x7FFFF800) - RVTEST_IO_ASSERT_GPR_EQ(x2, x21, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x22, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x800007FF) - RVTEST_IO_WRITE_STR(x31, "# Test part A4 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - general test of value 0x80000000 with 0, 1, -1, MIN, MAX immediate values\n"); - - # Addresses for test data and results - la x1, test_A5_data - la x2, test_A5_res - - # Load testdata - lw x23, 0(x1) - - # Test - xori x24, x23, 1 - xori x25, x23, 0x7FF - xori x26, x23, 0xFFFFFFFF - xori x27, x23, 0 - xori x28, x23, 0xFFFFF800 - - # Store results - sw x23, 0(x2) - sw x24, 4(x2) - sw x25, 8(x2) - sw x26, 12(x2) - sw x27, 16(x2) - sw x28, 20(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x23, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x24, 0x80000001) - RVTEST_IO_ASSERT_GPR_EQ(x2, x25, 0x800007FF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x7FFFFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x80000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x28, 0x7FFFF800) - - RVTEST_IO_WRITE_STR(x31, "# Test part A5 - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part B - testing forwarding between instructions\n"); - - # Addresses for test data and results - la x26, test_B_data - la x27, test_B_res - - # Load testdata - lw x28, 0(x26) - - # Test - xori x29, x28, 0x7F - xori x30, x29, 0x3F - xori x31, x30, 0x1F - xori x1, x31, 0x0F - xori x2, x1, 0x07 - xori x3, x2, 0x03 - - # Store results - sw x28, 0(x27) - sw x29, 4(x27) - sw x30, 8(x27) - sw x31, 12(x27) - sw x1, 16(x27) - sw x2, 20(x27) - sw x3, 24(x27) - - - RVTEST_IO_ASSERT_GPR_EQ(x27, x28, 0xABCDFFFF) - RVTEST_IO_ASSERT_GPR_EQ(x27, x29, 0xABCDFF80) - RVTEST_IO_ASSERT_GPR_EQ(x27, x30, 0xABCDFFBF) - RVTEST_IO_ASSERT_GPR_EQ(x27, x31, 0xABCDFFA0) - RVTEST_IO_ASSERT_GPR_EQ(x27, x1, 0xABCDFFAF) - RVTEST_IO_ASSERT_GPR_EQ(x27, x2, 0xABCDFFA8) - RVTEST_IO_ASSERT_GPR_EQ(x27, x3, 0xABCDFFAB) - - RVTEST_IO_WRITE_STR(x31, "# Test part B - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part C - testing writing to x0\n"); - - # Addresses for test data and results - la x1, test_C_data - la x2, test_C_res - - # Load testdata - lw x5, 0(x1) - - # Test - xori x0, x5, 1 - - # Store results - sw x0, 0(x2) - - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - - RVTEST_IO_WRITE_STR(x31, "# Test part C - Complete\n"); - - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part D - testing forwarding throught x0\n"); - - # Addresses for test data and results - la x1, test_D_data - la x2, test_D_res - - # Load testdata - lw x5, 0(x1) - - # Test - xori x0, x5, 1 - xori x5, x0, 1 + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 6\n") - # Store results - sw x0, 0(x2) - sw x5, 4(x2) - RVTEST_IO_ASSERT_GPR_EQ(x2, x0, 0x00000000) - RVTEST_IO_ASSERT_GPR_EQ(x2, x5, 0x00000001) + # address for test results + la x1, test_6_res - RVTEST_IO_WRITE_STR(x31, "# Test part D - Complete\n"); + TEST_IMM_OP(xori, x25, x6, 0x7ff, 0xffffffff, 0x800, x1, 0, x7) # Testcase 25 + TEST_IMM_OP(xori, x26, x5, 0xffffea34, 0x1234, 0x800, x1, 4, x7) # Testcase 26 + TEST_IMM_OP(xori, x27, x4, 0x80000000, 0x80000000, 0x0, x1, 8, x7) # Testcase 27 + TEST_IMM_OP(xori, x28, x3, 0xffffea33, -0x1234, 0x7ff, x1, 12, x7) # Testcase 28 + TEST_IMM_OP(xori, x29, x2, 0x0, -0x1, -0x1, x1, 16, x7) # Testcase 29 - # --------------------------------------------------------------------------------------------- - RVTEST_IO_WRITE_STR(x31, "# Test part E - testing moving (xori with 0)\n"); - # Addresses for test data and results - la x1, test_E_data - la x2, test_E_res + # --------------------------------------------------------------------------------------------- + RVTEST_IO_WRITE_STR(x31, "# Test number 7\n") - # Load testdata - lw x3, 0(x1) - # Test - xori x4, x3, 0 - xori x5, x4, 0 - xori x6, x5, 0 - xori x14, x6, 0 - xori x15, x14, 0 - xori x16, x15, 0 - xori x25, x16, 0 - xori x26, x25, 0 - xori x27, x26, 0 + # address for test results + la x2, test_7_res - # Store results - sw x3, 0(x2) - sw x4, 4(x2) - sw x26, 8(x2) - sw x27, 12(x2) + TEST_IMM_OP(xori, x30, x1, 0xfffff800, -0x7ff, 0x1, x2, 0, x3) # Testcase 30 + TEST_IMM_OP(xori, x31, x0, 0x0, 0x0, 0x0, x2, 4, x3) # Testcase 31 - RVTEST_IO_ASSERT_GPR_EQ(x2, x3, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x4, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x26, 0x36925814) - RVTEST_IO_ASSERT_GPR_EQ(x2, x27, 0x36925814) - RVTEST_IO_WRITE_STR(x31, "# Test part E - Complete\n"); + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "Test End\n") - RVTEST_IO_WRITE_STR(x31, "# Test End\n") + # --------------------------------------------------------------------------------------------- - # --------------------------------------------------------------------------------------------- - # HALT - RV_COMPLIANCE_HALT + RV_COMPLIANCE_HALT RV_COMPLIANCE_CODE_END # Input data section. - .data - .align 4 - -test_A1_data: - .word 0 -test_A2_data: - .word 1 -test_A3_data: - .word -1 -test_A4_data: - .word 0x7FFFFFFF -test_A5_data: - .word 0x80000000 -test_B_data: - .word 0xABCDFFFF -test_C_data: - .word 0x12345678 -test_D_data: - .word 0xFEDCBA98 -test_E_data: - .word 0x36925814 - + .data # Output data section. RV_COMPLIANCE_DATA_BEGIN - .align 4 -test_A1_res: - .fill 6, 4, -1 -test_A2_res: - .fill 6, 4, -1 -test_A3_res: - .fill 6, 4, -1 -test_A4_res: - .fill 6, 4, -1 -test_A5_res: - .fill 6, 4, -1 -test_B_res: - .fill 7, 4, -1 -test_C_res: - .fill 1, 4, -1 -test_D_res: - .fill 2, 4, -1 -test_E_res: - .fill 4, 4, -1 +test_1_res: + .fill 5, 4, -1 +test_2_res: + .fill 5, 4, -1 +test_3_res: + .fill 5, 4, -1 +test_4_res: + .fill 5, 4, -1 +test_5_res: + .fill 5, 4, -1 +test_6_res: + .fill 5, 4, -1 +test_7_res: + .fill 5, 4, -1 RV_COMPLIANCE_DATA_END +
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/Makefile index 22bbb42..6f37d7e 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/Makefile +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/Makefile
@@ -8,6 +8,9 @@ work_dir_isa := $(work_dir)/$(RISCV_ISA) include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif default: all @@ -26,33 +29,28 @@ #------------------------------------------------------------ # Build and run assembly tests -%.out32: %.elf - $(RUN_TARGET) +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) define compile_template -$$($(1)_tests): %.elf: $(src_dir)/%.S - @mkdir -p $(work_dir_isa)/$$(@D) - $(COMPILE_TARGET) -$(1)_tests += $$($(1)_p_tests) +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) -.PHONY: $(1) - -tests += $$($(1)_tests) +.PRECIOUS: $(work_dir_isa)/%.elf endef -$(eval $(call compile_template,rv32im,-march=rv32im -mabi=ilp32)) +$(eval $(call compile_template,-march=rv32im -mabi=ilp32)) -tests32_out = $(patsubst %.elf,%.out32,$(target32_tests)) +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) -run: $(tests32_out) - -#------------------------------------------------------------ -# Default - -all: $(tests_dump) +run: $(target_log) #------------------------------------------------------------ # Clean up
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/Makefrag index fb0d283..0a5ce44 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/Makefrag +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/Makefrag
@@ -43,4 +43,4 @@ rv32im_tests = $(addsuffix .elf, $(rv32im_sc_tests)) -target32_tests += $(rv32im_tests) +target_tests += $(rv32im_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/coverage/report.txt b/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/coverage/report.txt new file mode 100644 index 0000000..d4dc572 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/coverage/report.txt
@@ -0,0 +1,1149 @@ +This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv + +COVERGROUP COVERAGE: +---------------------------------------------------------------------------------------------------------- +Covergroup Metric Goal Status + +---------------------------------------------------------------------------------------------------------- + TYPE /riscv_instr_pkg/riscv_instr_cover_group/mul_cg + 89.28% 100 Uncovered + covered/total bins: 82 106 + missing/total bins: 24 106 + % Hit: 77.35% 100 + Coverpoint mul_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mul_cg::cp_rs2 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mul_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mul_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint mul_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint mul_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Cross mul_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 9 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 6 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 6 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/mulh_cg + 89.28% 100 Uncovered + covered/total bins: 82 106 + missing/total bins: 24 106 + % Hit: 77.35% 100 + Coverpoint mulh_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mulh_cg::cp_rs2 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mulh_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mulh_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint mulh_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint mulh_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 17 1 Covered + bin auto[NEGATIVE] 8 1 Covered + Cross mulh_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 9 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 6 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 6 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/mulhsu_cg + 89.28% 100 Uncovered + covered/total bins: 82 106 + missing/total bins: 24 106 + % Hit: 77.35% 100 + Coverpoint mulhsu_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mulhsu_cg::cp_rs2 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mulhsu_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mulhsu_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint mulhsu_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint mulhsu_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 17 1 Covered + bin auto[NEGATIVE] 8 1 Covered + Cross mulhsu_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 9 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 6 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 6 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/mulhu_cg + 89.28% 100 Uncovered + covered/total bins: 82 106 + missing/total bins: 24 106 + % Hit: 77.35% 100 + Coverpoint mulhu_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mulhu_cg::cp_rs2 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mulhu_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint mulhu_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint mulhu_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint mulhu_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 24 1 Covered + bin auto[NEGATIVE] 1 1 Covered + Cross mulhu_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 9 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 6 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 6 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/div_cg + 90.62% 100 Uncovered + covered/total bins: 85 109 + missing/total bins: 24 109 + % Hit: 77.98% 100 + Coverpoint div_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint div_cg::cp_rs2 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint div_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint div_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint div_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint div_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 14 1 Covered + bin auto[NEGATIVE] 11 1 Covered + Coverpoint div_cg::cp_div_result 100.00% 100 Covered + covered/total bins: 3 3 + missing/total bins: 0 3 + % Hit: 100.00% 100 + bin auto[DIV_NORMAL] 19 1 Covered + bin auto[DIV_BY_ZERO] 5 1 Covered + bin auto[DIV_OVERFLOW] 1 1 Covered + Cross div_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 9 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 6 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 6 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/divu_cg + 90.62% 100 Uncovered + covered/total bins: 85 109 + missing/total bins: 24 109 + % Hit: 77.98% 100 + Coverpoint divu_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint divu_cg::cp_rs2 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint divu_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint divu_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint divu_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint divu_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 18 1 Covered + bin auto[NEGATIVE] 7 1 Covered + Coverpoint divu_cg::cp_div_result 100.00% 100 Covered + covered/total bins: 3 3 + missing/total bins: 0 3 + % Hit: 100.00% 100 + bin auto[DIV_NORMAL] 19 1 Covered + bin auto[DIV_BY_ZERO] 5 1 Covered + bin auto[DIV_OVERFLOW] 1 1 Covered + Cross divu_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 9 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 6 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 6 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/rem_cg + 90.62% 100 Uncovered + covered/total bins: 85 109 + missing/total bins: 24 109 + % Hit: 77.98% 100 + Coverpoint rem_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint rem_cg::cp_rs2 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint rem_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint rem_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint rem_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint rem_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 20 1 Covered + bin auto[NEGATIVE] 5 1 Covered + Coverpoint rem_cg::cp_div_result 100.00% 100 Covered + covered/total bins: 3 3 + missing/total bins: 0 3 + % Hit: 100.00% 100 + bin auto[DIV_NORMAL] 19 1 Covered + bin auto[DIV_BY_ZERO] 5 1 Covered + bin auto[DIV_OVERFLOW] 1 1 Covered + Cross rem_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 9 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 6 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 6 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/remu_cg + 90.62% 100 Uncovered + covered/total bins: 85 109 + missing/total bins: 24 109 + % Hit: 77.98% 100 + Coverpoint remu_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint remu_cg::cp_rs2 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint remu_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint remu_cg::cp_rs1_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint remu_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 15 1 Covered + bin auto[NEGATIVE] 10 1 Covered + Coverpoint remu_cg::cp_rd_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 22 1 Covered + bin auto[NEGATIVE] 3 1 Covered + Coverpoint remu_cg::cp_div_result 100.00% 100 Covered + covered/total bins: 3 3 + missing/total bins: 0 3 + % Hit: 100.00% 100 + bin auto[DIV_NORMAL] 19 1 Covered + bin auto[DIV_BY_ZERO] 5 1 Covered + bin auto[DIV_OVERFLOW] 1 1 Covered + Cross remu_cg::cp_sign_cross 100.00% 100 Covered + covered/total bins: 4 4 + missing/total bins: 0 4 + % Hit: 100.00% 100 + bin <auto[POSITIVE],auto[POSITIVE]> 9 1 Covered + bin <auto[NEGATIVE],auto[POSITIVE]> 6 1 Covered + bin <auto[POSITIVE],auto[NEGATIVE]> 6 1 Covered + bin <auto[NEGATIVE],auto[NEGATIVE]> 4 1 Covered + +TOTAL COVERGROUP COVERAGE: 89.95% COVERGROUP TYPES: 8
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/coverage/summary.txt b/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/coverage/summary.txt new file mode 100644 index 0000000..1066a7a --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32im/coverage/summary.txt
@@ -0,0 +1,54 @@ +This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv + + Coverpoint mul_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint mul_cg::cp_rs2 75.00% 100 Uncovered + Coverpoint mul_cg::cp_rd 75.00% 100 Uncovered + Coverpoint mul_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint mul_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint mul_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint mulh_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint mulh_cg::cp_rs2 75.00% 100 Uncovered + Coverpoint mulh_cg::cp_rd 75.00% 100 Uncovered + Coverpoint mulh_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint mulh_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint mulh_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint mulhsu_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint mulhsu_cg::cp_rs2 75.00% 100 Uncovered + Coverpoint mulhsu_cg::cp_rd 75.00% 100 Uncovered + Coverpoint mulhsu_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint mulhsu_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint mulhsu_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint mulhu_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint mulhu_cg::cp_rs2 75.00% 100 Uncovered + Coverpoint mulhu_cg::cp_rd 75.00% 100 Uncovered + Coverpoint mulhu_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint mulhu_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint mulhu_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint div_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint div_cg::cp_rs2 75.00% 100 Uncovered + Coverpoint div_cg::cp_rd 75.00% 100 Uncovered + Coverpoint div_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint div_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint div_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint div_cg::cp_div_result 100.00% 100 Covered + Coverpoint divu_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint divu_cg::cp_rs2 75.00% 100 Uncovered + Coverpoint divu_cg::cp_rd 75.00% 100 Uncovered + Coverpoint divu_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint divu_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint divu_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint divu_cg::cp_div_result 100.00% 100 Covered + Coverpoint rem_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint rem_cg::cp_rs2 75.00% 100 Uncovered + Coverpoint rem_cg::cp_rd 75.00% 100 Uncovered + Coverpoint rem_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint rem_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint rem_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint rem_cg::cp_div_result 100.00% 100 Covered + Coverpoint remu_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint remu_cg::cp_rs2 75.00% 100 Uncovered + Coverpoint remu_cg::cp_rd 75.00% 100 Uncovered + Coverpoint remu_cg::cp_rs1_sign 100.00% 100 Covered + Coverpoint remu_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint remu_cg::cp_rd_sign 100.00% 100 Covered + Coverpoint remu_cg::cp_div_result 100.00% 100 Covered
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/Makefile index 90e9572..bc04c30 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/Makefile +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/Makefile
@@ -8,6 +8,9 @@ work_dir_isa := $(work_dir)/$(RISCV_ISA) include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif default: all @@ -26,33 +29,28 @@ #------------------------------------------------------------ # Build and run assembly tests -%.out32: %.elf - $(RUN_TARGET) +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) define compile_template -$$($(1)_tests): %.elf: $(src_dir)/%.S - @mkdir -p $(work_dir_isa)/$$(@D) - $(COMPILE_TARGET) -$(1)_tests += $$($(1)_p_tests) +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) -.PHONY: $(1) - -tests += $$($(1)_tests) +.PRECIOUS: $(work_dir_isa)/%.elf endef -$(eval $(call compile_template,rv32imc,-march=rv32imc -mabi=ilp32)) +$(eval $(call compile_template,-march=rv32imc -mabi=ilp32)) -tests32_out = $(patsubst %.elf,%.out32,$(target32_tests)) +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) -run: $(tests32_out) - -#------------------------------------------------------------ -# Default - -all: $(tests_dump) +run: $(target_log) #------------------------------------------------------------ # Clean up
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/Makefrag index a38b59d..04b45ec 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/Makefrag +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/Makefrag
@@ -56,4 +56,4 @@ rv32imc_tests = $(addsuffix .elf, $(rv32imc_sc_tests)) -target32_tests += $(rv32imc_tests) +target_tests += $(rv32imc_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/coverage/report.txt b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/coverage/report.txt new file mode 100644 index 0000000..9f06f63 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/coverage/report.txt
@@ -0,0 +1,812 @@ +This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv + +COVERGROUP COVERAGE: +---------------------------------------------------------------------------------------------------------- +Covergroup Metric Goal Status + +---------------------------------------------------------------------------------------------------------- + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_lw_cg + 75.00% 100 Uncovered + covered/total bins: 12 16 + missing/total bins: 4 16 + % Hit: 75.00% 100 + Coverpoint c_lw_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 6 8 + missing/total bins: 2 8 + % Hit: 75.00% 100 + bin gpr[S0] 1 1 Covered + bin gpr[S1] 2 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 0 1 ZERO + bin gpr[A2] 2 1 Covered + bin gpr[A3] 1 1 Covered + bin gpr[A4] 2 1 Covered + bin gpr[A5] 2 1 Covered + Coverpoint c_lw_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 6 8 + missing/total bins: 2 8 + % Hit: 75.00% 100 + bin gpr[S0] 3 1 Covered + bin gpr[S1] 2 1 Covered + bin gpr[A0] 1 1 Covered + bin gpr[A1] 0 1 ZERO + bin gpr[A2] 0 1 ZERO + bin gpr[A3] 2 1 Covered + bin gpr[A4] 1 1 Covered + bin gpr[A5] 2 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_lwsp_cg + 0.00% 100 ZERO + covered/total bins: 0 8 + missing/total bins: 8 8 + % Hit: 0.00% 100 + Coverpoint c_lwsp_cg::cp_rd 0.00% 100 ZERO + covered/total bins: 0 8 + missing/total bins: 8 8 + % Hit: 0.00% 100 + bin gpr[S0] 0 1 ZERO + bin gpr[S1] 0 1 ZERO + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 0 1 ZERO + bin gpr[A2] 0 1 ZERO + bin gpr[A3] 0 1 ZERO + bin gpr[A4] 0 1 ZERO + bin gpr[A5] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_sw_cg + 75.00% 100 Uncovered + covered/total bins: 12 16 + missing/total bins: 4 16 + % Hit: 75.00% 100 + Coverpoint c_sw_cg::cp_rs1 50.00% 100 Uncovered + covered/total bins: 4 8 + missing/total bins: 4 8 + % Hit: 50.00% 100 + bin gpr[S0] 0 1 ZERO + bin gpr[S1] 1 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 0 1 ZERO + bin gpr[A2] 2 1 Covered + bin gpr[A3] 0 1 ZERO + bin gpr[A4] 1 1 Covered + bin gpr[A5] 1 1 Covered + Coverpoint c_sw_cg::cp_rs2 100.00% 100 Covered + covered/total bins: 8 8 + missing/total bins: 0 8 + % Hit: 100.00% 100 + bin gpr[S0] 39 1 Covered + bin gpr[S1] 41 1 Covered + bin gpr[A0] 12 1 Covered + bin gpr[A1] 36 1 Covered + bin gpr[A2] 37 1 Covered + bin gpr[A3] 39 1 Covered + bin gpr[A4] 37 1 Covered + bin gpr[A5] 39 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_swsp_cg + 0.00% 100 ZERO + covered/total bins: 0 8 + missing/total bins: 8 8 + % Hit: 0.00% 100 + Coverpoint c_swsp_cg::cp_rs2 0.00% 100 ZERO + covered/total bins: 0 8 + missing/total bins: 8 8 + % Hit: 0.00% 100 + bin gpr[S0] 0 1 ZERO + bin gpr[S1] 0 1 ZERO + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 0 1 ZERO + bin gpr[A2] 0 1 ZERO + bin gpr[A3] 0 1 ZERO + bin gpr[A4] 0 1 ZERO + bin gpr[A5] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_addi4spn_cg + 0.00% 100 ZERO + covered/total bins: 0 10 + missing/total bins: 10 10 + % Hit: 0.00% 100 + Coverpoint c_addi4spn_cg::cp_imm_sign 0.00% 100 ZERO + covered/total bins: 0 2 + missing/total bins: 2 2 + % Hit: 0.00% 100 + bin auto[POSITIVE] 0 1 ZERO + bin auto[NEGATIVE] 0 1 ZERO + Coverpoint c_addi4spn_cg::cp_rd 0.00% 100 ZERO + covered/total bins: 0 8 + missing/total bins: 8 8 + % Hit: 0.00% 100 + bin gpr[S0] 0 1 ZERO + bin gpr[S1] 0 1 ZERO + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 0 1 ZERO + bin gpr[A2] 0 1 ZERO + bin gpr[A3] 0 1 ZERO + bin gpr[A4] 0 1 ZERO + bin gpr[A5] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_addi_cg + 90.62% 100 Uncovered + covered/total bins: 28 34 + missing/total bins: 6 34 + % Hit: 82.35% 100 + Coverpoint c_addi_cg::cp_rd 81.25% 100 Uncovered + covered/total bins: 26 32 + missing/total bins: 6 32 + % Hit: 81.25% 100 + bin auto[ZERO] 25 1 Covered + bin auto[RA] 0 1 ZERO + bin auto[SP] 5 1 Covered + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 2 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 2 1 Covered + bin auto[A3] 2 1 Covered + bin auto[A4] 2 1 Covered + bin auto[A5] 2 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint c_addi_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 59 1 Covered + bin auto[NEGATIVE] 1 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_addi16sp_cg + 0.00% 100 ZERO + covered/total bins: 0 2 + missing/total bins: 2 2 + % Hit: 0.00% 100 + Coverpoint c_addi16sp_cg::cp_imm_sign 0.00% 100 ZERO + covered/total bins: 0 2 + missing/total bins: 2 2 + % Hit: 0.00% 100 + bin auto[POSITIVE] 0 1 ZERO + bin auto[NEGATIVE] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_li_cg + 92.18% 100 Uncovered + covered/total bins: 29 34 + missing/total bins: 5 34 + % Hit: 85.29% 100 + Coverpoint c_li_cg::cp_rd 84.37% 100 Uncovered + covered/total bins: 27 32 + missing/total bins: 5 32 + % Hit: 84.37% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 2 1 Covered + bin auto[GP] 57 1 Covered + bin auto[TP] 7 1 Covered + bin auto[T0] 50 1 Covered + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 27 1 Covered + bin auto[S1] 27 1 Covered + bin auto[A0] 32 1 Covered + bin auto[A1] 27 1 Covered + bin auto[A2] 27 1 Covered + bin auto[A3] 27 1 Covered + bin auto[A4] 25 1 Covered + bin auto[A5] 26 1 Covered + bin auto[A6] 7 1 Covered + bin auto[A7] 2 1 Covered + bin auto[S2] 2 1 Covered + bin auto[S3] 2 1 Covered + bin auto[S4] 2 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 3 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 3 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 2 1 Covered + bin auto[S11] 2 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 2 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint c_li_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 329 1 Covered + bin auto[NEGATIVE] 38 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_lui_cg + 78.12% 100 Uncovered + covered/total bins: 25 32 + missing/total bins: 7 32 + % Hit: 78.12% 100 + Coverpoint c_lui_cg::cp_rd 78.12% 100 Uncovered + covered/total bins: 25 32 + missing/total bins: 7 32 + % Hit: 78.12% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 10 1 Covered + bin auto[S1] 11 1 Covered + bin auto[A0] 2 1 Covered + bin auto[A1] 9 1 Covered + bin auto[A2] 7 1 Covered + bin auto[A3] 8 1 Covered + bin auto[A4] 8 1 Covered + bin auto[A5] 11 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 2 1 Covered + bin auto[S5] 4 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 2 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 3 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 2 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 2 1 Covered + bin auto[T5] 2 1 Covered + bin auto[T6] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_sub_cg + 87.50% 100 Uncovered + covered/total bins: 14 16 + missing/total bins: 2 16 + % Hit: 87.50% 100 + Coverpoint c_sub_cg::cp_rd 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 5 1 Covered + bin gpr[S1] 5 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 4 1 Covered + bin gpr[A2] 5 1 Covered + bin gpr[A3] 3 1 Covered + bin gpr[A4] 4 1 Covered + bin gpr[A5] 4 1 Covered + Coverpoint c_sub_cg::cp_rs2 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 5 1 Covered + bin gpr[S1] 5 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 4 1 Covered + bin gpr[A2] 5 1 Covered + bin gpr[A3] 3 1 Covered + bin gpr[A4] 4 1 Covered + bin gpr[A5] 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_add_cg + 83.33% 100 Uncovered + covered/total bins: 50 66 + missing/total bins: 16 66 + % Hit: 75.75% 100 + Coverpoint c_add_cg::cp_rs2 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint c_add_cg::cp_rd 75.00% 100 Uncovered + covered/total bins: 24 32 + missing/total bins: 8 32 + % Hit: 75.00% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint c_add_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 20 1 Covered + bin auto[NEGATIVE] 5 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_mv_cg + 47.91% 100 Uncovered + covered/total bins: 16 66 + missing/total bins: 50 66 + % Hit: 24.24% 100 + Coverpoint c_mv_cg::cp_rs2 21.87% 100 Uncovered + covered/total bins: 7 32 + missing/total bins: 25 32 + % Hit: 21.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 0 1 ZERO + bin auto[TP] 0 1 ZERO + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 4 1 Covered + bin auto[S1] 3 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 4 1 Covered + bin auto[A2] 4 1 Covered + bin auto[A3] 3 1 Covered + bin auto[A4] 4 1 Covered + bin auto[A5] 3 1 Covered + bin auto[A6] 0 1 ZERO + bin auto[A7] 0 1 ZERO + bin auto[S2] 0 1 ZERO + bin auto[S3] 0 1 ZERO + bin auto[S4] 0 1 ZERO + bin auto[S5] 0 1 ZERO + bin auto[S6] 0 1 ZERO + bin auto[S7] 0 1 ZERO + bin auto[S8] 0 1 ZERO + bin auto[S9] 0 1 ZERO + bin auto[S10] 0 1 ZERO + bin auto[S11] 0 1 ZERO + bin auto[T3] 0 1 ZERO + bin auto[T4] 0 1 ZERO + bin auto[T5] 0 1 ZERO + bin auto[T6] 0 1 ZERO + Coverpoint c_mv_cg::cp_rd 21.87% 100 Uncovered + covered/total bins: 7 32 + missing/total bins: 25 32 + % Hit: 21.87% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 0 1 ZERO + bin auto[TP] 0 1 ZERO + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 3 1 Covered + bin auto[S1] 4 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 4 1 Covered + bin auto[A2] 3 1 Covered + bin auto[A3] 4 1 Covered + bin auto[A4] 3 1 Covered + bin auto[A5] 4 1 Covered + bin auto[A6] 0 1 ZERO + bin auto[A7] 0 1 ZERO + bin auto[S2] 0 1 ZERO + bin auto[S3] 0 1 ZERO + bin auto[S4] 0 1 ZERO + bin auto[S5] 0 1 ZERO + bin auto[S6] 0 1 ZERO + bin auto[S7] 0 1 ZERO + bin auto[S8] 0 1 ZERO + bin auto[S9] 0 1 ZERO + bin auto[S10] 0 1 ZERO + bin auto[S11] 0 1 ZERO + bin auto[T3] 0 1 ZERO + bin auto[T4] 0 1 ZERO + bin auto[T5] 0 1 ZERO + bin auto[T6] 0 1 ZERO + Coverpoint c_mv_cg::cp_rs2_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 20 1 Covered + bin auto[NEGATIVE] 5 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_andi_cg + 93.75% 100 Uncovered + covered/total bins: 9 10 + missing/total bins: 1 10 + % Hit: 90.00% 100 + Coverpoint c_andi_cg::cp_rs1 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 3 1 Covered + bin gpr[S1] 3 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 4 1 Covered + bin gpr[A2] 4 1 Covered + bin gpr[A3] 4 1 Covered + bin gpr[A4] 4 1 Covered + bin gpr[A5] 3 1 Covered + Coverpoint c_andi_cg::cp_imm_sign 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[POSITIVE] 20 1 Covered + bin auto[NEGATIVE] 5 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_xor_cg + 87.50% 100 Uncovered + covered/total bins: 14 16 + missing/total bins: 2 16 + % Hit: 87.50% 100 + Coverpoint c_xor_cg::cp_rd 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 4 1 Covered + bin gpr[S1] 3 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 4 1 Covered + bin gpr[A2] 3 1 Covered + bin gpr[A3] 4 1 Covered + bin gpr[A4] 3 1 Covered + bin gpr[A5] 4 1 Covered + Coverpoint c_xor_cg::cp_rs2 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 4 1 Covered + bin gpr[S1] 3 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 4 1 Covered + bin gpr[A2] 3 1 Covered + bin gpr[A3] 4 1 Covered + bin gpr[A4] 3 1 Covered + bin gpr[A5] 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_or_cg + 87.50% 100 Uncovered + covered/total bins: 14 16 + missing/total bins: 2 16 + % Hit: 87.50% 100 + Coverpoint c_or_cg::cp_rd 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 3 1 Covered + bin gpr[S1] 4 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 3 1 Covered + bin gpr[A2] 4 1 Covered + bin gpr[A3] 3 1 Covered + bin gpr[A4] 4 1 Covered + bin gpr[A5] 4 1 Covered + Coverpoint c_or_cg::cp_rs2 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 3 1 Covered + bin gpr[S1] 4 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 3 1 Covered + bin gpr[A2] 4 1 Covered + bin gpr[A3] 3 1 Covered + bin gpr[A4] 4 1 Covered + bin gpr[A5] 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_and_cg + 87.50% 100 Uncovered + covered/total bins: 14 16 + missing/total bins: 2 16 + % Hit: 87.50% 100 + Coverpoint c_and_cg::cp_rd 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 4 1 Covered + bin gpr[S1] 4 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 3 1 Covered + bin gpr[A2] 4 1 Covered + bin gpr[A3] 3 1 Covered + bin gpr[A4] 4 1 Covered + bin gpr[A5] 3 1 Covered + Coverpoint c_and_cg::cp_rs2 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 4 1 Covered + bin gpr[S1] 4 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 3 1 Covered + bin gpr[A2] 4 1 Covered + bin gpr[A3] 3 1 Covered + bin gpr[A4] 4 1 Covered + bin gpr[A5] 3 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_beqz_cg + 56.25% 100 Uncovered + covered/total bins: 6 10 + missing/total bins: 4 10 + % Hit: 60.00% 100 + Coverpoint c_beqz_cg::cp_rs1 62.50% 100 Uncovered + covered/total bins: 5 8 + missing/total bins: 3 8 + % Hit: 62.50% 100 + bin gpr[S0] 1 1 Covered + bin gpr[S1] 1 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 1 1 Covered + bin gpr[A2] 1 1 Covered + bin gpr[A3] 0 1 ZERO + bin gpr[A4] 0 1 ZERO + bin gpr[A5] 1 1 Covered + Coverpoint c_beqz_cg::cp_imm_sign 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[POSITIVE] 5 1 Covered + bin auto[NEGATIVE] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_bnez_cg + 62.50% 100 Uncovered + covered/total bins: 7 10 + missing/total bins: 3 10 + % Hit: 70.00% 100 + Coverpoint c_bnez_cg::cp_rs1 75.00% 100 Uncovered + covered/total bins: 6 8 + missing/total bins: 2 8 + % Hit: 75.00% 100 + bin gpr[S0] 1 1 Covered + bin gpr[S1] 1 1 Covered + bin gpr[A0] 25 1 Covered + bin gpr[A1] 0 1 ZERO + bin gpr[A2] 0 1 ZERO + bin gpr[A3] 1 1 Covered + bin gpr[A4] 1 1 Covered + bin gpr[A5] 1 1 Covered + Coverpoint c_bnez_cg::cp_imm_sign 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[POSITIVE] 30 1 Covered + bin auto[NEGATIVE] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_srli_cg + 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + Coverpoint c_srli_cg::cp_rs1 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 4 1 Covered + bin gpr[S1] 4 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 3 1 Covered + bin gpr[A2] 3 1 Covered + bin gpr[A3] 3 1 Covered + bin gpr[A4] 4 1 Covered + bin gpr[A5] 4 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_srai_cg + 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + Coverpoint c_srai_cg::cp_rs1 87.50% 100 Uncovered + covered/total bins: 7 8 + missing/total bins: 1 8 + % Hit: 87.50% 100 + bin gpr[S0] 3 1 Covered + bin gpr[S1] 4 1 Covered + bin gpr[A0] 0 1 ZERO + bin gpr[A1] 4 1 Covered + bin gpr[A2] 4 1 Covered + bin gpr[A3] 4 1 Covered + bin gpr[A4] 3 1 Covered + bin gpr[A5] 3 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_slli_cg + 39.06% 100 Uncovered + covered/total bins: 25 34 + missing/total bins: 9 34 + % Hit: 73.52% 100 + Coverpoint c_slli_cg::cp_rd 78.12% 100 Uncovered + covered/total bins: 25 32 + missing/total bins: 7 32 + % Hit: 78.12% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 25 1 Covered + bin auto[A1] 1 1 Covered + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 1 1 Covered + bin auto[S2] 1 1 Covered + bin auto[S3] 1 1 Covered + bin auto[S4] 1 1 Covered + bin auto[S5] 2 1 Covered + bin auto[S6] 1 1 Covered + bin auto[S7] 1 1 Covered + bin auto[S8] 1 1 Covered + bin auto[S9] 1 1 Covered + bin auto[S10] 1 1 Covered + bin auto[S11] 1 1 Covered + bin auto[T3] 1 1 Covered + bin auto[T4] 1 1 Covered + bin auto[T5] 1 1 Covered + bin auto[T6] 0 1 ZERO + Coverpoint c_slli_cg::cp_gpr_hazard 0.00% 100 ZERO + covered/total bins: 0 2 + missing/total bins: 2 2 + % Hit: 0.00% 100 + bin valid_hazard[NO_HAZARD] 0 1 ZERO + bin valid_hazard[RAW_HAZARD] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_j_cg + 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + Coverpoint c_j_cg::cp_imm_sign 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[POSITIVE] 0 1 ZERO + bin auto[NEGATIVE] 30 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_jal_cg + 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + Coverpoint c_jal_cg::cp_imm_sign 50.00% 100 Uncovered + covered/total bins: 1 2 + missing/total bins: 1 2 + % Hit: 50.00% 100 + bin auto[POSITIVE] 0 1 ZERO + bin auto[NEGATIVE] 5 1 Covered + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_jr_cg + 15.62% 100 Uncovered + covered/total bins: 5 32 + missing/total bins: 27 32 + % Hit: 15.62% 100 + Coverpoint c_jr_cg::cp_rs1 15.62% 100 Uncovered + covered/total bins: 5 32 + missing/total bins: 27 32 + % Hit: 15.62% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 1 1 Covered + bin auto[TP] 1 1 Covered + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 1 1 Covered + bin auto[S1] 1 1 Covered + bin auto[A0] 0 1 ZERO + bin auto[A1] 1 1 Covered + bin auto[A2] 0 1 ZERO + bin auto[A3] 0 1 ZERO + bin auto[A4] 0 1 ZERO + bin auto[A5] 0 1 ZERO + bin auto[A6] 0 1 ZERO + bin auto[A7] 0 1 ZERO + bin auto[S2] 0 1 ZERO + bin auto[S3] 0 1 ZERO + bin auto[S4] 0 1 ZERO + bin auto[S5] 0 1 ZERO + bin auto[S6] 0 1 ZERO + bin auto[S7] 0 1 ZERO + bin auto[S8] 0 1 ZERO + bin auto[S9] 0 1 ZERO + bin auto[S10] 0 1 ZERO + bin auto[S11] 0 1 ZERO + bin auto[T3] 0 1 ZERO + bin auto[T4] 0 1 ZERO + bin auto[T5] 0 1 ZERO + bin auto[T6] 0 1 ZERO + TYPE /riscv_instr_pkg/riscv_instr_cover_group/c_jalr_cg + 57.81% 100 Uncovered + covered/total bins: 7 34 + missing/total bins: 27 34 + % Hit: 20.58% 100 + Coverpoint c_jalr_cg::cp_rs1 15.62% 100 Uncovered + covered/total bins: 5 32 + missing/total bins: 27 32 + % Hit: 15.62% 100 + bin auto[ZERO] 0 1 ZERO + bin auto[RA] 0 1 ZERO + bin auto[SP] 0 1 ZERO + bin auto[GP] 0 1 ZERO + bin auto[TP] 0 1 ZERO + bin auto[T0] 0 1 ZERO + bin auto[T1] 0 1 ZERO + bin auto[T2] 0 1 ZERO + bin auto[S0] 0 1 ZERO + bin auto[S1] 0 1 ZERO + bin auto[A0] 0 1 ZERO + bin auto[A1] 0 1 ZERO + bin auto[A2] 1 1 Covered + bin auto[A3] 1 1 Covered + bin auto[A4] 1 1 Covered + bin auto[A5] 1 1 Covered + bin auto[A6] 1 1 Covered + bin auto[A7] 0 1 ZERO + bin auto[S2] 0 1 ZERO + bin auto[S3] 0 1 ZERO + bin auto[S4] 0 1 ZERO + bin auto[S5] 0 1 ZERO + bin auto[S6] 0 1 ZERO + bin auto[S7] 0 1 ZERO + bin auto[S8] 0 1 ZERO + bin auto[S9] 0 1 ZERO + bin auto[S10] 0 1 ZERO + bin auto[S11] 0 1 ZERO + bin auto[T3] 0 1 ZERO + bin auto[T4] 0 1 ZERO + bin auto[T5] 0 1 ZERO + bin auto[T6] 0 1 ZERO + Coverpoint c_jalr_cg::cp_rd_align 100.00% 100 Covered + covered/total bins: 2 2 + missing/total bins: 0 2 + % Hit: 100.00% 100 + bin auto[0] 3 1 Covered + bin auto[1] 2 1 Covered + +TOTAL COVERGROUP COVERAGE: 59.68% COVERGROUP TYPES: 25
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/coverage/summary.txt b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/coverage/summary.txt new file mode 100644 index 0000000..1b3aa49 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/coverage/summary.txt
@@ -0,0 +1,43 @@ +This coverage created by Imperas using Mentor Questa simulator and SystemVerilog UVM coverage from github.com/google/riscv-dv + + Coverpoint c_lw_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint c_lw_cg::cp_rd 75.00% 100 Uncovered + Coverpoint c_lwsp_cg::cp_rd 0.00% 100 ZERO + Coverpoint c_sw_cg::cp_rs1 50.00% 100 Uncovered + Coverpoint c_sw_cg::cp_rs2 100.00% 100 Covered + Coverpoint c_swsp_cg::cp_rs2 0.00% 100 ZERO + Coverpoint c_addi4spn_cg::cp_imm_sign 0.00% 100 ZERO + Coverpoint c_addi4spn_cg::cp_rd 0.00% 100 ZERO + Coverpoint c_addi_cg::cp_rd 81.25% 100 Uncovered + Coverpoint c_addi_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint c_addi16sp_cg::cp_imm_sign 0.00% 100 ZERO + Coverpoint c_li_cg::cp_rd 84.37% 100 Uncovered + Coverpoint c_li_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint c_lui_cg::cp_rd 78.12% 100 Uncovered + Coverpoint c_sub_cg::cp_rd 87.50% 100 Uncovered + Coverpoint c_sub_cg::cp_rs2 87.50% 100 Uncovered + Coverpoint c_add_cg::cp_rs2 75.00% 100 Uncovered + Coverpoint c_add_cg::cp_rd 75.00% 100 Uncovered + Coverpoint c_add_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint c_mv_cg::cp_rs2 21.87% 100 Uncovered + Coverpoint c_mv_cg::cp_rd 21.87% 100 Uncovered + Coverpoint c_mv_cg::cp_rs2_sign 100.00% 100 Covered + Coverpoint c_andi_cg::cp_rs1 87.50% 100 Uncovered + Coverpoint c_andi_cg::cp_imm_sign 100.00% 100 Covered + Coverpoint c_xor_cg::cp_rd 87.50% 100 Uncovered + Coverpoint c_xor_cg::cp_rs2 87.50% 100 Uncovered + Coverpoint c_or_cg::cp_rd 87.50% 100 Uncovered + Coverpoint c_or_cg::cp_rs2 87.50% 100 Uncovered + Coverpoint c_and_cg::cp_rd 87.50% 100 Uncovered + Coverpoint c_and_cg::cp_rs2 87.50% 100 Uncovered + Coverpoint c_beqz_cg::cp_rs1 62.50% 100 Uncovered + Coverpoint c_beqz_cg::cp_imm_sign 50.00% 100 Uncovered + Coverpoint c_bnez_cg::cp_rs1 75.00% 100 Uncovered + Coverpoint c_bnez_cg::cp_imm_sign 50.00% 100 Uncovered + Coverpoint c_srli_cg::cp_rs1 87.50% 100 Uncovered + Coverpoint c_srai_cg::cp_rs1 87.50% 100 Uncovered + Coverpoint c_slli_cg::cp_rd 78.12% 100 Uncovered + Coverpoint c_j_cg::cp_imm_sign 50.00% 100 Uncovered + Coverpoint c_jal_cg::cp_imm_sign 50.00% 100 Uncovered + Coverpoint c_jr_cg::cp_rs1 15.62% 100 Uncovered + Coverpoint c_jalr_cg::cp_rs1 15.62% 100 Uncovered
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/references/C-SWSP.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/references/C-SWSP.reference_output index cc38f2a..c672737 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/references/C-SWSP.reference_output +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/references/C-SWSP.reference_output
@@ -19,22 +19,22 @@ ffffffff ffffffff ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff -ffffffff 00007fff ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +ffffffff +00008000 00000000 00000000 00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/src/C-SWSP.S b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/src/C-SWSP.S index 7d7d818..5a9c7ed 100644 --- a/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/src/C-SWSP.S +++ b/sw/vendor/riscv_compliance/riscv-test-suite/rv32imc/src/C-SWSP.S
@@ -65,7 +65,7 @@ # address for test results la x1, test_3_res - TEST_CSWSP(test_data, x16, -0x1, 64, x1, 0) + TEST_CSWSP(test_data, x16, -0x1, 8, x1, 0) # --------------------------------------------------------------------------------------------- @@ -74,7 +74,7 @@ # address for test results la x1, test_4_res - TEST_CSWSP(test_data, x24, 0x7fff, 120, x1, 0) + TEST_CSWSP(test_data, x24, 0x7fff, 64, x1, 0) # --------------------------------------------------------------------------------------------- @@ -83,7 +83,7 @@ # address for test results la x1, test_5_res - TEST_CSWSP(test_data, x21, 0x8000, 252, x1, 0) + TEST_CSWSP(test_data, x21, 0x8000, 124, x1, 0) RVTEST_IO_WRITE_STR(x31, "Test End\n")
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/Makefile new file mode 100644 index 0000000..cc61314 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv64i -mabi=lp64)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/Makefrag new file mode 100644 index 0000000..aa74371 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/Makefrag
@@ -0,0 +1,43 @@ +# RISC-V Compliance Test RV64I Makefrag +# +# Copyright (c) 2017, Codasip Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Codasip Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Description: Makefrag for RV64I compliance tests + +rv64i_sc_tests = \ + SLLIW \ + SUBW \ + SRAW \ + SRLW \ + ADDW \ + ADDIW \ + SRAIW \ + SRLIW \ + SLLW \ + +rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) + +target_tests += $(rv64i_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/ADDIW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/ADDIW.reference_output new file mode 100644 index 0000000..9ff172f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/ADDIW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +000007ff +00000000 +fffff800 +00000000 +00000001 +00000000 +00000002 +00000000 +00000000 +00000000 +00000800 +00000000 +fffff801 +00000000 +ffffffff +00000000 +00000000 +00000000 +fffffffe +00000000 +000007fe +00000000 +fffff7ff +00000000 +ffffffff +00000000 +00000000 +00000000 +fffffffe +00000000 +000007fe +00000000 +fffff7ff +00000000 +00000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +000007ff +00000000 +fffff800 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/ADDW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/ADDW.reference_output new file mode 100644 index 0000000..430e580 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/ADDW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +00000001 +00000000 +00000002 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +00000000 +00000000 +fffffffe +00000000 +fffffffe +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +fffffffe +00000000 +fffffffe +00000000 +ffffffff +00000000 +00000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SLLIW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SLLIW.reference_output new file mode 100644 index 0000000..36f0eed --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SLLIW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000002 +00000000 +00008000 +00000000 +00010000 +00000000 +80000000 +00000000 +ffffffff +00000000 +fffffffe +00000000 +ffff8000 +00000000 +ffff0000 +00000000 +80000000 +00000000 +ffffffff +00000000 +fffffffe +00000000 +ffff8000 +00000000 +ffff0000 +00000000 +80000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SLLW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SLLW.reference_output new file mode 100644 index 0000000..fe46cb0 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SLLW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000002 +00000000 +80000000 +00000000 +80000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +fffffffe +00000000 +80000000 +00000000 +80000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +fffffffe +00000000 +80000000 +00000000 +80000000 +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRAIW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRAIW.reference_output new file mode 100644 index 0000000..6ab92cc --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRAIW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRAW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRAW.reference_output new file mode 100644 index 0000000..0ba2e9f --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRAW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRLIW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRLIW.reference_output new file mode 100644 index 0000000..8aee672 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRLIW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +7fffffff +00000000 +0001ffff +00000000 +0000ffff +00000000 +00000001 +00000000 +ffffffff +00000000 +7fffffff +00000000 +0001ffff +00000000 +0000ffff +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRLW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRLW.reference_output new file mode 100644 index 0000000..c940c0b --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SRLW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +7fffffff +00000000 +00000001 +00000000 +00000001 +00000000 +ffffffff +00000000 +ffffffff +00000000 +7fffffff +00000000 +00000001 +00000000 +00000001 +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SUBW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SUBW.reference_output new file mode 100644 index 0000000..bbb0d40 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/references/SUBW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +ffffffff +00000000 +00000001 +00000000 +00000001 +00000000 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000002 +00000000 +00000002 +00000000 +00000001 +00000000 +ffffffff +00000000 +fffffffe +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +fffffffe +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +00000000 +00000000 +ffffffff +00000000 +00000001 +00000000 +00000001 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/ADDIW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/ADDIW.S new file mode 100644 index 0000000..70ab1fa --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/ADDIW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64I-ADDIW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64I Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction ADDIW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_IMM_OP(addiw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_IMM_OP(addiw, x8, x9, 0x1, 0x0, 0x1, x2, 8) + TEST_IMM_OP(addiw, x11, x12, 0xffffffffffffffff, 0x0, -0x1, x2, 16) + TEST_IMM_OP(addiw, x13, x14, 0x7ff, 0x0, 0x7ff, x2, 24) + TEST_IMM_OP(addiw, x15, x16, 0xfffffffffffff800, 0x0, 0x800, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_IMM_OP(addiw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_IMM_OP(addiw, x19, x20, 0x2, 0x1, 0x1, x2, 8) + TEST_IMM_OP(addiw, x21, x22, 0, 0x1, -0x1, x2, 16) + TEST_IMM_OP(addiw, x23, x24, 0x800, 0x1, 0x7ff, x2, 24) + TEST_IMM_OP(addiw, x25, x26, 0xfffffffffffff801, 0x1, 0x800, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_IMM_OP(addiw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_IMM_OP(addiw, x29, x30, 0, -0x1, 0x1, x2, 8) + TEST_IMM_OP(addiw, x21, x3, 0xfffffffffffffffe, -0x1, -0x1, x2, 16) + TEST_IMM_OP(addiw, x4, x8, 0x7fe, -0x1, 0x7ff, x2, 24) + TEST_IMM_OP(addiw, x9, x11, 0xfffffffffffff7ff, -0x1, 0x800, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_IMM_OP(addiw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_IMM_OP(addiw, x14, x15, 0, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_IMM_OP(addiw, x16, x17, 0xfffffffffffffffe, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_IMM_OP(addiw, x18, x19, 0x7fe, 0x7fffffffffffffff, 0x7ff, x2, 24) + TEST_IMM_OP(addiw, x20, x21, 0xfffffffffffff7ff, 0x7fffffffffffffff, 0x800, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_IMM_OP(addiw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_IMM_OP(addiw, x24, x25, 0x1, 0x8000000000000000, 0x1, x2, 8) + TEST_IMM_OP(addiw, x26, x27, 0xffffffffffffffff, 0x8000000000000000, -0x1, x2, 16) + TEST_IMM_OP(addiw, x28, x29, 0x7ff, 0x8000000000000000, 0x7ff, x2, 24) + TEST_IMM_OP(addiw, x30, x21, 0xfffffffffffff800, 0x8000000000000000, 0x800, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/ADDW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/ADDW.S new file mode 100644 index 0000000..bc4f133 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/ADDW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64I-ADDW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64I Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction ADDW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_RR_SRC2(addw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_RR_SRC2(addw, x8, x9, 0x1, 0x0, 0x1, x2, 8) + TEST_RR_SRC2(addw, x11, x12, 0xffffffffffffffff, 0x0, -0x1, x2, 16) + TEST_RR_SRC2(addw, x13, x14, 0xffffffffffffffff, 0x0, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(addw, x15, x16, 0, 0x0, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_RR_SRC2(addw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_RR_SRC2(addw, x19, x20, 0x2, 0x1, 0x1, x2, 8) + TEST_RR_SRC2(addw, x21, x22, 0, 0x1, -0x1, x2, 16) + TEST_RR_SRC2(addw, x23, x24, 0, 0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(addw, x25, x26, 0x1, 0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_RR_SRC2(addw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_RR_SRC2(addw, x29, x30, 0, -0x1, 0x1, x2, 8) + TEST_RR_SRC2(addw, x21, x3, 0xfffffffffffffffe, -0x1, -0x1, x2, 16) + TEST_RR_SRC2(addw, x4, x8, 0xfffffffffffffffe, -0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(addw, x9, x11, 0xffffffffffffffff, -0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_RR_SRC2(addw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_RR_SRC2(addw, x14, x15, 0, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_RR_SRC2(addw, x16, x17, 0xfffffffffffffffe, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_RR_SRC2(addw, x18, x19, 0xfffffffffffffffe, 0x7fffffffffffffff, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(addw, x20, x21, 0xffffffffffffffff, 0x7fffffffffffffff, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_RR_SRC2(addw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_RR_SRC2(addw, x24, x25, 0x1, 0x8000000000000000, 0x1, x2, 8) + TEST_RR_SRC2(addw, x26, x27, 0xffffffffffffffff, 0x8000000000000000, -0x1, x2, 16) + TEST_RR_SRC2(addw, x28, x29, 0xffffffffffffffff, 0x8000000000000000, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(addw, x30, x21, 0, 0x8000000000000000, 0x8000000000000000, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SLLIW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SLLIW.S new file mode 100644 index 0000000..7762b96 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SLLIW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64I-SLLIW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64I Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction SLLIW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_IMM_OP(slliw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_IMM_OP(slliw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_IMM_OP(slliw, x11, x12, 0, 0x0, 0xf, x2, 16) + TEST_IMM_OP(slliw, x13, x14, 0, 0x0, 0x10, x2, 24) + TEST_IMM_OP(slliw, x15, x16, 0, 0x0, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_IMM_OP(slliw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_IMM_OP(slliw, x19, x20, 0x2, 0x1, 0x1, x2, 8) + TEST_IMM_OP(slliw, x21, x22, 0x8000, 0x1, 0xf, x2, 16) + TEST_IMM_OP(slliw, x23, x24, 0x10000, 0x1, 0x10, x2, 24) + TEST_IMM_OP(slliw, x25, x26, 0xffffffff80000000, 0x1, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_IMM_OP(slliw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_IMM_OP(slliw, x29, x30, 0xfffffffffffffffe, -0x1, 0x1, x2, 8) + TEST_IMM_OP(slliw, x21, x3, 0xffffffffffff8000, -0x1, 0xf, x2, 16) + TEST_IMM_OP(slliw, x4, x8, 0xffffffffffff0000, -0x1, 0x10, x2, 24) + TEST_IMM_OP(slliw, x9, x11, 0xffffffff80000000, -0x1, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_IMM_OP(slliw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_IMM_OP(slliw, x14, x15, 0xfffffffffffffffe, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_IMM_OP(slliw, x16, x17, 0xffffffffffff8000, 0x7fffffffffffffff, 0xf, x2, 16) + TEST_IMM_OP(slliw, x18, x19, 0xffffffffffff0000, 0x7fffffffffffffff, 0x10, x2, 24) + TEST_IMM_OP(slliw, x20, x21, 0xffffffff80000000, 0x7fffffffffffffff, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_IMM_OP(slliw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_IMM_OP(slliw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_IMM_OP(slliw, x26, x27, 0, 0x8000000000000000, 0xf, x2, 16) + TEST_IMM_OP(slliw, x28, x29, 0, 0x8000000000000000, 0x10, x2, 24) + TEST_IMM_OP(slliw, x30, x21, 0, 0x8000000000000000, 0x1f, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SLLW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SLLW.S new file mode 100644 index 0000000..eb8eab8 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SLLW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64I-SLLW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64I Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction SLLW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_RR_SRC2(sllw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_RR_SRC2(sllw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_RR_SRC2(sllw, x11, x12, 0, 0x0, -0x1, x2, 16) + TEST_RR_SRC2(sllw, x13, x14, 0, 0x0, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sllw, x15, x16, 0, 0x0, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_RR_SRC2(sllw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_RR_SRC2(sllw, x19, x20, 0x2, 0x1, 0x1, x2, 8) + TEST_RR_SRC2(sllw, x21, x22, 0xffffffff80000000, 0x1, -0x1, x2, 16) + TEST_RR_SRC2(sllw, x23, x24, 0xffffffff80000000, 0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sllw, x25, x26, 0x1, 0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_RR_SRC2(sllw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_RR_SRC2(sllw, x29, x30, 0xfffffffffffffffe, -0x1, 0x1, x2, 8) + TEST_RR_SRC2(sllw, x21, x3, 0xffffffff80000000, -0x1, -0x1, x2, 16) + TEST_RR_SRC2(sllw, x4, x8, 0xffffffff80000000, -0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sllw, x9, x11, 0xffffffffffffffff, -0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_RR_SRC2(sllw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_RR_SRC2(sllw, x14, x15, 0xfffffffffffffffe, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_RR_SRC2(sllw, x16, x17, 0xffffffff80000000, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_RR_SRC2(sllw, x18, x19, 0xffffffff80000000, 0x7fffffffffffffff, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sllw, x20, x21, 0xffffffffffffffff, 0x7fffffffffffffff, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_RR_SRC2(sllw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_RR_SRC2(sllw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_RR_SRC2(sllw, x26, x27, 0, 0x8000000000000000, -0x1, x2, 16) + TEST_RR_SRC2(sllw, x28, x29, 0, 0x8000000000000000, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sllw, x30, x21, 0, 0x8000000000000000, 0x8000000000000000, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRAIW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRAIW.S new file mode 100644 index 0000000..459fa88 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRAIW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64I-SRAIW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64I Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction SRAIW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_IMM_OP(sraiw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_IMM_OP(sraiw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_IMM_OP(sraiw, x11, x12, 0, 0x0, 0xf, x2, 16) + TEST_IMM_OP(sraiw, x13, x14, 0, 0x0, 0x10, x2, 24) + TEST_IMM_OP(sraiw, x15, x16, 0, 0x0, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_IMM_OP(sraiw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_IMM_OP(sraiw, x19, x20, 0, 0x1, 0x1, x2, 8) + TEST_IMM_OP(sraiw, x21, x22, 0, 0x1, 0xf, x2, 16) + TEST_IMM_OP(sraiw, x23, x24, 0, 0x1, 0x10, x2, 24) + TEST_IMM_OP(sraiw, x25, x26, 0, 0x1, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_IMM_OP(sraiw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_IMM_OP(sraiw, x29, x30, 0xffffffffffffffff, -0x1, 0x1, x2, 8) + TEST_IMM_OP(sraiw, x21, x3, 0xffffffffffffffff, -0x1, 0xf, x2, 16) + TEST_IMM_OP(sraiw, x4, x8, 0xffffffffffffffff, -0x1, 0x10, x2, 24) + TEST_IMM_OP(sraiw, x9, x11, 0xffffffffffffffff, -0x1, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_IMM_OP(sraiw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_IMM_OP(sraiw, x14, x15, 0xffffffffffffffff, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_IMM_OP(sraiw, x16, x17, 0xffffffffffffffff, 0x7fffffffffffffff, 0xf, x2, 16) + TEST_IMM_OP(sraiw, x18, x19, 0xffffffffffffffff, 0x7fffffffffffffff, 0x10, x2, 24) + TEST_IMM_OP(sraiw, x20, x21, 0xffffffffffffffff, 0x7fffffffffffffff, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_IMM_OP(sraiw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_IMM_OP(sraiw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_IMM_OP(sraiw, x26, x27, 0, 0x8000000000000000, 0xf, x2, 16) + TEST_IMM_OP(sraiw, x28, x29, 0, 0x8000000000000000, 0x10, x2, 24) + TEST_IMM_OP(sraiw, x30, x21, 0, 0x8000000000000000, 0x1f, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRAW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRAW.S new file mode 100644 index 0000000..5e12cf1 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRAW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64I-SRAW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64I Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction SRAW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_RR_SRC2(sraw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_RR_SRC2(sraw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_RR_SRC2(sraw, x11, x12, 0, 0x0, -0x1, x2, 16) + TEST_RR_SRC2(sraw, x13, x14, 0, 0x0, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sraw, x15, x16, 0, 0x0, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_RR_SRC2(sraw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_RR_SRC2(sraw, x19, x20, 0, 0x1, 0x1, x2, 8) + TEST_RR_SRC2(sraw, x21, x22, 0, 0x1, -0x1, x2, 16) + TEST_RR_SRC2(sraw, x23, x24, 0, 0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sraw, x25, x26, 0x1, 0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_RR_SRC2(sraw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_RR_SRC2(sraw, x29, x30, 0xffffffffffffffff, -0x1, 0x1, x2, 8) + TEST_RR_SRC2(sraw, x21, x3, 0xffffffffffffffff, -0x1, -0x1, x2, 16) + TEST_RR_SRC2(sraw, x4, x8, 0xffffffffffffffff, -0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sraw, x9, x11, 0xffffffffffffffff, -0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_RR_SRC2(sraw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_RR_SRC2(sraw, x14, x15, 0xffffffffffffffff, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_RR_SRC2(sraw, x16, x17, 0xffffffffffffffff, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_RR_SRC2(sraw, x18, x19, 0xffffffffffffffff, 0x7fffffffffffffff, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sraw, x20, x21, 0xffffffffffffffff, 0x7fffffffffffffff, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_RR_SRC2(sraw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_RR_SRC2(sraw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_RR_SRC2(sraw, x26, x27, 0, 0x8000000000000000, -0x1, x2, 16) + TEST_RR_SRC2(sraw, x28, x29, 0, 0x8000000000000000, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(sraw, x30, x21, 0, 0x8000000000000000, 0x8000000000000000, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRLIW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRLIW.S new file mode 100644 index 0000000..bcb9caf --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRLIW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64I-SRLIW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64I Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction SRLIW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_IMM_OP(srliw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_IMM_OP(srliw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_IMM_OP(srliw, x11, x12, 0, 0x0, 0xf, x2, 16) + TEST_IMM_OP(srliw, x13, x14, 0, 0x0, 0x10, x2, 24) + TEST_IMM_OP(srliw, x15, x16, 0, 0x0, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_IMM_OP(srliw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_IMM_OP(srliw, x19, x20, 0, 0x1, 0x1, x2, 8) + TEST_IMM_OP(srliw, x21, x22, 0, 0x1, 0xf, x2, 16) + TEST_IMM_OP(srliw, x23, x24, 0, 0x1, 0x10, x2, 24) + TEST_IMM_OP(srliw, x25, x26, 0, 0x1, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_IMM_OP(srliw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_IMM_OP(srliw, x29, x30, 0x7fffffff, -0x1, 0x1, x2, 8) + TEST_IMM_OP(srliw, x21, x3, 0x1ffff, -0x1, 0xf, x2, 16) + TEST_IMM_OP(srliw, x4, x8, 0xffff, -0x1, 0x10, x2, 24) + TEST_IMM_OP(srliw, x9, x11, 0x1, -0x1, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_IMM_OP(srliw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_IMM_OP(srliw, x14, x15, 0x7fffffff, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_IMM_OP(srliw, x16, x17, 0x1ffff, 0x7fffffffffffffff, 0xf, x2, 16) + TEST_IMM_OP(srliw, x18, x19, 0xffff, 0x7fffffffffffffff, 0x10, x2, 24) + TEST_IMM_OP(srliw, x20, x21, 0x1, 0x7fffffffffffffff, 0x1f, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_IMM_OP(srliw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_IMM_OP(srliw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_IMM_OP(srliw, x26, x27, 0, 0x8000000000000000, 0xf, x2, 16) + TEST_IMM_OP(srliw, x28, x29, 0, 0x8000000000000000, 0x10, x2, 24) + TEST_IMM_OP(srliw, x30, x21, 0, 0x8000000000000000, 0x1f, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRLW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRLW.S new file mode 100644 index 0000000..9f04e64 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SRLW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64I-SRLW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64I Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction SRLW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_RR_SRC2(srlw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_RR_SRC2(srlw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_RR_SRC2(srlw, x11, x12, 0, 0x0, -0x1, x2, 16) + TEST_RR_SRC2(srlw, x13, x14, 0, 0x0, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(srlw, x15, x16, 0, 0x0, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_RR_SRC2(srlw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_RR_SRC2(srlw, x19, x20, 0, 0x1, 0x1, x2, 8) + TEST_RR_SRC2(srlw, x21, x22, 0, 0x1, -0x1, x2, 16) + TEST_RR_SRC2(srlw, x23, x24, 0, 0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(srlw, x25, x26, 0x1, 0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_RR_SRC2(srlw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_RR_SRC2(srlw, x29, x30, 0x7fffffff, -0x1, 0x1, x2, 8) + TEST_RR_SRC2(srlw, x21, x3, 0x1, -0x1, -0x1, x2, 16) + TEST_RR_SRC2(srlw, x4, x8, 0x1, -0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(srlw, x9, x11, 0xffffffffffffffff, -0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_RR_SRC2(srlw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_RR_SRC2(srlw, x14, x15, 0x7fffffff, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_RR_SRC2(srlw, x16, x17, 0x1, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_RR_SRC2(srlw, x18, x19, 0x1, 0x7fffffffffffffff, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(srlw, x20, x21, 0xffffffffffffffff, 0x7fffffffffffffff, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_RR_SRC2(srlw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_RR_SRC2(srlw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_RR_SRC2(srlw, x26, x27, 0, 0x8000000000000000, -0x1, x2, 16) + TEST_RR_SRC2(srlw, x28, x29, 0, 0x8000000000000000, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(srlw, x30, x21, 0, 0x8000000000000000, 0x8000000000000000, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SUBW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SUBW.S new file mode 100644 index 0000000..bd36f50 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64i/src/SUBW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64I-SUBW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64I Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction SUBW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_RR_SRC2(subw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_RR_SRC2(subw, x8, x9, 0xffffffffffffffff, 0x0, 0x1, x2, 8) + TEST_RR_SRC2(subw, x11, x12, 0x1, 0x0, -0x1, x2, 16) + TEST_RR_SRC2(subw, x13, x14, 0x1, 0x0, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(subw, x15, x16, 0, 0x0, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_RR_SRC2(subw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_RR_SRC2(subw, x19, x20, 0, 0x1, 0x1, x2, 8) + TEST_RR_SRC2(subw, x21, x22, 0x2, 0x1, -0x1, x2, 16) + TEST_RR_SRC2(subw, x23, x24, 0x2, 0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(subw, x25, x26, 0x1, 0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_RR_SRC2(subw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_RR_SRC2(subw, x29, x30, 0xfffffffffffffffe, -0x1, 0x1, x2, 8) + TEST_RR_SRC2(subw, x21, x3, 0, -0x1, -0x1, x2, 16) + TEST_RR_SRC2(subw, x4, x8, 0, -0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(subw, x9, x11, 0xffffffffffffffff, -0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_RR_SRC2(subw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_RR_SRC2(subw, x14, x15, 0xfffffffffffffffe, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_RR_SRC2(subw, x16, x17, 0, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_RR_SRC2(subw, x18, x19, 0, 0x7fffffffffffffff, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(subw, x20, x21, 0xffffffffffffffff, 0x7fffffffffffffff, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_RR_SRC2(subw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_RR_SRC2(subw, x24, x25, 0xffffffffffffffff, 0x8000000000000000, 0x1, x2, 8) + TEST_RR_SRC2(subw, x26, x27, 0x1, 0x8000000000000000, -0x1, x2, 16) + TEST_RR_SRC2(subw, x28, x29, 0x1, 0x8000000000000000, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(subw, x30, x21, 0, 0x8000000000000000, 0x8000000000000000, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/Makefile b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/Makefile new file mode 100644 index 0000000..7f248f1 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/Makefile
@@ -0,0 +1,59 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +act_dir := . +src_dir := $(act_dir)/src +work_dir := $(ROOTDIR)/work +work_dir_isa := $(work_dir)/$(RISCV_ISA) + +include $(act_dir)/Makefrag +ifneq ($(RISCV_TEST),) + target_tests = $(RISCV_TEST).elf +endif + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +vpath %.S $(act_dir) + +INCLUDE=$(TARGETDIR)/$(RISCV_TARGET)/device/$(RISCV_DEVICE)/Makefile.include +ifeq ($(wildcard $(INCLUDE)),) + $(error Cannot find '$(INCLUDE)`. Check that RISCV_TARGET and RISCV_DEVICE are set correctly.) +endif +-include $(INCLUDE) + +#------------------------------------------------------------ +# Build and run assembly tests + +%.log: %.elf + $(V) echo "Execute $(@)" + $(V) $(RUN_TARGET) + + +define compile_template + +$(work_dir_isa)/%.elf: $(src_dir)/%.S + $(V) echo "Compile $$(@)" + @mkdir -p $$(@D) + $(V) $(COMPILE_TARGET) + +.PRECIOUS: $(work_dir_isa)/%.elf + +endef + +$(eval $(call compile_template,-march=rv64im -mabi=lp64)) + +target_elf = $(foreach e,$(target_tests),$(work_dir_isa)/$(e)) +target_log = $(patsubst %.elf,%.log,$(target_elf)) + +run: $(target_log) + +#------------------------------------------------------------ +# Clean up + +clean: + rm -rf $(work_dir)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/Makefrag b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/Makefrag new file mode 100644 index 0000000..f2a1289 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/Makefrag
@@ -0,0 +1,38 @@ +# RISC-V Compliance Test RV64im Makefrag +# +# Copyright (c) 2017, Codasip Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Codasip Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Codasip Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Description: Makefrag for RV64im compliance tests + +rv64im_sc_tests = \ + MULW \ + REMW \ + REMUW \ + DIVW \ + +rv64im_tests = $(addsuffix .elf, $(rv64im_sc_tests)) + +target_tests += $(rv64im_tests)
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/DIVW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/DIVW.reference_output new file mode 100644 index 0000000..5e5d67d --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/DIVW.reference_output
@@ -0,0 +1,100 @@ +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000001 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000001 +00000000 +00000001 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000001 +00000000 +00000001 +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/MULW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/MULW.reference_output new file mode 100644 index 0000000..52f3670 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/MULW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +00000001 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +00000001 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/REMUW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/REMUW.reference_output new file mode 100644 index 0000000..6aed0a5 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/REMUW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000001 +00000000 +00000001 +00000000 +00000001 +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/REMW.reference_output b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/REMW.reference_output new file mode 100644 index 0000000..0990cb9 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/references/REMW.reference_output
@@ -0,0 +1,100 @@ +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000 +ffffffff +00000000
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/DIVW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/DIVW.S new file mode 100644 index 0000000..f472502 --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/DIVW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64IM-DIVW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64IM Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction DIVW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_RR_SRC2(divw, x3, x4, 0xffffffffffffffff, 0x0, 0x0, x2, 0) + TEST_RR_SRC2(divw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_RR_SRC2(divw, x11, x12, 0, 0x0, -0x1, x2, 16) + TEST_RR_SRC2(divw, x13, x14, 0, 0x0, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(divw, x15, x16, 0xffffffffffffffff, 0x0, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_RR_SRC2(divw, x17, x18, 0xffffffffffffffff, 0x1, 0x0, x2, 0) + TEST_RR_SRC2(divw, x19, x20, 0x1, 0x1, 0x1, x2, 8) + TEST_RR_SRC2(divw, x21, x22, 0xffffffffffffffff, 0x1, -0x1, x2, 16) + TEST_RR_SRC2(divw, x23, x24, 0xffffffffffffffff, 0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(divw, x25, x26, 0xffffffffffffffff, 0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_RR_SRC2(divw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_RR_SRC2(divw, x29, x30, 0xffffffffffffffff, -0x1, 0x1, x2, 8) + TEST_RR_SRC2(divw, x21, x3, 0x1, -0x1, -0x1, x2, 16) + TEST_RR_SRC2(divw, x4, x8, 0x1, -0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(divw, x9, x11, 0xffffffffffffffff, -0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_RR_SRC2(divw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_RR_SRC2(divw, x14, x15, 0xffffffffffffffff, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_RR_SRC2(divw, x16, x17, 0x1, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_RR_SRC2(divw, x18, x19, 0x1, 0x7fffffffffffffff, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(divw, x20, x21, 0xffffffffffffffff, 0x7fffffffffffffff, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_RR_SRC2(divw, x22, x23, 0xffffffffffffffff, 0x8000000000000000, 0x0, x2, 0) + TEST_RR_SRC2(divw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_RR_SRC2(divw, x26, x27, 0, 0x8000000000000000, -0x1, x2, 16) + TEST_RR_SRC2(divw, x28, x29, 0, 0x8000000000000000, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(divw, x30, x21, 0xffffffffffffffff, 0x8000000000000000, 0x8000000000000000, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/MULW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/MULW.S new file mode 100644 index 0000000..491d87e --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/MULW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64IM-MULW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64IM Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction MULW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_RR_SRC2(mulw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_RR_SRC2(mulw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_RR_SRC2(mulw, x11, x12, 0, 0x0, -0x1, x2, 16) + TEST_RR_SRC2(mulw, x13, x14, 0, 0x0, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(mulw, x15, x16, 0, 0x0, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_RR_SRC2(mulw, x17, x18, 0, 0x1, 0x0, x2, 0) + TEST_RR_SRC2(mulw, x19, x20, 0x1, 0x1, 0x1, x2, 8) + TEST_RR_SRC2(mulw, x21, x22, 0xffffffffffffffff, 0x1, -0x1, x2, 16) + TEST_RR_SRC2(mulw, x23, x24, 0xffffffffffffffff, 0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(mulw, x25, x26, 0, 0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_RR_SRC2(mulw, x27, x28, 0, -0x1, 0x0, x2, 0) + TEST_RR_SRC2(mulw, x29, x30, 0xffffffffffffffff, -0x1, 0x1, x2, 8) + TEST_RR_SRC2(mulw, x21, x3, 0x1, -0x1, -0x1, x2, 16) + TEST_RR_SRC2(mulw, x4, x8, 0x1, -0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(mulw, x9, x11, 0, -0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_RR_SRC2(mulw, x12, x13, 0, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_RR_SRC2(mulw, x14, x15, 0xffffffffffffffff, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_RR_SRC2(mulw, x16, x17, 0x1, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_RR_SRC2(mulw, x18, x19, 0x1, 0x7fffffffffffffff, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(mulw, x20, x21, 0, 0x7fffffffffffffff, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_RR_SRC2(mulw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_RR_SRC2(mulw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_RR_SRC2(mulw, x26, x27, 0, 0x8000000000000000, -0x1, x2, 16) + TEST_RR_SRC2(mulw, x28, x29, 0, 0x8000000000000000, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(mulw, x30, x21, 0, 0x8000000000000000, 0x8000000000000000, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/REMUW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/REMUW.S new file mode 100644 index 0000000..c8b217c --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/REMUW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64IM-REMUW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64IM Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction REMUW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_RR_SRC2(remuw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_RR_SRC2(remuw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_RR_SRC2(remuw, x11, x12, 0, 0x0, -0x1, x2, 16) + TEST_RR_SRC2(remuw, x13, x14, 0, 0x0, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remuw, x15, x16, 0, 0x0, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_RR_SRC2(remuw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_RR_SRC2(remuw, x19, x20, 0, 0x1, 0x1, x2, 8) + TEST_RR_SRC2(remuw, x21, x22, 0x1, 0x1, -0x1, x2, 16) + TEST_RR_SRC2(remuw, x23, x24, 0x1, 0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remuw, x25, x26, 0x1, 0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_RR_SRC2(remuw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_RR_SRC2(remuw, x29, x30, 0, -0x1, 0x1, x2, 8) + TEST_RR_SRC2(remuw, x21, x3, 0, -0x1, -0x1, x2, 16) + TEST_RR_SRC2(remuw, x4, x8, 0, -0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remuw, x9, x11, 0xffffffffffffffff, -0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_RR_SRC2(remuw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_RR_SRC2(remuw, x14, x15, 0, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_RR_SRC2(remuw, x16, x17, 0, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_RR_SRC2(remuw, x18, x19, 0, 0x7fffffffffffffff, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remuw, x20, x21, 0xffffffffffffffff, 0x7fffffffffffffff, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_RR_SRC2(remuw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_RR_SRC2(remuw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_RR_SRC2(remuw, x26, x27, 0, 0x8000000000000000, -0x1, x2, 16) + TEST_RR_SRC2(remuw, x28, x29, 0, 0x8000000000000000, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remuw, x30, x21, 0, 0x8000000000000000, 0x8000000000000000, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END
diff --git a/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/REMW.S b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/REMW.S new file mode 100644 index 0000000..680a8da --- /dev/null +++ b/sw/vendor/riscv_compliance/riscv-test-suite/wip/rv64im/src/REMW.S
@@ -0,0 +1,142 @@ +# RISC-V Compliance Test RV64IM-REMW-01 +# +# Copyright (c) 2018, Imperas Software Ltd. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the Imperas Software Ltd. nor the +# names of its contributors may be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL Imperas Software Ltd. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Specification: RV64IM Base Integer Instruction Set, Version 2.0 +# Description: Testing instruction REMW. + +#include "test_macros.h" +#include "compliance_test.h" +#include "compliance_io.h" + +RV_COMPLIANCE_RV32M + +RV_COMPLIANCE_CODE_BEGIN + + RVTEST_IO_INIT + RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000) + RVTEST_IO_WRITE_STR(x31, "Test Begin Reserved regs ra(x1) a0(x10) t0(x5)\n") + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 1 - corner cases\n") + + # address for test results + la x2, test_1_res + + TEST_RR_SRC2(remw, x3, x4, 0, 0x0, 0x0, x2, 0) + TEST_RR_SRC2(remw, x8, x9, 0, 0x0, 0x1, x2, 8) + TEST_RR_SRC2(remw, x11, x12, 0, 0x0, -0x1, x2, 16) + TEST_RR_SRC2(remw, x13, x14, 0, 0x0, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remw, x15, x16, 0, 0x0, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 2 - corner cases\n") + + # address for test results + la x2, test_2_res + + TEST_RR_SRC2(remw, x17, x18, 0x1, 0x1, 0x0, x2, 0) + TEST_RR_SRC2(remw, x19, x20, 0, 0x1, 0x1, x2, 8) + TEST_RR_SRC2(remw, x21, x22, 0, 0x1, -0x1, x2, 16) + TEST_RR_SRC2(remw, x23, x24, 0, 0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remw, x25, x26, 0x1, 0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 3 - corner cases\n") + + # address for test results + la x2, test_3_res + + TEST_RR_SRC2(remw, x27, x28, 0xffffffffffffffff, -0x1, 0x0, x2, 0) + TEST_RR_SRC2(remw, x29, x30, 0, -0x1, 0x1, x2, 8) + TEST_RR_SRC2(remw, x21, x3, 0, -0x1, -0x1, x2, 16) + TEST_RR_SRC2(remw, x4, x8, 0, -0x1, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remw, x9, x11, 0xffffffffffffffff, -0x1, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 4 - corner cases\n") + + # address for test results + la x2, test_4_res + + TEST_RR_SRC2(remw, x12, x13, 0xffffffffffffffff, 0x7fffffffffffffff, 0x0, x2, 0) + TEST_RR_SRC2(remw, x14, x15, 0, 0x7fffffffffffffff, 0x1, x2, 8) + TEST_RR_SRC2(remw, x16, x17, 0, 0x7fffffffffffffff, -0x1, x2, 16) + TEST_RR_SRC2(remw, x18, x19, 0, 0x7fffffffffffffff, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remw, x20, x21, 0xffffffffffffffff, 0x7fffffffffffffff, 0x8000000000000000, x2, 32) + + # --------------------------------------------------------------------------------------------- + + RVTEST_IO_WRITE_STR(x31, "# Test number 5 - corner cases\n") + + # address for test results + la x2, test_5_res + + TEST_RR_SRC2(remw, x22, x23, 0, 0x8000000000000000, 0x0, x2, 0) + TEST_RR_SRC2(remw, x24, x25, 0, 0x8000000000000000, 0x1, x2, 8) + TEST_RR_SRC2(remw, x26, x27, 0, 0x8000000000000000, -0x1, x2, 16) + TEST_RR_SRC2(remw, x28, x29, 0, 0x8000000000000000, 0x7fffffffffffffff, x2, 24) + TEST_RR_SRC2(remw, x30, x21, 0, 0x8000000000000000, 0x8000000000000000, x2, 32) + + RVTEST_IO_WRITE_STR(x31, "Test End\n") + + # --------------------------------------------------------------------------------------------- + + RV_COMPLIANCE_HALT + +RV_COMPLIANCE_CODE_END + +# Input data section. + .data + +# Output data section. +RV_COMPLIANCE_DATA_BEGIN +test_1_res: + .fill 5, 8, -1 +test_2_res: + .fill 5, 8, -1 +test_3_res: + .fill 5, 8, -1 +test_4_res: + .fill 5, 8, -1 +test_5_res: + .fill 5, 8, -1 +test_6_res: + .fill 5, 8, -1 +test_7_res: + .fill 5, 8, -1 +test_8_res: + .fill 5, 8, -1 +test_9_res: + .fill 5, 8, -1 +test_10_res: + .fill 5, 8, -1 + +RV_COMPLIANCE_DATA_END