[pinmux] Wire up integrity alert
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/pinmux/data/pinmux.hjson b/hw/ip/pinmux/data/pinmux.hjson
index a8b5abf..94e8a84 100644
--- a/hw/ip/pinmux/data/pinmux.hjson
+++ b/hw/ip/pinmux/data/pinmux.hjson
@@ -19,6 +19,14 @@
regwidth: "32",
scan: "true",
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the PINMUX unit.
+ '''
+ }
+ ],
+
wakeup_list: [
{ name: "aon_wkup_req",
desc: "pin wake request"
@@ -71,6 +79,14 @@
package: "pinmux_pkg",
default: "'0"
}
+ // DFT indication to stop tap strap sampling
+ { struct: "logic",
+ type: "uni",
+ name: "dft_hold_tap_sel",
+ act: "rcv",
+ package: "",
+ default: "'0"
+ }
// Define pwr mgr <-> pinmux signals
{ struct: "logic",
type: "uni",
diff --git a/hw/ip/pinmux/data/pinmux.hjson.tpl b/hw/ip/pinmux/data/pinmux.hjson.tpl
index 62ce49d..6f37f4c 100644
--- a/hw/ip/pinmux/data/pinmux.hjson.tpl
+++ b/hw/ip/pinmux/data/pinmux.hjson.tpl
@@ -31,6 +31,14 @@
regwidth: "32",
scan: "true",
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the PINMUX unit.
+ '''
+ }
+ ],
+
wakeup_list: [
{ name: "aon_wkup_req",
desc: "pin wake request"
diff --git a/hw/ip/pinmux/rtl/pinmux.sv b/hw/ip/pinmux/rtl/pinmux.sv
index 3512d43..714e740 100644
--- a/hw/ip/pinmux/rtl/pinmux.sv
+++ b/hw/ip/pinmux/rtl/pinmux.sv
@@ -14,7 +14,8 @@
#(
// Taget-specific pinmux configuration passed down from the
// target-specific top-level.
- parameter target_cfg_t TargetCfg = DefaultTargetCfg
+ parameter target_cfg_t TargetCfg = DefaultTargetCfg,
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
) (
input clk_i,
input rst_ni,
@@ -54,6 +55,9 @@
// Bus Interface (device)
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
+ // Alerts
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
// Muxed Peripheral side
input [NMioPeriphOut-1:0] periph_to_mio_i,
input [NMioPeriphOut-1:0] periph_to_mio_oe_i,
@@ -79,6 +83,7 @@
// Regfile Breakout and Mapping //
//////////////////////////////////
+ logic [NumAlerts-1:0] alert_test, alerts;
pinmux_reg2hw_t reg2hw;
pinmux_hw2reg_t hw2reg;
@@ -89,10 +94,35 @@
.tl_o ,
.reg2hw ,
.hw2reg ,
- .intg_err_o(),
+ .intg_err_o(alerts[0]),
.devmode_i(1'b1)
);
+ ////////////
+ // Alerts //
+ ////////////
+
+ assign alert_test = {
+ reg2hw.alert_test.q &
+ reg2hw.alert_test.qe
+ };
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(1'b1)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i ( alert_test[i] ),
+ .alert_req_i ( alerts[0] ),
+ .alert_ack_o ( ),
+ .alert_state_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
/////////////////////////////
// Pad attribute registers //
/////////////////////////////
@@ -412,6 +442,7 @@
`ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
`ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
+ `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o)
// `ASSERT_KNOWN(MioToPeriphKnownO_A, mio_to_periph_o)
`ASSERT_KNOWN(MioOeKnownO_A, mio_oe_o)
// `ASSERT_KNOWN(DioToPeriphKnownO_A, dio_to_periph_o)
diff --git a/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv b/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv
index 4efbdcc..5a8bd10 100644
--- a/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv
+++ b/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv
@@ -14,6 +14,7 @@
parameter int NDioPads = 16;
parameter int NWkupDetect = 8;
parameter int WkupCntWidth = 8;
+ parameter int NumAlerts = 1;
// Address widths within the block
parameter int BlockAw = 11;
@@ -23,6 +24,11 @@
////////////////////////////
typedef struct packed {
+ logic q;
+ logic qe;
+ } pinmux_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
logic [5:0] q;
} pinmux_reg2hw_mio_periph_insel_mreg_t;
@@ -117,6 +123,7 @@
// Register -> HW type
typedef struct packed {
+ pinmux_reg2hw_alert_test_reg_t alert_test; // [1431:1430]
pinmux_reg2hw_mio_periph_insel_mreg_t [32:0] mio_periph_insel; // [1429:1232]
pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [1231:1040]
pinmux_reg2hw_mio_pad_attr_mreg_t [31:0] mio_pad_attr; // [1039:592]
@@ -144,421 +151,424 @@
} pinmux_hw2reg_t;
// Register offsets
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET = 11'h 0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET = 11'h 4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET = 11'h 8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET = 11'h c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET = 11'h 10;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET = 11'h 14;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET = 11'h 18;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET = 11'h 1c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET = 11'h 20;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET = 11'h 24;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET = 11'h 28;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET = 11'h 2c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET = 11'h 30;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET = 11'h 34;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET = 11'h 38;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET = 11'h 3c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET = 11'h 40;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET = 11'h 44;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET = 11'h 48;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET = 11'h 4c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET = 11'h 50;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET = 11'h 54;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET = 11'h 58;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET = 11'h 5c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET = 11'h 60;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET = 11'h 64;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET = 11'h 68;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET = 11'h 6c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET = 11'h 70;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET = 11'h 74;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET = 11'h 78;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET = 11'h 7c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET = 11'h 80;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 11'h 84;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 11'h 88;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 11'h 8c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 11'h 90;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 11'h 94;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 11'h 98;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 11'h 9c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 11'h a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 11'h a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 11'h a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 11'h ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 11'h b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 11'h b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 11'h b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 11'h bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 11'h c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 11'h c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 11'h c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 11'h cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 11'h d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 11'h d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 11'h d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 11'h dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 11'h e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 11'h e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 11'h e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 11'h ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 11'h f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 11'h f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 11'h f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 11'h fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 11'h 100;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 11'h 104;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 11'h 108;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 11'h 10c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 11'h 110;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 11'h 114;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 11'h 118;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 11'h 11c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 11'h 120;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 11'h 124;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 11'h 128;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 11'h 12c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 11'h 130;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 11'h 134;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 11'h 138;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 11'h 13c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 11'h 140;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 11'h 144;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 11'h 148;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 11'h 14c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 11'h 150;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 11'h 154;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 11'h 158;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 11'h 15c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 11'h 160;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 11'h 164;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 11'h 168;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 11'h 16c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 11'h 170;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 11'h 174;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 11'h 178;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 11'h 17c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 11'h 180;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 11'h 184;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 11'h 188;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 11'h 18c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 11'h 190;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 11'h 194;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 11'h 198;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 11'h 19c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 11'h 1a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 11'h 1a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 11'h 1a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 11'h 1ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 11'h 1b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 11'h 1b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 11'h 1b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 11'h 1bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 11'h 1c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 11'h 1c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 11'h 1c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 11'h 1cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 11'h 1d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 11'h 1d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 11'h 1d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 11'h 1dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 11'h 1e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 11'h 1e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 11'h 1e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 11'h 1ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 11'h 1f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 11'h 1f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 11'h 1f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 11'h 1fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 11'h 200;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 11'h 204;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 208;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 20c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 210;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 214;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 218;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 21c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 220;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 224;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 228;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 22c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 230;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 234;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 238;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 23c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 240;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 244;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 11'h 248;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 11'h 24c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 11'h 250;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 11'h 254;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 11'h 258;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 11'h 25c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 11'h 260;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 11'h 264;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 11'h 268;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 11'h 26c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 11'h 270;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 11'h 274;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 11'h 278;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 11'h 27c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 11'h 280;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 11'h 284;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 11'h 288;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 11'h 28c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 11'h 290;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 11'h 294;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 11'h 298;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 11'h 29c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 11'h 2a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 11'h 2a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 11'h 2a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 11'h 2ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 11'h 2b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 11'h 2b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 11'h 2b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 11'h 2bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 11'h 2c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 11'h 2c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 11'h 2c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 11'h 2cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 11'h 2d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 11'h 2d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 11'h 2d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 11'h 2dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 11'h 2e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 11'h 2e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 11'h 2e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 11'h 2ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 11'h 2f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 11'h 2f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 11'h 2f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 11'h 2fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 11'h 300;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 11'h 304;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 308;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 30c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 310;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 314;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 318;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 31c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 320;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 324;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 328;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 32c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 330;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 334;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 338;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 33c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 340;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 344;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 11'h 348;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 11'h 34c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 11'h 350;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 11'h 354;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 11'h 358;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 11'h 35c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 11'h 360;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 11'h 364;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 11'h 368;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 11'h 36c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 11'h 370;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 11'h 374;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 11'h 378;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 11'h 37c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 11'h 380;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 11'h 384;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET = 11'h 388;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 38c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 390;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 394;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 398;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 39c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 3a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 3a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 3a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 3ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 3b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 3b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 3b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 3bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 3c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 3c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 3c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 11'h 3cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 11'h 3d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 11'h 3d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 11'h 3d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 11'h 3dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 11'h 3e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 11'h 3e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 11'h 3e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 11'h 3ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 11'h 3f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 11'h 3f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 11'h 3f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 11'h 3fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 11'h 400;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 11'h 404;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 11'h 408;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 11'h 40c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 11'h 410;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 11'h 414;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 11'h 418;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 11'h 41c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 11'h 420;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 11'h 424;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 11'h 428;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 11'h 42c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 11'h 430;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 11'h 434;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 11'h 438;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 11'h 43c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 11'h 440;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 11'h 444;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 11'h 448;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 11'h 44c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 11'h 450;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 11'h 454;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 11'h 458;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 11'h 45c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 11'h 460;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 11'h 464;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 11'h 468;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 11'h 46c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 11'h 470;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 11'h 474;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 11'h 478;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 11'h 47c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 11'h 480;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 11'h 484;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 11'h 488;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 48c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 490;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 494;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 498;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 49c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 4a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 4a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 4a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 4ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 4b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 4b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 4b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 4bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 4c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 4c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 4c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 11'h 4cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 11'h 4d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 11'h 4d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 11'h 4d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 11'h 4dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 11'h 4e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 11'h 4e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 11'h 4e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 11'h 4ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 11'h 4f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 11'h 4f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 11'h 4f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 11'h 4fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 11'h 500;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 11'h 504;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 11'h 508;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 11'h 50c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 510;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 514;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 518;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 51c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 520;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 524;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 528;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 52c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 530;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 534;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 538;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 53c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 540;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 544;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 548;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 54c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 11'h 550;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 11'h 554;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 11'h 558;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 11'h 55c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 11'h 560;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 11'h 564;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 11'h 568;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 11'h 56c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 11'h 570;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 11'h 574;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 11'h 578;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 11'h 57c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 11'h 580;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 11'h 584;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 11'h 588;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 11'h 58c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 590;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 594;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 598;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 59c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 5a0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 5a4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 5a8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 5ac;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 5b0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 5b4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 5b8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 5bc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 5c0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 5c4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 5c8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 5cc;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 5d0;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 5d4;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 5d8;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 5dc;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 5e0;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 5e4;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 5e8;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 5ec;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 5f0;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 5f4;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 5f8;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 5fc;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 600;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 604;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 608;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 60c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 610;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 614;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 618;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 61c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 620;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 624;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 628;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 62c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 630;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 634;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 638;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 63c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 640;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 644;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 648;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 64c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 650;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 654;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 658;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 65c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 660;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 664;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 668;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 66c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 670;
+ parameter logic [BlockAw-1:0] PINMUX_ALERT_TEST_OFFSET = 11'h 0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET = 11'h 4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET = 11'h 8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET = 11'h c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET = 11'h 10;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET = 11'h 14;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET = 11'h 18;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET = 11'h 1c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET = 11'h 20;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET = 11'h 24;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET = 11'h 28;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET = 11'h 2c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET = 11'h 30;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET = 11'h 34;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET = 11'h 38;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET = 11'h 3c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET = 11'h 40;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET = 11'h 44;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET = 11'h 48;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET = 11'h 4c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET = 11'h 50;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET = 11'h 54;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET = 11'h 58;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET = 11'h 5c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET = 11'h 60;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET = 11'h 64;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET = 11'h 68;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET = 11'h 6c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET = 11'h 70;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET = 11'h 74;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET = 11'h 78;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET = 11'h 7c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET = 11'h 80;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET = 11'h 84;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 11'h 88;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 11'h 8c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 11'h 90;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 11'h 94;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 11'h 98;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 11'h 9c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 11'h a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 11'h a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 11'h a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 11'h ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 11'h b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 11'h b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 11'h b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 11'h bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 11'h c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 11'h c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 11'h c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 11'h cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 11'h d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 11'h d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 11'h d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 11'h dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 11'h e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 11'h e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 11'h e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 11'h ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 11'h f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 11'h f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 11'h f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 11'h fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 11'h 100;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 11'h 104;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 11'h 108;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 11'h 10c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 11'h 110;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 11'h 114;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 11'h 118;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 11'h 11c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 11'h 120;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 11'h 124;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 11'h 128;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 11'h 12c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 11'h 130;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 11'h 134;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 11'h 138;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 11'h 13c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 11'h 140;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 11'h 144;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 11'h 148;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 11'h 14c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 11'h 150;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 11'h 154;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 11'h 158;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 11'h 15c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 11'h 160;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 11'h 164;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 11'h 168;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 11'h 16c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 11'h 170;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 11'h 174;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 11'h 178;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 11'h 17c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 11'h 180;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 11'h 184;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 11'h 188;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 11'h 18c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 11'h 190;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 11'h 194;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 11'h 198;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 11'h 19c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 11'h 1a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 11'h 1a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 11'h 1a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 11'h 1ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 11'h 1b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 11'h 1b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 11'h 1b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 11'h 1bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 11'h 1c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 11'h 1c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 11'h 1c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 11'h 1cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 11'h 1d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 11'h 1d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 11'h 1d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 11'h 1dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 11'h 1e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 11'h 1e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 11'h 1e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 11'h 1ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 11'h 1f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 11'h 1f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 11'h 1f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 11'h 1fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 11'h 200;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 11'h 204;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 11'h 208;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 20c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 210;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 214;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 218;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 21c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 220;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 224;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 228;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 22c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 230;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 234;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 238;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 23c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 240;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 244;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 248;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 11'h 24c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 11'h 250;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 11'h 254;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 11'h 258;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 11'h 25c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 11'h 260;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 11'h 264;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 11'h 268;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 11'h 26c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 11'h 270;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 11'h 274;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 11'h 278;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 11'h 27c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 11'h 280;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 11'h 284;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 11'h 288;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 11'h 28c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 11'h 290;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 11'h 294;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 11'h 298;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 11'h 29c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 11'h 2a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 11'h 2a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 11'h 2a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 11'h 2ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 11'h 2b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 11'h 2b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 11'h 2b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 11'h 2bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 11'h 2c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 11'h 2c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 11'h 2c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 11'h 2cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 11'h 2d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 11'h 2d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 11'h 2d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 11'h 2dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 11'h 2e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 11'h 2e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 11'h 2e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 11'h 2ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 11'h 2f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 11'h 2f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 11'h 2f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 11'h 2fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 11'h 300;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 11'h 304;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 11'h 308;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 30c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 310;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 314;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 318;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 31c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 320;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 324;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 328;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 32c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 330;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 334;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 338;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 33c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 340;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 344;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 348;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 11'h 34c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 11'h 350;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 11'h 354;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 11'h 358;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 11'h 35c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 11'h 360;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 11'h 364;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 11'h 368;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 11'h 36c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 11'h 370;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 11'h 374;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 11'h 378;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 11'h 37c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 11'h 380;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 11'h 384;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 11'h 388;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET = 11'h 38c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 390;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 394;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 398;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 39c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 3a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 3a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 3a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 3ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 3b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 3b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 3b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 3bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 3c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 3c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 3c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 3cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 11'h 3d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 11'h 3d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 11'h 3d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 11'h 3dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 11'h 3e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 11'h 3e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 11'h 3e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 11'h 3ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 11'h 3f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 11'h 3f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 11'h 3f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 11'h 3fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 11'h 400;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 11'h 404;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 11'h 408;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 11'h 40c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 11'h 410;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 11'h 414;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 11'h 418;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 11'h 41c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 11'h 420;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 11'h 424;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 11'h 428;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 11'h 42c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 11'h 430;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 11'h 434;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 11'h 438;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 11'h 43c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 11'h 440;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 11'h 444;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 11'h 448;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 11'h 44c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 11'h 450;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 11'h 454;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 11'h 458;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 11'h 45c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 11'h 460;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 11'h 464;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 11'h 468;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 11'h 46c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 11'h 470;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 11'h 474;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 11'h 478;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 11'h 47c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 11'h 480;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 11'h 484;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 11'h 488;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 11'h 48c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 490;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 494;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 498;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 49c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 4a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 4a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 4a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 4ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 4b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 4b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 4b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 4bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 4c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 4c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 4c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 4cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 11'h 4d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 11'h 4d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 11'h 4d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 11'h 4dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 11'h 4e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 11'h 4e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 11'h 4e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 11'h 4ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 11'h 4f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 11'h 4f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 11'h 4f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 11'h 4fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 11'h 500;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 11'h 504;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 11'h 508;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 11'h 50c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 11'h 510;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 514;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 518;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 51c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 520;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 524;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 528;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 52c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 530;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 534;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 538;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 53c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 540;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 544;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 548;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 54c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 550;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 11'h 554;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 11'h 558;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 11'h 55c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 11'h 560;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 11'h 564;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 11'h 568;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 11'h 56c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 11'h 570;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 11'h 574;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 11'h 578;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 11'h 57c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 11'h 580;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 11'h 584;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 11'h 588;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 11'h 58c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 11'h 590;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 594;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 598;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 59c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 5a0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 5a4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 5a8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 5ac;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 5b0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 5b4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 5b8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 5bc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 5c0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 5c4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 5c8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 5cc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 5d0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 5d4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 5d8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 5dc;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 5e0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 5e4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 5e8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 5ec;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 5f0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 5f4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 5f8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 5fc;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 600;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 604;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 608;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 60c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 610;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 614;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 618;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 61c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 620;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 624;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 628;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 62c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 630;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 634;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 638;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 63c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 640;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 644;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 648;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 64c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 650;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 654;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 658;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 65c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 660;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 664;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 668;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 66c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 670;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 674;
// Reset values for hwext registers and their fields
+ parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
parameter logic [12:0] PINMUX_MIO_PAD_ATTR_0_RESVAL = 13'h 0;
parameter logic [12:0] PINMUX_MIO_PAD_ATTR_0_ATTR_0_RESVAL = 13'h 0;
parameter logic [12:0] PINMUX_MIO_PAD_ATTR_1_RESVAL = 13'h 0;
@@ -667,6 +677,7 @@
// Register index
typedef enum int {
+ PINMUX_ALERT_TEST,
PINMUX_MIO_PERIPH_INSEL_REGWEN_0,
PINMUX_MIO_PERIPH_INSEL_REGWEN_1,
PINMUX_MIO_PERIPH_INSEL_REGWEN_2,
@@ -1083,420 +1094,421 @@
} pinmux_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] PINMUX_PERMIT [413] = '{
- 4'b 0001, // index[ 0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0
- 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_1
- 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_2
- 4'b 0001, // index[ 3] PINMUX_MIO_PERIPH_INSEL_REGWEN_3
- 4'b 0001, // index[ 4] PINMUX_MIO_PERIPH_INSEL_REGWEN_4
- 4'b 0001, // index[ 5] PINMUX_MIO_PERIPH_INSEL_REGWEN_5
- 4'b 0001, // index[ 6] PINMUX_MIO_PERIPH_INSEL_REGWEN_6
- 4'b 0001, // index[ 7] PINMUX_MIO_PERIPH_INSEL_REGWEN_7
- 4'b 0001, // index[ 8] PINMUX_MIO_PERIPH_INSEL_REGWEN_8
- 4'b 0001, // index[ 9] PINMUX_MIO_PERIPH_INSEL_REGWEN_9
- 4'b 0001, // index[ 10] PINMUX_MIO_PERIPH_INSEL_REGWEN_10
- 4'b 0001, // index[ 11] PINMUX_MIO_PERIPH_INSEL_REGWEN_11
- 4'b 0001, // index[ 12] PINMUX_MIO_PERIPH_INSEL_REGWEN_12
- 4'b 0001, // index[ 13] PINMUX_MIO_PERIPH_INSEL_REGWEN_13
- 4'b 0001, // index[ 14] PINMUX_MIO_PERIPH_INSEL_REGWEN_14
- 4'b 0001, // index[ 15] PINMUX_MIO_PERIPH_INSEL_REGWEN_15
- 4'b 0001, // index[ 16] PINMUX_MIO_PERIPH_INSEL_REGWEN_16
- 4'b 0001, // index[ 17] PINMUX_MIO_PERIPH_INSEL_REGWEN_17
- 4'b 0001, // index[ 18] PINMUX_MIO_PERIPH_INSEL_REGWEN_18
- 4'b 0001, // index[ 19] PINMUX_MIO_PERIPH_INSEL_REGWEN_19
- 4'b 0001, // index[ 20] PINMUX_MIO_PERIPH_INSEL_REGWEN_20
- 4'b 0001, // index[ 21] PINMUX_MIO_PERIPH_INSEL_REGWEN_21
- 4'b 0001, // index[ 22] PINMUX_MIO_PERIPH_INSEL_REGWEN_22
- 4'b 0001, // index[ 23] PINMUX_MIO_PERIPH_INSEL_REGWEN_23
- 4'b 0001, // index[ 24] PINMUX_MIO_PERIPH_INSEL_REGWEN_24
- 4'b 0001, // index[ 25] PINMUX_MIO_PERIPH_INSEL_REGWEN_25
- 4'b 0001, // index[ 26] PINMUX_MIO_PERIPH_INSEL_REGWEN_26
- 4'b 0001, // index[ 27] PINMUX_MIO_PERIPH_INSEL_REGWEN_27
- 4'b 0001, // index[ 28] PINMUX_MIO_PERIPH_INSEL_REGWEN_28
- 4'b 0001, // index[ 29] PINMUX_MIO_PERIPH_INSEL_REGWEN_29
- 4'b 0001, // index[ 30] PINMUX_MIO_PERIPH_INSEL_REGWEN_30
- 4'b 0001, // index[ 31] PINMUX_MIO_PERIPH_INSEL_REGWEN_31
- 4'b 0001, // index[ 32] PINMUX_MIO_PERIPH_INSEL_REGWEN_32
- 4'b 0001, // index[ 33] PINMUX_MIO_PERIPH_INSEL_0
- 4'b 0001, // index[ 34] PINMUX_MIO_PERIPH_INSEL_1
- 4'b 0001, // index[ 35] PINMUX_MIO_PERIPH_INSEL_2
- 4'b 0001, // index[ 36] PINMUX_MIO_PERIPH_INSEL_3
- 4'b 0001, // index[ 37] PINMUX_MIO_PERIPH_INSEL_4
- 4'b 0001, // index[ 38] PINMUX_MIO_PERIPH_INSEL_5
- 4'b 0001, // index[ 39] PINMUX_MIO_PERIPH_INSEL_6
- 4'b 0001, // index[ 40] PINMUX_MIO_PERIPH_INSEL_7
- 4'b 0001, // index[ 41] PINMUX_MIO_PERIPH_INSEL_8
- 4'b 0001, // index[ 42] PINMUX_MIO_PERIPH_INSEL_9
- 4'b 0001, // index[ 43] PINMUX_MIO_PERIPH_INSEL_10
- 4'b 0001, // index[ 44] PINMUX_MIO_PERIPH_INSEL_11
- 4'b 0001, // index[ 45] PINMUX_MIO_PERIPH_INSEL_12
- 4'b 0001, // index[ 46] PINMUX_MIO_PERIPH_INSEL_13
- 4'b 0001, // index[ 47] PINMUX_MIO_PERIPH_INSEL_14
- 4'b 0001, // index[ 48] PINMUX_MIO_PERIPH_INSEL_15
- 4'b 0001, // index[ 49] PINMUX_MIO_PERIPH_INSEL_16
- 4'b 0001, // index[ 50] PINMUX_MIO_PERIPH_INSEL_17
- 4'b 0001, // index[ 51] PINMUX_MIO_PERIPH_INSEL_18
- 4'b 0001, // index[ 52] PINMUX_MIO_PERIPH_INSEL_19
- 4'b 0001, // index[ 53] PINMUX_MIO_PERIPH_INSEL_20
- 4'b 0001, // index[ 54] PINMUX_MIO_PERIPH_INSEL_21
- 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_22
- 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_23
- 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_24
- 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_25
- 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_26
- 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_27
- 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_28
- 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_29
- 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_30
- 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_31
- 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_32
- 4'b 0001, // index[ 66] PINMUX_MIO_OUTSEL_REGWEN_0
- 4'b 0001, // index[ 67] PINMUX_MIO_OUTSEL_REGWEN_1
- 4'b 0001, // index[ 68] PINMUX_MIO_OUTSEL_REGWEN_2
- 4'b 0001, // index[ 69] PINMUX_MIO_OUTSEL_REGWEN_3
- 4'b 0001, // index[ 70] PINMUX_MIO_OUTSEL_REGWEN_4
- 4'b 0001, // index[ 71] PINMUX_MIO_OUTSEL_REGWEN_5
- 4'b 0001, // index[ 72] PINMUX_MIO_OUTSEL_REGWEN_6
- 4'b 0001, // index[ 73] PINMUX_MIO_OUTSEL_REGWEN_7
- 4'b 0001, // index[ 74] PINMUX_MIO_OUTSEL_REGWEN_8
- 4'b 0001, // index[ 75] PINMUX_MIO_OUTSEL_REGWEN_9
- 4'b 0001, // index[ 76] PINMUX_MIO_OUTSEL_REGWEN_10
- 4'b 0001, // index[ 77] PINMUX_MIO_OUTSEL_REGWEN_11
- 4'b 0001, // index[ 78] PINMUX_MIO_OUTSEL_REGWEN_12
- 4'b 0001, // index[ 79] PINMUX_MIO_OUTSEL_REGWEN_13
- 4'b 0001, // index[ 80] PINMUX_MIO_OUTSEL_REGWEN_14
- 4'b 0001, // index[ 81] PINMUX_MIO_OUTSEL_REGWEN_15
- 4'b 0001, // index[ 82] PINMUX_MIO_OUTSEL_REGWEN_16
- 4'b 0001, // index[ 83] PINMUX_MIO_OUTSEL_REGWEN_17
- 4'b 0001, // index[ 84] PINMUX_MIO_OUTSEL_REGWEN_18
- 4'b 0001, // index[ 85] PINMUX_MIO_OUTSEL_REGWEN_19
- 4'b 0001, // index[ 86] PINMUX_MIO_OUTSEL_REGWEN_20
- 4'b 0001, // index[ 87] PINMUX_MIO_OUTSEL_REGWEN_21
- 4'b 0001, // index[ 88] PINMUX_MIO_OUTSEL_REGWEN_22
- 4'b 0001, // index[ 89] PINMUX_MIO_OUTSEL_REGWEN_23
- 4'b 0001, // index[ 90] PINMUX_MIO_OUTSEL_REGWEN_24
- 4'b 0001, // index[ 91] PINMUX_MIO_OUTSEL_REGWEN_25
- 4'b 0001, // index[ 92] PINMUX_MIO_OUTSEL_REGWEN_26
- 4'b 0001, // index[ 93] PINMUX_MIO_OUTSEL_REGWEN_27
- 4'b 0001, // index[ 94] PINMUX_MIO_OUTSEL_REGWEN_28
- 4'b 0001, // index[ 95] PINMUX_MIO_OUTSEL_REGWEN_29
- 4'b 0001, // index[ 96] PINMUX_MIO_OUTSEL_REGWEN_30
- 4'b 0001, // index[ 97] PINMUX_MIO_OUTSEL_REGWEN_31
- 4'b 0001, // index[ 98] PINMUX_MIO_OUTSEL_0
- 4'b 0001, // index[ 99] PINMUX_MIO_OUTSEL_1
- 4'b 0001, // index[100] PINMUX_MIO_OUTSEL_2
- 4'b 0001, // index[101] PINMUX_MIO_OUTSEL_3
- 4'b 0001, // index[102] PINMUX_MIO_OUTSEL_4
- 4'b 0001, // index[103] PINMUX_MIO_OUTSEL_5
- 4'b 0001, // index[104] PINMUX_MIO_OUTSEL_6
- 4'b 0001, // index[105] PINMUX_MIO_OUTSEL_7
- 4'b 0001, // index[106] PINMUX_MIO_OUTSEL_8
- 4'b 0001, // index[107] PINMUX_MIO_OUTSEL_9
- 4'b 0001, // index[108] PINMUX_MIO_OUTSEL_10
- 4'b 0001, // index[109] PINMUX_MIO_OUTSEL_11
- 4'b 0001, // index[110] PINMUX_MIO_OUTSEL_12
- 4'b 0001, // index[111] PINMUX_MIO_OUTSEL_13
- 4'b 0001, // index[112] PINMUX_MIO_OUTSEL_14
- 4'b 0001, // index[113] PINMUX_MIO_OUTSEL_15
- 4'b 0001, // index[114] PINMUX_MIO_OUTSEL_16
- 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_17
- 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_18
- 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_19
- 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_20
- 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_21
- 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_22
- 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_23
- 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_24
- 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_25
- 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_26
- 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_27
- 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_28
- 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_29
- 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_30
- 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_31
- 4'b 0001, // index[130] PINMUX_MIO_PAD_ATTR_REGWEN_0
- 4'b 0001, // index[131] PINMUX_MIO_PAD_ATTR_REGWEN_1
- 4'b 0001, // index[132] PINMUX_MIO_PAD_ATTR_REGWEN_2
- 4'b 0001, // index[133] PINMUX_MIO_PAD_ATTR_REGWEN_3
- 4'b 0001, // index[134] PINMUX_MIO_PAD_ATTR_REGWEN_4
- 4'b 0001, // index[135] PINMUX_MIO_PAD_ATTR_REGWEN_5
- 4'b 0001, // index[136] PINMUX_MIO_PAD_ATTR_REGWEN_6
- 4'b 0001, // index[137] PINMUX_MIO_PAD_ATTR_REGWEN_7
- 4'b 0001, // index[138] PINMUX_MIO_PAD_ATTR_REGWEN_8
- 4'b 0001, // index[139] PINMUX_MIO_PAD_ATTR_REGWEN_9
- 4'b 0001, // index[140] PINMUX_MIO_PAD_ATTR_REGWEN_10
- 4'b 0001, // index[141] PINMUX_MIO_PAD_ATTR_REGWEN_11
- 4'b 0001, // index[142] PINMUX_MIO_PAD_ATTR_REGWEN_12
- 4'b 0001, // index[143] PINMUX_MIO_PAD_ATTR_REGWEN_13
- 4'b 0001, // index[144] PINMUX_MIO_PAD_ATTR_REGWEN_14
- 4'b 0001, // index[145] PINMUX_MIO_PAD_ATTR_REGWEN_15
- 4'b 0001, // index[146] PINMUX_MIO_PAD_ATTR_REGWEN_16
- 4'b 0001, // index[147] PINMUX_MIO_PAD_ATTR_REGWEN_17
- 4'b 0001, // index[148] PINMUX_MIO_PAD_ATTR_REGWEN_18
- 4'b 0001, // index[149] PINMUX_MIO_PAD_ATTR_REGWEN_19
- 4'b 0001, // index[150] PINMUX_MIO_PAD_ATTR_REGWEN_20
- 4'b 0001, // index[151] PINMUX_MIO_PAD_ATTR_REGWEN_21
- 4'b 0001, // index[152] PINMUX_MIO_PAD_ATTR_REGWEN_22
- 4'b 0001, // index[153] PINMUX_MIO_PAD_ATTR_REGWEN_23
- 4'b 0001, // index[154] PINMUX_MIO_PAD_ATTR_REGWEN_24
- 4'b 0001, // index[155] PINMUX_MIO_PAD_ATTR_REGWEN_25
- 4'b 0001, // index[156] PINMUX_MIO_PAD_ATTR_REGWEN_26
- 4'b 0001, // index[157] PINMUX_MIO_PAD_ATTR_REGWEN_27
- 4'b 0001, // index[158] PINMUX_MIO_PAD_ATTR_REGWEN_28
- 4'b 0001, // index[159] PINMUX_MIO_PAD_ATTR_REGWEN_29
- 4'b 0001, // index[160] PINMUX_MIO_PAD_ATTR_REGWEN_30
- 4'b 0001, // index[161] PINMUX_MIO_PAD_ATTR_REGWEN_31
- 4'b 0011, // index[162] PINMUX_MIO_PAD_ATTR_0
- 4'b 0011, // index[163] PINMUX_MIO_PAD_ATTR_1
- 4'b 0011, // index[164] PINMUX_MIO_PAD_ATTR_2
- 4'b 0011, // index[165] PINMUX_MIO_PAD_ATTR_3
- 4'b 0011, // index[166] PINMUX_MIO_PAD_ATTR_4
- 4'b 0011, // index[167] PINMUX_MIO_PAD_ATTR_5
- 4'b 0011, // index[168] PINMUX_MIO_PAD_ATTR_6
- 4'b 0011, // index[169] PINMUX_MIO_PAD_ATTR_7
- 4'b 0011, // index[170] PINMUX_MIO_PAD_ATTR_8
- 4'b 0011, // index[171] PINMUX_MIO_PAD_ATTR_9
- 4'b 0011, // index[172] PINMUX_MIO_PAD_ATTR_10
- 4'b 0011, // index[173] PINMUX_MIO_PAD_ATTR_11
- 4'b 0011, // index[174] PINMUX_MIO_PAD_ATTR_12
- 4'b 0011, // index[175] PINMUX_MIO_PAD_ATTR_13
- 4'b 0011, // index[176] PINMUX_MIO_PAD_ATTR_14
- 4'b 0011, // index[177] PINMUX_MIO_PAD_ATTR_15
- 4'b 0011, // index[178] PINMUX_MIO_PAD_ATTR_16
- 4'b 0011, // index[179] PINMUX_MIO_PAD_ATTR_17
- 4'b 0011, // index[180] PINMUX_MIO_PAD_ATTR_18
- 4'b 0011, // index[181] PINMUX_MIO_PAD_ATTR_19
- 4'b 0011, // index[182] PINMUX_MIO_PAD_ATTR_20
- 4'b 0011, // index[183] PINMUX_MIO_PAD_ATTR_21
- 4'b 0011, // index[184] PINMUX_MIO_PAD_ATTR_22
- 4'b 0011, // index[185] PINMUX_MIO_PAD_ATTR_23
- 4'b 0011, // index[186] PINMUX_MIO_PAD_ATTR_24
- 4'b 0011, // index[187] PINMUX_MIO_PAD_ATTR_25
- 4'b 0011, // index[188] PINMUX_MIO_PAD_ATTR_26
- 4'b 0011, // index[189] PINMUX_MIO_PAD_ATTR_27
- 4'b 0011, // index[190] PINMUX_MIO_PAD_ATTR_28
- 4'b 0011, // index[191] PINMUX_MIO_PAD_ATTR_29
- 4'b 0011, // index[192] PINMUX_MIO_PAD_ATTR_30
- 4'b 0011, // index[193] PINMUX_MIO_PAD_ATTR_31
- 4'b 0001, // index[194] PINMUX_DIO_PAD_ATTR_REGWEN_0
- 4'b 0001, // index[195] PINMUX_DIO_PAD_ATTR_REGWEN_1
- 4'b 0001, // index[196] PINMUX_DIO_PAD_ATTR_REGWEN_2
- 4'b 0001, // index[197] PINMUX_DIO_PAD_ATTR_REGWEN_3
- 4'b 0001, // index[198] PINMUX_DIO_PAD_ATTR_REGWEN_4
- 4'b 0001, // index[199] PINMUX_DIO_PAD_ATTR_REGWEN_5
- 4'b 0001, // index[200] PINMUX_DIO_PAD_ATTR_REGWEN_6
- 4'b 0001, // index[201] PINMUX_DIO_PAD_ATTR_REGWEN_7
- 4'b 0001, // index[202] PINMUX_DIO_PAD_ATTR_REGWEN_8
- 4'b 0001, // index[203] PINMUX_DIO_PAD_ATTR_REGWEN_9
- 4'b 0001, // index[204] PINMUX_DIO_PAD_ATTR_REGWEN_10
- 4'b 0001, // index[205] PINMUX_DIO_PAD_ATTR_REGWEN_11
- 4'b 0001, // index[206] PINMUX_DIO_PAD_ATTR_REGWEN_12
- 4'b 0001, // index[207] PINMUX_DIO_PAD_ATTR_REGWEN_13
- 4'b 0001, // index[208] PINMUX_DIO_PAD_ATTR_REGWEN_14
- 4'b 0001, // index[209] PINMUX_DIO_PAD_ATTR_REGWEN_15
- 4'b 0011, // index[210] PINMUX_DIO_PAD_ATTR_0
- 4'b 0011, // index[211] PINMUX_DIO_PAD_ATTR_1
- 4'b 0011, // index[212] PINMUX_DIO_PAD_ATTR_2
- 4'b 0011, // index[213] PINMUX_DIO_PAD_ATTR_3
- 4'b 0011, // index[214] PINMUX_DIO_PAD_ATTR_4
- 4'b 0011, // index[215] PINMUX_DIO_PAD_ATTR_5
- 4'b 0011, // index[216] PINMUX_DIO_PAD_ATTR_6
- 4'b 0011, // index[217] PINMUX_DIO_PAD_ATTR_7
- 4'b 0011, // index[218] PINMUX_DIO_PAD_ATTR_8
- 4'b 0011, // index[219] PINMUX_DIO_PAD_ATTR_9
- 4'b 0011, // index[220] PINMUX_DIO_PAD_ATTR_10
- 4'b 0011, // index[221] PINMUX_DIO_PAD_ATTR_11
- 4'b 0011, // index[222] PINMUX_DIO_PAD_ATTR_12
- 4'b 0011, // index[223] PINMUX_DIO_PAD_ATTR_13
- 4'b 0011, // index[224] PINMUX_DIO_PAD_ATTR_14
- 4'b 0011, // index[225] PINMUX_DIO_PAD_ATTR_15
- 4'b 1111, // index[226] PINMUX_MIO_PAD_SLEEP_STATUS
- 4'b 0001, // index[227] PINMUX_MIO_PAD_SLEEP_REGWEN_0
- 4'b 0001, // index[228] PINMUX_MIO_PAD_SLEEP_REGWEN_1
- 4'b 0001, // index[229] PINMUX_MIO_PAD_SLEEP_REGWEN_2
- 4'b 0001, // index[230] PINMUX_MIO_PAD_SLEEP_REGWEN_3
- 4'b 0001, // index[231] PINMUX_MIO_PAD_SLEEP_REGWEN_4
- 4'b 0001, // index[232] PINMUX_MIO_PAD_SLEEP_REGWEN_5
- 4'b 0001, // index[233] PINMUX_MIO_PAD_SLEEP_REGWEN_6
- 4'b 0001, // index[234] PINMUX_MIO_PAD_SLEEP_REGWEN_7
- 4'b 0001, // index[235] PINMUX_MIO_PAD_SLEEP_REGWEN_8
- 4'b 0001, // index[236] PINMUX_MIO_PAD_SLEEP_REGWEN_9
- 4'b 0001, // index[237] PINMUX_MIO_PAD_SLEEP_REGWEN_10
- 4'b 0001, // index[238] PINMUX_MIO_PAD_SLEEP_REGWEN_11
- 4'b 0001, // index[239] PINMUX_MIO_PAD_SLEEP_REGWEN_12
- 4'b 0001, // index[240] PINMUX_MIO_PAD_SLEEP_REGWEN_13
- 4'b 0001, // index[241] PINMUX_MIO_PAD_SLEEP_REGWEN_14
- 4'b 0001, // index[242] PINMUX_MIO_PAD_SLEEP_REGWEN_15
- 4'b 0001, // index[243] PINMUX_MIO_PAD_SLEEP_REGWEN_16
- 4'b 0001, // index[244] PINMUX_MIO_PAD_SLEEP_REGWEN_17
- 4'b 0001, // index[245] PINMUX_MIO_PAD_SLEEP_REGWEN_18
- 4'b 0001, // index[246] PINMUX_MIO_PAD_SLEEP_REGWEN_19
- 4'b 0001, // index[247] PINMUX_MIO_PAD_SLEEP_REGWEN_20
- 4'b 0001, // index[248] PINMUX_MIO_PAD_SLEEP_REGWEN_21
- 4'b 0001, // index[249] PINMUX_MIO_PAD_SLEEP_REGWEN_22
- 4'b 0001, // index[250] PINMUX_MIO_PAD_SLEEP_REGWEN_23
- 4'b 0001, // index[251] PINMUX_MIO_PAD_SLEEP_REGWEN_24
- 4'b 0001, // index[252] PINMUX_MIO_PAD_SLEEP_REGWEN_25
- 4'b 0001, // index[253] PINMUX_MIO_PAD_SLEEP_REGWEN_26
- 4'b 0001, // index[254] PINMUX_MIO_PAD_SLEEP_REGWEN_27
- 4'b 0001, // index[255] PINMUX_MIO_PAD_SLEEP_REGWEN_28
- 4'b 0001, // index[256] PINMUX_MIO_PAD_SLEEP_REGWEN_29
- 4'b 0001, // index[257] PINMUX_MIO_PAD_SLEEP_REGWEN_30
- 4'b 0001, // index[258] PINMUX_MIO_PAD_SLEEP_REGWEN_31
- 4'b 0001, // index[259] PINMUX_MIO_PAD_SLEEP_EN_0
- 4'b 0001, // index[260] PINMUX_MIO_PAD_SLEEP_EN_1
- 4'b 0001, // index[261] PINMUX_MIO_PAD_SLEEP_EN_2
- 4'b 0001, // index[262] PINMUX_MIO_PAD_SLEEP_EN_3
- 4'b 0001, // index[263] PINMUX_MIO_PAD_SLEEP_EN_4
- 4'b 0001, // index[264] PINMUX_MIO_PAD_SLEEP_EN_5
- 4'b 0001, // index[265] PINMUX_MIO_PAD_SLEEP_EN_6
- 4'b 0001, // index[266] PINMUX_MIO_PAD_SLEEP_EN_7
- 4'b 0001, // index[267] PINMUX_MIO_PAD_SLEEP_EN_8
- 4'b 0001, // index[268] PINMUX_MIO_PAD_SLEEP_EN_9
- 4'b 0001, // index[269] PINMUX_MIO_PAD_SLEEP_EN_10
- 4'b 0001, // index[270] PINMUX_MIO_PAD_SLEEP_EN_11
- 4'b 0001, // index[271] PINMUX_MIO_PAD_SLEEP_EN_12
- 4'b 0001, // index[272] PINMUX_MIO_PAD_SLEEP_EN_13
- 4'b 0001, // index[273] PINMUX_MIO_PAD_SLEEP_EN_14
- 4'b 0001, // index[274] PINMUX_MIO_PAD_SLEEP_EN_15
- 4'b 0001, // index[275] PINMUX_MIO_PAD_SLEEP_EN_16
- 4'b 0001, // index[276] PINMUX_MIO_PAD_SLEEP_EN_17
- 4'b 0001, // index[277] PINMUX_MIO_PAD_SLEEP_EN_18
- 4'b 0001, // index[278] PINMUX_MIO_PAD_SLEEP_EN_19
- 4'b 0001, // index[279] PINMUX_MIO_PAD_SLEEP_EN_20
- 4'b 0001, // index[280] PINMUX_MIO_PAD_SLEEP_EN_21
- 4'b 0001, // index[281] PINMUX_MIO_PAD_SLEEP_EN_22
- 4'b 0001, // index[282] PINMUX_MIO_PAD_SLEEP_EN_23
- 4'b 0001, // index[283] PINMUX_MIO_PAD_SLEEP_EN_24
- 4'b 0001, // index[284] PINMUX_MIO_PAD_SLEEP_EN_25
- 4'b 0001, // index[285] PINMUX_MIO_PAD_SLEEP_EN_26
- 4'b 0001, // index[286] PINMUX_MIO_PAD_SLEEP_EN_27
- 4'b 0001, // index[287] PINMUX_MIO_PAD_SLEEP_EN_28
- 4'b 0001, // index[288] PINMUX_MIO_PAD_SLEEP_EN_29
- 4'b 0001, // index[289] PINMUX_MIO_PAD_SLEEP_EN_30
- 4'b 0001, // index[290] PINMUX_MIO_PAD_SLEEP_EN_31
- 4'b 0001, // index[291] PINMUX_MIO_PAD_SLEEP_MODE_0
- 4'b 0001, // index[292] PINMUX_MIO_PAD_SLEEP_MODE_1
- 4'b 0001, // index[293] PINMUX_MIO_PAD_SLEEP_MODE_2
- 4'b 0001, // index[294] PINMUX_MIO_PAD_SLEEP_MODE_3
- 4'b 0001, // index[295] PINMUX_MIO_PAD_SLEEP_MODE_4
- 4'b 0001, // index[296] PINMUX_MIO_PAD_SLEEP_MODE_5
- 4'b 0001, // index[297] PINMUX_MIO_PAD_SLEEP_MODE_6
- 4'b 0001, // index[298] PINMUX_MIO_PAD_SLEEP_MODE_7
- 4'b 0001, // index[299] PINMUX_MIO_PAD_SLEEP_MODE_8
- 4'b 0001, // index[300] PINMUX_MIO_PAD_SLEEP_MODE_9
- 4'b 0001, // index[301] PINMUX_MIO_PAD_SLEEP_MODE_10
- 4'b 0001, // index[302] PINMUX_MIO_PAD_SLEEP_MODE_11
- 4'b 0001, // index[303] PINMUX_MIO_PAD_SLEEP_MODE_12
- 4'b 0001, // index[304] PINMUX_MIO_PAD_SLEEP_MODE_13
- 4'b 0001, // index[305] PINMUX_MIO_PAD_SLEEP_MODE_14
- 4'b 0001, // index[306] PINMUX_MIO_PAD_SLEEP_MODE_15
- 4'b 0001, // index[307] PINMUX_MIO_PAD_SLEEP_MODE_16
- 4'b 0001, // index[308] PINMUX_MIO_PAD_SLEEP_MODE_17
- 4'b 0001, // index[309] PINMUX_MIO_PAD_SLEEP_MODE_18
- 4'b 0001, // index[310] PINMUX_MIO_PAD_SLEEP_MODE_19
- 4'b 0001, // index[311] PINMUX_MIO_PAD_SLEEP_MODE_20
- 4'b 0001, // index[312] PINMUX_MIO_PAD_SLEEP_MODE_21
- 4'b 0001, // index[313] PINMUX_MIO_PAD_SLEEP_MODE_22
- 4'b 0001, // index[314] PINMUX_MIO_PAD_SLEEP_MODE_23
- 4'b 0001, // index[315] PINMUX_MIO_PAD_SLEEP_MODE_24
- 4'b 0001, // index[316] PINMUX_MIO_PAD_SLEEP_MODE_25
- 4'b 0001, // index[317] PINMUX_MIO_PAD_SLEEP_MODE_26
- 4'b 0001, // index[318] PINMUX_MIO_PAD_SLEEP_MODE_27
- 4'b 0001, // index[319] PINMUX_MIO_PAD_SLEEP_MODE_28
- 4'b 0001, // index[320] PINMUX_MIO_PAD_SLEEP_MODE_29
- 4'b 0001, // index[321] PINMUX_MIO_PAD_SLEEP_MODE_30
- 4'b 0001, // index[322] PINMUX_MIO_PAD_SLEEP_MODE_31
- 4'b 0011, // index[323] PINMUX_DIO_PAD_SLEEP_STATUS
- 4'b 0001, // index[324] PINMUX_DIO_PAD_SLEEP_REGWEN_0
- 4'b 0001, // index[325] PINMUX_DIO_PAD_SLEEP_REGWEN_1
- 4'b 0001, // index[326] PINMUX_DIO_PAD_SLEEP_REGWEN_2
- 4'b 0001, // index[327] PINMUX_DIO_PAD_SLEEP_REGWEN_3
- 4'b 0001, // index[328] PINMUX_DIO_PAD_SLEEP_REGWEN_4
- 4'b 0001, // index[329] PINMUX_DIO_PAD_SLEEP_REGWEN_5
- 4'b 0001, // index[330] PINMUX_DIO_PAD_SLEEP_REGWEN_6
- 4'b 0001, // index[331] PINMUX_DIO_PAD_SLEEP_REGWEN_7
- 4'b 0001, // index[332] PINMUX_DIO_PAD_SLEEP_REGWEN_8
- 4'b 0001, // index[333] PINMUX_DIO_PAD_SLEEP_REGWEN_9
- 4'b 0001, // index[334] PINMUX_DIO_PAD_SLEEP_REGWEN_10
- 4'b 0001, // index[335] PINMUX_DIO_PAD_SLEEP_REGWEN_11
- 4'b 0001, // index[336] PINMUX_DIO_PAD_SLEEP_REGWEN_12
- 4'b 0001, // index[337] PINMUX_DIO_PAD_SLEEP_REGWEN_13
- 4'b 0001, // index[338] PINMUX_DIO_PAD_SLEEP_REGWEN_14
- 4'b 0001, // index[339] PINMUX_DIO_PAD_SLEEP_REGWEN_15
- 4'b 0001, // index[340] PINMUX_DIO_PAD_SLEEP_EN_0
- 4'b 0001, // index[341] PINMUX_DIO_PAD_SLEEP_EN_1
- 4'b 0001, // index[342] PINMUX_DIO_PAD_SLEEP_EN_2
- 4'b 0001, // index[343] PINMUX_DIO_PAD_SLEEP_EN_3
- 4'b 0001, // index[344] PINMUX_DIO_PAD_SLEEP_EN_4
- 4'b 0001, // index[345] PINMUX_DIO_PAD_SLEEP_EN_5
- 4'b 0001, // index[346] PINMUX_DIO_PAD_SLEEP_EN_6
- 4'b 0001, // index[347] PINMUX_DIO_PAD_SLEEP_EN_7
- 4'b 0001, // index[348] PINMUX_DIO_PAD_SLEEP_EN_8
- 4'b 0001, // index[349] PINMUX_DIO_PAD_SLEEP_EN_9
- 4'b 0001, // index[350] PINMUX_DIO_PAD_SLEEP_EN_10
- 4'b 0001, // index[351] PINMUX_DIO_PAD_SLEEP_EN_11
- 4'b 0001, // index[352] PINMUX_DIO_PAD_SLEEP_EN_12
- 4'b 0001, // index[353] PINMUX_DIO_PAD_SLEEP_EN_13
- 4'b 0001, // index[354] PINMUX_DIO_PAD_SLEEP_EN_14
- 4'b 0001, // index[355] PINMUX_DIO_PAD_SLEEP_EN_15
- 4'b 0001, // index[356] PINMUX_DIO_PAD_SLEEP_MODE_0
- 4'b 0001, // index[357] PINMUX_DIO_PAD_SLEEP_MODE_1
- 4'b 0001, // index[358] PINMUX_DIO_PAD_SLEEP_MODE_2
- 4'b 0001, // index[359] PINMUX_DIO_PAD_SLEEP_MODE_3
- 4'b 0001, // index[360] PINMUX_DIO_PAD_SLEEP_MODE_4
- 4'b 0001, // index[361] PINMUX_DIO_PAD_SLEEP_MODE_5
- 4'b 0001, // index[362] PINMUX_DIO_PAD_SLEEP_MODE_6
- 4'b 0001, // index[363] PINMUX_DIO_PAD_SLEEP_MODE_7
- 4'b 0001, // index[364] PINMUX_DIO_PAD_SLEEP_MODE_8
- 4'b 0001, // index[365] PINMUX_DIO_PAD_SLEEP_MODE_9
- 4'b 0001, // index[366] PINMUX_DIO_PAD_SLEEP_MODE_10
- 4'b 0001, // index[367] PINMUX_DIO_PAD_SLEEP_MODE_11
- 4'b 0001, // index[368] PINMUX_DIO_PAD_SLEEP_MODE_12
- 4'b 0001, // index[369] PINMUX_DIO_PAD_SLEEP_MODE_13
- 4'b 0001, // index[370] PINMUX_DIO_PAD_SLEEP_MODE_14
- 4'b 0001, // index[371] PINMUX_DIO_PAD_SLEEP_MODE_15
- 4'b 0001, // index[372] PINMUX_WKUP_DETECTOR_REGWEN_0
- 4'b 0001, // index[373] PINMUX_WKUP_DETECTOR_REGWEN_1
- 4'b 0001, // index[374] PINMUX_WKUP_DETECTOR_REGWEN_2
- 4'b 0001, // index[375] PINMUX_WKUP_DETECTOR_REGWEN_3
- 4'b 0001, // index[376] PINMUX_WKUP_DETECTOR_REGWEN_4
- 4'b 0001, // index[377] PINMUX_WKUP_DETECTOR_REGWEN_5
- 4'b 0001, // index[378] PINMUX_WKUP_DETECTOR_REGWEN_6
- 4'b 0001, // index[379] PINMUX_WKUP_DETECTOR_REGWEN_7
- 4'b 0001, // index[380] PINMUX_WKUP_DETECTOR_EN_0
- 4'b 0001, // index[381] PINMUX_WKUP_DETECTOR_EN_1
- 4'b 0001, // index[382] PINMUX_WKUP_DETECTOR_EN_2
- 4'b 0001, // index[383] PINMUX_WKUP_DETECTOR_EN_3
- 4'b 0001, // index[384] PINMUX_WKUP_DETECTOR_EN_4
- 4'b 0001, // index[385] PINMUX_WKUP_DETECTOR_EN_5
- 4'b 0001, // index[386] PINMUX_WKUP_DETECTOR_EN_6
- 4'b 0001, // index[387] PINMUX_WKUP_DETECTOR_EN_7
- 4'b 0001, // index[388] PINMUX_WKUP_DETECTOR_0
- 4'b 0001, // index[389] PINMUX_WKUP_DETECTOR_1
- 4'b 0001, // index[390] PINMUX_WKUP_DETECTOR_2
- 4'b 0001, // index[391] PINMUX_WKUP_DETECTOR_3
- 4'b 0001, // index[392] PINMUX_WKUP_DETECTOR_4
- 4'b 0001, // index[393] PINMUX_WKUP_DETECTOR_5
- 4'b 0001, // index[394] PINMUX_WKUP_DETECTOR_6
- 4'b 0001, // index[395] PINMUX_WKUP_DETECTOR_7
- 4'b 0001, // index[396] PINMUX_WKUP_DETECTOR_CNT_TH_0
- 4'b 0001, // index[397] PINMUX_WKUP_DETECTOR_CNT_TH_1
- 4'b 0001, // index[398] PINMUX_WKUP_DETECTOR_CNT_TH_2
- 4'b 0001, // index[399] PINMUX_WKUP_DETECTOR_CNT_TH_3
- 4'b 0001, // index[400] PINMUX_WKUP_DETECTOR_CNT_TH_4
- 4'b 0001, // index[401] PINMUX_WKUP_DETECTOR_CNT_TH_5
- 4'b 0001, // index[402] PINMUX_WKUP_DETECTOR_CNT_TH_6
- 4'b 0001, // index[403] PINMUX_WKUP_DETECTOR_CNT_TH_7
- 4'b 0001, // index[404] PINMUX_WKUP_DETECTOR_PADSEL_0
- 4'b 0001, // index[405] PINMUX_WKUP_DETECTOR_PADSEL_1
- 4'b 0001, // index[406] PINMUX_WKUP_DETECTOR_PADSEL_2
- 4'b 0001, // index[407] PINMUX_WKUP_DETECTOR_PADSEL_3
- 4'b 0001, // index[408] PINMUX_WKUP_DETECTOR_PADSEL_4
- 4'b 0001, // index[409] PINMUX_WKUP_DETECTOR_PADSEL_5
- 4'b 0001, // index[410] PINMUX_WKUP_DETECTOR_PADSEL_6
- 4'b 0001, // index[411] PINMUX_WKUP_DETECTOR_PADSEL_7
- 4'b 0001 // index[412] PINMUX_WKUP_CAUSE
+ parameter logic [3:0] PINMUX_PERMIT [414] = '{
+ 4'b 0001, // index[ 0] PINMUX_ALERT_TEST
+ 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0
+ 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1
+ 4'b 0001, // index[ 3] PINMUX_MIO_PERIPH_INSEL_REGWEN_2
+ 4'b 0001, // index[ 4] PINMUX_MIO_PERIPH_INSEL_REGWEN_3
+ 4'b 0001, // index[ 5] PINMUX_MIO_PERIPH_INSEL_REGWEN_4
+ 4'b 0001, // index[ 6] PINMUX_MIO_PERIPH_INSEL_REGWEN_5
+ 4'b 0001, // index[ 7] PINMUX_MIO_PERIPH_INSEL_REGWEN_6
+ 4'b 0001, // index[ 8] PINMUX_MIO_PERIPH_INSEL_REGWEN_7
+ 4'b 0001, // index[ 9] PINMUX_MIO_PERIPH_INSEL_REGWEN_8
+ 4'b 0001, // index[ 10] PINMUX_MIO_PERIPH_INSEL_REGWEN_9
+ 4'b 0001, // index[ 11] PINMUX_MIO_PERIPH_INSEL_REGWEN_10
+ 4'b 0001, // index[ 12] PINMUX_MIO_PERIPH_INSEL_REGWEN_11
+ 4'b 0001, // index[ 13] PINMUX_MIO_PERIPH_INSEL_REGWEN_12
+ 4'b 0001, // index[ 14] PINMUX_MIO_PERIPH_INSEL_REGWEN_13
+ 4'b 0001, // index[ 15] PINMUX_MIO_PERIPH_INSEL_REGWEN_14
+ 4'b 0001, // index[ 16] PINMUX_MIO_PERIPH_INSEL_REGWEN_15
+ 4'b 0001, // index[ 17] PINMUX_MIO_PERIPH_INSEL_REGWEN_16
+ 4'b 0001, // index[ 18] PINMUX_MIO_PERIPH_INSEL_REGWEN_17
+ 4'b 0001, // index[ 19] PINMUX_MIO_PERIPH_INSEL_REGWEN_18
+ 4'b 0001, // index[ 20] PINMUX_MIO_PERIPH_INSEL_REGWEN_19
+ 4'b 0001, // index[ 21] PINMUX_MIO_PERIPH_INSEL_REGWEN_20
+ 4'b 0001, // index[ 22] PINMUX_MIO_PERIPH_INSEL_REGWEN_21
+ 4'b 0001, // index[ 23] PINMUX_MIO_PERIPH_INSEL_REGWEN_22
+ 4'b 0001, // index[ 24] PINMUX_MIO_PERIPH_INSEL_REGWEN_23
+ 4'b 0001, // index[ 25] PINMUX_MIO_PERIPH_INSEL_REGWEN_24
+ 4'b 0001, // index[ 26] PINMUX_MIO_PERIPH_INSEL_REGWEN_25
+ 4'b 0001, // index[ 27] PINMUX_MIO_PERIPH_INSEL_REGWEN_26
+ 4'b 0001, // index[ 28] PINMUX_MIO_PERIPH_INSEL_REGWEN_27
+ 4'b 0001, // index[ 29] PINMUX_MIO_PERIPH_INSEL_REGWEN_28
+ 4'b 0001, // index[ 30] PINMUX_MIO_PERIPH_INSEL_REGWEN_29
+ 4'b 0001, // index[ 31] PINMUX_MIO_PERIPH_INSEL_REGWEN_30
+ 4'b 0001, // index[ 32] PINMUX_MIO_PERIPH_INSEL_REGWEN_31
+ 4'b 0001, // index[ 33] PINMUX_MIO_PERIPH_INSEL_REGWEN_32
+ 4'b 0001, // index[ 34] PINMUX_MIO_PERIPH_INSEL_0
+ 4'b 0001, // index[ 35] PINMUX_MIO_PERIPH_INSEL_1
+ 4'b 0001, // index[ 36] PINMUX_MIO_PERIPH_INSEL_2
+ 4'b 0001, // index[ 37] PINMUX_MIO_PERIPH_INSEL_3
+ 4'b 0001, // index[ 38] PINMUX_MIO_PERIPH_INSEL_4
+ 4'b 0001, // index[ 39] PINMUX_MIO_PERIPH_INSEL_5
+ 4'b 0001, // index[ 40] PINMUX_MIO_PERIPH_INSEL_6
+ 4'b 0001, // index[ 41] PINMUX_MIO_PERIPH_INSEL_7
+ 4'b 0001, // index[ 42] PINMUX_MIO_PERIPH_INSEL_8
+ 4'b 0001, // index[ 43] PINMUX_MIO_PERIPH_INSEL_9
+ 4'b 0001, // index[ 44] PINMUX_MIO_PERIPH_INSEL_10
+ 4'b 0001, // index[ 45] PINMUX_MIO_PERIPH_INSEL_11
+ 4'b 0001, // index[ 46] PINMUX_MIO_PERIPH_INSEL_12
+ 4'b 0001, // index[ 47] PINMUX_MIO_PERIPH_INSEL_13
+ 4'b 0001, // index[ 48] PINMUX_MIO_PERIPH_INSEL_14
+ 4'b 0001, // index[ 49] PINMUX_MIO_PERIPH_INSEL_15
+ 4'b 0001, // index[ 50] PINMUX_MIO_PERIPH_INSEL_16
+ 4'b 0001, // index[ 51] PINMUX_MIO_PERIPH_INSEL_17
+ 4'b 0001, // index[ 52] PINMUX_MIO_PERIPH_INSEL_18
+ 4'b 0001, // index[ 53] PINMUX_MIO_PERIPH_INSEL_19
+ 4'b 0001, // index[ 54] PINMUX_MIO_PERIPH_INSEL_20
+ 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_21
+ 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_22
+ 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_23
+ 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_24
+ 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_25
+ 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_26
+ 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_27
+ 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_28
+ 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_29
+ 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_30
+ 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_31
+ 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_32
+ 4'b 0001, // index[ 67] PINMUX_MIO_OUTSEL_REGWEN_0
+ 4'b 0001, // index[ 68] PINMUX_MIO_OUTSEL_REGWEN_1
+ 4'b 0001, // index[ 69] PINMUX_MIO_OUTSEL_REGWEN_2
+ 4'b 0001, // index[ 70] PINMUX_MIO_OUTSEL_REGWEN_3
+ 4'b 0001, // index[ 71] PINMUX_MIO_OUTSEL_REGWEN_4
+ 4'b 0001, // index[ 72] PINMUX_MIO_OUTSEL_REGWEN_5
+ 4'b 0001, // index[ 73] PINMUX_MIO_OUTSEL_REGWEN_6
+ 4'b 0001, // index[ 74] PINMUX_MIO_OUTSEL_REGWEN_7
+ 4'b 0001, // index[ 75] PINMUX_MIO_OUTSEL_REGWEN_8
+ 4'b 0001, // index[ 76] PINMUX_MIO_OUTSEL_REGWEN_9
+ 4'b 0001, // index[ 77] PINMUX_MIO_OUTSEL_REGWEN_10
+ 4'b 0001, // index[ 78] PINMUX_MIO_OUTSEL_REGWEN_11
+ 4'b 0001, // index[ 79] PINMUX_MIO_OUTSEL_REGWEN_12
+ 4'b 0001, // index[ 80] PINMUX_MIO_OUTSEL_REGWEN_13
+ 4'b 0001, // index[ 81] PINMUX_MIO_OUTSEL_REGWEN_14
+ 4'b 0001, // index[ 82] PINMUX_MIO_OUTSEL_REGWEN_15
+ 4'b 0001, // index[ 83] PINMUX_MIO_OUTSEL_REGWEN_16
+ 4'b 0001, // index[ 84] PINMUX_MIO_OUTSEL_REGWEN_17
+ 4'b 0001, // index[ 85] PINMUX_MIO_OUTSEL_REGWEN_18
+ 4'b 0001, // index[ 86] PINMUX_MIO_OUTSEL_REGWEN_19
+ 4'b 0001, // index[ 87] PINMUX_MIO_OUTSEL_REGWEN_20
+ 4'b 0001, // index[ 88] PINMUX_MIO_OUTSEL_REGWEN_21
+ 4'b 0001, // index[ 89] PINMUX_MIO_OUTSEL_REGWEN_22
+ 4'b 0001, // index[ 90] PINMUX_MIO_OUTSEL_REGWEN_23
+ 4'b 0001, // index[ 91] PINMUX_MIO_OUTSEL_REGWEN_24
+ 4'b 0001, // index[ 92] PINMUX_MIO_OUTSEL_REGWEN_25
+ 4'b 0001, // index[ 93] PINMUX_MIO_OUTSEL_REGWEN_26
+ 4'b 0001, // index[ 94] PINMUX_MIO_OUTSEL_REGWEN_27
+ 4'b 0001, // index[ 95] PINMUX_MIO_OUTSEL_REGWEN_28
+ 4'b 0001, // index[ 96] PINMUX_MIO_OUTSEL_REGWEN_29
+ 4'b 0001, // index[ 97] PINMUX_MIO_OUTSEL_REGWEN_30
+ 4'b 0001, // index[ 98] PINMUX_MIO_OUTSEL_REGWEN_31
+ 4'b 0001, // index[ 99] PINMUX_MIO_OUTSEL_0
+ 4'b 0001, // index[100] PINMUX_MIO_OUTSEL_1
+ 4'b 0001, // index[101] PINMUX_MIO_OUTSEL_2
+ 4'b 0001, // index[102] PINMUX_MIO_OUTSEL_3
+ 4'b 0001, // index[103] PINMUX_MIO_OUTSEL_4
+ 4'b 0001, // index[104] PINMUX_MIO_OUTSEL_5
+ 4'b 0001, // index[105] PINMUX_MIO_OUTSEL_6
+ 4'b 0001, // index[106] PINMUX_MIO_OUTSEL_7
+ 4'b 0001, // index[107] PINMUX_MIO_OUTSEL_8
+ 4'b 0001, // index[108] PINMUX_MIO_OUTSEL_9
+ 4'b 0001, // index[109] PINMUX_MIO_OUTSEL_10
+ 4'b 0001, // index[110] PINMUX_MIO_OUTSEL_11
+ 4'b 0001, // index[111] PINMUX_MIO_OUTSEL_12
+ 4'b 0001, // index[112] PINMUX_MIO_OUTSEL_13
+ 4'b 0001, // index[113] PINMUX_MIO_OUTSEL_14
+ 4'b 0001, // index[114] PINMUX_MIO_OUTSEL_15
+ 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_16
+ 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_17
+ 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_18
+ 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_19
+ 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_20
+ 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_21
+ 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_22
+ 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_23
+ 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_24
+ 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_25
+ 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_26
+ 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_27
+ 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_28
+ 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_29
+ 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_30
+ 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_31
+ 4'b 0001, // index[131] PINMUX_MIO_PAD_ATTR_REGWEN_0
+ 4'b 0001, // index[132] PINMUX_MIO_PAD_ATTR_REGWEN_1
+ 4'b 0001, // index[133] PINMUX_MIO_PAD_ATTR_REGWEN_2
+ 4'b 0001, // index[134] PINMUX_MIO_PAD_ATTR_REGWEN_3
+ 4'b 0001, // index[135] PINMUX_MIO_PAD_ATTR_REGWEN_4
+ 4'b 0001, // index[136] PINMUX_MIO_PAD_ATTR_REGWEN_5
+ 4'b 0001, // index[137] PINMUX_MIO_PAD_ATTR_REGWEN_6
+ 4'b 0001, // index[138] PINMUX_MIO_PAD_ATTR_REGWEN_7
+ 4'b 0001, // index[139] PINMUX_MIO_PAD_ATTR_REGWEN_8
+ 4'b 0001, // index[140] PINMUX_MIO_PAD_ATTR_REGWEN_9
+ 4'b 0001, // index[141] PINMUX_MIO_PAD_ATTR_REGWEN_10
+ 4'b 0001, // index[142] PINMUX_MIO_PAD_ATTR_REGWEN_11
+ 4'b 0001, // index[143] PINMUX_MIO_PAD_ATTR_REGWEN_12
+ 4'b 0001, // index[144] PINMUX_MIO_PAD_ATTR_REGWEN_13
+ 4'b 0001, // index[145] PINMUX_MIO_PAD_ATTR_REGWEN_14
+ 4'b 0001, // index[146] PINMUX_MIO_PAD_ATTR_REGWEN_15
+ 4'b 0001, // index[147] PINMUX_MIO_PAD_ATTR_REGWEN_16
+ 4'b 0001, // index[148] PINMUX_MIO_PAD_ATTR_REGWEN_17
+ 4'b 0001, // index[149] PINMUX_MIO_PAD_ATTR_REGWEN_18
+ 4'b 0001, // index[150] PINMUX_MIO_PAD_ATTR_REGWEN_19
+ 4'b 0001, // index[151] PINMUX_MIO_PAD_ATTR_REGWEN_20
+ 4'b 0001, // index[152] PINMUX_MIO_PAD_ATTR_REGWEN_21
+ 4'b 0001, // index[153] PINMUX_MIO_PAD_ATTR_REGWEN_22
+ 4'b 0001, // index[154] PINMUX_MIO_PAD_ATTR_REGWEN_23
+ 4'b 0001, // index[155] PINMUX_MIO_PAD_ATTR_REGWEN_24
+ 4'b 0001, // index[156] PINMUX_MIO_PAD_ATTR_REGWEN_25
+ 4'b 0001, // index[157] PINMUX_MIO_PAD_ATTR_REGWEN_26
+ 4'b 0001, // index[158] PINMUX_MIO_PAD_ATTR_REGWEN_27
+ 4'b 0001, // index[159] PINMUX_MIO_PAD_ATTR_REGWEN_28
+ 4'b 0001, // index[160] PINMUX_MIO_PAD_ATTR_REGWEN_29
+ 4'b 0001, // index[161] PINMUX_MIO_PAD_ATTR_REGWEN_30
+ 4'b 0001, // index[162] PINMUX_MIO_PAD_ATTR_REGWEN_31
+ 4'b 0011, // index[163] PINMUX_MIO_PAD_ATTR_0
+ 4'b 0011, // index[164] PINMUX_MIO_PAD_ATTR_1
+ 4'b 0011, // index[165] PINMUX_MIO_PAD_ATTR_2
+ 4'b 0011, // index[166] PINMUX_MIO_PAD_ATTR_3
+ 4'b 0011, // index[167] PINMUX_MIO_PAD_ATTR_4
+ 4'b 0011, // index[168] PINMUX_MIO_PAD_ATTR_5
+ 4'b 0011, // index[169] PINMUX_MIO_PAD_ATTR_6
+ 4'b 0011, // index[170] PINMUX_MIO_PAD_ATTR_7
+ 4'b 0011, // index[171] PINMUX_MIO_PAD_ATTR_8
+ 4'b 0011, // index[172] PINMUX_MIO_PAD_ATTR_9
+ 4'b 0011, // index[173] PINMUX_MIO_PAD_ATTR_10
+ 4'b 0011, // index[174] PINMUX_MIO_PAD_ATTR_11
+ 4'b 0011, // index[175] PINMUX_MIO_PAD_ATTR_12
+ 4'b 0011, // index[176] PINMUX_MIO_PAD_ATTR_13
+ 4'b 0011, // index[177] PINMUX_MIO_PAD_ATTR_14
+ 4'b 0011, // index[178] PINMUX_MIO_PAD_ATTR_15
+ 4'b 0011, // index[179] PINMUX_MIO_PAD_ATTR_16
+ 4'b 0011, // index[180] PINMUX_MIO_PAD_ATTR_17
+ 4'b 0011, // index[181] PINMUX_MIO_PAD_ATTR_18
+ 4'b 0011, // index[182] PINMUX_MIO_PAD_ATTR_19
+ 4'b 0011, // index[183] PINMUX_MIO_PAD_ATTR_20
+ 4'b 0011, // index[184] PINMUX_MIO_PAD_ATTR_21
+ 4'b 0011, // index[185] PINMUX_MIO_PAD_ATTR_22
+ 4'b 0011, // index[186] PINMUX_MIO_PAD_ATTR_23
+ 4'b 0011, // index[187] PINMUX_MIO_PAD_ATTR_24
+ 4'b 0011, // index[188] PINMUX_MIO_PAD_ATTR_25
+ 4'b 0011, // index[189] PINMUX_MIO_PAD_ATTR_26
+ 4'b 0011, // index[190] PINMUX_MIO_PAD_ATTR_27
+ 4'b 0011, // index[191] PINMUX_MIO_PAD_ATTR_28
+ 4'b 0011, // index[192] PINMUX_MIO_PAD_ATTR_29
+ 4'b 0011, // index[193] PINMUX_MIO_PAD_ATTR_30
+ 4'b 0011, // index[194] PINMUX_MIO_PAD_ATTR_31
+ 4'b 0001, // index[195] PINMUX_DIO_PAD_ATTR_REGWEN_0
+ 4'b 0001, // index[196] PINMUX_DIO_PAD_ATTR_REGWEN_1
+ 4'b 0001, // index[197] PINMUX_DIO_PAD_ATTR_REGWEN_2
+ 4'b 0001, // index[198] PINMUX_DIO_PAD_ATTR_REGWEN_3
+ 4'b 0001, // index[199] PINMUX_DIO_PAD_ATTR_REGWEN_4
+ 4'b 0001, // index[200] PINMUX_DIO_PAD_ATTR_REGWEN_5
+ 4'b 0001, // index[201] PINMUX_DIO_PAD_ATTR_REGWEN_6
+ 4'b 0001, // index[202] PINMUX_DIO_PAD_ATTR_REGWEN_7
+ 4'b 0001, // index[203] PINMUX_DIO_PAD_ATTR_REGWEN_8
+ 4'b 0001, // index[204] PINMUX_DIO_PAD_ATTR_REGWEN_9
+ 4'b 0001, // index[205] PINMUX_DIO_PAD_ATTR_REGWEN_10
+ 4'b 0001, // index[206] PINMUX_DIO_PAD_ATTR_REGWEN_11
+ 4'b 0001, // index[207] PINMUX_DIO_PAD_ATTR_REGWEN_12
+ 4'b 0001, // index[208] PINMUX_DIO_PAD_ATTR_REGWEN_13
+ 4'b 0001, // index[209] PINMUX_DIO_PAD_ATTR_REGWEN_14
+ 4'b 0001, // index[210] PINMUX_DIO_PAD_ATTR_REGWEN_15
+ 4'b 0011, // index[211] PINMUX_DIO_PAD_ATTR_0
+ 4'b 0011, // index[212] PINMUX_DIO_PAD_ATTR_1
+ 4'b 0011, // index[213] PINMUX_DIO_PAD_ATTR_2
+ 4'b 0011, // index[214] PINMUX_DIO_PAD_ATTR_3
+ 4'b 0011, // index[215] PINMUX_DIO_PAD_ATTR_4
+ 4'b 0011, // index[216] PINMUX_DIO_PAD_ATTR_5
+ 4'b 0011, // index[217] PINMUX_DIO_PAD_ATTR_6
+ 4'b 0011, // index[218] PINMUX_DIO_PAD_ATTR_7
+ 4'b 0011, // index[219] PINMUX_DIO_PAD_ATTR_8
+ 4'b 0011, // index[220] PINMUX_DIO_PAD_ATTR_9
+ 4'b 0011, // index[221] PINMUX_DIO_PAD_ATTR_10
+ 4'b 0011, // index[222] PINMUX_DIO_PAD_ATTR_11
+ 4'b 0011, // index[223] PINMUX_DIO_PAD_ATTR_12
+ 4'b 0011, // index[224] PINMUX_DIO_PAD_ATTR_13
+ 4'b 0011, // index[225] PINMUX_DIO_PAD_ATTR_14
+ 4'b 0011, // index[226] PINMUX_DIO_PAD_ATTR_15
+ 4'b 1111, // index[227] PINMUX_MIO_PAD_SLEEP_STATUS
+ 4'b 0001, // index[228] PINMUX_MIO_PAD_SLEEP_REGWEN_0
+ 4'b 0001, // index[229] PINMUX_MIO_PAD_SLEEP_REGWEN_1
+ 4'b 0001, // index[230] PINMUX_MIO_PAD_SLEEP_REGWEN_2
+ 4'b 0001, // index[231] PINMUX_MIO_PAD_SLEEP_REGWEN_3
+ 4'b 0001, // index[232] PINMUX_MIO_PAD_SLEEP_REGWEN_4
+ 4'b 0001, // index[233] PINMUX_MIO_PAD_SLEEP_REGWEN_5
+ 4'b 0001, // index[234] PINMUX_MIO_PAD_SLEEP_REGWEN_6
+ 4'b 0001, // index[235] PINMUX_MIO_PAD_SLEEP_REGWEN_7
+ 4'b 0001, // index[236] PINMUX_MIO_PAD_SLEEP_REGWEN_8
+ 4'b 0001, // index[237] PINMUX_MIO_PAD_SLEEP_REGWEN_9
+ 4'b 0001, // index[238] PINMUX_MIO_PAD_SLEEP_REGWEN_10
+ 4'b 0001, // index[239] PINMUX_MIO_PAD_SLEEP_REGWEN_11
+ 4'b 0001, // index[240] PINMUX_MIO_PAD_SLEEP_REGWEN_12
+ 4'b 0001, // index[241] PINMUX_MIO_PAD_SLEEP_REGWEN_13
+ 4'b 0001, // index[242] PINMUX_MIO_PAD_SLEEP_REGWEN_14
+ 4'b 0001, // index[243] PINMUX_MIO_PAD_SLEEP_REGWEN_15
+ 4'b 0001, // index[244] PINMUX_MIO_PAD_SLEEP_REGWEN_16
+ 4'b 0001, // index[245] PINMUX_MIO_PAD_SLEEP_REGWEN_17
+ 4'b 0001, // index[246] PINMUX_MIO_PAD_SLEEP_REGWEN_18
+ 4'b 0001, // index[247] PINMUX_MIO_PAD_SLEEP_REGWEN_19
+ 4'b 0001, // index[248] PINMUX_MIO_PAD_SLEEP_REGWEN_20
+ 4'b 0001, // index[249] PINMUX_MIO_PAD_SLEEP_REGWEN_21
+ 4'b 0001, // index[250] PINMUX_MIO_PAD_SLEEP_REGWEN_22
+ 4'b 0001, // index[251] PINMUX_MIO_PAD_SLEEP_REGWEN_23
+ 4'b 0001, // index[252] PINMUX_MIO_PAD_SLEEP_REGWEN_24
+ 4'b 0001, // index[253] PINMUX_MIO_PAD_SLEEP_REGWEN_25
+ 4'b 0001, // index[254] PINMUX_MIO_PAD_SLEEP_REGWEN_26
+ 4'b 0001, // index[255] PINMUX_MIO_PAD_SLEEP_REGWEN_27
+ 4'b 0001, // index[256] PINMUX_MIO_PAD_SLEEP_REGWEN_28
+ 4'b 0001, // index[257] PINMUX_MIO_PAD_SLEEP_REGWEN_29
+ 4'b 0001, // index[258] PINMUX_MIO_PAD_SLEEP_REGWEN_30
+ 4'b 0001, // index[259] PINMUX_MIO_PAD_SLEEP_REGWEN_31
+ 4'b 0001, // index[260] PINMUX_MIO_PAD_SLEEP_EN_0
+ 4'b 0001, // index[261] PINMUX_MIO_PAD_SLEEP_EN_1
+ 4'b 0001, // index[262] PINMUX_MIO_PAD_SLEEP_EN_2
+ 4'b 0001, // index[263] PINMUX_MIO_PAD_SLEEP_EN_3
+ 4'b 0001, // index[264] PINMUX_MIO_PAD_SLEEP_EN_4
+ 4'b 0001, // index[265] PINMUX_MIO_PAD_SLEEP_EN_5
+ 4'b 0001, // index[266] PINMUX_MIO_PAD_SLEEP_EN_6
+ 4'b 0001, // index[267] PINMUX_MIO_PAD_SLEEP_EN_7
+ 4'b 0001, // index[268] PINMUX_MIO_PAD_SLEEP_EN_8
+ 4'b 0001, // index[269] PINMUX_MIO_PAD_SLEEP_EN_9
+ 4'b 0001, // index[270] PINMUX_MIO_PAD_SLEEP_EN_10
+ 4'b 0001, // index[271] PINMUX_MIO_PAD_SLEEP_EN_11
+ 4'b 0001, // index[272] PINMUX_MIO_PAD_SLEEP_EN_12
+ 4'b 0001, // index[273] PINMUX_MIO_PAD_SLEEP_EN_13
+ 4'b 0001, // index[274] PINMUX_MIO_PAD_SLEEP_EN_14
+ 4'b 0001, // index[275] PINMUX_MIO_PAD_SLEEP_EN_15
+ 4'b 0001, // index[276] PINMUX_MIO_PAD_SLEEP_EN_16
+ 4'b 0001, // index[277] PINMUX_MIO_PAD_SLEEP_EN_17
+ 4'b 0001, // index[278] PINMUX_MIO_PAD_SLEEP_EN_18
+ 4'b 0001, // index[279] PINMUX_MIO_PAD_SLEEP_EN_19
+ 4'b 0001, // index[280] PINMUX_MIO_PAD_SLEEP_EN_20
+ 4'b 0001, // index[281] PINMUX_MIO_PAD_SLEEP_EN_21
+ 4'b 0001, // index[282] PINMUX_MIO_PAD_SLEEP_EN_22
+ 4'b 0001, // index[283] PINMUX_MIO_PAD_SLEEP_EN_23
+ 4'b 0001, // index[284] PINMUX_MIO_PAD_SLEEP_EN_24
+ 4'b 0001, // index[285] PINMUX_MIO_PAD_SLEEP_EN_25
+ 4'b 0001, // index[286] PINMUX_MIO_PAD_SLEEP_EN_26
+ 4'b 0001, // index[287] PINMUX_MIO_PAD_SLEEP_EN_27
+ 4'b 0001, // index[288] PINMUX_MIO_PAD_SLEEP_EN_28
+ 4'b 0001, // index[289] PINMUX_MIO_PAD_SLEEP_EN_29
+ 4'b 0001, // index[290] PINMUX_MIO_PAD_SLEEP_EN_30
+ 4'b 0001, // index[291] PINMUX_MIO_PAD_SLEEP_EN_31
+ 4'b 0001, // index[292] PINMUX_MIO_PAD_SLEEP_MODE_0
+ 4'b 0001, // index[293] PINMUX_MIO_PAD_SLEEP_MODE_1
+ 4'b 0001, // index[294] PINMUX_MIO_PAD_SLEEP_MODE_2
+ 4'b 0001, // index[295] PINMUX_MIO_PAD_SLEEP_MODE_3
+ 4'b 0001, // index[296] PINMUX_MIO_PAD_SLEEP_MODE_4
+ 4'b 0001, // index[297] PINMUX_MIO_PAD_SLEEP_MODE_5
+ 4'b 0001, // index[298] PINMUX_MIO_PAD_SLEEP_MODE_6
+ 4'b 0001, // index[299] PINMUX_MIO_PAD_SLEEP_MODE_7
+ 4'b 0001, // index[300] PINMUX_MIO_PAD_SLEEP_MODE_8
+ 4'b 0001, // index[301] PINMUX_MIO_PAD_SLEEP_MODE_9
+ 4'b 0001, // index[302] PINMUX_MIO_PAD_SLEEP_MODE_10
+ 4'b 0001, // index[303] PINMUX_MIO_PAD_SLEEP_MODE_11
+ 4'b 0001, // index[304] PINMUX_MIO_PAD_SLEEP_MODE_12
+ 4'b 0001, // index[305] PINMUX_MIO_PAD_SLEEP_MODE_13
+ 4'b 0001, // index[306] PINMUX_MIO_PAD_SLEEP_MODE_14
+ 4'b 0001, // index[307] PINMUX_MIO_PAD_SLEEP_MODE_15
+ 4'b 0001, // index[308] PINMUX_MIO_PAD_SLEEP_MODE_16
+ 4'b 0001, // index[309] PINMUX_MIO_PAD_SLEEP_MODE_17
+ 4'b 0001, // index[310] PINMUX_MIO_PAD_SLEEP_MODE_18
+ 4'b 0001, // index[311] PINMUX_MIO_PAD_SLEEP_MODE_19
+ 4'b 0001, // index[312] PINMUX_MIO_PAD_SLEEP_MODE_20
+ 4'b 0001, // index[313] PINMUX_MIO_PAD_SLEEP_MODE_21
+ 4'b 0001, // index[314] PINMUX_MIO_PAD_SLEEP_MODE_22
+ 4'b 0001, // index[315] PINMUX_MIO_PAD_SLEEP_MODE_23
+ 4'b 0001, // index[316] PINMUX_MIO_PAD_SLEEP_MODE_24
+ 4'b 0001, // index[317] PINMUX_MIO_PAD_SLEEP_MODE_25
+ 4'b 0001, // index[318] PINMUX_MIO_PAD_SLEEP_MODE_26
+ 4'b 0001, // index[319] PINMUX_MIO_PAD_SLEEP_MODE_27
+ 4'b 0001, // index[320] PINMUX_MIO_PAD_SLEEP_MODE_28
+ 4'b 0001, // index[321] PINMUX_MIO_PAD_SLEEP_MODE_29
+ 4'b 0001, // index[322] PINMUX_MIO_PAD_SLEEP_MODE_30
+ 4'b 0001, // index[323] PINMUX_MIO_PAD_SLEEP_MODE_31
+ 4'b 0011, // index[324] PINMUX_DIO_PAD_SLEEP_STATUS
+ 4'b 0001, // index[325] PINMUX_DIO_PAD_SLEEP_REGWEN_0
+ 4'b 0001, // index[326] PINMUX_DIO_PAD_SLEEP_REGWEN_1
+ 4'b 0001, // index[327] PINMUX_DIO_PAD_SLEEP_REGWEN_2
+ 4'b 0001, // index[328] PINMUX_DIO_PAD_SLEEP_REGWEN_3
+ 4'b 0001, // index[329] PINMUX_DIO_PAD_SLEEP_REGWEN_4
+ 4'b 0001, // index[330] PINMUX_DIO_PAD_SLEEP_REGWEN_5
+ 4'b 0001, // index[331] PINMUX_DIO_PAD_SLEEP_REGWEN_6
+ 4'b 0001, // index[332] PINMUX_DIO_PAD_SLEEP_REGWEN_7
+ 4'b 0001, // index[333] PINMUX_DIO_PAD_SLEEP_REGWEN_8
+ 4'b 0001, // index[334] PINMUX_DIO_PAD_SLEEP_REGWEN_9
+ 4'b 0001, // index[335] PINMUX_DIO_PAD_SLEEP_REGWEN_10
+ 4'b 0001, // index[336] PINMUX_DIO_PAD_SLEEP_REGWEN_11
+ 4'b 0001, // index[337] PINMUX_DIO_PAD_SLEEP_REGWEN_12
+ 4'b 0001, // index[338] PINMUX_DIO_PAD_SLEEP_REGWEN_13
+ 4'b 0001, // index[339] PINMUX_DIO_PAD_SLEEP_REGWEN_14
+ 4'b 0001, // index[340] PINMUX_DIO_PAD_SLEEP_REGWEN_15
+ 4'b 0001, // index[341] PINMUX_DIO_PAD_SLEEP_EN_0
+ 4'b 0001, // index[342] PINMUX_DIO_PAD_SLEEP_EN_1
+ 4'b 0001, // index[343] PINMUX_DIO_PAD_SLEEP_EN_2
+ 4'b 0001, // index[344] PINMUX_DIO_PAD_SLEEP_EN_3
+ 4'b 0001, // index[345] PINMUX_DIO_PAD_SLEEP_EN_4
+ 4'b 0001, // index[346] PINMUX_DIO_PAD_SLEEP_EN_5
+ 4'b 0001, // index[347] PINMUX_DIO_PAD_SLEEP_EN_6
+ 4'b 0001, // index[348] PINMUX_DIO_PAD_SLEEP_EN_7
+ 4'b 0001, // index[349] PINMUX_DIO_PAD_SLEEP_EN_8
+ 4'b 0001, // index[350] PINMUX_DIO_PAD_SLEEP_EN_9
+ 4'b 0001, // index[351] PINMUX_DIO_PAD_SLEEP_EN_10
+ 4'b 0001, // index[352] PINMUX_DIO_PAD_SLEEP_EN_11
+ 4'b 0001, // index[353] PINMUX_DIO_PAD_SLEEP_EN_12
+ 4'b 0001, // index[354] PINMUX_DIO_PAD_SLEEP_EN_13
+ 4'b 0001, // index[355] PINMUX_DIO_PAD_SLEEP_EN_14
+ 4'b 0001, // index[356] PINMUX_DIO_PAD_SLEEP_EN_15
+ 4'b 0001, // index[357] PINMUX_DIO_PAD_SLEEP_MODE_0
+ 4'b 0001, // index[358] PINMUX_DIO_PAD_SLEEP_MODE_1
+ 4'b 0001, // index[359] PINMUX_DIO_PAD_SLEEP_MODE_2
+ 4'b 0001, // index[360] PINMUX_DIO_PAD_SLEEP_MODE_3
+ 4'b 0001, // index[361] PINMUX_DIO_PAD_SLEEP_MODE_4
+ 4'b 0001, // index[362] PINMUX_DIO_PAD_SLEEP_MODE_5
+ 4'b 0001, // index[363] PINMUX_DIO_PAD_SLEEP_MODE_6
+ 4'b 0001, // index[364] PINMUX_DIO_PAD_SLEEP_MODE_7
+ 4'b 0001, // index[365] PINMUX_DIO_PAD_SLEEP_MODE_8
+ 4'b 0001, // index[366] PINMUX_DIO_PAD_SLEEP_MODE_9
+ 4'b 0001, // index[367] PINMUX_DIO_PAD_SLEEP_MODE_10
+ 4'b 0001, // index[368] PINMUX_DIO_PAD_SLEEP_MODE_11
+ 4'b 0001, // index[369] PINMUX_DIO_PAD_SLEEP_MODE_12
+ 4'b 0001, // index[370] PINMUX_DIO_PAD_SLEEP_MODE_13
+ 4'b 0001, // index[371] PINMUX_DIO_PAD_SLEEP_MODE_14
+ 4'b 0001, // index[372] PINMUX_DIO_PAD_SLEEP_MODE_15
+ 4'b 0001, // index[373] PINMUX_WKUP_DETECTOR_REGWEN_0
+ 4'b 0001, // index[374] PINMUX_WKUP_DETECTOR_REGWEN_1
+ 4'b 0001, // index[375] PINMUX_WKUP_DETECTOR_REGWEN_2
+ 4'b 0001, // index[376] PINMUX_WKUP_DETECTOR_REGWEN_3
+ 4'b 0001, // index[377] PINMUX_WKUP_DETECTOR_REGWEN_4
+ 4'b 0001, // index[378] PINMUX_WKUP_DETECTOR_REGWEN_5
+ 4'b 0001, // index[379] PINMUX_WKUP_DETECTOR_REGWEN_6
+ 4'b 0001, // index[380] PINMUX_WKUP_DETECTOR_REGWEN_7
+ 4'b 0001, // index[381] PINMUX_WKUP_DETECTOR_EN_0
+ 4'b 0001, // index[382] PINMUX_WKUP_DETECTOR_EN_1
+ 4'b 0001, // index[383] PINMUX_WKUP_DETECTOR_EN_2
+ 4'b 0001, // index[384] PINMUX_WKUP_DETECTOR_EN_3
+ 4'b 0001, // index[385] PINMUX_WKUP_DETECTOR_EN_4
+ 4'b 0001, // index[386] PINMUX_WKUP_DETECTOR_EN_5
+ 4'b 0001, // index[387] PINMUX_WKUP_DETECTOR_EN_6
+ 4'b 0001, // index[388] PINMUX_WKUP_DETECTOR_EN_7
+ 4'b 0001, // index[389] PINMUX_WKUP_DETECTOR_0
+ 4'b 0001, // index[390] PINMUX_WKUP_DETECTOR_1
+ 4'b 0001, // index[391] PINMUX_WKUP_DETECTOR_2
+ 4'b 0001, // index[392] PINMUX_WKUP_DETECTOR_3
+ 4'b 0001, // index[393] PINMUX_WKUP_DETECTOR_4
+ 4'b 0001, // index[394] PINMUX_WKUP_DETECTOR_5
+ 4'b 0001, // index[395] PINMUX_WKUP_DETECTOR_6
+ 4'b 0001, // index[396] PINMUX_WKUP_DETECTOR_7
+ 4'b 0001, // index[397] PINMUX_WKUP_DETECTOR_CNT_TH_0
+ 4'b 0001, // index[398] PINMUX_WKUP_DETECTOR_CNT_TH_1
+ 4'b 0001, // index[399] PINMUX_WKUP_DETECTOR_CNT_TH_2
+ 4'b 0001, // index[400] PINMUX_WKUP_DETECTOR_CNT_TH_3
+ 4'b 0001, // index[401] PINMUX_WKUP_DETECTOR_CNT_TH_4
+ 4'b 0001, // index[402] PINMUX_WKUP_DETECTOR_CNT_TH_5
+ 4'b 0001, // index[403] PINMUX_WKUP_DETECTOR_CNT_TH_6
+ 4'b 0001, // index[404] PINMUX_WKUP_DETECTOR_CNT_TH_7
+ 4'b 0001, // index[405] PINMUX_WKUP_DETECTOR_PADSEL_0
+ 4'b 0001, // index[406] PINMUX_WKUP_DETECTOR_PADSEL_1
+ 4'b 0001, // index[407] PINMUX_WKUP_DETECTOR_PADSEL_2
+ 4'b 0001, // index[408] PINMUX_WKUP_DETECTOR_PADSEL_3
+ 4'b 0001, // index[409] PINMUX_WKUP_DETECTOR_PADSEL_4
+ 4'b 0001, // index[410] PINMUX_WKUP_DETECTOR_PADSEL_5
+ 4'b 0001, // index[411] PINMUX_WKUP_DETECTOR_PADSEL_6
+ 4'b 0001, // index[412] PINMUX_WKUP_DETECTOR_PADSEL_7
+ 4'b 0001 // index[413] PINMUX_WKUP_CAUSE
};
endpackage
diff --git a/hw/ip/pinmux/rtl/pinmux_reg_top.sv b/hw/ip/pinmux/rtl/pinmux_reg_top.sv
index 4fb1823..6cd064a 100644
--- a/hw/ip/pinmux/rtl/pinmux_reg_top.sv
+++ b/hw/ip/pinmux/rtl/pinmux_reg_top.sv
@@ -104,6 +104,8 @@
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
+ logic alert_test_wd;
+ logic alert_test_we;
logic mio_periph_insel_regwen_0_qs;
logic mio_periph_insel_regwen_0_wd;
logic mio_periph_insel_regwen_0_we;
@@ -1608,6 +1610,22 @@
logic wkup_cause_cause_7_re;
// Register instances
+ // R[alert_test]: V(True)
+
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.qe),
+ .q (reg2hw.alert_test.q),
+ .qs ()
+ );
+
+
// Subregister 0 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_0]: V(False)
@@ -14005,422 +14023,423 @@
- logic [412:0] addr_hit;
+ logic [413:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[ 0] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET);
- addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET);
- addr_hit[ 2] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET);
- addr_hit[ 3] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET);
- addr_hit[ 4] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET);
- addr_hit[ 5] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET);
- addr_hit[ 6] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET);
- addr_hit[ 7] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET);
- addr_hit[ 8] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET);
- addr_hit[ 9] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET);
- addr_hit[ 10] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET);
- addr_hit[ 11] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET);
- addr_hit[ 12] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET);
- addr_hit[ 13] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET);
- addr_hit[ 14] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET);
- addr_hit[ 15] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET);
- addr_hit[ 16] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET);
- addr_hit[ 17] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET);
- addr_hit[ 18] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET);
- addr_hit[ 19] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET);
- addr_hit[ 20] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET);
- addr_hit[ 21] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET);
- addr_hit[ 22] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET);
- addr_hit[ 23] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET);
- addr_hit[ 24] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET);
- addr_hit[ 25] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET);
- addr_hit[ 26] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET);
- addr_hit[ 27] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET);
- addr_hit[ 28] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET);
- addr_hit[ 29] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET);
- addr_hit[ 30] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET);
- addr_hit[ 31] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET);
- addr_hit[ 32] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET);
- addr_hit[ 33] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET);
- addr_hit[ 34] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET);
- addr_hit[ 35] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET);
- addr_hit[ 36] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET);
- addr_hit[ 37] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET);
- addr_hit[ 38] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET);
- addr_hit[ 39] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET);
- addr_hit[ 40] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET);
- addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET);
- addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET);
- addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET);
- addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET);
- addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET);
- addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET);
- addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET);
- addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET);
- addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET);
- addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET);
- addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET);
- addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET);
- addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET);
- addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET);
- addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET);
- addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET);
- addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET);
- addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET);
- addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET);
- addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET);
- addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET);
- addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET);
- addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET);
- addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET);
- addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET);
- addr_hit[ 66] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET);
- addr_hit[ 67] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET);
- addr_hit[ 68] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET);
- addr_hit[ 69] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET);
- addr_hit[ 70] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET);
- addr_hit[ 71] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET);
- addr_hit[ 72] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET);
- addr_hit[ 73] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET);
- addr_hit[ 74] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET);
- addr_hit[ 75] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET);
- addr_hit[ 76] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET);
- addr_hit[ 77] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET);
- addr_hit[ 78] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET);
- addr_hit[ 79] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET);
- addr_hit[ 80] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET);
- addr_hit[ 81] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET);
- addr_hit[ 82] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET);
- addr_hit[ 83] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET);
- addr_hit[ 84] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET);
- addr_hit[ 85] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET);
- addr_hit[ 86] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET);
- addr_hit[ 87] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET);
- addr_hit[ 88] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET);
- addr_hit[ 89] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET);
- addr_hit[ 90] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET);
- addr_hit[ 91] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET);
- addr_hit[ 92] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET);
- addr_hit[ 93] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET);
- addr_hit[ 94] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET);
- addr_hit[ 95] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET);
- addr_hit[ 96] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET);
- addr_hit[ 97] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET);
- addr_hit[ 98] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
- addr_hit[ 99] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
- addr_hit[100] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
- addr_hit[101] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
- addr_hit[102] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
- addr_hit[103] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
- addr_hit[104] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
- addr_hit[105] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
- addr_hit[106] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
- addr_hit[107] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
- addr_hit[108] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
- addr_hit[109] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
- addr_hit[110] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
- addr_hit[111] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
- addr_hit[112] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
- addr_hit[113] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
- addr_hit[114] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
- addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
- addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
- addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
- addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
- addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
- addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
- addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
- addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
- addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
- addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
- addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
- addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
- addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
- addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
- addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
- addr_hit[130] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
- addr_hit[131] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
- addr_hit[132] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
- addr_hit[133] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
- addr_hit[134] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
- addr_hit[135] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
- addr_hit[136] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
- addr_hit[137] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
- addr_hit[138] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
- addr_hit[139] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
- addr_hit[140] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
- addr_hit[141] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
- addr_hit[142] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
- addr_hit[143] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
- addr_hit[144] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
- addr_hit[145] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
- addr_hit[146] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
- addr_hit[147] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
- addr_hit[148] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
- addr_hit[149] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
- addr_hit[150] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
- addr_hit[151] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
- addr_hit[152] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
- addr_hit[153] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
- addr_hit[154] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
- addr_hit[155] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
- addr_hit[156] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
- addr_hit[157] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
- addr_hit[158] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
- addr_hit[159] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
- addr_hit[160] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
- addr_hit[161] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
- addr_hit[162] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
- addr_hit[163] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
- addr_hit[164] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
- addr_hit[165] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
- addr_hit[166] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
- addr_hit[167] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
- addr_hit[168] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
- addr_hit[169] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
- addr_hit[170] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
- addr_hit[171] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
- addr_hit[172] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
- addr_hit[173] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
- addr_hit[174] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
- addr_hit[175] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
- addr_hit[176] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
- addr_hit[177] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
- addr_hit[178] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
- addr_hit[179] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
- addr_hit[180] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
- addr_hit[181] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
- addr_hit[182] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
- addr_hit[183] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
- addr_hit[184] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
- addr_hit[185] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
- addr_hit[186] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
- addr_hit[187] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
- addr_hit[188] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
- addr_hit[189] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
- addr_hit[190] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
- addr_hit[191] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
- addr_hit[192] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
- addr_hit[193] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
- addr_hit[194] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
- addr_hit[195] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
- addr_hit[196] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
- addr_hit[197] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
- addr_hit[198] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
- addr_hit[199] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
- addr_hit[200] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
- addr_hit[201] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
- addr_hit[202] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
- addr_hit[203] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
- addr_hit[204] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
- addr_hit[205] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
- addr_hit[206] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
- addr_hit[207] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
- addr_hit[208] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
- addr_hit[209] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET);
- addr_hit[210] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
- addr_hit[211] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
- addr_hit[212] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
- addr_hit[213] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
- addr_hit[214] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
- addr_hit[215] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
- addr_hit[216] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
- addr_hit[217] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
- addr_hit[218] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
- addr_hit[219] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
- addr_hit[220] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
- addr_hit[221] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
- addr_hit[222] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
- addr_hit[223] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
- addr_hit[224] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
- addr_hit[225] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET);
- addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET);
- addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
- addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
- addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
- addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
- addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
- addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
- addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
- addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
- addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
- addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
- addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
- addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
- addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
- addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
- addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
- addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
- addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
- addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
- addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
- addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
- addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
- addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
- addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
- addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
- addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
- addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
- addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
- addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
- addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
- addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
- addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
- addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
- addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
- addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
- addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
- addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
- addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
- addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
- addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
- addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
- addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
- addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
- addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
- addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
- addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
- addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
- addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
- addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
- addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
- addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
- addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
- addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
- addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
- addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
- addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
- addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
- addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
- addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
- addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
- addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
- addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
- addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
- addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
- addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
- addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
- addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
- addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
- addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
- addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
- addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
- addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
- addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
- addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
- addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
- addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
- addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
- addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
- addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
- addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
- addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
- addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
- addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
- addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
- addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
- addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
- addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
- addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
- addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
- addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
- addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
- addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
- addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
- addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
- addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
- addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
- addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
- addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
- addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
- addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
- addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
- addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
- addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
- addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
- addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
- addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
- addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
- addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
- addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
- addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
- addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
- addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
- addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
- addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET);
- addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
- addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
- addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
- addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
- addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
- addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
- addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
- addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
- addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
- addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
- addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
- addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
- addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
- addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
- addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
- addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET);
- addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
- addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
- addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
- addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
- addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
- addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
- addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
- addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
- addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
- addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
- addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
- addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
- addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
- addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
- addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
- addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET);
- addr_hit[372] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
- addr_hit[373] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
- addr_hit[374] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
- addr_hit[375] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
- addr_hit[376] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
- addr_hit[377] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
- addr_hit[378] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
- addr_hit[379] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
- addr_hit[380] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
- addr_hit[381] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
- addr_hit[382] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
- addr_hit[383] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
- addr_hit[384] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
- addr_hit[385] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
- addr_hit[386] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
- addr_hit[387] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
- addr_hit[388] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
- addr_hit[389] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
- addr_hit[390] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
- addr_hit[391] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
- addr_hit[392] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
- addr_hit[393] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
- addr_hit[394] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
- addr_hit[395] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
- addr_hit[396] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
- addr_hit[397] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
- addr_hit[398] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
- addr_hit[399] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
- addr_hit[400] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
- addr_hit[401] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
- addr_hit[402] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
- addr_hit[403] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
- addr_hit[404] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
- addr_hit[405] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
- addr_hit[406] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
- addr_hit[407] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
- addr_hit[408] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
- addr_hit[409] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
- addr_hit[410] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
- addr_hit[411] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
- addr_hit[412] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
+ addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET);
+ addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET);
+ addr_hit[ 2] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET);
+ addr_hit[ 3] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET);
+ addr_hit[ 4] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET);
+ addr_hit[ 5] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET);
+ addr_hit[ 6] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET);
+ addr_hit[ 7] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET);
+ addr_hit[ 8] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET);
+ addr_hit[ 9] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET);
+ addr_hit[ 10] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET);
+ addr_hit[ 11] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET);
+ addr_hit[ 12] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET);
+ addr_hit[ 13] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET);
+ addr_hit[ 14] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET);
+ addr_hit[ 15] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET);
+ addr_hit[ 16] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET);
+ addr_hit[ 17] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET);
+ addr_hit[ 18] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET);
+ addr_hit[ 19] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET);
+ addr_hit[ 20] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET);
+ addr_hit[ 21] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET);
+ addr_hit[ 22] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET);
+ addr_hit[ 23] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET);
+ addr_hit[ 24] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET);
+ addr_hit[ 25] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET);
+ addr_hit[ 26] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET);
+ addr_hit[ 27] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET);
+ addr_hit[ 28] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET);
+ addr_hit[ 29] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET);
+ addr_hit[ 30] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET);
+ addr_hit[ 31] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET);
+ addr_hit[ 32] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET);
+ addr_hit[ 33] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET);
+ addr_hit[ 34] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET);
+ addr_hit[ 35] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET);
+ addr_hit[ 36] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET);
+ addr_hit[ 37] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET);
+ addr_hit[ 38] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET);
+ addr_hit[ 39] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET);
+ addr_hit[ 40] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET);
+ addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET);
+ addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET);
+ addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET);
+ addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET);
+ addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET);
+ addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET);
+ addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET);
+ addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET);
+ addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET);
+ addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET);
+ addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET);
+ addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET);
+ addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET);
+ addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET);
+ addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET);
+ addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET);
+ addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET);
+ addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET);
+ addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET);
+ addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET);
+ addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET);
+ addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET);
+ addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET);
+ addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET);
+ addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET);
+ addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET);
+ addr_hit[ 67] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET);
+ addr_hit[ 68] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET);
+ addr_hit[ 69] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET);
+ addr_hit[ 70] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET);
+ addr_hit[ 71] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET);
+ addr_hit[ 72] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET);
+ addr_hit[ 73] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET);
+ addr_hit[ 74] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET);
+ addr_hit[ 75] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET);
+ addr_hit[ 76] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET);
+ addr_hit[ 77] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET);
+ addr_hit[ 78] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET);
+ addr_hit[ 79] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET);
+ addr_hit[ 80] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET);
+ addr_hit[ 81] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET);
+ addr_hit[ 82] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET);
+ addr_hit[ 83] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET);
+ addr_hit[ 84] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET);
+ addr_hit[ 85] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET);
+ addr_hit[ 86] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET);
+ addr_hit[ 87] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET);
+ addr_hit[ 88] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET);
+ addr_hit[ 89] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET);
+ addr_hit[ 90] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET);
+ addr_hit[ 91] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET);
+ addr_hit[ 92] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET);
+ addr_hit[ 93] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET);
+ addr_hit[ 94] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET);
+ addr_hit[ 95] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET);
+ addr_hit[ 96] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET);
+ addr_hit[ 97] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET);
+ addr_hit[ 98] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET);
+ addr_hit[ 99] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
+ addr_hit[100] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
+ addr_hit[101] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
+ addr_hit[102] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
+ addr_hit[103] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
+ addr_hit[104] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
+ addr_hit[105] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
+ addr_hit[106] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
+ addr_hit[107] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
+ addr_hit[108] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
+ addr_hit[109] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
+ addr_hit[110] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
+ addr_hit[111] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
+ addr_hit[112] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
+ addr_hit[113] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
+ addr_hit[114] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
+ addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
+ addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
+ addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
+ addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
+ addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
+ addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
+ addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
+ addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
+ addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
+ addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
+ addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
+ addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
+ addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
+ addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
+ addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
+ addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
+ addr_hit[131] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
+ addr_hit[132] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
+ addr_hit[133] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
+ addr_hit[134] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
+ addr_hit[135] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
+ addr_hit[136] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
+ addr_hit[137] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
+ addr_hit[138] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
+ addr_hit[139] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
+ addr_hit[140] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
+ addr_hit[141] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
+ addr_hit[142] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
+ addr_hit[143] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
+ addr_hit[144] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
+ addr_hit[145] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
+ addr_hit[146] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
+ addr_hit[147] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
+ addr_hit[148] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
+ addr_hit[149] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
+ addr_hit[150] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
+ addr_hit[151] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
+ addr_hit[152] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
+ addr_hit[153] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
+ addr_hit[154] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
+ addr_hit[155] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
+ addr_hit[156] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
+ addr_hit[157] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
+ addr_hit[158] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
+ addr_hit[159] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
+ addr_hit[160] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
+ addr_hit[161] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
+ addr_hit[162] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
+ addr_hit[163] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
+ addr_hit[164] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
+ addr_hit[165] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
+ addr_hit[166] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
+ addr_hit[167] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
+ addr_hit[168] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
+ addr_hit[169] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
+ addr_hit[170] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
+ addr_hit[171] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
+ addr_hit[172] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
+ addr_hit[173] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
+ addr_hit[174] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
+ addr_hit[175] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
+ addr_hit[176] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
+ addr_hit[177] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
+ addr_hit[178] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
+ addr_hit[179] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
+ addr_hit[180] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
+ addr_hit[181] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
+ addr_hit[182] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
+ addr_hit[183] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
+ addr_hit[184] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
+ addr_hit[185] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
+ addr_hit[186] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
+ addr_hit[187] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
+ addr_hit[188] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
+ addr_hit[189] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
+ addr_hit[190] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
+ addr_hit[191] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
+ addr_hit[192] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
+ addr_hit[193] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
+ addr_hit[194] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
+ addr_hit[195] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
+ addr_hit[196] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
+ addr_hit[197] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
+ addr_hit[198] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
+ addr_hit[199] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
+ addr_hit[200] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
+ addr_hit[201] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
+ addr_hit[202] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
+ addr_hit[203] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
+ addr_hit[204] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
+ addr_hit[205] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
+ addr_hit[206] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
+ addr_hit[207] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
+ addr_hit[208] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
+ addr_hit[209] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
+ addr_hit[210] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET);
+ addr_hit[211] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
+ addr_hit[212] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
+ addr_hit[213] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
+ addr_hit[214] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
+ addr_hit[215] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
+ addr_hit[216] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
+ addr_hit[217] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
+ addr_hit[218] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
+ addr_hit[219] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
+ addr_hit[220] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
+ addr_hit[221] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
+ addr_hit[222] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
+ addr_hit[223] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
+ addr_hit[224] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
+ addr_hit[225] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
+ addr_hit[226] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET);
+ addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET);
+ addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
+ addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
+ addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
+ addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
+ addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
+ addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
+ addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
+ addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
+ addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
+ addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
+ addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
+ addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
+ addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
+ addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
+ addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
+ addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
+ addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
+ addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
+ addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
+ addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
+ addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
+ addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
+ addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
+ addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
+ addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
+ addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
+ addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
+ addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
+ addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
+ addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
+ addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
+ addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
+ addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
+ addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
+ addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
+ addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
+ addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
+ addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
+ addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
+ addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
+ addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
+ addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
+ addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
+ addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
+ addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
+ addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
+ addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
+ addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
+ addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
+ addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
+ addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
+ addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
+ addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
+ addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
+ addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
+ addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
+ addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
+ addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
+ addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
+ addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
+ addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
+ addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
+ addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
+ addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
+ addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
+ addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
+ addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
+ addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
+ addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
+ addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
+ addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
+ addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
+ addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
+ addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
+ addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
+ addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
+ addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
+ addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
+ addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
+ addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
+ addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
+ addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
+ addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
+ addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
+ addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
+ addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
+ addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
+ addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
+ addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
+ addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
+ addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
+ addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
+ addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
+ addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
+ addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
+ addr_hit[323] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
+ addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
+ addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
+ addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
+ addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
+ addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
+ addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
+ addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
+ addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
+ addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
+ addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
+ addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
+ addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
+ addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
+ addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
+ addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
+ addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
+ addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET);
+ addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
+ addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
+ addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
+ addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
+ addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
+ addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
+ addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
+ addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
+ addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
+ addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
+ addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
+ addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
+ addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
+ addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
+ addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
+ addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET);
+ addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
+ addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
+ addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
+ addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
+ addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
+ addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
+ addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
+ addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
+ addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
+ addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
+ addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
+ addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
+ addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
+ addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
+ addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
+ addr_hit[372] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET);
+ addr_hit[373] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
+ addr_hit[374] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
+ addr_hit[375] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
+ addr_hit[376] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
+ addr_hit[377] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
+ addr_hit[378] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
+ addr_hit[379] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
+ addr_hit[380] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
+ addr_hit[381] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
+ addr_hit[382] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
+ addr_hit[383] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
+ addr_hit[384] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
+ addr_hit[385] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
+ addr_hit[386] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
+ addr_hit[387] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
+ addr_hit[388] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
+ addr_hit[389] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
+ addr_hit[390] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
+ addr_hit[391] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
+ addr_hit[392] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
+ addr_hit[393] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
+ addr_hit[394] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
+ addr_hit[395] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
+ addr_hit[396] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
+ addr_hit[397] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
+ addr_hit[398] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
+ addr_hit[399] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
+ addr_hit[400] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
+ addr_hit[401] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
+ addr_hit[402] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
+ addr_hit[403] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
+ addr_hit[404] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
+ addr_hit[405] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
+ addr_hit[406] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
+ addr_hit[407] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
+ addr_hit[408] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
+ addr_hit[409] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
+ addr_hit[410] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
+ addr_hit[411] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
+ addr_hit[412] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
+ addr_hit[413] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -14840,2420 +14859,2428 @@
(addr_hit[409] & (|(PINMUX_PERMIT[409] & ~reg_be))) |
(addr_hit[410] & (|(PINMUX_PERMIT[410] & ~reg_be))) |
(addr_hit[411] & (|(PINMUX_PERMIT[411] & ~reg_be))) |
- (addr_hit[412] & (|(PINMUX_PERMIT[412] & ~reg_be)))));
+ (addr_hit[412] & (|(PINMUX_PERMIT[412] & ~reg_be))) |
+ (addr_hit[413] & (|(PINMUX_PERMIT[413] & ~reg_be)))));
end
- assign mio_periph_insel_regwen_0_we = addr_hit[0] & reg_we & !reg_error;
+ assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
+ assign alert_test_wd = reg_wdata[0];
+
+ assign mio_periph_insel_regwen_0_we = addr_hit[1] & reg_we & !reg_error;
assign mio_periph_insel_regwen_0_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_1_we = addr_hit[1] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_1_we = addr_hit[2] & reg_we & !reg_error;
assign mio_periph_insel_regwen_1_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_2_we = addr_hit[2] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_2_we = addr_hit[3] & reg_we & !reg_error;
assign mio_periph_insel_regwen_2_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_3_we = addr_hit[3] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_3_we = addr_hit[4] & reg_we & !reg_error;
assign mio_periph_insel_regwen_3_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_4_we = addr_hit[4] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_4_we = addr_hit[5] & reg_we & !reg_error;
assign mio_periph_insel_regwen_4_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_5_we = addr_hit[5] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_5_we = addr_hit[6] & reg_we & !reg_error;
assign mio_periph_insel_regwen_5_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_6_we = addr_hit[6] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_6_we = addr_hit[7] & reg_we & !reg_error;
assign mio_periph_insel_regwen_6_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_7_we = addr_hit[7] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_7_we = addr_hit[8] & reg_we & !reg_error;
assign mio_periph_insel_regwen_7_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_8_we = addr_hit[8] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_8_we = addr_hit[9] & reg_we & !reg_error;
assign mio_periph_insel_regwen_8_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_9_we = addr_hit[9] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_9_we = addr_hit[10] & reg_we & !reg_error;
assign mio_periph_insel_regwen_9_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_10_we = addr_hit[10] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_10_we = addr_hit[11] & reg_we & !reg_error;
assign mio_periph_insel_regwen_10_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_11_we = addr_hit[11] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_11_we = addr_hit[12] & reg_we & !reg_error;
assign mio_periph_insel_regwen_11_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_12_we = addr_hit[12] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_12_we = addr_hit[13] & reg_we & !reg_error;
assign mio_periph_insel_regwen_12_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_13_we = addr_hit[13] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_13_we = addr_hit[14] & reg_we & !reg_error;
assign mio_periph_insel_regwen_13_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_14_we = addr_hit[14] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_14_we = addr_hit[15] & reg_we & !reg_error;
assign mio_periph_insel_regwen_14_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_15_we = addr_hit[15] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_15_we = addr_hit[16] & reg_we & !reg_error;
assign mio_periph_insel_regwen_15_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_16_we = addr_hit[16] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_16_we = addr_hit[17] & reg_we & !reg_error;
assign mio_periph_insel_regwen_16_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_17_we = addr_hit[17] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_17_we = addr_hit[18] & reg_we & !reg_error;
assign mio_periph_insel_regwen_17_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_18_we = addr_hit[18] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_18_we = addr_hit[19] & reg_we & !reg_error;
assign mio_periph_insel_regwen_18_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_19_we = addr_hit[19] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_19_we = addr_hit[20] & reg_we & !reg_error;
assign mio_periph_insel_regwen_19_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_20_we = addr_hit[20] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_20_we = addr_hit[21] & reg_we & !reg_error;
assign mio_periph_insel_regwen_20_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_21_we = addr_hit[21] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_21_we = addr_hit[22] & reg_we & !reg_error;
assign mio_periph_insel_regwen_21_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_22_we = addr_hit[22] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_22_we = addr_hit[23] & reg_we & !reg_error;
assign mio_periph_insel_regwen_22_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_23_we = addr_hit[23] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_23_we = addr_hit[24] & reg_we & !reg_error;
assign mio_periph_insel_regwen_23_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_24_we = addr_hit[24] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_24_we = addr_hit[25] & reg_we & !reg_error;
assign mio_periph_insel_regwen_24_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_25_we = addr_hit[25] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_25_we = addr_hit[26] & reg_we & !reg_error;
assign mio_periph_insel_regwen_25_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_26_we = addr_hit[26] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_26_we = addr_hit[27] & reg_we & !reg_error;
assign mio_periph_insel_regwen_26_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_27_we = addr_hit[27] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_27_we = addr_hit[28] & reg_we & !reg_error;
assign mio_periph_insel_regwen_27_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_28_we = addr_hit[28] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_28_we = addr_hit[29] & reg_we & !reg_error;
assign mio_periph_insel_regwen_28_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_29_we = addr_hit[29] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_29_we = addr_hit[30] & reg_we & !reg_error;
assign mio_periph_insel_regwen_29_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_30_we = addr_hit[30] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_30_we = addr_hit[31] & reg_we & !reg_error;
assign mio_periph_insel_regwen_30_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_31_we = addr_hit[31] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_31_we = addr_hit[32] & reg_we & !reg_error;
assign mio_periph_insel_regwen_31_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_32_we = addr_hit[32] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_32_we = addr_hit[33] & reg_we & !reg_error;
assign mio_periph_insel_regwen_32_wd = reg_wdata[0];
- assign mio_periph_insel_0_we = addr_hit[33] & reg_we & !reg_error;
+ assign mio_periph_insel_0_we = addr_hit[34] & reg_we & !reg_error;
assign mio_periph_insel_0_wd = reg_wdata[5:0];
- assign mio_periph_insel_1_we = addr_hit[34] & reg_we & !reg_error;
+ assign mio_periph_insel_1_we = addr_hit[35] & reg_we & !reg_error;
assign mio_periph_insel_1_wd = reg_wdata[5:0];
- assign mio_periph_insel_2_we = addr_hit[35] & reg_we & !reg_error;
+ assign mio_periph_insel_2_we = addr_hit[36] & reg_we & !reg_error;
assign mio_periph_insel_2_wd = reg_wdata[5:0];
- assign mio_periph_insel_3_we = addr_hit[36] & reg_we & !reg_error;
+ assign mio_periph_insel_3_we = addr_hit[37] & reg_we & !reg_error;
assign mio_periph_insel_3_wd = reg_wdata[5:0];
- assign mio_periph_insel_4_we = addr_hit[37] & reg_we & !reg_error;
+ assign mio_periph_insel_4_we = addr_hit[38] & reg_we & !reg_error;
assign mio_periph_insel_4_wd = reg_wdata[5:0];
- assign mio_periph_insel_5_we = addr_hit[38] & reg_we & !reg_error;
+ assign mio_periph_insel_5_we = addr_hit[39] & reg_we & !reg_error;
assign mio_periph_insel_5_wd = reg_wdata[5:0];
- assign mio_periph_insel_6_we = addr_hit[39] & reg_we & !reg_error;
+ assign mio_periph_insel_6_we = addr_hit[40] & reg_we & !reg_error;
assign mio_periph_insel_6_wd = reg_wdata[5:0];
- assign mio_periph_insel_7_we = addr_hit[40] & reg_we & !reg_error;
+ assign mio_periph_insel_7_we = addr_hit[41] & reg_we & !reg_error;
assign mio_periph_insel_7_wd = reg_wdata[5:0];
- assign mio_periph_insel_8_we = addr_hit[41] & reg_we & !reg_error;
+ assign mio_periph_insel_8_we = addr_hit[42] & reg_we & !reg_error;
assign mio_periph_insel_8_wd = reg_wdata[5:0];
- assign mio_periph_insel_9_we = addr_hit[42] & reg_we & !reg_error;
+ assign mio_periph_insel_9_we = addr_hit[43] & reg_we & !reg_error;
assign mio_periph_insel_9_wd = reg_wdata[5:0];
- assign mio_periph_insel_10_we = addr_hit[43] & reg_we & !reg_error;
+ assign mio_periph_insel_10_we = addr_hit[44] & reg_we & !reg_error;
assign mio_periph_insel_10_wd = reg_wdata[5:0];
- assign mio_periph_insel_11_we = addr_hit[44] & reg_we & !reg_error;
+ assign mio_periph_insel_11_we = addr_hit[45] & reg_we & !reg_error;
assign mio_periph_insel_11_wd = reg_wdata[5:0];
- assign mio_periph_insel_12_we = addr_hit[45] & reg_we & !reg_error;
+ assign mio_periph_insel_12_we = addr_hit[46] & reg_we & !reg_error;
assign mio_periph_insel_12_wd = reg_wdata[5:0];
- assign mio_periph_insel_13_we = addr_hit[46] & reg_we & !reg_error;
+ assign mio_periph_insel_13_we = addr_hit[47] & reg_we & !reg_error;
assign mio_periph_insel_13_wd = reg_wdata[5:0];
- assign mio_periph_insel_14_we = addr_hit[47] & reg_we & !reg_error;
+ assign mio_periph_insel_14_we = addr_hit[48] & reg_we & !reg_error;
assign mio_periph_insel_14_wd = reg_wdata[5:0];
- assign mio_periph_insel_15_we = addr_hit[48] & reg_we & !reg_error;
+ assign mio_periph_insel_15_we = addr_hit[49] & reg_we & !reg_error;
assign mio_periph_insel_15_wd = reg_wdata[5:0];
- assign mio_periph_insel_16_we = addr_hit[49] & reg_we & !reg_error;
+ assign mio_periph_insel_16_we = addr_hit[50] & reg_we & !reg_error;
assign mio_periph_insel_16_wd = reg_wdata[5:0];
- assign mio_periph_insel_17_we = addr_hit[50] & reg_we & !reg_error;
+ assign mio_periph_insel_17_we = addr_hit[51] & reg_we & !reg_error;
assign mio_periph_insel_17_wd = reg_wdata[5:0];
- assign mio_periph_insel_18_we = addr_hit[51] & reg_we & !reg_error;
+ assign mio_periph_insel_18_we = addr_hit[52] & reg_we & !reg_error;
assign mio_periph_insel_18_wd = reg_wdata[5:0];
- assign mio_periph_insel_19_we = addr_hit[52] & reg_we & !reg_error;
+ assign mio_periph_insel_19_we = addr_hit[53] & reg_we & !reg_error;
assign mio_periph_insel_19_wd = reg_wdata[5:0];
- assign mio_periph_insel_20_we = addr_hit[53] & reg_we & !reg_error;
+ assign mio_periph_insel_20_we = addr_hit[54] & reg_we & !reg_error;
assign mio_periph_insel_20_wd = reg_wdata[5:0];
- assign mio_periph_insel_21_we = addr_hit[54] & reg_we & !reg_error;
+ assign mio_periph_insel_21_we = addr_hit[55] & reg_we & !reg_error;
assign mio_periph_insel_21_wd = reg_wdata[5:0];
- assign mio_periph_insel_22_we = addr_hit[55] & reg_we & !reg_error;
+ assign mio_periph_insel_22_we = addr_hit[56] & reg_we & !reg_error;
assign mio_periph_insel_22_wd = reg_wdata[5:0];
- assign mio_periph_insel_23_we = addr_hit[56] & reg_we & !reg_error;
+ assign mio_periph_insel_23_we = addr_hit[57] & reg_we & !reg_error;
assign mio_periph_insel_23_wd = reg_wdata[5:0];
- assign mio_periph_insel_24_we = addr_hit[57] & reg_we & !reg_error;
+ assign mio_periph_insel_24_we = addr_hit[58] & reg_we & !reg_error;
assign mio_periph_insel_24_wd = reg_wdata[5:0];
- assign mio_periph_insel_25_we = addr_hit[58] & reg_we & !reg_error;
+ assign mio_periph_insel_25_we = addr_hit[59] & reg_we & !reg_error;
assign mio_periph_insel_25_wd = reg_wdata[5:0];
- assign mio_periph_insel_26_we = addr_hit[59] & reg_we & !reg_error;
+ assign mio_periph_insel_26_we = addr_hit[60] & reg_we & !reg_error;
assign mio_periph_insel_26_wd = reg_wdata[5:0];
- assign mio_periph_insel_27_we = addr_hit[60] & reg_we & !reg_error;
+ assign mio_periph_insel_27_we = addr_hit[61] & reg_we & !reg_error;
assign mio_periph_insel_27_wd = reg_wdata[5:0];
- assign mio_periph_insel_28_we = addr_hit[61] & reg_we & !reg_error;
+ assign mio_periph_insel_28_we = addr_hit[62] & reg_we & !reg_error;
assign mio_periph_insel_28_wd = reg_wdata[5:0];
- assign mio_periph_insel_29_we = addr_hit[62] & reg_we & !reg_error;
+ assign mio_periph_insel_29_we = addr_hit[63] & reg_we & !reg_error;
assign mio_periph_insel_29_wd = reg_wdata[5:0];
- assign mio_periph_insel_30_we = addr_hit[63] & reg_we & !reg_error;
+ assign mio_periph_insel_30_we = addr_hit[64] & reg_we & !reg_error;
assign mio_periph_insel_30_wd = reg_wdata[5:0];
- assign mio_periph_insel_31_we = addr_hit[64] & reg_we & !reg_error;
+ assign mio_periph_insel_31_we = addr_hit[65] & reg_we & !reg_error;
assign mio_periph_insel_31_wd = reg_wdata[5:0];
- assign mio_periph_insel_32_we = addr_hit[65] & reg_we & !reg_error;
+ assign mio_periph_insel_32_we = addr_hit[66] & reg_we & !reg_error;
assign mio_periph_insel_32_wd = reg_wdata[5:0];
- assign mio_outsel_regwen_0_we = addr_hit[66] & reg_we & !reg_error;
+ assign mio_outsel_regwen_0_we = addr_hit[67] & reg_we & !reg_error;
assign mio_outsel_regwen_0_wd = reg_wdata[0];
- assign mio_outsel_regwen_1_we = addr_hit[67] & reg_we & !reg_error;
+ assign mio_outsel_regwen_1_we = addr_hit[68] & reg_we & !reg_error;
assign mio_outsel_regwen_1_wd = reg_wdata[0];
- assign mio_outsel_regwen_2_we = addr_hit[68] & reg_we & !reg_error;
+ assign mio_outsel_regwen_2_we = addr_hit[69] & reg_we & !reg_error;
assign mio_outsel_regwen_2_wd = reg_wdata[0];
- assign mio_outsel_regwen_3_we = addr_hit[69] & reg_we & !reg_error;
+ assign mio_outsel_regwen_3_we = addr_hit[70] & reg_we & !reg_error;
assign mio_outsel_regwen_3_wd = reg_wdata[0];
- assign mio_outsel_regwen_4_we = addr_hit[70] & reg_we & !reg_error;
+ assign mio_outsel_regwen_4_we = addr_hit[71] & reg_we & !reg_error;
assign mio_outsel_regwen_4_wd = reg_wdata[0];
- assign mio_outsel_regwen_5_we = addr_hit[71] & reg_we & !reg_error;
+ assign mio_outsel_regwen_5_we = addr_hit[72] & reg_we & !reg_error;
assign mio_outsel_regwen_5_wd = reg_wdata[0];
- assign mio_outsel_regwen_6_we = addr_hit[72] & reg_we & !reg_error;
+ assign mio_outsel_regwen_6_we = addr_hit[73] & reg_we & !reg_error;
assign mio_outsel_regwen_6_wd = reg_wdata[0];
- assign mio_outsel_regwen_7_we = addr_hit[73] & reg_we & !reg_error;
+ assign mio_outsel_regwen_7_we = addr_hit[74] & reg_we & !reg_error;
assign mio_outsel_regwen_7_wd = reg_wdata[0];
- assign mio_outsel_regwen_8_we = addr_hit[74] & reg_we & !reg_error;
+ assign mio_outsel_regwen_8_we = addr_hit[75] & reg_we & !reg_error;
assign mio_outsel_regwen_8_wd = reg_wdata[0];
- assign mio_outsel_regwen_9_we = addr_hit[75] & reg_we & !reg_error;
+ assign mio_outsel_regwen_9_we = addr_hit[76] & reg_we & !reg_error;
assign mio_outsel_regwen_9_wd = reg_wdata[0];
- assign mio_outsel_regwen_10_we = addr_hit[76] & reg_we & !reg_error;
+ assign mio_outsel_regwen_10_we = addr_hit[77] & reg_we & !reg_error;
assign mio_outsel_regwen_10_wd = reg_wdata[0];
- assign mio_outsel_regwen_11_we = addr_hit[77] & reg_we & !reg_error;
+ assign mio_outsel_regwen_11_we = addr_hit[78] & reg_we & !reg_error;
assign mio_outsel_regwen_11_wd = reg_wdata[0];
- assign mio_outsel_regwen_12_we = addr_hit[78] & reg_we & !reg_error;
+ assign mio_outsel_regwen_12_we = addr_hit[79] & reg_we & !reg_error;
assign mio_outsel_regwen_12_wd = reg_wdata[0];
- assign mio_outsel_regwen_13_we = addr_hit[79] & reg_we & !reg_error;
+ assign mio_outsel_regwen_13_we = addr_hit[80] & reg_we & !reg_error;
assign mio_outsel_regwen_13_wd = reg_wdata[0];
- assign mio_outsel_regwen_14_we = addr_hit[80] & reg_we & !reg_error;
+ assign mio_outsel_regwen_14_we = addr_hit[81] & reg_we & !reg_error;
assign mio_outsel_regwen_14_wd = reg_wdata[0];
- assign mio_outsel_regwen_15_we = addr_hit[81] & reg_we & !reg_error;
+ assign mio_outsel_regwen_15_we = addr_hit[82] & reg_we & !reg_error;
assign mio_outsel_regwen_15_wd = reg_wdata[0];
- assign mio_outsel_regwen_16_we = addr_hit[82] & reg_we & !reg_error;
+ assign mio_outsel_regwen_16_we = addr_hit[83] & reg_we & !reg_error;
assign mio_outsel_regwen_16_wd = reg_wdata[0];
- assign mio_outsel_regwen_17_we = addr_hit[83] & reg_we & !reg_error;
+ assign mio_outsel_regwen_17_we = addr_hit[84] & reg_we & !reg_error;
assign mio_outsel_regwen_17_wd = reg_wdata[0];
- assign mio_outsel_regwen_18_we = addr_hit[84] & reg_we & !reg_error;
+ assign mio_outsel_regwen_18_we = addr_hit[85] & reg_we & !reg_error;
assign mio_outsel_regwen_18_wd = reg_wdata[0];
- assign mio_outsel_regwen_19_we = addr_hit[85] & reg_we & !reg_error;
+ assign mio_outsel_regwen_19_we = addr_hit[86] & reg_we & !reg_error;
assign mio_outsel_regwen_19_wd = reg_wdata[0];
- assign mio_outsel_regwen_20_we = addr_hit[86] & reg_we & !reg_error;
+ assign mio_outsel_regwen_20_we = addr_hit[87] & reg_we & !reg_error;
assign mio_outsel_regwen_20_wd = reg_wdata[0];
- assign mio_outsel_regwen_21_we = addr_hit[87] & reg_we & !reg_error;
+ assign mio_outsel_regwen_21_we = addr_hit[88] & reg_we & !reg_error;
assign mio_outsel_regwen_21_wd = reg_wdata[0];
- assign mio_outsel_regwen_22_we = addr_hit[88] & reg_we & !reg_error;
+ assign mio_outsel_regwen_22_we = addr_hit[89] & reg_we & !reg_error;
assign mio_outsel_regwen_22_wd = reg_wdata[0];
- assign mio_outsel_regwen_23_we = addr_hit[89] & reg_we & !reg_error;
+ assign mio_outsel_regwen_23_we = addr_hit[90] & reg_we & !reg_error;
assign mio_outsel_regwen_23_wd = reg_wdata[0];
- assign mio_outsel_regwen_24_we = addr_hit[90] & reg_we & !reg_error;
+ assign mio_outsel_regwen_24_we = addr_hit[91] & reg_we & !reg_error;
assign mio_outsel_regwen_24_wd = reg_wdata[0];
- assign mio_outsel_regwen_25_we = addr_hit[91] & reg_we & !reg_error;
+ assign mio_outsel_regwen_25_we = addr_hit[92] & reg_we & !reg_error;
assign mio_outsel_regwen_25_wd = reg_wdata[0];
- assign mio_outsel_regwen_26_we = addr_hit[92] & reg_we & !reg_error;
+ assign mio_outsel_regwen_26_we = addr_hit[93] & reg_we & !reg_error;
assign mio_outsel_regwen_26_wd = reg_wdata[0];
- assign mio_outsel_regwen_27_we = addr_hit[93] & reg_we & !reg_error;
+ assign mio_outsel_regwen_27_we = addr_hit[94] & reg_we & !reg_error;
assign mio_outsel_regwen_27_wd = reg_wdata[0];
- assign mio_outsel_regwen_28_we = addr_hit[94] & reg_we & !reg_error;
+ assign mio_outsel_regwen_28_we = addr_hit[95] & reg_we & !reg_error;
assign mio_outsel_regwen_28_wd = reg_wdata[0];
- assign mio_outsel_regwen_29_we = addr_hit[95] & reg_we & !reg_error;
+ assign mio_outsel_regwen_29_we = addr_hit[96] & reg_we & !reg_error;
assign mio_outsel_regwen_29_wd = reg_wdata[0];
- assign mio_outsel_regwen_30_we = addr_hit[96] & reg_we & !reg_error;
+ assign mio_outsel_regwen_30_we = addr_hit[97] & reg_we & !reg_error;
assign mio_outsel_regwen_30_wd = reg_wdata[0];
- assign mio_outsel_regwen_31_we = addr_hit[97] & reg_we & !reg_error;
+ assign mio_outsel_regwen_31_we = addr_hit[98] & reg_we & !reg_error;
assign mio_outsel_regwen_31_wd = reg_wdata[0];
- assign mio_outsel_0_we = addr_hit[98] & reg_we & !reg_error;
+ assign mio_outsel_0_we = addr_hit[99] & reg_we & !reg_error;
assign mio_outsel_0_wd = reg_wdata[5:0];
- assign mio_outsel_1_we = addr_hit[99] & reg_we & !reg_error;
+ assign mio_outsel_1_we = addr_hit[100] & reg_we & !reg_error;
assign mio_outsel_1_wd = reg_wdata[5:0];
- assign mio_outsel_2_we = addr_hit[100] & reg_we & !reg_error;
+ assign mio_outsel_2_we = addr_hit[101] & reg_we & !reg_error;
assign mio_outsel_2_wd = reg_wdata[5:0];
- assign mio_outsel_3_we = addr_hit[101] & reg_we & !reg_error;
+ assign mio_outsel_3_we = addr_hit[102] & reg_we & !reg_error;
assign mio_outsel_3_wd = reg_wdata[5:0];
- assign mio_outsel_4_we = addr_hit[102] & reg_we & !reg_error;
+ assign mio_outsel_4_we = addr_hit[103] & reg_we & !reg_error;
assign mio_outsel_4_wd = reg_wdata[5:0];
- assign mio_outsel_5_we = addr_hit[103] & reg_we & !reg_error;
+ assign mio_outsel_5_we = addr_hit[104] & reg_we & !reg_error;
assign mio_outsel_5_wd = reg_wdata[5:0];
- assign mio_outsel_6_we = addr_hit[104] & reg_we & !reg_error;
+ assign mio_outsel_6_we = addr_hit[105] & reg_we & !reg_error;
assign mio_outsel_6_wd = reg_wdata[5:0];
- assign mio_outsel_7_we = addr_hit[105] & reg_we & !reg_error;
+ assign mio_outsel_7_we = addr_hit[106] & reg_we & !reg_error;
assign mio_outsel_7_wd = reg_wdata[5:0];
- assign mio_outsel_8_we = addr_hit[106] & reg_we & !reg_error;
+ assign mio_outsel_8_we = addr_hit[107] & reg_we & !reg_error;
assign mio_outsel_8_wd = reg_wdata[5:0];
- assign mio_outsel_9_we = addr_hit[107] & reg_we & !reg_error;
+ assign mio_outsel_9_we = addr_hit[108] & reg_we & !reg_error;
assign mio_outsel_9_wd = reg_wdata[5:0];
- assign mio_outsel_10_we = addr_hit[108] & reg_we & !reg_error;
+ assign mio_outsel_10_we = addr_hit[109] & reg_we & !reg_error;
assign mio_outsel_10_wd = reg_wdata[5:0];
- assign mio_outsel_11_we = addr_hit[109] & reg_we & !reg_error;
+ assign mio_outsel_11_we = addr_hit[110] & reg_we & !reg_error;
assign mio_outsel_11_wd = reg_wdata[5:0];
- assign mio_outsel_12_we = addr_hit[110] & reg_we & !reg_error;
+ assign mio_outsel_12_we = addr_hit[111] & reg_we & !reg_error;
assign mio_outsel_12_wd = reg_wdata[5:0];
- assign mio_outsel_13_we = addr_hit[111] & reg_we & !reg_error;
+ assign mio_outsel_13_we = addr_hit[112] & reg_we & !reg_error;
assign mio_outsel_13_wd = reg_wdata[5:0];
- assign mio_outsel_14_we = addr_hit[112] & reg_we & !reg_error;
+ assign mio_outsel_14_we = addr_hit[113] & reg_we & !reg_error;
assign mio_outsel_14_wd = reg_wdata[5:0];
- assign mio_outsel_15_we = addr_hit[113] & reg_we & !reg_error;
+ assign mio_outsel_15_we = addr_hit[114] & reg_we & !reg_error;
assign mio_outsel_15_wd = reg_wdata[5:0];
- assign mio_outsel_16_we = addr_hit[114] & reg_we & !reg_error;
+ assign mio_outsel_16_we = addr_hit[115] & reg_we & !reg_error;
assign mio_outsel_16_wd = reg_wdata[5:0];
- assign mio_outsel_17_we = addr_hit[115] & reg_we & !reg_error;
+ assign mio_outsel_17_we = addr_hit[116] & reg_we & !reg_error;
assign mio_outsel_17_wd = reg_wdata[5:0];
- assign mio_outsel_18_we = addr_hit[116] & reg_we & !reg_error;
+ assign mio_outsel_18_we = addr_hit[117] & reg_we & !reg_error;
assign mio_outsel_18_wd = reg_wdata[5:0];
- assign mio_outsel_19_we = addr_hit[117] & reg_we & !reg_error;
+ assign mio_outsel_19_we = addr_hit[118] & reg_we & !reg_error;
assign mio_outsel_19_wd = reg_wdata[5:0];
- assign mio_outsel_20_we = addr_hit[118] & reg_we & !reg_error;
+ assign mio_outsel_20_we = addr_hit[119] & reg_we & !reg_error;
assign mio_outsel_20_wd = reg_wdata[5:0];
- assign mio_outsel_21_we = addr_hit[119] & reg_we & !reg_error;
+ assign mio_outsel_21_we = addr_hit[120] & reg_we & !reg_error;
assign mio_outsel_21_wd = reg_wdata[5:0];
- assign mio_outsel_22_we = addr_hit[120] & reg_we & !reg_error;
+ assign mio_outsel_22_we = addr_hit[121] & reg_we & !reg_error;
assign mio_outsel_22_wd = reg_wdata[5:0];
- assign mio_outsel_23_we = addr_hit[121] & reg_we & !reg_error;
+ assign mio_outsel_23_we = addr_hit[122] & reg_we & !reg_error;
assign mio_outsel_23_wd = reg_wdata[5:0];
- assign mio_outsel_24_we = addr_hit[122] & reg_we & !reg_error;
+ assign mio_outsel_24_we = addr_hit[123] & reg_we & !reg_error;
assign mio_outsel_24_wd = reg_wdata[5:0];
- assign mio_outsel_25_we = addr_hit[123] & reg_we & !reg_error;
+ assign mio_outsel_25_we = addr_hit[124] & reg_we & !reg_error;
assign mio_outsel_25_wd = reg_wdata[5:0];
- assign mio_outsel_26_we = addr_hit[124] & reg_we & !reg_error;
+ assign mio_outsel_26_we = addr_hit[125] & reg_we & !reg_error;
assign mio_outsel_26_wd = reg_wdata[5:0];
- assign mio_outsel_27_we = addr_hit[125] & reg_we & !reg_error;
+ assign mio_outsel_27_we = addr_hit[126] & reg_we & !reg_error;
assign mio_outsel_27_wd = reg_wdata[5:0];
- assign mio_outsel_28_we = addr_hit[126] & reg_we & !reg_error;
+ assign mio_outsel_28_we = addr_hit[127] & reg_we & !reg_error;
assign mio_outsel_28_wd = reg_wdata[5:0];
- assign mio_outsel_29_we = addr_hit[127] & reg_we & !reg_error;
+ assign mio_outsel_29_we = addr_hit[128] & reg_we & !reg_error;
assign mio_outsel_29_wd = reg_wdata[5:0];
- assign mio_outsel_30_we = addr_hit[128] & reg_we & !reg_error;
+ assign mio_outsel_30_we = addr_hit[129] & reg_we & !reg_error;
assign mio_outsel_30_wd = reg_wdata[5:0];
- assign mio_outsel_31_we = addr_hit[129] & reg_we & !reg_error;
+ assign mio_outsel_31_we = addr_hit[130] & reg_we & !reg_error;
assign mio_outsel_31_wd = reg_wdata[5:0];
- assign mio_pad_attr_regwen_0_we = addr_hit[130] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_0_we = addr_hit[131] & reg_we & !reg_error;
assign mio_pad_attr_regwen_0_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_1_we = addr_hit[131] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_1_we = addr_hit[132] & reg_we & !reg_error;
assign mio_pad_attr_regwen_1_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_2_we = addr_hit[132] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_2_we = addr_hit[133] & reg_we & !reg_error;
assign mio_pad_attr_regwen_2_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_3_we = addr_hit[133] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_3_we = addr_hit[134] & reg_we & !reg_error;
assign mio_pad_attr_regwen_3_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_4_we = addr_hit[134] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_4_we = addr_hit[135] & reg_we & !reg_error;
assign mio_pad_attr_regwen_4_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_5_we = addr_hit[135] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_5_we = addr_hit[136] & reg_we & !reg_error;
assign mio_pad_attr_regwen_5_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_6_we = addr_hit[136] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_6_we = addr_hit[137] & reg_we & !reg_error;
assign mio_pad_attr_regwen_6_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_7_we = addr_hit[137] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_7_we = addr_hit[138] & reg_we & !reg_error;
assign mio_pad_attr_regwen_7_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_8_we = addr_hit[138] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_8_we = addr_hit[139] & reg_we & !reg_error;
assign mio_pad_attr_regwen_8_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_9_we = addr_hit[139] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_9_we = addr_hit[140] & reg_we & !reg_error;
assign mio_pad_attr_regwen_9_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_10_we = addr_hit[140] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_10_we = addr_hit[141] & reg_we & !reg_error;
assign mio_pad_attr_regwen_10_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_11_we = addr_hit[141] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_11_we = addr_hit[142] & reg_we & !reg_error;
assign mio_pad_attr_regwen_11_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_12_we = addr_hit[142] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_12_we = addr_hit[143] & reg_we & !reg_error;
assign mio_pad_attr_regwen_12_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_13_we = addr_hit[143] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_13_we = addr_hit[144] & reg_we & !reg_error;
assign mio_pad_attr_regwen_13_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_14_we = addr_hit[144] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_14_we = addr_hit[145] & reg_we & !reg_error;
assign mio_pad_attr_regwen_14_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_15_we = addr_hit[145] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_15_we = addr_hit[146] & reg_we & !reg_error;
assign mio_pad_attr_regwen_15_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_16_we = addr_hit[146] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_16_we = addr_hit[147] & reg_we & !reg_error;
assign mio_pad_attr_regwen_16_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_17_we = addr_hit[147] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_17_we = addr_hit[148] & reg_we & !reg_error;
assign mio_pad_attr_regwen_17_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_18_we = addr_hit[148] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_18_we = addr_hit[149] & reg_we & !reg_error;
assign mio_pad_attr_regwen_18_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_19_we = addr_hit[149] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_19_we = addr_hit[150] & reg_we & !reg_error;
assign mio_pad_attr_regwen_19_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_20_we = addr_hit[150] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_20_we = addr_hit[151] & reg_we & !reg_error;
assign mio_pad_attr_regwen_20_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_21_we = addr_hit[151] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_21_we = addr_hit[152] & reg_we & !reg_error;
assign mio_pad_attr_regwen_21_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_22_we = addr_hit[152] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_22_we = addr_hit[153] & reg_we & !reg_error;
assign mio_pad_attr_regwen_22_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_23_we = addr_hit[153] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_23_we = addr_hit[154] & reg_we & !reg_error;
assign mio_pad_attr_regwen_23_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_24_we = addr_hit[154] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_24_we = addr_hit[155] & reg_we & !reg_error;
assign mio_pad_attr_regwen_24_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_25_we = addr_hit[155] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_25_we = addr_hit[156] & reg_we & !reg_error;
assign mio_pad_attr_regwen_25_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_26_we = addr_hit[156] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_26_we = addr_hit[157] & reg_we & !reg_error;
assign mio_pad_attr_regwen_26_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_27_we = addr_hit[157] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_27_we = addr_hit[158] & reg_we & !reg_error;
assign mio_pad_attr_regwen_27_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_28_we = addr_hit[158] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_28_we = addr_hit[159] & reg_we & !reg_error;
assign mio_pad_attr_regwen_28_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_29_we = addr_hit[159] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_29_we = addr_hit[160] & reg_we & !reg_error;
assign mio_pad_attr_regwen_29_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_30_we = addr_hit[160] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_30_we = addr_hit[161] & reg_we & !reg_error;
assign mio_pad_attr_regwen_30_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_31_we = addr_hit[161] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_31_we = addr_hit[162] & reg_we & !reg_error;
assign mio_pad_attr_regwen_31_wd = reg_wdata[0];
- assign mio_pad_attr_0_we = addr_hit[162] & reg_we & !reg_error;
+ assign mio_pad_attr_0_we = addr_hit[163] & reg_we & !reg_error;
assign mio_pad_attr_0_wd = reg_wdata[12:0];
- assign mio_pad_attr_0_re = addr_hit[162] & reg_re & !reg_error;
+ assign mio_pad_attr_0_re = addr_hit[163] & reg_re & !reg_error;
- assign mio_pad_attr_1_we = addr_hit[163] & reg_we & !reg_error;
+ assign mio_pad_attr_1_we = addr_hit[164] & reg_we & !reg_error;
assign mio_pad_attr_1_wd = reg_wdata[12:0];
- assign mio_pad_attr_1_re = addr_hit[163] & reg_re & !reg_error;
+ assign mio_pad_attr_1_re = addr_hit[164] & reg_re & !reg_error;
- assign mio_pad_attr_2_we = addr_hit[164] & reg_we & !reg_error;
+ assign mio_pad_attr_2_we = addr_hit[165] & reg_we & !reg_error;
assign mio_pad_attr_2_wd = reg_wdata[12:0];
- assign mio_pad_attr_2_re = addr_hit[164] & reg_re & !reg_error;
+ assign mio_pad_attr_2_re = addr_hit[165] & reg_re & !reg_error;
- assign mio_pad_attr_3_we = addr_hit[165] & reg_we & !reg_error;
+ assign mio_pad_attr_3_we = addr_hit[166] & reg_we & !reg_error;
assign mio_pad_attr_3_wd = reg_wdata[12:0];
- assign mio_pad_attr_3_re = addr_hit[165] & reg_re & !reg_error;
+ assign mio_pad_attr_3_re = addr_hit[166] & reg_re & !reg_error;
- assign mio_pad_attr_4_we = addr_hit[166] & reg_we & !reg_error;
+ assign mio_pad_attr_4_we = addr_hit[167] & reg_we & !reg_error;
assign mio_pad_attr_4_wd = reg_wdata[12:0];
- assign mio_pad_attr_4_re = addr_hit[166] & reg_re & !reg_error;
+ assign mio_pad_attr_4_re = addr_hit[167] & reg_re & !reg_error;
- assign mio_pad_attr_5_we = addr_hit[167] & reg_we & !reg_error;
+ assign mio_pad_attr_5_we = addr_hit[168] & reg_we & !reg_error;
assign mio_pad_attr_5_wd = reg_wdata[12:0];
- assign mio_pad_attr_5_re = addr_hit[167] & reg_re & !reg_error;
+ assign mio_pad_attr_5_re = addr_hit[168] & reg_re & !reg_error;
- assign mio_pad_attr_6_we = addr_hit[168] & reg_we & !reg_error;
+ assign mio_pad_attr_6_we = addr_hit[169] & reg_we & !reg_error;
assign mio_pad_attr_6_wd = reg_wdata[12:0];
- assign mio_pad_attr_6_re = addr_hit[168] & reg_re & !reg_error;
+ assign mio_pad_attr_6_re = addr_hit[169] & reg_re & !reg_error;
- assign mio_pad_attr_7_we = addr_hit[169] & reg_we & !reg_error;
+ assign mio_pad_attr_7_we = addr_hit[170] & reg_we & !reg_error;
assign mio_pad_attr_7_wd = reg_wdata[12:0];
- assign mio_pad_attr_7_re = addr_hit[169] & reg_re & !reg_error;
+ assign mio_pad_attr_7_re = addr_hit[170] & reg_re & !reg_error;
- assign mio_pad_attr_8_we = addr_hit[170] & reg_we & !reg_error;
+ assign mio_pad_attr_8_we = addr_hit[171] & reg_we & !reg_error;
assign mio_pad_attr_8_wd = reg_wdata[12:0];
- assign mio_pad_attr_8_re = addr_hit[170] & reg_re & !reg_error;
+ assign mio_pad_attr_8_re = addr_hit[171] & reg_re & !reg_error;
- assign mio_pad_attr_9_we = addr_hit[171] & reg_we & !reg_error;
+ assign mio_pad_attr_9_we = addr_hit[172] & reg_we & !reg_error;
assign mio_pad_attr_9_wd = reg_wdata[12:0];
- assign mio_pad_attr_9_re = addr_hit[171] & reg_re & !reg_error;
+ assign mio_pad_attr_9_re = addr_hit[172] & reg_re & !reg_error;
- assign mio_pad_attr_10_we = addr_hit[172] & reg_we & !reg_error;
+ assign mio_pad_attr_10_we = addr_hit[173] & reg_we & !reg_error;
assign mio_pad_attr_10_wd = reg_wdata[12:0];
- assign mio_pad_attr_10_re = addr_hit[172] & reg_re & !reg_error;
+ assign mio_pad_attr_10_re = addr_hit[173] & reg_re & !reg_error;
- assign mio_pad_attr_11_we = addr_hit[173] & reg_we & !reg_error;
+ assign mio_pad_attr_11_we = addr_hit[174] & reg_we & !reg_error;
assign mio_pad_attr_11_wd = reg_wdata[12:0];
- assign mio_pad_attr_11_re = addr_hit[173] & reg_re & !reg_error;
+ assign mio_pad_attr_11_re = addr_hit[174] & reg_re & !reg_error;
- assign mio_pad_attr_12_we = addr_hit[174] & reg_we & !reg_error;
+ assign mio_pad_attr_12_we = addr_hit[175] & reg_we & !reg_error;
assign mio_pad_attr_12_wd = reg_wdata[12:0];
- assign mio_pad_attr_12_re = addr_hit[174] & reg_re & !reg_error;
+ assign mio_pad_attr_12_re = addr_hit[175] & reg_re & !reg_error;
- assign mio_pad_attr_13_we = addr_hit[175] & reg_we & !reg_error;
+ assign mio_pad_attr_13_we = addr_hit[176] & reg_we & !reg_error;
assign mio_pad_attr_13_wd = reg_wdata[12:0];
- assign mio_pad_attr_13_re = addr_hit[175] & reg_re & !reg_error;
+ assign mio_pad_attr_13_re = addr_hit[176] & reg_re & !reg_error;
- assign mio_pad_attr_14_we = addr_hit[176] & reg_we & !reg_error;
+ assign mio_pad_attr_14_we = addr_hit[177] & reg_we & !reg_error;
assign mio_pad_attr_14_wd = reg_wdata[12:0];
- assign mio_pad_attr_14_re = addr_hit[176] & reg_re & !reg_error;
+ assign mio_pad_attr_14_re = addr_hit[177] & reg_re & !reg_error;
- assign mio_pad_attr_15_we = addr_hit[177] & reg_we & !reg_error;
+ assign mio_pad_attr_15_we = addr_hit[178] & reg_we & !reg_error;
assign mio_pad_attr_15_wd = reg_wdata[12:0];
- assign mio_pad_attr_15_re = addr_hit[177] & reg_re & !reg_error;
+ assign mio_pad_attr_15_re = addr_hit[178] & reg_re & !reg_error;
- assign mio_pad_attr_16_we = addr_hit[178] & reg_we & !reg_error;
+ assign mio_pad_attr_16_we = addr_hit[179] & reg_we & !reg_error;
assign mio_pad_attr_16_wd = reg_wdata[12:0];
- assign mio_pad_attr_16_re = addr_hit[178] & reg_re & !reg_error;
+ assign mio_pad_attr_16_re = addr_hit[179] & reg_re & !reg_error;
- assign mio_pad_attr_17_we = addr_hit[179] & reg_we & !reg_error;
+ assign mio_pad_attr_17_we = addr_hit[180] & reg_we & !reg_error;
assign mio_pad_attr_17_wd = reg_wdata[12:0];
- assign mio_pad_attr_17_re = addr_hit[179] & reg_re & !reg_error;
+ assign mio_pad_attr_17_re = addr_hit[180] & reg_re & !reg_error;
- assign mio_pad_attr_18_we = addr_hit[180] & reg_we & !reg_error;
+ assign mio_pad_attr_18_we = addr_hit[181] & reg_we & !reg_error;
assign mio_pad_attr_18_wd = reg_wdata[12:0];
- assign mio_pad_attr_18_re = addr_hit[180] & reg_re & !reg_error;
+ assign mio_pad_attr_18_re = addr_hit[181] & reg_re & !reg_error;
- assign mio_pad_attr_19_we = addr_hit[181] & reg_we & !reg_error;
+ assign mio_pad_attr_19_we = addr_hit[182] & reg_we & !reg_error;
assign mio_pad_attr_19_wd = reg_wdata[12:0];
- assign mio_pad_attr_19_re = addr_hit[181] & reg_re & !reg_error;
+ assign mio_pad_attr_19_re = addr_hit[182] & reg_re & !reg_error;
- assign mio_pad_attr_20_we = addr_hit[182] & reg_we & !reg_error;
+ assign mio_pad_attr_20_we = addr_hit[183] & reg_we & !reg_error;
assign mio_pad_attr_20_wd = reg_wdata[12:0];
- assign mio_pad_attr_20_re = addr_hit[182] & reg_re & !reg_error;
+ assign mio_pad_attr_20_re = addr_hit[183] & reg_re & !reg_error;
- assign mio_pad_attr_21_we = addr_hit[183] & reg_we & !reg_error;
+ assign mio_pad_attr_21_we = addr_hit[184] & reg_we & !reg_error;
assign mio_pad_attr_21_wd = reg_wdata[12:0];
- assign mio_pad_attr_21_re = addr_hit[183] & reg_re & !reg_error;
+ assign mio_pad_attr_21_re = addr_hit[184] & reg_re & !reg_error;
- assign mio_pad_attr_22_we = addr_hit[184] & reg_we & !reg_error;
+ assign mio_pad_attr_22_we = addr_hit[185] & reg_we & !reg_error;
assign mio_pad_attr_22_wd = reg_wdata[12:0];
- assign mio_pad_attr_22_re = addr_hit[184] & reg_re & !reg_error;
+ assign mio_pad_attr_22_re = addr_hit[185] & reg_re & !reg_error;
- assign mio_pad_attr_23_we = addr_hit[185] & reg_we & !reg_error;
+ assign mio_pad_attr_23_we = addr_hit[186] & reg_we & !reg_error;
assign mio_pad_attr_23_wd = reg_wdata[12:0];
- assign mio_pad_attr_23_re = addr_hit[185] & reg_re & !reg_error;
+ assign mio_pad_attr_23_re = addr_hit[186] & reg_re & !reg_error;
- assign mio_pad_attr_24_we = addr_hit[186] & reg_we & !reg_error;
+ assign mio_pad_attr_24_we = addr_hit[187] & reg_we & !reg_error;
assign mio_pad_attr_24_wd = reg_wdata[12:0];
- assign mio_pad_attr_24_re = addr_hit[186] & reg_re & !reg_error;
+ assign mio_pad_attr_24_re = addr_hit[187] & reg_re & !reg_error;
- assign mio_pad_attr_25_we = addr_hit[187] & reg_we & !reg_error;
+ assign mio_pad_attr_25_we = addr_hit[188] & reg_we & !reg_error;
assign mio_pad_attr_25_wd = reg_wdata[12:0];
- assign mio_pad_attr_25_re = addr_hit[187] & reg_re & !reg_error;
+ assign mio_pad_attr_25_re = addr_hit[188] & reg_re & !reg_error;
- assign mio_pad_attr_26_we = addr_hit[188] & reg_we & !reg_error;
+ assign mio_pad_attr_26_we = addr_hit[189] & reg_we & !reg_error;
assign mio_pad_attr_26_wd = reg_wdata[12:0];
- assign mio_pad_attr_26_re = addr_hit[188] & reg_re & !reg_error;
+ assign mio_pad_attr_26_re = addr_hit[189] & reg_re & !reg_error;
- assign mio_pad_attr_27_we = addr_hit[189] & reg_we & !reg_error;
+ assign mio_pad_attr_27_we = addr_hit[190] & reg_we & !reg_error;
assign mio_pad_attr_27_wd = reg_wdata[12:0];
- assign mio_pad_attr_27_re = addr_hit[189] & reg_re & !reg_error;
+ assign mio_pad_attr_27_re = addr_hit[190] & reg_re & !reg_error;
- assign mio_pad_attr_28_we = addr_hit[190] & reg_we & !reg_error;
+ assign mio_pad_attr_28_we = addr_hit[191] & reg_we & !reg_error;
assign mio_pad_attr_28_wd = reg_wdata[12:0];
- assign mio_pad_attr_28_re = addr_hit[190] & reg_re & !reg_error;
+ assign mio_pad_attr_28_re = addr_hit[191] & reg_re & !reg_error;
- assign mio_pad_attr_29_we = addr_hit[191] & reg_we & !reg_error;
+ assign mio_pad_attr_29_we = addr_hit[192] & reg_we & !reg_error;
assign mio_pad_attr_29_wd = reg_wdata[12:0];
- assign mio_pad_attr_29_re = addr_hit[191] & reg_re & !reg_error;
+ assign mio_pad_attr_29_re = addr_hit[192] & reg_re & !reg_error;
- assign mio_pad_attr_30_we = addr_hit[192] & reg_we & !reg_error;
+ assign mio_pad_attr_30_we = addr_hit[193] & reg_we & !reg_error;
assign mio_pad_attr_30_wd = reg_wdata[12:0];
- assign mio_pad_attr_30_re = addr_hit[192] & reg_re & !reg_error;
+ assign mio_pad_attr_30_re = addr_hit[193] & reg_re & !reg_error;
- assign mio_pad_attr_31_we = addr_hit[193] & reg_we & !reg_error;
+ assign mio_pad_attr_31_we = addr_hit[194] & reg_we & !reg_error;
assign mio_pad_attr_31_wd = reg_wdata[12:0];
- assign mio_pad_attr_31_re = addr_hit[193] & reg_re & !reg_error;
+ assign mio_pad_attr_31_re = addr_hit[194] & reg_re & !reg_error;
- assign dio_pad_attr_regwen_0_we = addr_hit[194] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_0_we = addr_hit[195] & reg_we & !reg_error;
assign dio_pad_attr_regwen_0_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_1_we = addr_hit[195] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_1_we = addr_hit[196] & reg_we & !reg_error;
assign dio_pad_attr_regwen_1_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_2_we = addr_hit[196] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_2_we = addr_hit[197] & reg_we & !reg_error;
assign dio_pad_attr_regwen_2_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_3_we = addr_hit[197] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_3_we = addr_hit[198] & reg_we & !reg_error;
assign dio_pad_attr_regwen_3_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_4_we = addr_hit[198] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_4_we = addr_hit[199] & reg_we & !reg_error;
assign dio_pad_attr_regwen_4_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_5_we = addr_hit[199] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_5_we = addr_hit[200] & reg_we & !reg_error;
assign dio_pad_attr_regwen_5_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_6_we = addr_hit[200] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_6_we = addr_hit[201] & reg_we & !reg_error;
assign dio_pad_attr_regwen_6_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_7_we = addr_hit[201] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_7_we = addr_hit[202] & reg_we & !reg_error;
assign dio_pad_attr_regwen_7_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_8_we = addr_hit[202] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_8_we = addr_hit[203] & reg_we & !reg_error;
assign dio_pad_attr_regwen_8_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_9_we = addr_hit[203] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_9_we = addr_hit[204] & reg_we & !reg_error;
assign dio_pad_attr_regwen_9_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_10_we = addr_hit[204] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_10_we = addr_hit[205] & reg_we & !reg_error;
assign dio_pad_attr_regwen_10_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_11_we = addr_hit[205] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_11_we = addr_hit[206] & reg_we & !reg_error;
assign dio_pad_attr_regwen_11_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_12_we = addr_hit[206] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_12_we = addr_hit[207] & reg_we & !reg_error;
assign dio_pad_attr_regwen_12_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_13_we = addr_hit[207] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_13_we = addr_hit[208] & reg_we & !reg_error;
assign dio_pad_attr_regwen_13_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_14_we = addr_hit[208] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_14_we = addr_hit[209] & reg_we & !reg_error;
assign dio_pad_attr_regwen_14_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_15_we = addr_hit[209] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_15_we = addr_hit[210] & reg_we & !reg_error;
assign dio_pad_attr_regwen_15_wd = reg_wdata[0];
- assign dio_pad_attr_0_we = addr_hit[210] & reg_we & !reg_error;
+ assign dio_pad_attr_0_we = addr_hit[211] & reg_we & !reg_error;
assign dio_pad_attr_0_wd = reg_wdata[12:0];
- assign dio_pad_attr_0_re = addr_hit[210] & reg_re & !reg_error;
+ assign dio_pad_attr_0_re = addr_hit[211] & reg_re & !reg_error;
- assign dio_pad_attr_1_we = addr_hit[211] & reg_we & !reg_error;
+ assign dio_pad_attr_1_we = addr_hit[212] & reg_we & !reg_error;
assign dio_pad_attr_1_wd = reg_wdata[12:0];
- assign dio_pad_attr_1_re = addr_hit[211] & reg_re & !reg_error;
+ assign dio_pad_attr_1_re = addr_hit[212] & reg_re & !reg_error;
- assign dio_pad_attr_2_we = addr_hit[212] & reg_we & !reg_error;
+ assign dio_pad_attr_2_we = addr_hit[213] & reg_we & !reg_error;
assign dio_pad_attr_2_wd = reg_wdata[12:0];
- assign dio_pad_attr_2_re = addr_hit[212] & reg_re & !reg_error;
+ assign dio_pad_attr_2_re = addr_hit[213] & reg_re & !reg_error;
- assign dio_pad_attr_3_we = addr_hit[213] & reg_we & !reg_error;
+ assign dio_pad_attr_3_we = addr_hit[214] & reg_we & !reg_error;
assign dio_pad_attr_3_wd = reg_wdata[12:0];
- assign dio_pad_attr_3_re = addr_hit[213] & reg_re & !reg_error;
+ assign dio_pad_attr_3_re = addr_hit[214] & reg_re & !reg_error;
- assign dio_pad_attr_4_we = addr_hit[214] & reg_we & !reg_error;
+ assign dio_pad_attr_4_we = addr_hit[215] & reg_we & !reg_error;
assign dio_pad_attr_4_wd = reg_wdata[12:0];
- assign dio_pad_attr_4_re = addr_hit[214] & reg_re & !reg_error;
+ assign dio_pad_attr_4_re = addr_hit[215] & reg_re & !reg_error;
- assign dio_pad_attr_5_we = addr_hit[215] & reg_we & !reg_error;
+ assign dio_pad_attr_5_we = addr_hit[216] & reg_we & !reg_error;
assign dio_pad_attr_5_wd = reg_wdata[12:0];
- assign dio_pad_attr_5_re = addr_hit[215] & reg_re & !reg_error;
+ assign dio_pad_attr_5_re = addr_hit[216] & reg_re & !reg_error;
- assign dio_pad_attr_6_we = addr_hit[216] & reg_we & !reg_error;
+ assign dio_pad_attr_6_we = addr_hit[217] & reg_we & !reg_error;
assign dio_pad_attr_6_wd = reg_wdata[12:0];
- assign dio_pad_attr_6_re = addr_hit[216] & reg_re & !reg_error;
+ assign dio_pad_attr_6_re = addr_hit[217] & reg_re & !reg_error;
- assign dio_pad_attr_7_we = addr_hit[217] & reg_we & !reg_error;
+ assign dio_pad_attr_7_we = addr_hit[218] & reg_we & !reg_error;
assign dio_pad_attr_7_wd = reg_wdata[12:0];
- assign dio_pad_attr_7_re = addr_hit[217] & reg_re & !reg_error;
+ assign dio_pad_attr_7_re = addr_hit[218] & reg_re & !reg_error;
- assign dio_pad_attr_8_we = addr_hit[218] & reg_we & !reg_error;
+ assign dio_pad_attr_8_we = addr_hit[219] & reg_we & !reg_error;
assign dio_pad_attr_8_wd = reg_wdata[12:0];
- assign dio_pad_attr_8_re = addr_hit[218] & reg_re & !reg_error;
+ assign dio_pad_attr_8_re = addr_hit[219] & reg_re & !reg_error;
- assign dio_pad_attr_9_we = addr_hit[219] & reg_we & !reg_error;
+ assign dio_pad_attr_9_we = addr_hit[220] & reg_we & !reg_error;
assign dio_pad_attr_9_wd = reg_wdata[12:0];
- assign dio_pad_attr_9_re = addr_hit[219] & reg_re & !reg_error;
+ assign dio_pad_attr_9_re = addr_hit[220] & reg_re & !reg_error;
- assign dio_pad_attr_10_we = addr_hit[220] & reg_we & !reg_error;
+ assign dio_pad_attr_10_we = addr_hit[221] & reg_we & !reg_error;
assign dio_pad_attr_10_wd = reg_wdata[12:0];
- assign dio_pad_attr_10_re = addr_hit[220] & reg_re & !reg_error;
+ assign dio_pad_attr_10_re = addr_hit[221] & reg_re & !reg_error;
- assign dio_pad_attr_11_we = addr_hit[221] & reg_we & !reg_error;
+ assign dio_pad_attr_11_we = addr_hit[222] & reg_we & !reg_error;
assign dio_pad_attr_11_wd = reg_wdata[12:0];
- assign dio_pad_attr_11_re = addr_hit[221] & reg_re & !reg_error;
+ assign dio_pad_attr_11_re = addr_hit[222] & reg_re & !reg_error;
- assign dio_pad_attr_12_we = addr_hit[222] & reg_we & !reg_error;
+ assign dio_pad_attr_12_we = addr_hit[223] & reg_we & !reg_error;
assign dio_pad_attr_12_wd = reg_wdata[12:0];
- assign dio_pad_attr_12_re = addr_hit[222] & reg_re & !reg_error;
+ assign dio_pad_attr_12_re = addr_hit[223] & reg_re & !reg_error;
- assign dio_pad_attr_13_we = addr_hit[223] & reg_we & !reg_error;
+ assign dio_pad_attr_13_we = addr_hit[224] & reg_we & !reg_error;
assign dio_pad_attr_13_wd = reg_wdata[12:0];
- assign dio_pad_attr_13_re = addr_hit[223] & reg_re & !reg_error;
+ assign dio_pad_attr_13_re = addr_hit[224] & reg_re & !reg_error;
- assign dio_pad_attr_14_we = addr_hit[224] & reg_we & !reg_error;
+ assign dio_pad_attr_14_we = addr_hit[225] & reg_we & !reg_error;
assign dio_pad_attr_14_wd = reg_wdata[12:0];
- assign dio_pad_attr_14_re = addr_hit[224] & reg_re & !reg_error;
+ assign dio_pad_attr_14_re = addr_hit[225] & reg_re & !reg_error;
- assign dio_pad_attr_15_we = addr_hit[225] & reg_we & !reg_error;
+ assign dio_pad_attr_15_we = addr_hit[226] & reg_we & !reg_error;
assign dio_pad_attr_15_wd = reg_wdata[12:0];
- assign dio_pad_attr_15_re = addr_hit[225] & reg_re & !reg_error;
+ assign dio_pad_attr_15_re = addr_hit[226] & reg_re & !reg_error;
- assign mio_pad_sleep_status_en_0_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_0_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_0_wd = reg_wdata[0];
- assign mio_pad_sleep_status_en_1_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_1_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_1_wd = reg_wdata[1];
- assign mio_pad_sleep_status_en_2_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_2_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_2_wd = reg_wdata[2];
- assign mio_pad_sleep_status_en_3_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_3_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_3_wd = reg_wdata[3];
- assign mio_pad_sleep_status_en_4_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_4_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_4_wd = reg_wdata[4];
- assign mio_pad_sleep_status_en_5_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_5_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_5_wd = reg_wdata[5];
- assign mio_pad_sleep_status_en_6_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_6_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_6_wd = reg_wdata[6];
- assign mio_pad_sleep_status_en_7_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_7_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_7_wd = reg_wdata[7];
- assign mio_pad_sleep_status_en_8_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_8_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_8_wd = reg_wdata[8];
- assign mio_pad_sleep_status_en_9_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_9_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_9_wd = reg_wdata[9];
- assign mio_pad_sleep_status_en_10_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_10_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_10_wd = reg_wdata[10];
- assign mio_pad_sleep_status_en_11_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_11_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_11_wd = reg_wdata[11];
- assign mio_pad_sleep_status_en_12_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_12_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_12_wd = reg_wdata[12];
- assign mio_pad_sleep_status_en_13_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_13_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_13_wd = reg_wdata[13];
- assign mio_pad_sleep_status_en_14_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_14_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_14_wd = reg_wdata[14];
- assign mio_pad_sleep_status_en_15_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_15_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_15_wd = reg_wdata[15];
- assign mio_pad_sleep_status_en_16_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_16_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_16_wd = reg_wdata[16];
- assign mio_pad_sleep_status_en_17_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_17_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_17_wd = reg_wdata[17];
- assign mio_pad_sleep_status_en_18_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_18_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_18_wd = reg_wdata[18];
- assign mio_pad_sleep_status_en_19_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_19_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_19_wd = reg_wdata[19];
- assign mio_pad_sleep_status_en_20_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_20_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_20_wd = reg_wdata[20];
- assign mio_pad_sleep_status_en_21_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_21_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_21_wd = reg_wdata[21];
- assign mio_pad_sleep_status_en_22_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_22_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_22_wd = reg_wdata[22];
- assign mio_pad_sleep_status_en_23_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_23_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_23_wd = reg_wdata[23];
- assign mio_pad_sleep_status_en_24_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_24_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_24_wd = reg_wdata[24];
- assign mio_pad_sleep_status_en_25_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_25_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_25_wd = reg_wdata[25];
- assign mio_pad_sleep_status_en_26_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_26_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_26_wd = reg_wdata[26];
- assign mio_pad_sleep_status_en_27_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_27_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_27_wd = reg_wdata[27];
- assign mio_pad_sleep_status_en_28_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_28_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_28_wd = reg_wdata[28];
- assign mio_pad_sleep_status_en_29_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_29_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_29_wd = reg_wdata[29];
- assign mio_pad_sleep_status_en_30_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_30_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_30_wd = reg_wdata[30];
- assign mio_pad_sleep_status_en_31_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_en_31_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_sleep_status_en_31_wd = reg_wdata[31];
- assign mio_pad_sleep_regwen_0_we = addr_hit[227] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_0_we = addr_hit[228] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_0_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_1_we = addr_hit[228] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_1_we = addr_hit[229] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_1_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_2_we = addr_hit[229] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_2_we = addr_hit[230] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_2_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_3_we = addr_hit[230] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_3_we = addr_hit[231] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_3_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_4_we = addr_hit[231] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_4_we = addr_hit[232] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_4_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_5_we = addr_hit[232] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_5_we = addr_hit[233] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_5_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_6_we = addr_hit[233] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_6_we = addr_hit[234] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_6_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_7_we = addr_hit[234] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_7_we = addr_hit[235] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_7_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_8_we = addr_hit[235] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_8_we = addr_hit[236] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_8_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_9_we = addr_hit[236] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_9_we = addr_hit[237] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_9_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_10_we = addr_hit[237] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_10_we = addr_hit[238] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_10_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_11_we = addr_hit[238] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_11_we = addr_hit[239] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_11_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_12_we = addr_hit[239] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_12_we = addr_hit[240] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_12_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_13_we = addr_hit[240] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_13_we = addr_hit[241] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_13_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_14_we = addr_hit[241] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_14_we = addr_hit[242] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_14_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_15_we = addr_hit[242] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_15_we = addr_hit[243] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_15_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_16_we = addr_hit[243] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_16_we = addr_hit[244] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_16_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_17_we = addr_hit[244] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_17_we = addr_hit[245] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_17_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_18_we = addr_hit[245] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_18_we = addr_hit[246] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_18_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_19_we = addr_hit[246] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_19_we = addr_hit[247] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_19_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_20_we = addr_hit[247] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_20_we = addr_hit[248] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_20_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_21_we = addr_hit[248] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_21_we = addr_hit[249] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_21_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_22_we = addr_hit[249] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_22_we = addr_hit[250] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_22_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_23_we = addr_hit[250] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_23_we = addr_hit[251] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_23_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_24_we = addr_hit[251] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_24_we = addr_hit[252] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_24_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_25_we = addr_hit[252] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_25_we = addr_hit[253] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_25_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_26_we = addr_hit[253] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_26_we = addr_hit[254] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_26_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_27_we = addr_hit[254] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_27_we = addr_hit[255] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_27_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_28_we = addr_hit[255] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_28_we = addr_hit[256] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_28_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_29_we = addr_hit[256] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_29_we = addr_hit[257] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_29_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_30_we = addr_hit[257] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_30_we = addr_hit[258] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_30_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_31_we = addr_hit[258] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_31_we = addr_hit[259] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_31_wd = reg_wdata[0];
- assign mio_pad_sleep_en_0_we = addr_hit[259] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_0_we = addr_hit[260] & reg_we & !reg_error;
assign mio_pad_sleep_en_0_wd = reg_wdata[0];
- assign mio_pad_sleep_en_1_we = addr_hit[260] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_1_we = addr_hit[261] & reg_we & !reg_error;
assign mio_pad_sleep_en_1_wd = reg_wdata[0];
- assign mio_pad_sleep_en_2_we = addr_hit[261] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_2_we = addr_hit[262] & reg_we & !reg_error;
assign mio_pad_sleep_en_2_wd = reg_wdata[0];
- assign mio_pad_sleep_en_3_we = addr_hit[262] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_3_we = addr_hit[263] & reg_we & !reg_error;
assign mio_pad_sleep_en_3_wd = reg_wdata[0];
- assign mio_pad_sleep_en_4_we = addr_hit[263] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_4_we = addr_hit[264] & reg_we & !reg_error;
assign mio_pad_sleep_en_4_wd = reg_wdata[0];
- assign mio_pad_sleep_en_5_we = addr_hit[264] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_5_we = addr_hit[265] & reg_we & !reg_error;
assign mio_pad_sleep_en_5_wd = reg_wdata[0];
- assign mio_pad_sleep_en_6_we = addr_hit[265] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_6_we = addr_hit[266] & reg_we & !reg_error;
assign mio_pad_sleep_en_6_wd = reg_wdata[0];
- assign mio_pad_sleep_en_7_we = addr_hit[266] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_7_we = addr_hit[267] & reg_we & !reg_error;
assign mio_pad_sleep_en_7_wd = reg_wdata[0];
- assign mio_pad_sleep_en_8_we = addr_hit[267] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_8_we = addr_hit[268] & reg_we & !reg_error;
assign mio_pad_sleep_en_8_wd = reg_wdata[0];
- assign mio_pad_sleep_en_9_we = addr_hit[268] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_9_we = addr_hit[269] & reg_we & !reg_error;
assign mio_pad_sleep_en_9_wd = reg_wdata[0];
- assign mio_pad_sleep_en_10_we = addr_hit[269] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_10_we = addr_hit[270] & reg_we & !reg_error;
assign mio_pad_sleep_en_10_wd = reg_wdata[0];
- assign mio_pad_sleep_en_11_we = addr_hit[270] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_11_we = addr_hit[271] & reg_we & !reg_error;
assign mio_pad_sleep_en_11_wd = reg_wdata[0];
- assign mio_pad_sleep_en_12_we = addr_hit[271] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_12_we = addr_hit[272] & reg_we & !reg_error;
assign mio_pad_sleep_en_12_wd = reg_wdata[0];
- assign mio_pad_sleep_en_13_we = addr_hit[272] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_13_we = addr_hit[273] & reg_we & !reg_error;
assign mio_pad_sleep_en_13_wd = reg_wdata[0];
- assign mio_pad_sleep_en_14_we = addr_hit[273] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_14_we = addr_hit[274] & reg_we & !reg_error;
assign mio_pad_sleep_en_14_wd = reg_wdata[0];
- assign mio_pad_sleep_en_15_we = addr_hit[274] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_15_we = addr_hit[275] & reg_we & !reg_error;
assign mio_pad_sleep_en_15_wd = reg_wdata[0];
- assign mio_pad_sleep_en_16_we = addr_hit[275] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_16_we = addr_hit[276] & reg_we & !reg_error;
assign mio_pad_sleep_en_16_wd = reg_wdata[0];
- assign mio_pad_sleep_en_17_we = addr_hit[276] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_17_we = addr_hit[277] & reg_we & !reg_error;
assign mio_pad_sleep_en_17_wd = reg_wdata[0];
- assign mio_pad_sleep_en_18_we = addr_hit[277] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_18_we = addr_hit[278] & reg_we & !reg_error;
assign mio_pad_sleep_en_18_wd = reg_wdata[0];
- assign mio_pad_sleep_en_19_we = addr_hit[278] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_19_we = addr_hit[279] & reg_we & !reg_error;
assign mio_pad_sleep_en_19_wd = reg_wdata[0];
- assign mio_pad_sleep_en_20_we = addr_hit[279] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_20_we = addr_hit[280] & reg_we & !reg_error;
assign mio_pad_sleep_en_20_wd = reg_wdata[0];
- assign mio_pad_sleep_en_21_we = addr_hit[280] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_21_we = addr_hit[281] & reg_we & !reg_error;
assign mio_pad_sleep_en_21_wd = reg_wdata[0];
- assign mio_pad_sleep_en_22_we = addr_hit[281] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_22_we = addr_hit[282] & reg_we & !reg_error;
assign mio_pad_sleep_en_22_wd = reg_wdata[0];
- assign mio_pad_sleep_en_23_we = addr_hit[282] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_23_we = addr_hit[283] & reg_we & !reg_error;
assign mio_pad_sleep_en_23_wd = reg_wdata[0];
- assign mio_pad_sleep_en_24_we = addr_hit[283] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_24_we = addr_hit[284] & reg_we & !reg_error;
assign mio_pad_sleep_en_24_wd = reg_wdata[0];
- assign mio_pad_sleep_en_25_we = addr_hit[284] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_25_we = addr_hit[285] & reg_we & !reg_error;
assign mio_pad_sleep_en_25_wd = reg_wdata[0];
- assign mio_pad_sleep_en_26_we = addr_hit[285] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_26_we = addr_hit[286] & reg_we & !reg_error;
assign mio_pad_sleep_en_26_wd = reg_wdata[0];
- assign mio_pad_sleep_en_27_we = addr_hit[286] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_27_we = addr_hit[287] & reg_we & !reg_error;
assign mio_pad_sleep_en_27_wd = reg_wdata[0];
- assign mio_pad_sleep_en_28_we = addr_hit[287] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_28_we = addr_hit[288] & reg_we & !reg_error;
assign mio_pad_sleep_en_28_wd = reg_wdata[0];
- assign mio_pad_sleep_en_29_we = addr_hit[288] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_29_we = addr_hit[289] & reg_we & !reg_error;
assign mio_pad_sleep_en_29_wd = reg_wdata[0];
- assign mio_pad_sleep_en_30_we = addr_hit[289] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_30_we = addr_hit[290] & reg_we & !reg_error;
assign mio_pad_sleep_en_30_wd = reg_wdata[0];
- assign mio_pad_sleep_en_31_we = addr_hit[290] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_31_we = addr_hit[291] & reg_we & !reg_error;
assign mio_pad_sleep_en_31_wd = reg_wdata[0];
- assign mio_pad_sleep_mode_0_we = addr_hit[291] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_0_we = addr_hit[292] & reg_we & !reg_error;
assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_1_we = addr_hit[292] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_1_we = addr_hit[293] & reg_we & !reg_error;
assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_2_we = addr_hit[293] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_2_we = addr_hit[294] & reg_we & !reg_error;
assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_3_we = addr_hit[294] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_3_we = addr_hit[295] & reg_we & !reg_error;
assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_4_we = addr_hit[295] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_4_we = addr_hit[296] & reg_we & !reg_error;
assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_5_we = addr_hit[296] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_5_we = addr_hit[297] & reg_we & !reg_error;
assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_6_we = addr_hit[297] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_6_we = addr_hit[298] & reg_we & !reg_error;
assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_7_we = addr_hit[298] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_7_we = addr_hit[299] & reg_we & !reg_error;
assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_8_we = addr_hit[299] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_8_we = addr_hit[300] & reg_we & !reg_error;
assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_9_we = addr_hit[300] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_9_we = addr_hit[301] & reg_we & !reg_error;
assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_10_we = addr_hit[301] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_10_we = addr_hit[302] & reg_we & !reg_error;
assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_11_we = addr_hit[302] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_11_we = addr_hit[303] & reg_we & !reg_error;
assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_12_we = addr_hit[303] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_12_we = addr_hit[304] & reg_we & !reg_error;
assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_13_we = addr_hit[304] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_13_we = addr_hit[305] & reg_we & !reg_error;
assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_14_we = addr_hit[305] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_14_we = addr_hit[306] & reg_we & !reg_error;
assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_15_we = addr_hit[306] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_15_we = addr_hit[307] & reg_we & !reg_error;
assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_16_we = addr_hit[307] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_16_we = addr_hit[308] & reg_we & !reg_error;
assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_17_we = addr_hit[308] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_17_we = addr_hit[309] & reg_we & !reg_error;
assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_18_we = addr_hit[309] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_18_we = addr_hit[310] & reg_we & !reg_error;
assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_19_we = addr_hit[310] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_19_we = addr_hit[311] & reg_we & !reg_error;
assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_20_we = addr_hit[311] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_20_we = addr_hit[312] & reg_we & !reg_error;
assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_21_we = addr_hit[312] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_21_we = addr_hit[313] & reg_we & !reg_error;
assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_22_we = addr_hit[313] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_22_we = addr_hit[314] & reg_we & !reg_error;
assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_23_we = addr_hit[314] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_23_we = addr_hit[315] & reg_we & !reg_error;
assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_24_we = addr_hit[315] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_24_we = addr_hit[316] & reg_we & !reg_error;
assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_25_we = addr_hit[316] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_25_we = addr_hit[317] & reg_we & !reg_error;
assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_26_we = addr_hit[317] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_26_we = addr_hit[318] & reg_we & !reg_error;
assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_27_we = addr_hit[318] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_27_we = addr_hit[319] & reg_we & !reg_error;
assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_28_we = addr_hit[319] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_28_we = addr_hit[320] & reg_we & !reg_error;
assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_29_we = addr_hit[320] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_29_we = addr_hit[321] & reg_we & !reg_error;
assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_30_we = addr_hit[321] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_30_we = addr_hit[322] & reg_we & !reg_error;
assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_31_we = addr_hit[322] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_31_we = addr_hit[323] & reg_we & !reg_error;
assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0];
- assign dio_pad_sleep_status_en_0_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_0_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_0_wd = reg_wdata[0];
- assign dio_pad_sleep_status_en_1_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_1_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_1_wd = reg_wdata[1];
- assign dio_pad_sleep_status_en_2_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_2_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_2_wd = reg_wdata[2];
- assign dio_pad_sleep_status_en_3_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_3_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_3_wd = reg_wdata[3];
- assign dio_pad_sleep_status_en_4_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_4_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_4_wd = reg_wdata[4];
- assign dio_pad_sleep_status_en_5_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_5_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_5_wd = reg_wdata[5];
- assign dio_pad_sleep_status_en_6_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_6_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_6_wd = reg_wdata[6];
- assign dio_pad_sleep_status_en_7_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_7_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_7_wd = reg_wdata[7];
- assign dio_pad_sleep_status_en_8_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_8_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_8_wd = reg_wdata[8];
- assign dio_pad_sleep_status_en_9_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_9_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_9_wd = reg_wdata[9];
- assign dio_pad_sleep_status_en_10_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_10_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_10_wd = reg_wdata[10];
- assign dio_pad_sleep_status_en_11_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_11_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_11_wd = reg_wdata[11];
- assign dio_pad_sleep_status_en_12_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_12_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_12_wd = reg_wdata[12];
- assign dio_pad_sleep_status_en_13_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_13_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_13_wd = reg_wdata[13];
- assign dio_pad_sleep_status_en_14_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_14_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_14_wd = reg_wdata[14];
- assign dio_pad_sleep_status_en_15_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_15_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_15_wd = reg_wdata[15];
- assign dio_pad_sleep_regwen_0_we = addr_hit[324] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_0_we = addr_hit[325] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_0_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_1_we = addr_hit[325] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_1_we = addr_hit[326] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_1_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_2_we = addr_hit[326] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_2_we = addr_hit[327] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_2_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_3_we = addr_hit[327] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_3_we = addr_hit[328] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_3_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_4_we = addr_hit[328] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_4_we = addr_hit[329] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_4_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_5_we = addr_hit[329] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_5_we = addr_hit[330] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_5_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_6_we = addr_hit[330] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_6_we = addr_hit[331] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_6_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_7_we = addr_hit[331] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_7_we = addr_hit[332] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_7_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_8_we = addr_hit[332] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_8_we = addr_hit[333] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_8_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_9_we = addr_hit[333] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_9_we = addr_hit[334] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_9_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_10_we = addr_hit[334] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_10_we = addr_hit[335] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_10_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_11_we = addr_hit[335] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_11_we = addr_hit[336] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_11_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_12_we = addr_hit[336] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_12_we = addr_hit[337] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_12_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_13_we = addr_hit[337] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_13_we = addr_hit[338] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_13_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_14_we = addr_hit[338] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_14_we = addr_hit[339] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_14_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_15_we = addr_hit[339] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_15_we = addr_hit[340] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_15_wd = reg_wdata[0];
- assign dio_pad_sleep_en_0_we = addr_hit[340] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_0_we = addr_hit[341] & reg_we & !reg_error;
assign dio_pad_sleep_en_0_wd = reg_wdata[0];
- assign dio_pad_sleep_en_1_we = addr_hit[341] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_1_we = addr_hit[342] & reg_we & !reg_error;
assign dio_pad_sleep_en_1_wd = reg_wdata[0];
- assign dio_pad_sleep_en_2_we = addr_hit[342] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_2_we = addr_hit[343] & reg_we & !reg_error;
assign dio_pad_sleep_en_2_wd = reg_wdata[0];
- assign dio_pad_sleep_en_3_we = addr_hit[343] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_3_we = addr_hit[344] & reg_we & !reg_error;
assign dio_pad_sleep_en_3_wd = reg_wdata[0];
- assign dio_pad_sleep_en_4_we = addr_hit[344] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_4_we = addr_hit[345] & reg_we & !reg_error;
assign dio_pad_sleep_en_4_wd = reg_wdata[0];
- assign dio_pad_sleep_en_5_we = addr_hit[345] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_5_we = addr_hit[346] & reg_we & !reg_error;
assign dio_pad_sleep_en_5_wd = reg_wdata[0];
- assign dio_pad_sleep_en_6_we = addr_hit[346] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_6_we = addr_hit[347] & reg_we & !reg_error;
assign dio_pad_sleep_en_6_wd = reg_wdata[0];
- assign dio_pad_sleep_en_7_we = addr_hit[347] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_7_we = addr_hit[348] & reg_we & !reg_error;
assign dio_pad_sleep_en_7_wd = reg_wdata[0];
- assign dio_pad_sleep_en_8_we = addr_hit[348] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_8_we = addr_hit[349] & reg_we & !reg_error;
assign dio_pad_sleep_en_8_wd = reg_wdata[0];
- assign dio_pad_sleep_en_9_we = addr_hit[349] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_9_we = addr_hit[350] & reg_we & !reg_error;
assign dio_pad_sleep_en_9_wd = reg_wdata[0];
- assign dio_pad_sleep_en_10_we = addr_hit[350] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_10_we = addr_hit[351] & reg_we & !reg_error;
assign dio_pad_sleep_en_10_wd = reg_wdata[0];
- assign dio_pad_sleep_en_11_we = addr_hit[351] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_11_we = addr_hit[352] & reg_we & !reg_error;
assign dio_pad_sleep_en_11_wd = reg_wdata[0];
- assign dio_pad_sleep_en_12_we = addr_hit[352] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_12_we = addr_hit[353] & reg_we & !reg_error;
assign dio_pad_sleep_en_12_wd = reg_wdata[0];
- assign dio_pad_sleep_en_13_we = addr_hit[353] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_13_we = addr_hit[354] & reg_we & !reg_error;
assign dio_pad_sleep_en_13_wd = reg_wdata[0];
- assign dio_pad_sleep_en_14_we = addr_hit[354] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_14_we = addr_hit[355] & reg_we & !reg_error;
assign dio_pad_sleep_en_14_wd = reg_wdata[0];
- assign dio_pad_sleep_en_15_we = addr_hit[355] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_15_we = addr_hit[356] & reg_we & !reg_error;
assign dio_pad_sleep_en_15_wd = reg_wdata[0];
- assign dio_pad_sleep_mode_0_we = addr_hit[356] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_0_we = addr_hit[357] & reg_we & !reg_error;
assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_1_we = addr_hit[357] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_1_we = addr_hit[358] & reg_we & !reg_error;
assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_2_we = addr_hit[358] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_2_we = addr_hit[359] & reg_we & !reg_error;
assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_3_we = addr_hit[359] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_3_we = addr_hit[360] & reg_we & !reg_error;
assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_4_we = addr_hit[360] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_4_we = addr_hit[361] & reg_we & !reg_error;
assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_5_we = addr_hit[361] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_5_we = addr_hit[362] & reg_we & !reg_error;
assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_6_we = addr_hit[362] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_6_we = addr_hit[363] & reg_we & !reg_error;
assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_7_we = addr_hit[363] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_7_we = addr_hit[364] & reg_we & !reg_error;
assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_8_we = addr_hit[364] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_8_we = addr_hit[365] & reg_we & !reg_error;
assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_9_we = addr_hit[365] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_9_we = addr_hit[366] & reg_we & !reg_error;
assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_10_we = addr_hit[366] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_10_we = addr_hit[367] & reg_we & !reg_error;
assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_11_we = addr_hit[367] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_11_we = addr_hit[368] & reg_we & !reg_error;
assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_12_we = addr_hit[368] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_12_we = addr_hit[369] & reg_we & !reg_error;
assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_13_we = addr_hit[369] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_13_we = addr_hit[370] & reg_we & !reg_error;
assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_14_we = addr_hit[370] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_14_we = addr_hit[371] & reg_we & !reg_error;
assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_15_we = addr_hit[371] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_15_we = addr_hit[372] & reg_we & !reg_error;
assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0];
- assign wkup_detector_regwen_0_we = addr_hit[372] & reg_we & !reg_error;
+ assign wkup_detector_regwen_0_we = addr_hit[373] & reg_we & !reg_error;
assign wkup_detector_regwen_0_wd = reg_wdata[0];
- assign wkup_detector_regwen_1_we = addr_hit[373] & reg_we & !reg_error;
+ assign wkup_detector_regwen_1_we = addr_hit[374] & reg_we & !reg_error;
assign wkup_detector_regwen_1_wd = reg_wdata[0];
- assign wkup_detector_regwen_2_we = addr_hit[374] & reg_we & !reg_error;
+ assign wkup_detector_regwen_2_we = addr_hit[375] & reg_we & !reg_error;
assign wkup_detector_regwen_2_wd = reg_wdata[0];
- assign wkup_detector_regwen_3_we = addr_hit[375] & reg_we & !reg_error;
+ assign wkup_detector_regwen_3_we = addr_hit[376] & reg_we & !reg_error;
assign wkup_detector_regwen_3_wd = reg_wdata[0];
- assign wkup_detector_regwen_4_we = addr_hit[376] & reg_we & !reg_error;
+ assign wkup_detector_regwen_4_we = addr_hit[377] & reg_we & !reg_error;
assign wkup_detector_regwen_4_wd = reg_wdata[0];
- assign wkup_detector_regwen_5_we = addr_hit[377] & reg_we & !reg_error;
+ assign wkup_detector_regwen_5_we = addr_hit[378] & reg_we & !reg_error;
assign wkup_detector_regwen_5_wd = reg_wdata[0];
- assign wkup_detector_regwen_6_we = addr_hit[378] & reg_we & !reg_error;
+ assign wkup_detector_regwen_6_we = addr_hit[379] & reg_we & !reg_error;
assign wkup_detector_regwen_6_wd = reg_wdata[0];
- assign wkup_detector_regwen_7_we = addr_hit[379] & reg_we & !reg_error;
+ assign wkup_detector_regwen_7_we = addr_hit[380] & reg_we & !reg_error;
assign wkup_detector_regwen_7_wd = reg_wdata[0];
- assign wkup_detector_en_0_we = addr_hit[380] & reg_we & !reg_error;
+ assign wkup_detector_en_0_we = addr_hit[381] & reg_we & !reg_error;
assign wkup_detector_en_0_wd = reg_wdata[0];
- assign wkup_detector_en_1_we = addr_hit[381] & reg_we & !reg_error;
+ assign wkup_detector_en_1_we = addr_hit[382] & reg_we & !reg_error;
assign wkup_detector_en_1_wd = reg_wdata[0];
- assign wkup_detector_en_2_we = addr_hit[382] & reg_we & !reg_error;
+ assign wkup_detector_en_2_we = addr_hit[383] & reg_we & !reg_error;
assign wkup_detector_en_2_wd = reg_wdata[0];
- assign wkup_detector_en_3_we = addr_hit[383] & reg_we & !reg_error;
+ assign wkup_detector_en_3_we = addr_hit[384] & reg_we & !reg_error;
assign wkup_detector_en_3_wd = reg_wdata[0];
- assign wkup_detector_en_4_we = addr_hit[384] & reg_we & !reg_error;
+ assign wkup_detector_en_4_we = addr_hit[385] & reg_we & !reg_error;
assign wkup_detector_en_4_wd = reg_wdata[0];
- assign wkup_detector_en_5_we = addr_hit[385] & reg_we & !reg_error;
+ assign wkup_detector_en_5_we = addr_hit[386] & reg_we & !reg_error;
assign wkup_detector_en_5_wd = reg_wdata[0];
- assign wkup_detector_en_6_we = addr_hit[386] & reg_we & !reg_error;
+ assign wkup_detector_en_6_we = addr_hit[387] & reg_we & !reg_error;
assign wkup_detector_en_6_wd = reg_wdata[0];
- assign wkup_detector_en_7_we = addr_hit[387] & reg_we & !reg_error;
+ assign wkup_detector_en_7_we = addr_hit[388] & reg_we & !reg_error;
assign wkup_detector_en_7_wd = reg_wdata[0];
- assign wkup_detector_0_mode_0_we = addr_hit[388] & reg_we & !reg_error;
+ assign wkup_detector_0_mode_0_we = addr_hit[389] & reg_we & !reg_error;
assign wkup_detector_0_mode_0_wd = reg_wdata[2:0];
- assign wkup_detector_0_filter_0_we = addr_hit[388] & reg_we & !reg_error;
+ assign wkup_detector_0_filter_0_we = addr_hit[389] & reg_we & !reg_error;
assign wkup_detector_0_filter_0_wd = reg_wdata[3];
- assign wkup_detector_0_miodio_0_we = addr_hit[388] & reg_we & !reg_error;
+ assign wkup_detector_0_miodio_0_we = addr_hit[389] & reg_we & !reg_error;
assign wkup_detector_0_miodio_0_wd = reg_wdata[4];
- assign wkup_detector_1_mode_1_we = addr_hit[389] & reg_we & !reg_error;
+ assign wkup_detector_1_mode_1_we = addr_hit[390] & reg_we & !reg_error;
assign wkup_detector_1_mode_1_wd = reg_wdata[2:0];
- assign wkup_detector_1_filter_1_we = addr_hit[389] & reg_we & !reg_error;
+ assign wkup_detector_1_filter_1_we = addr_hit[390] & reg_we & !reg_error;
assign wkup_detector_1_filter_1_wd = reg_wdata[3];
- assign wkup_detector_1_miodio_1_we = addr_hit[389] & reg_we & !reg_error;
+ assign wkup_detector_1_miodio_1_we = addr_hit[390] & reg_we & !reg_error;
assign wkup_detector_1_miodio_1_wd = reg_wdata[4];
- assign wkup_detector_2_mode_2_we = addr_hit[390] & reg_we & !reg_error;
+ assign wkup_detector_2_mode_2_we = addr_hit[391] & reg_we & !reg_error;
assign wkup_detector_2_mode_2_wd = reg_wdata[2:0];
- assign wkup_detector_2_filter_2_we = addr_hit[390] & reg_we & !reg_error;
+ assign wkup_detector_2_filter_2_we = addr_hit[391] & reg_we & !reg_error;
assign wkup_detector_2_filter_2_wd = reg_wdata[3];
- assign wkup_detector_2_miodio_2_we = addr_hit[390] & reg_we & !reg_error;
+ assign wkup_detector_2_miodio_2_we = addr_hit[391] & reg_we & !reg_error;
assign wkup_detector_2_miodio_2_wd = reg_wdata[4];
- assign wkup_detector_3_mode_3_we = addr_hit[391] & reg_we & !reg_error;
+ assign wkup_detector_3_mode_3_we = addr_hit[392] & reg_we & !reg_error;
assign wkup_detector_3_mode_3_wd = reg_wdata[2:0];
- assign wkup_detector_3_filter_3_we = addr_hit[391] & reg_we & !reg_error;
+ assign wkup_detector_3_filter_3_we = addr_hit[392] & reg_we & !reg_error;
assign wkup_detector_3_filter_3_wd = reg_wdata[3];
- assign wkup_detector_3_miodio_3_we = addr_hit[391] & reg_we & !reg_error;
+ assign wkup_detector_3_miodio_3_we = addr_hit[392] & reg_we & !reg_error;
assign wkup_detector_3_miodio_3_wd = reg_wdata[4];
- assign wkup_detector_4_mode_4_we = addr_hit[392] & reg_we & !reg_error;
+ assign wkup_detector_4_mode_4_we = addr_hit[393] & reg_we & !reg_error;
assign wkup_detector_4_mode_4_wd = reg_wdata[2:0];
- assign wkup_detector_4_filter_4_we = addr_hit[392] & reg_we & !reg_error;
+ assign wkup_detector_4_filter_4_we = addr_hit[393] & reg_we & !reg_error;
assign wkup_detector_4_filter_4_wd = reg_wdata[3];
- assign wkup_detector_4_miodio_4_we = addr_hit[392] & reg_we & !reg_error;
+ assign wkup_detector_4_miodio_4_we = addr_hit[393] & reg_we & !reg_error;
assign wkup_detector_4_miodio_4_wd = reg_wdata[4];
- assign wkup_detector_5_mode_5_we = addr_hit[393] & reg_we & !reg_error;
+ assign wkup_detector_5_mode_5_we = addr_hit[394] & reg_we & !reg_error;
assign wkup_detector_5_mode_5_wd = reg_wdata[2:0];
- assign wkup_detector_5_filter_5_we = addr_hit[393] & reg_we & !reg_error;
+ assign wkup_detector_5_filter_5_we = addr_hit[394] & reg_we & !reg_error;
assign wkup_detector_5_filter_5_wd = reg_wdata[3];
- assign wkup_detector_5_miodio_5_we = addr_hit[393] & reg_we & !reg_error;
+ assign wkup_detector_5_miodio_5_we = addr_hit[394] & reg_we & !reg_error;
assign wkup_detector_5_miodio_5_wd = reg_wdata[4];
- assign wkup_detector_6_mode_6_we = addr_hit[394] & reg_we & !reg_error;
+ assign wkup_detector_6_mode_6_we = addr_hit[395] & reg_we & !reg_error;
assign wkup_detector_6_mode_6_wd = reg_wdata[2:0];
- assign wkup_detector_6_filter_6_we = addr_hit[394] & reg_we & !reg_error;
+ assign wkup_detector_6_filter_6_we = addr_hit[395] & reg_we & !reg_error;
assign wkup_detector_6_filter_6_wd = reg_wdata[3];
- assign wkup_detector_6_miodio_6_we = addr_hit[394] & reg_we & !reg_error;
+ assign wkup_detector_6_miodio_6_we = addr_hit[395] & reg_we & !reg_error;
assign wkup_detector_6_miodio_6_wd = reg_wdata[4];
- assign wkup_detector_7_mode_7_we = addr_hit[395] & reg_we & !reg_error;
+ assign wkup_detector_7_mode_7_we = addr_hit[396] & reg_we & !reg_error;
assign wkup_detector_7_mode_7_wd = reg_wdata[2:0];
- assign wkup_detector_7_filter_7_we = addr_hit[395] & reg_we & !reg_error;
+ assign wkup_detector_7_filter_7_we = addr_hit[396] & reg_we & !reg_error;
assign wkup_detector_7_filter_7_wd = reg_wdata[3];
- assign wkup_detector_7_miodio_7_we = addr_hit[395] & reg_we & !reg_error;
+ assign wkup_detector_7_miodio_7_we = addr_hit[396] & reg_we & !reg_error;
assign wkup_detector_7_miodio_7_wd = reg_wdata[4];
- assign wkup_detector_cnt_th_0_we = addr_hit[396] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_0_we = addr_hit[397] & reg_we & !reg_error;
assign wkup_detector_cnt_th_0_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_1_we = addr_hit[397] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_1_we = addr_hit[398] & reg_we & !reg_error;
assign wkup_detector_cnt_th_1_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_2_we = addr_hit[398] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_2_we = addr_hit[399] & reg_we & !reg_error;
assign wkup_detector_cnt_th_2_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_3_we = addr_hit[399] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_3_we = addr_hit[400] & reg_we & !reg_error;
assign wkup_detector_cnt_th_3_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_4_we = addr_hit[400] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_4_we = addr_hit[401] & reg_we & !reg_error;
assign wkup_detector_cnt_th_4_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_5_we = addr_hit[401] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_5_we = addr_hit[402] & reg_we & !reg_error;
assign wkup_detector_cnt_th_5_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_6_we = addr_hit[402] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_6_we = addr_hit[403] & reg_we & !reg_error;
assign wkup_detector_cnt_th_6_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_7_we = addr_hit[403] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_7_we = addr_hit[404] & reg_we & !reg_error;
assign wkup_detector_cnt_th_7_wd = reg_wdata[7:0];
- assign wkup_detector_padsel_0_we = addr_hit[404] & reg_we & !reg_error;
+ assign wkup_detector_padsel_0_we = addr_hit[405] & reg_we & !reg_error;
assign wkup_detector_padsel_0_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_1_we = addr_hit[405] & reg_we & !reg_error;
+ assign wkup_detector_padsel_1_we = addr_hit[406] & reg_we & !reg_error;
assign wkup_detector_padsel_1_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_2_we = addr_hit[406] & reg_we & !reg_error;
+ assign wkup_detector_padsel_2_we = addr_hit[407] & reg_we & !reg_error;
assign wkup_detector_padsel_2_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_3_we = addr_hit[407] & reg_we & !reg_error;
+ assign wkup_detector_padsel_3_we = addr_hit[408] & reg_we & !reg_error;
assign wkup_detector_padsel_3_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_4_we = addr_hit[408] & reg_we & !reg_error;
+ assign wkup_detector_padsel_4_we = addr_hit[409] & reg_we & !reg_error;
assign wkup_detector_padsel_4_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_5_we = addr_hit[409] & reg_we & !reg_error;
+ assign wkup_detector_padsel_5_we = addr_hit[410] & reg_we & !reg_error;
assign wkup_detector_padsel_5_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_6_we = addr_hit[410] & reg_we & !reg_error;
+ assign wkup_detector_padsel_6_we = addr_hit[411] & reg_we & !reg_error;
assign wkup_detector_padsel_6_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_7_we = addr_hit[411] & reg_we & !reg_error;
+ assign wkup_detector_padsel_7_we = addr_hit[412] & reg_we & !reg_error;
assign wkup_detector_padsel_7_wd = reg_wdata[5:0];
- assign wkup_cause_cause_0_we = addr_hit[412] & reg_we & !reg_error;
+ assign wkup_cause_cause_0_we = addr_hit[413] & reg_we & !reg_error;
assign wkup_cause_cause_0_wd = reg_wdata[0];
- assign wkup_cause_cause_0_re = addr_hit[412] & reg_re & !reg_error;
+ assign wkup_cause_cause_0_re = addr_hit[413] & reg_re & !reg_error;
- assign wkup_cause_cause_1_we = addr_hit[412] & reg_we & !reg_error;
+ assign wkup_cause_cause_1_we = addr_hit[413] & reg_we & !reg_error;
assign wkup_cause_cause_1_wd = reg_wdata[1];
- assign wkup_cause_cause_1_re = addr_hit[412] & reg_re & !reg_error;
+ assign wkup_cause_cause_1_re = addr_hit[413] & reg_re & !reg_error;
- assign wkup_cause_cause_2_we = addr_hit[412] & reg_we & !reg_error;
+ assign wkup_cause_cause_2_we = addr_hit[413] & reg_we & !reg_error;
assign wkup_cause_cause_2_wd = reg_wdata[2];
- assign wkup_cause_cause_2_re = addr_hit[412] & reg_re & !reg_error;
+ assign wkup_cause_cause_2_re = addr_hit[413] & reg_re & !reg_error;
- assign wkup_cause_cause_3_we = addr_hit[412] & reg_we & !reg_error;
+ assign wkup_cause_cause_3_we = addr_hit[413] & reg_we & !reg_error;
assign wkup_cause_cause_3_wd = reg_wdata[3];
- assign wkup_cause_cause_3_re = addr_hit[412] & reg_re & !reg_error;
+ assign wkup_cause_cause_3_re = addr_hit[413] & reg_re & !reg_error;
- assign wkup_cause_cause_4_we = addr_hit[412] & reg_we & !reg_error;
+ assign wkup_cause_cause_4_we = addr_hit[413] & reg_we & !reg_error;
assign wkup_cause_cause_4_wd = reg_wdata[4];
- assign wkup_cause_cause_4_re = addr_hit[412] & reg_re & !reg_error;
+ assign wkup_cause_cause_4_re = addr_hit[413] & reg_re & !reg_error;
- assign wkup_cause_cause_5_we = addr_hit[412] & reg_we & !reg_error;
+ assign wkup_cause_cause_5_we = addr_hit[413] & reg_we & !reg_error;
assign wkup_cause_cause_5_wd = reg_wdata[5];
- assign wkup_cause_cause_5_re = addr_hit[412] & reg_re & !reg_error;
+ assign wkup_cause_cause_5_re = addr_hit[413] & reg_re & !reg_error;
- assign wkup_cause_cause_6_we = addr_hit[412] & reg_we & !reg_error;
+ assign wkup_cause_cause_6_we = addr_hit[413] & reg_we & !reg_error;
assign wkup_cause_cause_6_wd = reg_wdata[6];
- assign wkup_cause_cause_6_re = addr_hit[412] & reg_re & !reg_error;
+ assign wkup_cause_cause_6_re = addr_hit[413] & reg_re & !reg_error;
- assign wkup_cause_cause_7_we = addr_hit[412] & reg_we & !reg_error;
+ assign wkup_cause_cause_7_we = addr_hit[413] & reg_we & !reg_error;
assign wkup_cause_cause_7_wd = reg_wdata[7];
- assign wkup_cause_cause_7_re = addr_hit[412] & reg_re & !reg_error;
+ assign wkup_cause_cause_7_re = addr_hit[413] & reg_re & !reg_error;
// Read data return
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_0_qs;
+ reg_rdata_next[0] = '0;
end
addr_hit[1]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_1_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_0_qs;
end
addr_hit[2]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_2_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_1_qs;
end
addr_hit[3]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_3_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_2_qs;
end
addr_hit[4]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_4_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_3_qs;
end
addr_hit[5]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_5_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_4_qs;
end
addr_hit[6]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_6_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_5_qs;
end
addr_hit[7]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_7_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_6_qs;
end
addr_hit[8]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_8_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_7_qs;
end
addr_hit[9]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_9_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_8_qs;
end
addr_hit[10]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_10_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_9_qs;
end
addr_hit[11]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_11_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_10_qs;
end
addr_hit[12]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_12_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_11_qs;
end
addr_hit[13]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_13_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_12_qs;
end
addr_hit[14]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_14_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_13_qs;
end
addr_hit[15]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_15_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_14_qs;
end
addr_hit[16]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_16_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_15_qs;
end
addr_hit[17]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_17_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_16_qs;
end
addr_hit[18]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_18_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_17_qs;
end
addr_hit[19]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_19_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_18_qs;
end
addr_hit[20]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_20_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_19_qs;
end
addr_hit[21]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_21_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_20_qs;
end
addr_hit[22]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_22_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_21_qs;
end
addr_hit[23]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_23_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_22_qs;
end
addr_hit[24]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_24_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_23_qs;
end
addr_hit[25]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_25_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_24_qs;
end
addr_hit[26]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_26_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_25_qs;
end
addr_hit[27]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_27_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_26_qs;
end
addr_hit[28]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_28_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_27_qs;
end
addr_hit[29]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_29_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_28_qs;
end
addr_hit[30]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_30_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_29_qs;
end
addr_hit[31]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_31_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_30_qs;
end
addr_hit[32]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_32_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_31_qs;
end
addr_hit[33]: begin
- reg_rdata_next[5:0] = mio_periph_insel_0_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_32_qs;
end
addr_hit[34]: begin
- reg_rdata_next[5:0] = mio_periph_insel_1_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_0_qs;
end
addr_hit[35]: begin
- reg_rdata_next[5:0] = mio_periph_insel_2_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_1_qs;
end
addr_hit[36]: begin
- reg_rdata_next[5:0] = mio_periph_insel_3_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_2_qs;
end
addr_hit[37]: begin
- reg_rdata_next[5:0] = mio_periph_insel_4_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_3_qs;
end
addr_hit[38]: begin
- reg_rdata_next[5:0] = mio_periph_insel_5_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_4_qs;
end
addr_hit[39]: begin
- reg_rdata_next[5:0] = mio_periph_insel_6_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_5_qs;
end
addr_hit[40]: begin
- reg_rdata_next[5:0] = mio_periph_insel_7_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_6_qs;
end
addr_hit[41]: begin
- reg_rdata_next[5:0] = mio_periph_insel_8_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_7_qs;
end
addr_hit[42]: begin
- reg_rdata_next[5:0] = mio_periph_insel_9_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_8_qs;
end
addr_hit[43]: begin
- reg_rdata_next[5:0] = mio_periph_insel_10_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_9_qs;
end
addr_hit[44]: begin
- reg_rdata_next[5:0] = mio_periph_insel_11_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_10_qs;
end
addr_hit[45]: begin
- reg_rdata_next[5:0] = mio_periph_insel_12_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_11_qs;
end
addr_hit[46]: begin
- reg_rdata_next[5:0] = mio_periph_insel_13_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_12_qs;
end
addr_hit[47]: begin
- reg_rdata_next[5:0] = mio_periph_insel_14_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_13_qs;
end
addr_hit[48]: begin
- reg_rdata_next[5:0] = mio_periph_insel_15_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_14_qs;
end
addr_hit[49]: begin
- reg_rdata_next[5:0] = mio_periph_insel_16_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_15_qs;
end
addr_hit[50]: begin
- reg_rdata_next[5:0] = mio_periph_insel_17_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_16_qs;
end
addr_hit[51]: begin
- reg_rdata_next[5:0] = mio_periph_insel_18_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_17_qs;
end
addr_hit[52]: begin
- reg_rdata_next[5:0] = mio_periph_insel_19_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_18_qs;
end
addr_hit[53]: begin
- reg_rdata_next[5:0] = mio_periph_insel_20_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_19_qs;
end
addr_hit[54]: begin
- reg_rdata_next[5:0] = mio_periph_insel_21_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_20_qs;
end
addr_hit[55]: begin
- reg_rdata_next[5:0] = mio_periph_insel_22_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_21_qs;
end
addr_hit[56]: begin
- reg_rdata_next[5:0] = mio_periph_insel_23_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_22_qs;
end
addr_hit[57]: begin
- reg_rdata_next[5:0] = mio_periph_insel_24_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_23_qs;
end
addr_hit[58]: begin
- reg_rdata_next[5:0] = mio_periph_insel_25_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_24_qs;
end
addr_hit[59]: begin
- reg_rdata_next[5:0] = mio_periph_insel_26_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_25_qs;
end
addr_hit[60]: begin
- reg_rdata_next[5:0] = mio_periph_insel_27_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_26_qs;
end
addr_hit[61]: begin
- reg_rdata_next[5:0] = mio_periph_insel_28_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_27_qs;
end
addr_hit[62]: begin
- reg_rdata_next[5:0] = mio_periph_insel_29_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_28_qs;
end
addr_hit[63]: begin
- reg_rdata_next[5:0] = mio_periph_insel_30_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_29_qs;
end
addr_hit[64]: begin
- reg_rdata_next[5:0] = mio_periph_insel_31_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_30_qs;
end
addr_hit[65]: begin
- reg_rdata_next[5:0] = mio_periph_insel_32_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_31_qs;
end
addr_hit[66]: begin
- reg_rdata_next[0] = mio_outsel_regwen_0_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_32_qs;
end
addr_hit[67]: begin
- reg_rdata_next[0] = mio_outsel_regwen_1_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_0_qs;
end
addr_hit[68]: begin
- reg_rdata_next[0] = mio_outsel_regwen_2_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_1_qs;
end
addr_hit[69]: begin
- reg_rdata_next[0] = mio_outsel_regwen_3_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_2_qs;
end
addr_hit[70]: begin
- reg_rdata_next[0] = mio_outsel_regwen_4_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_3_qs;
end
addr_hit[71]: begin
- reg_rdata_next[0] = mio_outsel_regwen_5_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_4_qs;
end
addr_hit[72]: begin
- reg_rdata_next[0] = mio_outsel_regwen_6_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_5_qs;
end
addr_hit[73]: begin
- reg_rdata_next[0] = mio_outsel_regwen_7_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_6_qs;
end
addr_hit[74]: begin
- reg_rdata_next[0] = mio_outsel_regwen_8_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_7_qs;
end
addr_hit[75]: begin
- reg_rdata_next[0] = mio_outsel_regwen_9_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_8_qs;
end
addr_hit[76]: begin
- reg_rdata_next[0] = mio_outsel_regwen_10_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_9_qs;
end
addr_hit[77]: begin
- reg_rdata_next[0] = mio_outsel_regwen_11_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_10_qs;
end
addr_hit[78]: begin
- reg_rdata_next[0] = mio_outsel_regwen_12_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_11_qs;
end
addr_hit[79]: begin
- reg_rdata_next[0] = mio_outsel_regwen_13_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_12_qs;
end
addr_hit[80]: begin
- reg_rdata_next[0] = mio_outsel_regwen_14_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_13_qs;
end
addr_hit[81]: begin
- reg_rdata_next[0] = mio_outsel_regwen_15_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_14_qs;
end
addr_hit[82]: begin
- reg_rdata_next[0] = mio_outsel_regwen_16_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_15_qs;
end
addr_hit[83]: begin
- reg_rdata_next[0] = mio_outsel_regwen_17_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_16_qs;
end
addr_hit[84]: begin
- reg_rdata_next[0] = mio_outsel_regwen_18_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_17_qs;
end
addr_hit[85]: begin
- reg_rdata_next[0] = mio_outsel_regwen_19_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_18_qs;
end
addr_hit[86]: begin
- reg_rdata_next[0] = mio_outsel_regwen_20_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_19_qs;
end
addr_hit[87]: begin
- reg_rdata_next[0] = mio_outsel_regwen_21_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_20_qs;
end
addr_hit[88]: begin
- reg_rdata_next[0] = mio_outsel_regwen_22_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_21_qs;
end
addr_hit[89]: begin
- reg_rdata_next[0] = mio_outsel_regwen_23_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_22_qs;
end
addr_hit[90]: begin
- reg_rdata_next[0] = mio_outsel_regwen_24_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_23_qs;
end
addr_hit[91]: begin
- reg_rdata_next[0] = mio_outsel_regwen_25_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_24_qs;
end
addr_hit[92]: begin
- reg_rdata_next[0] = mio_outsel_regwen_26_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_25_qs;
end
addr_hit[93]: begin
- reg_rdata_next[0] = mio_outsel_regwen_27_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_26_qs;
end
addr_hit[94]: begin
- reg_rdata_next[0] = mio_outsel_regwen_28_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_27_qs;
end
addr_hit[95]: begin
- reg_rdata_next[0] = mio_outsel_regwen_29_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_28_qs;
end
addr_hit[96]: begin
- reg_rdata_next[0] = mio_outsel_regwen_30_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_29_qs;
end
addr_hit[97]: begin
- reg_rdata_next[0] = mio_outsel_regwen_31_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_30_qs;
end
addr_hit[98]: begin
- reg_rdata_next[5:0] = mio_outsel_0_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_31_qs;
end
addr_hit[99]: begin
- reg_rdata_next[5:0] = mio_outsel_1_qs;
+ reg_rdata_next[5:0] = mio_outsel_0_qs;
end
addr_hit[100]: begin
- reg_rdata_next[5:0] = mio_outsel_2_qs;
+ reg_rdata_next[5:0] = mio_outsel_1_qs;
end
addr_hit[101]: begin
- reg_rdata_next[5:0] = mio_outsel_3_qs;
+ reg_rdata_next[5:0] = mio_outsel_2_qs;
end
addr_hit[102]: begin
- reg_rdata_next[5:0] = mio_outsel_4_qs;
+ reg_rdata_next[5:0] = mio_outsel_3_qs;
end
addr_hit[103]: begin
- reg_rdata_next[5:0] = mio_outsel_5_qs;
+ reg_rdata_next[5:0] = mio_outsel_4_qs;
end
addr_hit[104]: begin
- reg_rdata_next[5:0] = mio_outsel_6_qs;
+ reg_rdata_next[5:0] = mio_outsel_5_qs;
end
addr_hit[105]: begin
- reg_rdata_next[5:0] = mio_outsel_7_qs;
+ reg_rdata_next[5:0] = mio_outsel_6_qs;
end
addr_hit[106]: begin
- reg_rdata_next[5:0] = mio_outsel_8_qs;
+ reg_rdata_next[5:0] = mio_outsel_7_qs;
end
addr_hit[107]: begin
- reg_rdata_next[5:0] = mio_outsel_9_qs;
+ reg_rdata_next[5:0] = mio_outsel_8_qs;
end
addr_hit[108]: begin
- reg_rdata_next[5:0] = mio_outsel_10_qs;
+ reg_rdata_next[5:0] = mio_outsel_9_qs;
end
addr_hit[109]: begin
- reg_rdata_next[5:0] = mio_outsel_11_qs;
+ reg_rdata_next[5:0] = mio_outsel_10_qs;
end
addr_hit[110]: begin
- reg_rdata_next[5:0] = mio_outsel_12_qs;
+ reg_rdata_next[5:0] = mio_outsel_11_qs;
end
addr_hit[111]: begin
- reg_rdata_next[5:0] = mio_outsel_13_qs;
+ reg_rdata_next[5:0] = mio_outsel_12_qs;
end
addr_hit[112]: begin
- reg_rdata_next[5:0] = mio_outsel_14_qs;
+ reg_rdata_next[5:0] = mio_outsel_13_qs;
end
addr_hit[113]: begin
- reg_rdata_next[5:0] = mio_outsel_15_qs;
+ reg_rdata_next[5:0] = mio_outsel_14_qs;
end
addr_hit[114]: begin
- reg_rdata_next[5:0] = mio_outsel_16_qs;
+ reg_rdata_next[5:0] = mio_outsel_15_qs;
end
addr_hit[115]: begin
- reg_rdata_next[5:0] = mio_outsel_17_qs;
+ reg_rdata_next[5:0] = mio_outsel_16_qs;
end
addr_hit[116]: begin
- reg_rdata_next[5:0] = mio_outsel_18_qs;
+ reg_rdata_next[5:0] = mio_outsel_17_qs;
end
addr_hit[117]: begin
- reg_rdata_next[5:0] = mio_outsel_19_qs;
+ reg_rdata_next[5:0] = mio_outsel_18_qs;
end
addr_hit[118]: begin
- reg_rdata_next[5:0] = mio_outsel_20_qs;
+ reg_rdata_next[5:0] = mio_outsel_19_qs;
end
addr_hit[119]: begin
- reg_rdata_next[5:0] = mio_outsel_21_qs;
+ reg_rdata_next[5:0] = mio_outsel_20_qs;
end
addr_hit[120]: begin
- reg_rdata_next[5:0] = mio_outsel_22_qs;
+ reg_rdata_next[5:0] = mio_outsel_21_qs;
end
addr_hit[121]: begin
- reg_rdata_next[5:0] = mio_outsel_23_qs;
+ reg_rdata_next[5:0] = mio_outsel_22_qs;
end
addr_hit[122]: begin
- reg_rdata_next[5:0] = mio_outsel_24_qs;
+ reg_rdata_next[5:0] = mio_outsel_23_qs;
end
addr_hit[123]: begin
- reg_rdata_next[5:0] = mio_outsel_25_qs;
+ reg_rdata_next[5:0] = mio_outsel_24_qs;
end
addr_hit[124]: begin
- reg_rdata_next[5:0] = mio_outsel_26_qs;
+ reg_rdata_next[5:0] = mio_outsel_25_qs;
end
addr_hit[125]: begin
- reg_rdata_next[5:0] = mio_outsel_27_qs;
+ reg_rdata_next[5:0] = mio_outsel_26_qs;
end
addr_hit[126]: begin
- reg_rdata_next[5:0] = mio_outsel_28_qs;
+ reg_rdata_next[5:0] = mio_outsel_27_qs;
end
addr_hit[127]: begin
- reg_rdata_next[5:0] = mio_outsel_29_qs;
+ reg_rdata_next[5:0] = mio_outsel_28_qs;
end
addr_hit[128]: begin
- reg_rdata_next[5:0] = mio_outsel_30_qs;
+ reg_rdata_next[5:0] = mio_outsel_29_qs;
end
addr_hit[129]: begin
- reg_rdata_next[5:0] = mio_outsel_31_qs;
+ reg_rdata_next[5:0] = mio_outsel_30_qs;
end
addr_hit[130]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
+ reg_rdata_next[5:0] = mio_outsel_31_qs;
end
addr_hit[131]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
end
addr_hit[132]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
end
addr_hit[133]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
end
addr_hit[134]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
end
addr_hit[135]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
end
addr_hit[136]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
end
addr_hit[137]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
end
addr_hit[138]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
end
addr_hit[139]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
end
addr_hit[140]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
end
addr_hit[141]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
end
addr_hit[142]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
end
addr_hit[143]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
end
addr_hit[144]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
end
addr_hit[145]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
end
addr_hit[146]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
end
addr_hit[147]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
end
addr_hit[148]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
end
addr_hit[149]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
end
addr_hit[150]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
end
addr_hit[151]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
end
addr_hit[152]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
end
addr_hit[153]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
end
addr_hit[154]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
end
addr_hit[155]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
end
addr_hit[156]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
end
addr_hit[157]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
end
addr_hit[158]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
end
addr_hit[159]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
end
addr_hit[160]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
end
addr_hit[161]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
end
addr_hit[162]: begin
- reg_rdata_next[12:0] = mio_pad_attr_0_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
end
addr_hit[163]: begin
- reg_rdata_next[12:0] = mio_pad_attr_1_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_0_qs;
end
addr_hit[164]: begin
- reg_rdata_next[12:0] = mio_pad_attr_2_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_1_qs;
end
addr_hit[165]: begin
- reg_rdata_next[12:0] = mio_pad_attr_3_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_2_qs;
end
addr_hit[166]: begin
- reg_rdata_next[12:0] = mio_pad_attr_4_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_3_qs;
end
addr_hit[167]: begin
- reg_rdata_next[12:0] = mio_pad_attr_5_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_4_qs;
end
addr_hit[168]: begin
- reg_rdata_next[12:0] = mio_pad_attr_6_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_5_qs;
end
addr_hit[169]: begin
- reg_rdata_next[12:0] = mio_pad_attr_7_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_6_qs;
end
addr_hit[170]: begin
- reg_rdata_next[12:0] = mio_pad_attr_8_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_7_qs;
end
addr_hit[171]: begin
- reg_rdata_next[12:0] = mio_pad_attr_9_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_8_qs;
end
addr_hit[172]: begin
- reg_rdata_next[12:0] = mio_pad_attr_10_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_9_qs;
end
addr_hit[173]: begin
- reg_rdata_next[12:0] = mio_pad_attr_11_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_10_qs;
end
addr_hit[174]: begin
- reg_rdata_next[12:0] = mio_pad_attr_12_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_11_qs;
end
addr_hit[175]: begin
- reg_rdata_next[12:0] = mio_pad_attr_13_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_12_qs;
end
addr_hit[176]: begin
- reg_rdata_next[12:0] = mio_pad_attr_14_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_13_qs;
end
addr_hit[177]: begin
- reg_rdata_next[12:0] = mio_pad_attr_15_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_14_qs;
end
addr_hit[178]: begin
- reg_rdata_next[12:0] = mio_pad_attr_16_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_15_qs;
end
addr_hit[179]: begin
- reg_rdata_next[12:0] = mio_pad_attr_17_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_16_qs;
end
addr_hit[180]: begin
- reg_rdata_next[12:0] = mio_pad_attr_18_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_17_qs;
end
addr_hit[181]: begin
- reg_rdata_next[12:0] = mio_pad_attr_19_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_18_qs;
end
addr_hit[182]: begin
- reg_rdata_next[12:0] = mio_pad_attr_20_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_19_qs;
end
addr_hit[183]: begin
- reg_rdata_next[12:0] = mio_pad_attr_21_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_20_qs;
end
addr_hit[184]: begin
- reg_rdata_next[12:0] = mio_pad_attr_22_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_21_qs;
end
addr_hit[185]: begin
- reg_rdata_next[12:0] = mio_pad_attr_23_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_22_qs;
end
addr_hit[186]: begin
- reg_rdata_next[12:0] = mio_pad_attr_24_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_23_qs;
end
addr_hit[187]: begin
- reg_rdata_next[12:0] = mio_pad_attr_25_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_24_qs;
end
addr_hit[188]: begin
- reg_rdata_next[12:0] = mio_pad_attr_26_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_25_qs;
end
addr_hit[189]: begin
- reg_rdata_next[12:0] = mio_pad_attr_27_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_26_qs;
end
addr_hit[190]: begin
- reg_rdata_next[12:0] = mio_pad_attr_28_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_27_qs;
end
addr_hit[191]: begin
- reg_rdata_next[12:0] = mio_pad_attr_29_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_28_qs;
end
addr_hit[192]: begin
- reg_rdata_next[12:0] = mio_pad_attr_30_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_29_qs;
end
addr_hit[193]: begin
- reg_rdata_next[12:0] = mio_pad_attr_31_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_30_qs;
end
addr_hit[194]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_31_qs;
end
addr_hit[195]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
end
addr_hit[196]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
end
addr_hit[197]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
end
addr_hit[198]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
end
addr_hit[199]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
end
addr_hit[200]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
end
addr_hit[201]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
end
addr_hit[202]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
end
addr_hit[203]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
end
addr_hit[204]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
end
addr_hit[205]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
end
addr_hit[206]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
end
addr_hit[207]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
end
addr_hit[208]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
end
addr_hit[209]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_15_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
end
addr_hit[210]: begin
- reg_rdata_next[12:0] = dio_pad_attr_0_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_15_qs;
end
addr_hit[211]: begin
- reg_rdata_next[12:0] = dio_pad_attr_1_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_0_qs;
end
addr_hit[212]: begin
- reg_rdata_next[12:0] = dio_pad_attr_2_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_1_qs;
end
addr_hit[213]: begin
- reg_rdata_next[12:0] = dio_pad_attr_3_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_2_qs;
end
addr_hit[214]: begin
- reg_rdata_next[12:0] = dio_pad_attr_4_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_3_qs;
end
addr_hit[215]: begin
- reg_rdata_next[12:0] = dio_pad_attr_5_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_4_qs;
end
addr_hit[216]: begin
- reg_rdata_next[12:0] = dio_pad_attr_6_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_5_qs;
end
addr_hit[217]: begin
- reg_rdata_next[12:0] = dio_pad_attr_7_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_6_qs;
end
addr_hit[218]: begin
- reg_rdata_next[12:0] = dio_pad_attr_8_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_7_qs;
end
addr_hit[219]: begin
- reg_rdata_next[12:0] = dio_pad_attr_9_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_8_qs;
end
addr_hit[220]: begin
- reg_rdata_next[12:0] = dio_pad_attr_10_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_9_qs;
end
addr_hit[221]: begin
- reg_rdata_next[12:0] = dio_pad_attr_11_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_10_qs;
end
addr_hit[222]: begin
- reg_rdata_next[12:0] = dio_pad_attr_12_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_11_qs;
end
addr_hit[223]: begin
- reg_rdata_next[12:0] = dio_pad_attr_13_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_12_qs;
end
addr_hit[224]: begin
- reg_rdata_next[12:0] = dio_pad_attr_14_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_13_qs;
end
addr_hit[225]: begin
- reg_rdata_next[12:0] = dio_pad_attr_15_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_14_qs;
end
addr_hit[226]: begin
+ reg_rdata_next[12:0] = dio_pad_attr_15_qs;
+ end
+
+ addr_hit[227]: begin
reg_rdata_next[0] = mio_pad_sleep_status_en_0_qs;
reg_rdata_next[1] = mio_pad_sleep_status_en_1_qs;
reg_rdata_next[2] = mio_pad_sleep_status_en_2_qs;
@@ -17288,391 +17315,391 @@
reg_rdata_next[31] = mio_pad_sleep_status_en_31_qs;
end
- addr_hit[227]: begin
+ addr_hit[228]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs;
end
- addr_hit[228]: begin
+ addr_hit[229]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs;
end
- addr_hit[229]: begin
+ addr_hit[230]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs;
end
- addr_hit[230]: begin
+ addr_hit[231]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs;
end
- addr_hit[231]: begin
+ addr_hit[232]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs;
end
- addr_hit[232]: begin
+ addr_hit[233]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs;
end
- addr_hit[233]: begin
+ addr_hit[234]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs;
end
- addr_hit[234]: begin
+ addr_hit[235]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs;
end
- addr_hit[235]: begin
+ addr_hit[236]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs;
end
- addr_hit[236]: begin
+ addr_hit[237]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs;
end
- addr_hit[237]: begin
+ addr_hit[238]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs;
end
- addr_hit[238]: begin
+ addr_hit[239]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs;
end
- addr_hit[239]: begin
+ addr_hit[240]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs;
end
- addr_hit[240]: begin
+ addr_hit[241]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs;
end
- addr_hit[241]: begin
+ addr_hit[242]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs;
end
- addr_hit[242]: begin
+ addr_hit[243]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs;
end
- addr_hit[243]: begin
+ addr_hit[244]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs;
end
- addr_hit[244]: begin
+ addr_hit[245]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs;
end
- addr_hit[245]: begin
+ addr_hit[246]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs;
end
- addr_hit[246]: begin
+ addr_hit[247]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs;
end
- addr_hit[247]: begin
+ addr_hit[248]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs;
end
- addr_hit[248]: begin
+ addr_hit[249]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs;
end
- addr_hit[249]: begin
+ addr_hit[250]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs;
end
- addr_hit[250]: begin
+ addr_hit[251]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs;
end
- addr_hit[251]: begin
+ addr_hit[252]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs;
end
- addr_hit[252]: begin
+ addr_hit[253]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs;
end
- addr_hit[253]: begin
+ addr_hit[254]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs;
end
- addr_hit[254]: begin
+ addr_hit[255]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs;
end
- addr_hit[255]: begin
+ addr_hit[256]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs;
end
- addr_hit[256]: begin
+ addr_hit[257]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs;
end
- addr_hit[257]: begin
+ addr_hit[258]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs;
end
- addr_hit[258]: begin
+ addr_hit[259]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs;
end
- addr_hit[259]: begin
+ addr_hit[260]: begin
reg_rdata_next[0] = mio_pad_sleep_en_0_qs;
end
- addr_hit[260]: begin
+ addr_hit[261]: begin
reg_rdata_next[0] = mio_pad_sleep_en_1_qs;
end
- addr_hit[261]: begin
+ addr_hit[262]: begin
reg_rdata_next[0] = mio_pad_sleep_en_2_qs;
end
- addr_hit[262]: begin
+ addr_hit[263]: begin
reg_rdata_next[0] = mio_pad_sleep_en_3_qs;
end
- addr_hit[263]: begin
+ addr_hit[264]: begin
reg_rdata_next[0] = mio_pad_sleep_en_4_qs;
end
- addr_hit[264]: begin
+ addr_hit[265]: begin
reg_rdata_next[0] = mio_pad_sleep_en_5_qs;
end
- addr_hit[265]: begin
+ addr_hit[266]: begin
reg_rdata_next[0] = mio_pad_sleep_en_6_qs;
end
- addr_hit[266]: begin
+ addr_hit[267]: begin
reg_rdata_next[0] = mio_pad_sleep_en_7_qs;
end
- addr_hit[267]: begin
+ addr_hit[268]: begin
reg_rdata_next[0] = mio_pad_sleep_en_8_qs;
end
- addr_hit[268]: begin
+ addr_hit[269]: begin
reg_rdata_next[0] = mio_pad_sleep_en_9_qs;
end
- addr_hit[269]: begin
+ addr_hit[270]: begin
reg_rdata_next[0] = mio_pad_sleep_en_10_qs;
end
- addr_hit[270]: begin
+ addr_hit[271]: begin
reg_rdata_next[0] = mio_pad_sleep_en_11_qs;
end
- addr_hit[271]: begin
+ addr_hit[272]: begin
reg_rdata_next[0] = mio_pad_sleep_en_12_qs;
end
- addr_hit[272]: begin
+ addr_hit[273]: begin
reg_rdata_next[0] = mio_pad_sleep_en_13_qs;
end
- addr_hit[273]: begin
+ addr_hit[274]: begin
reg_rdata_next[0] = mio_pad_sleep_en_14_qs;
end
- addr_hit[274]: begin
+ addr_hit[275]: begin
reg_rdata_next[0] = mio_pad_sleep_en_15_qs;
end
- addr_hit[275]: begin
+ addr_hit[276]: begin
reg_rdata_next[0] = mio_pad_sleep_en_16_qs;
end
- addr_hit[276]: begin
+ addr_hit[277]: begin
reg_rdata_next[0] = mio_pad_sleep_en_17_qs;
end
- addr_hit[277]: begin
+ addr_hit[278]: begin
reg_rdata_next[0] = mio_pad_sleep_en_18_qs;
end
- addr_hit[278]: begin
+ addr_hit[279]: begin
reg_rdata_next[0] = mio_pad_sleep_en_19_qs;
end
- addr_hit[279]: begin
+ addr_hit[280]: begin
reg_rdata_next[0] = mio_pad_sleep_en_20_qs;
end
- addr_hit[280]: begin
+ addr_hit[281]: begin
reg_rdata_next[0] = mio_pad_sleep_en_21_qs;
end
- addr_hit[281]: begin
+ addr_hit[282]: begin
reg_rdata_next[0] = mio_pad_sleep_en_22_qs;
end
- addr_hit[282]: begin
+ addr_hit[283]: begin
reg_rdata_next[0] = mio_pad_sleep_en_23_qs;
end
- addr_hit[283]: begin
+ addr_hit[284]: begin
reg_rdata_next[0] = mio_pad_sleep_en_24_qs;
end
- addr_hit[284]: begin
+ addr_hit[285]: begin
reg_rdata_next[0] = mio_pad_sleep_en_25_qs;
end
- addr_hit[285]: begin
+ addr_hit[286]: begin
reg_rdata_next[0] = mio_pad_sleep_en_26_qs;
end
- addr_hit[286]: begin
+ addr_hit[287]: begin
reg_rdata_next[0] = mio_pad_sleep_en_27_qs;
end
- addr_hit[287]: begin
+ addr_hit[288]: begin
reg_rdata_next[0] = mio_pad_sleep_en_28_qs;
end
- addr_hit[288]: begin
+ addr_hit[289]: begin
reg_rdata_next[0] = mio_pad_sleep_en_29_qs;
end
- addr_hit[289]: begin
+ addr_hit[290]: begin
reg_rdata_next[0] = mio_pad_sleep_en_30_qs;
end
- addr_hit[290]: begin
+ addr_hit[291]: begin
reg_rdata_next[0] = mio_pad_sleep_en_31_qs;
end
- addr_hit[291]: begin
+ addr_hit[292]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs;
end
- addr_hit[292]: begin
+ addr_hit[293]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs;
end
- addr_hit[293]: begin
+ addr_hit[294]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs;
end
- addr_hit[294]: begin
+ addr_hit[295]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs;
end
- addr_hit[295]: begin
+ addr_hit[296]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs;
end
- addr_hit[296]: begin
+ addr_hit[297]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs;
end
- addr_hit[297]: begin
+ addr_hit[298]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs;
end
- addr_hit[298]: begin
+ addr_hit[299]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs;
end
- addr_hit[299]: begin
+ addr_hit[300]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs;
end
- addr_hit[300]: begin
+ addr_hit[301]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs;
end
- addr_hit[301]: begin
+ addr_hit[302]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs;
end
- addr_hit[302]: begin
+ addr_hit[303]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs;
end
- addr_hit[303]: begin
+ addr_hit[304]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs;
end
- addr_hit[304]: begin
+ addr_hit[305]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs;
end
- addr_hit[305]: begin
+ addr_hit[306]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs;
end
- addr_hit[306]: begin
+ addr_hit[307]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs;
end
- addr_hit[307]: begin
+ addr_hit[308]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs;
end
- addr_hit[308]: begin
+ addr_hit[309]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs;
end
- addr_hit[309]: begin
+ addr_hit[310]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs;
end
- addr_hit[310]: begin
+ addr_hit[311]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs;
end
- addr_hit[311]: begin
+ addr_hit[312]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs;
end
- addr_hit[312]: begin
+ addr_hit[313]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs;
end
- addr_hit[313]: begin
+ addr_hit[314]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs;
end
- addr_hit[314]: begin
+ addr_hit[315]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs;
end
- addr_hit[315]: begin
+ addr_hit[316]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs;
end
- addr_hit[316]: begin
+ addr_hit[317]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs;
end
- addr_hit[317]: begin
+ addr_hit[318]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs;
end
- addr_hit[318]: begin
+ addr_hit[319]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs;
end
- addr_hit[319]: begin
+ addr_hit[320]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs;
end
- addr_hit[320]: begin
+ addr_hit[321]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs;
end
- addr_hit[321]: begin
+ addr_hit[322]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs;
end
- addr_hit[322]: begin
+ addr_hit[323]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs;
end
- addr_hit[323]: begin
+ addr_hit[324]: begin
reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs;
reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs;
reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs;
@@ -17691,375 +17718,375 @@
reg_rdata_next[15] = dio_pad_sleep_status_en_15_qs;
end
- addr_hit[324]: begin
+ addr_hit[325]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs;
end
- addr_hit[325]: begin
+ addr_hit[326]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs;
end
- addr_hit[326]: begin
+ addr_hit[327]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs;
end
- addr_hit[327]: begin
+ addr_hit[328]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs;
end
- addr_hit[328]: begin
+ addr_hit[329]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs;
end
- addr_hit[329]: begin
+ addr_hit[330]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs;
end
- addr_hit[330]: begin
+ addr_hit[331]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs;
end
- addr_hit[331]: begin
+ addr_hit[332]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs;
end
- addr_hit[332]: begin
+ addr_hit[333]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs;
end
- addr_hit[333]: begin
+ addr_hit[334]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs;
end
- addr_hit[334]: begin
+ addr_hit[335]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs;
end
- addr_hit[335]: begin
+ addr_hit[336]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs;
end
- addr_hit[336]: begin
+ addr_hit[337]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs;
end
- addr_hit[337]: begin
+ addr_hit[338]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs;
end
- addr_hit[338]: begin
+ addr_hit[339]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs;
end
- addr_hit[339]: begin
+ addr_hit[340]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs;
end
- addr_hit[340]: begin
+ addr_hit[341]: begin
reg_rdata_next[0] = dio_pad_sleep_en_0_qs;
end
- addr_hit[341]: begin
+ addr_hit[342]: begin
reg_rdata_next[0] = dio_pad_sleep_en_1_qs;
end
- addr_hit[342]: begin
+ addr_hit[343]: begin
reg_rdata_next[0] = dio_pad_sleep_en_2_qs;
end
- addr_hit[343]: begin
+ addr_hit[344]: begin
reg_rdata_next[0] = dio_pad_sleep_en_3_qs;
end
- addr_hit[344]: begin
+ addr_hit[345]: begin
reg_rdata_next[0] = dio_pad_sleep_en_4_qs;
end
- addr_hit[345]: begin
+ addr_hit[346]: begin
reg_rdata_next[0] = dio_pad_sleep_en_5_qs;
end
- addr_hit[346]: begin
+ addr_hit[347]: begin
reg_rdata_next[0] = dio_pad_sleep_en_6_qs;
end
- addr_hit[347]: begin
+ addr_hit[348]: begin
reg_rdata_next[0] = dio_pad_sleep_en_7_qs;
end
- addr_hit[348]: begin
+ addr_hit[349]: begin
reg_rdata_next[0] = dio_pad_sleep_en_8_qs;
end
- addr_hit[349]: begin
+ addr_hit[350]: begin
reg_rdata_next[0] = dio_pad_sleep_en_9_qs;
end
- addr_hit[350]: begin
+ addr_hit[351]: begin
reg_rdata_next[0] = dio_pad_sleep_en_10_qs;
end
- addr_hit[351]: begin
+ addr_hit[352]: begin
reg_rdata_next[0] = dio_pad_sleep_en_11_qs;
end
- addr_hit[352]: begin
+ addr_hit[353]: begin
reg_rdata_next[0] = dio_pad_sleep_en_12_qs;
end
- addr_hit[353]: begin
+ addr_hit[354]: begin
reg_rdata_next[0] = dio_pad_sleep_en_13_qs;
end
- addr_hit[354]: begin
+ addr_hit[355]: begin
reg_rdata_next[0] = dio_pad_sleep_en_14_qs;
end
- addr_hit[355]: begin
+ addr_hit[356]: begin
reg_rdata_next[0] = dio_pad_sleep_en_15_qs;
end
- addr_hit[356]: begin
+ addr_hit[357]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs;
end
- addr_hit[357]: begin
+ addr_hit[358]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs;
end
- addr_hit[358]: begin
+ addr_hit[359]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs;
end
- addr_hit[359]: begin
+ addr_hit[360]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs;
end
- addr_hit[360]: begin
+ addr_hit[361]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs;
end
- addr_hit[361]: begin
+ addr_hit[362]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs;
end
- addr_hit[362]: begin
+ addr_hit[363]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs;
end
- addr_hit[363]: begin
+ addr_hit[364]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs;
end
- addr_hit[364]: begin
+ addr_hit[365]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs;
end
- addr_hit[365]: begin
+ addr_hit[366]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs;
end
- addr_hit[366]: begin
+ addr_hit[367]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs;
end
- addr_hit[367]: begin
+ addr_hit[368]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs;
end
- addr_hit[368]: begin
+ addr_hit[369]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs;
end
- addr_hit[369]: begin
+ addr_hit[370]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs;
end
- addr_hit[370]: begin
+ addr_hit[371]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs;
end
- addr_hit[371]: begin
+ addr_hit[372]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs;
end
- addr_hit[372]: begin
+ addr_hit[373]: begin
reg_rdata_next[0] = wkup_detector_regwen_0_qs;
end
- addr_hit[373]: begin
+ addr_hit[374]: begin
reg_rdata_next[0] = wkup_detector_regwen_1_qs;
end
- addr_hit[374]: begin
+ addr_hit[375]: begin
reg_rdata_next[0] = wkup_detector_regwen_2_qs;
end
- addr_hit[375]: begin
+ addr_hit[376]: begin
reg_rdata_next[0] = wkup_detector_regwen_3_qs;
end
- addr_hit[376]: begin
+ addr_hit[377]: begin
reg_rdata_next[0] = wkup_detector_regwen_4_qs;
end
- addr_hit[377]: begin
+ addr_hit[378]: begin
reg_rdata_next[0] = wkup_detector_regwen_5_qs;
end
- addr_hit[378]: begin
+ addr_hit[379]: begin
reg_rdata_next[0] = wkup_detector_regwen_6_qs;
end
- addr_hit[379]: begin
+ addr_hit[380]: begin
reg_rdata_next[0] = wkup_detector_regwen_7_qs;
end
- addr_hit[380]: begin
+ addr_hit[381]: begin
reg_rdata_next[0] = wkup_detector_en_0_qs;
end
- addr_hit[381]: begin
+ addr_hit[382]: begin
reg_rdata_next[0] = wkup_detector_en_1_qs;
end
- addr_hit[382]: begin
+ addr_hit[383]: begin
reg_rdata_next[0] = wkup_detector_en_2_qs;
end
- addr_hit[383]: begin
+ addr_hit[384]: begin
reg_rdata_next[0] = wkup_detector_en_3_qs;
end
- addr_hit[384]: begin
+ addr_hit[385]: begin
reg_rdata_next[0] = wkup_detector_en_4_qs;
end
- addr_hit[385]: begin
+ addr_hit[386]: begin
reg_rdata_next[0] = wkup_detector_en_5_qs;
end
- addr_hit[386]: begin
+ addr_hit[387]: begin
reg_rdata_next[0] = wkup_detector_en_6_qs;
end
- addr_hit[387]: begin
+ addr_hit[388]: begin
reg_rdata_next[0] = wkup_detector_en_7_qs;
end
- addr_hit[388]: begin
+ addr_hit[389]: begin
reg_rdata_next[2:0] = wkup_detector_0_mode_0_qs;
reg_rdata_next[3] = wkup_detector_0_filter_0_qs;
reg_rdata_next[4] = wkup_detector_0_miodio_0_qs;
end
- addr_hit[389]: begin
+ addr_hit[390]: begin
reg_rdata_next[2:0] = wkup_detector_1_mode_1_qs;
reg_rdata_next[3] = wkup_detector_1_filter_1_qs;
reg_rdata_next[4] = wkup_detector_1_miodio_1_qs;
end
- addr_hit[390]: begin
+ addr_hit[391]: begin
reg_rdata_next[2:0] = wkup_detector_2_mode_2_qs;
reg_rdata_next[3] = wkup_detector_2_filter_2_qs;
reg_rdata_next[4] = wkup_detector_2_miodio_2_qs;
end
- addr_hit[391]: begin
+ addr_hit[392]: begin
reg_rdata_next[2:0] = wkup_detector_3_mode_3_qs;
reg_rdata_next[3] = wkup_detector_3_filter_3_qs;
reg_rdata_next[4] = wkup_detector_3_miodio_3_qs;
end
- addr_hit[392]: begin
+ addr_hit[393]: begin
reg_rdata_next[2:0] = wkup_detector_4_mode_4_qs;
reg_rdata_next[3] = wkup_detector_4_filter_4_qs;
reg_rdata_next[4] = wkup_detector_4_miodio_4_qs;
end
- addr_hit[393]: begin
+ addr_hit[394]: begin
reg_rdata_next[2:0] = wkup_detector_5_mode_5_qs;
reg_rdata_next[3] = wkup_detector_5_filter_5_qs;
reg_rdata_next[4] = wkup_detector_5_miodio_5_qs;
end
- addr_hit[394]: begin
+ addr_hit[395]: begin
reg_rdata_next[2:0] = wkup_detector_6_mode_6_qs;
reg_rdata_next[3] = wkup_detector_6_filter_6_qs;
reg_rdata_next[4] = wkup_detector_6_miodio_6_qs;
end
- addr_hit[395]: begin
+ addr_hit[396]: begin
reg_rdata_next[2:0] = wkup_detector_7_mode_7_qs;
reg_rdata_next[3] = wkup_detector_7_filter_7_qs;
reg_rdata_next[4] = wkup_detector_7_miodio_7_qs;
end
- addr_hit[396]: begin
+ addr_hit[397]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_0_qs;
end
- addr_hit[397]: begin
+ addr_hit[398]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_1_qs;
end
- addr_hit[398]: begin
+ addr_hit[399]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_2_qs;
end
- addr_hit[399]: begin
+ addr_hit[400]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_3_qs;
end
- addr_hit[400]: begin
+ addr_hit[401]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_4_qs;
end
- addr_hit[401]: begin
+ addr_hit[402]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_5_qs;
end
- addr_hit[402]: begin
+ addr_hit[403]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_6_qs;
end
- addr_hit[403]: begin
+ addr_hit[404]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_7_qs;
end
- addr_hit[404]: begin
+ addr_hit[405]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_0_qs;
end
- addr_hit[405]: begin
+ addr_hit[406]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_1_qs;
end
- addr_hit[406]: begin
+ addr_hit[407]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_2_qs;
end
- addr_hit[407]: begin
+ addr_hit[408]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_3_qs;
end
- addr_hit[408]: begin
+ addr_hit[409]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_4_qs;
end
- addr_hit[409]: begin
+ addr_hit[410]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_5_qs;
end
- addr_hit[410]: begin
+ addr_hit[411]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_6_qs;
end
- addr_hit[411]: begin
+ addr_hit[412]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_7_qs;
end
- addr_hit[412]: begin
+ addr_hit[413]: begin
reg_rdata_next[0] = wkup_cause_cause_0_qs;
reg_rdata_next[1] = wkup_cause_cause_1_qs;
reg_rdata_next[2] = wkup_cause_cause_2_qs;
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index d7a1a96..eae0098 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -11529,6 +11529,7 @@
pattgen
otp_ctrl
lc_ctrl
+ pinmux_aon
sensor_ctrl_aon
sram_ctrl_ret_aon
flash_ctrl
@@ -11617,6 +11618,13 @@
module_name: lc_ctrl
}
{
+ name: pinmux_aon_fatal_fault
+ width: 1
+ type: alert
+ async: "0"
+ module_name: pinmux_aon
+ }
+ {
name: sensor_ctrl_aon_recov_as
width: 1
type: alert
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 6b70923b..703c122 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -14,36 +14,37 @@
assign alert_if[7].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
assign alert_if[8].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
assign alert_if[9].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
-assign alert_if[10].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
-assign alert_if[11].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
-assign alert_if[12].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
-assign alert_if[13].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
-assign alert_if[14].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
-assign alert_if[15].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
-assign alert_if[16].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
-assign alert_if[17].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
-assign alert_if[18].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
-assign alert_if[20].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
-assign alert_if[21].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
-assign alert_if[22].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
-assign alert_if[23].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
-assign alert_if[24].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
-assign alert_if[25].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
-assign alert_if[26].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
-assign alert_if[27].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[28].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[29].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
-assign alert_if[30].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
-assign alert_if[31].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[32].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[33].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[34].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[35].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[36].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[37].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[38].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[39].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
-assign alert_if[40].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[41].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[42].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[10].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0];
+assign alert_if[11].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
+assign alert_if[12].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
+assign alert_if[13].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
+assign alert_if[14].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
+assign alert_if[15].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
+assign alert_if[16].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
+assign alert_if[17].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
+assign alert_if[20].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
+assign alert_if[21].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
+assign alert_if[22].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
+assign alert_if[23].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
+assign alert_if[24].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
+assign alert_if[25].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
+assign alert_if[26].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[27].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
+assign alert_if[28].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[29].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[30].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
+assign alert_if[31].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
+assign alert_if[32].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[33].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[34].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[35].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[36].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[37].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[38].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[39].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[40].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
+assign alert_if[41].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[42].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[43].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index d2f1c62..672e067 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -15,6 +15,7 @@
"lc_ctrl_fatal_prog_error",
"lc_ctrl_fatal_state_error",
"lc_ctrl_fatal_bus_integ_error",
+ "pinmux_aon_fatal_fault",
"sensor_ctrl_aon_recov_as",
"sensor_ctrl_aon_recov_cg",
"sensor_ctrl_aon_recov_gd",
@@ -50,4 +51,4 @@
"rom_ctrl_fatal"
};
-parameter uint NUM_ALERTS = 43;
+parameter uint NUM_ALERTS = 44;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index 754e2a5..3376679 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -48,7 +48,7 @@
{ name: "NAlerts",
desc: "Number of peripheral inputs",
type: "int",
- default: "43",
+ default: "44",
local: "true"
},
{ name: "EscCntDw",
@@ -66,7 +66,7 @@
{ name: "AsyncOn",
desc: "Number of peripheral outputs",
type: "logic [NAlerts-1:0]",
- default: "43'b1111111111111111111100000000000000000000000",
+ default: "44'b11111111111111111111000000000000000000000000",
local: "true"
},
{ name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index f67c403..6151e52 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@
package alert_handler_reg_pkg;
// Param list
- parameter int NAlerts = 43;
+ parameter int NAlerts = 44;
parameter int EscCntDw = 32;
parameter int AccuCntDw = 16;
- parameter logic [NAlerts-1:0] AsyncOn = 43'b1111111111111111111100000000000000000000000;
+ parameter logic [NAlerts-1:0] AsyncOn = 44'b11111111111111111111000000000000000000000000;
parameter int N_CLASSES = 4;
parameter int N_ESC_SEV = 4;
parameter int N_PHASES = 4;
@@ -458,15 +458,15 @@
// Register -> HW type
typedef struct packed {
- alert_handler_reg2hw_intr_state_reg_t intr_state; // [1043:1040]
- alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1039:1036]
- alert_handler_reg2hw_intr_test_reg_t intr_test; // [1035:1028]
- alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1027:1004]
- alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1003:1003]
- alert_handler_reg2hw_alert_regwen_mreg_t [42:0] alert_regwen; // [1002:960]
- alert_handler_reg2hw_alert_en_mreg_t [42:0] alert_en; // [959:917]
- alert_handler_reg2hw_alert_class_mreg_t [42:0] alert_class; // [916:831]
- alert_handler_reg2hw_alert_cause_mreg_t [42:0] alert_cause; // [830:788]
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [1048:1045]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1044:1041]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [1040:1033]
+ alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1032:1009]
+ alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1008:1008]
+ alert_handler_reg2hw_alert_regwen_mreg_t [43:0] alert_regwen; // [1007:964]
+ alert_handler_reg2hw_alert_en_mreg_t [43:0] alert_en; // [963:920]
+ alert_handler_reg2hw_alert_class_mreg_t [43:0] alert_class; // [919:832]
+ alert_handler_reg2hw_alert_cause_mreg_t [43:0] alert_cause; // [831:788]
alert_handler_reg2hw_loc_alert_en_mreg_t [4:0] loc_alert_en; // [787:783]
alert_handler_reg2hw_loc_alert_class_mreg_t [4:0] loc_alert_class; // [782:773]
alert_handler_reg2hw_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [772:768]
@@ -506,8 +506,8 @@
// HW -> register type
typedef struct packed {
- alert_handler_hw2reg_intr_state_reg_t intr_state; // [315:308]
- alert_handler_hw2reg_alert_cause_mreg_t [42:0] alert_cause; // [307:222]
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [317:310]
+ alert_handler_hw2reg_alert_cause_mreg_t [43:0] alert_cause; // [309:222]
alert_handler_hw2reg_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [221:212]
alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -577,207 +577,211 @@
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_40_OFFSET = 10'h b8;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_41_OFFSET = 10'h bc;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_42_OFFSET = 10'h c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 10'h c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 10'h c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 10'h cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 10'h d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 10'h d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 10'h d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 10'h dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 10'h e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 10'h e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 10'h e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 10'h ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 10'h f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 10'h f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 10'h f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 10'h fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 10'h 100;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 10'h 104;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 10'h 108;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 10'h 10c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 10'h 110;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 10'h 114;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 10'h 118;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 10'h 11c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 10'h 120;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 10'h 124;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 10'h 128;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 10'h 12c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 10'h 130;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 10'h 134;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 10'h 138;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 10'h 13c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 10'h 140;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 10'h 144;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 10'h 148;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 10'h 14c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 10'h 150;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 10'h 154;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 10'h 158;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 10'h 15c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 10'h 160;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 10'h 164;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 10'h 168;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 10'h 16c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 10'h 170;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 10'h 174;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 10'h 178;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 10'h 17c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 10'h 180;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 10'h 184;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 10'h 188;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 10'h 18c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 10'h 190;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 10'h 194;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 10'h 198;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 10'h 19c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 10'h 1a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 10'h 1a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 10'h 1a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 10'h 1ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 10'h 1b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 10'h 1b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 10'h 1b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 10'h 1bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 10'h 1c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 10'h 1c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 10'h 1c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 10'h 1cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 10'h 1d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 10'h 1d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 10'h 1d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 10'h 1dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 10'h 1e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 10'h 1e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 10'h 1e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 10'h 1ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 10'h 1f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 10'h 1f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 10'h 1f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 10'h 1fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 10'h 200;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 10'h 204;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 10'h 208;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 10'h 20c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 10'h 210;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 10'h 214;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 10'h 218;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 10'h 21c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 10'h 220;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 10'h 224;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 10'h 228;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 10'h 22c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 10'h 230;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 10'h 234;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 10'h 238;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 10'h 23c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 10'h 240;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 10'h 244;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 10'h 248;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 10'h 24c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 10'h 250;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 10'h 254;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 10'h 258;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 10'h 25c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 10'h 260;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 10'h 264;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 10'h 268;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 10'h 26c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 10'h 270;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 10'h 274;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 10'h 278;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 10'h 27c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 10'h 280;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 10'h 284;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 10'h 288;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 10'h 28c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 10'h 290;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 10'h 294;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 10'h 298;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 10'h 29c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 10'h 2a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 10'h 2a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 10'h 2a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 10'h 2ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 10'h 2b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 10'h 2b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 10'h 2b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 10'h 2bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 10'h 2c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 10'h 2c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 10'h 2c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 10'h 2cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 10'h 2d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 10'h 2d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 10'h 2d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 10'h 2dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 10'h 2e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 10'h 2e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 10'h 2e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 10'h 2ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 10'h 2f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 10'h 2f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 10'h 2f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 10'h 2fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 10'h 300;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 10'h 304;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 10'h 308;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 10'h 30c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 10'h 310;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 10'h 314;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 10'h 318;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 10'h 31c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 10'h 320;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 10'h 324;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 10'h 328;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 10'h 32c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 10'h 330;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 10'h 334;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 10'h 338;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 10'h 33c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 10'h 340;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 10'h 344;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 10'h 348;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 10'h 34c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 10'h 350;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 10'h 354;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 10'h 358;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 10'h 35c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 10'h 360;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 10'h 364;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 10'h 368;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 10'h 36c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 10'h 370;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 10'h 374;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 10'h 378;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 10'h 37c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 10'h 380;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 10'h 384;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 10'h 388;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 10'h 38c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 10'h 390;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 10'h 394;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 10'h 398;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 10'h 39c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 10'h 3a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 10'h 3a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 10'h 3a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 10'h 3ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 10'h 3b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 10'h 3b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 10'h 3b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 10'h 3bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 10'h 3c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 10'h 3c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 10'h 3c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 10'h 3cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 10'h 3d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 10'h 3d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 10'h 3d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 10'h 3dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 10'h 3e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 10'h 3e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_43_OFFSET = 10'h c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 10'h c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 10'h cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 10'h d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 10'h d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 10'h d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 10'h dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 10'h e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 10'h e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 10'h e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 10'h ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 10'h f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 10'h f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 10'h f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 10'h fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 10'h 100;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 10'h 104;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 10'h 108;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 10'h 10c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 10'h 110;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 10'h 114;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 10'h 118;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 10'h 11c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 10'h 120;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 10'h 124;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 10'h 128;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 10'h 12c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 10'h 130;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 10'h 134;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 10'h 138;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 10'h 13c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 10'h 140;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 10'h 144;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 10'h 148;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 10'h 14c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 10'h 150;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 10'h 154;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 10'h 158;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 10'h 15c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 10'h 160;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 10'h 164;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 10'h 168;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 10'h 16c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 10'h 170;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_43_OFFSET = 10'h 174;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 10'h 178;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 10'h 17c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 10'h 180;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 10'h 184;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 10'h 188;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 10'h 18c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 10'h 190;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 10'h 194;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 10'h 198;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 10'h 19c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 10'h 1a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 10'h 1a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 10'h 1a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 10'h 1ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 10'h 1b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 10'h 1b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 10'h 1b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 10'h 1bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 10'h 1c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 10'h 1c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 10'h 1c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 10'h 1cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 10'h 1d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 10'h 1d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 10'h 1d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 10'h 1dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 10'h 1e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 10'h 1e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 10'h 1e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 10'h 1ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 10'h 1f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 10'h 1f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 10'h 1f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 10'h 1fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 10'h 200;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 10'h 204;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 10'h 208;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 10'h 20c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 10'h 210;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 10'h 214;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 10'h 218;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 10'h 21c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 10'h 220;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_43_OFFSET = 10'h 224;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 10'h 228;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 10'h 22c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 10'h 230;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 10'h 234;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 10'h 238;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 10'h 23c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 10'h 240;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 10'h 244;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 10'h 248;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 10'h 24c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 10'h 250;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 10'h 254;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 10'h 258;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 10'h 25c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 10'h 260;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 10'h 264;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 10'h 268;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 10'h 26c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 10'h 270;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 10'h 274;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 10'h 278;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 10'h 27c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 10'h 280;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 10'h 284;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 10'h 288;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 10'h 28c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 10'h 290;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 10'h 294;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 10'h 298;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 10'h 29c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 10'h 2a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 10'h 2a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 10'h 2a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 10'h 2ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 10'h 2b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 10'h 2b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 10'h 2b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 10'h 2bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 10'h 2c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 10'h 2c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 10'h 2c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 10'h 2cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 10'h 2d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 10'h 2d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 10'h 2d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 10'h 2dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 10'h 2e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 10'h 2e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 10'h 2e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 10'h 2ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 10'h 2f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 10'h 2f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 10'h 2f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 10'h 2fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 10'h 300;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 10'h 304;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 10'h 308;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 10'h 30c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 10'h 310;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 10'h 314;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 10'h 318;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 10'h 31c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 10'h 320;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 10'h 324;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 10'h 328;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 10'h 32c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 10'h 330;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 10'h 334;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 10'h 338;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 10'h 33c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 10'h 340;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 10'h 344;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 10'h 348;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 10'h 34c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 10'h 350;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 10'h 354;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 10'h 358;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 10'h 35c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 10'h 360;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 10'h 364;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 10'h 368;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 10'h 36c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 10'h 370;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 10'h 374;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 10'h 378;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 10'h 37c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 10'h 380;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 10'h 384;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 10'h 388;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 10'h 38c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 10'h 390;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 10'h 394;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 10'h 398;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 10'h 39c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 10'h 3a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 10'h 3a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 10'h 3a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 10'h 3ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 10'h 3b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 10'h 3b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 10'h 3b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 10'h 3bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 10'h 3c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 10'h 3c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 10'h 3c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 10'h 3cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 10'h 3d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 10'h 3d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 10'h 3d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 10'h 3dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 10'h 3e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 10'h 3e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 10'h 3e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 10'h 3ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 10'h 3f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 10'h 3f4;
// Reset values for hwext registers and their fields
parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
@@ -849,6 +853,7 @@
ALERT_HANDLER_ALERT_REGWEN_40,
ALERT_HANDLER_ALERT_REGWEN_41,
ALERT_HANDLER_ALERT_REGWEN_42,
+ ALERT_HANDLER_ALERT_REGWEN_43,
ALERT_HANDLER_ALERT_EN_0,
ALERT_HANDLER_ALERT_EN_1,
ALERT_HANDLER_ALERT_EN_2,
@@ -892,6 +897,7 @@
ALERT_HANDLER_ALERT_EN_40,
ALERT_HANDLER_ALERT_EN_41,
ALERT_HANDLER_ALERT_EN_42,
+ ALERT_HANDLER_ALERT_EN_43,
ALERT_HANDLER_ALERT_CLASS_0,
ALERT_HANDLER_ALERT_CLASS_1,
ALERT_HANDLER_ALERT_CLASS_2,
@@ -935,6 +941,7 @@
ALERT_HANDLER_ALERT_CLASS_40,
ALERT_HANDLER_ALERT_CLASS_41,
ALERT_HANDLER_ALERT_CLASS_42,
+ ALERT_HANDLER_ALERT_CLASS_43,
ALERT_HANDLER_ALERT_CAUSE_0,
ALERT_HANDLER_ALERT_CAUSE_1,
ALERT_HANDLER_ALERT_CAUSE_2,
@@ -978,6 +985,7 @@
ALERT_HANDLER_ALERT_CAUSE_40,
ALERT_HANDLER_ALERT_CAUSE_41,
ALERT_HANDLER_ALERT_CAUSE_42,
+ ALERT_HANDLER_ALERT_CAUSE_43,
ALERT_HANDLER_LOC_ALERT_REGWEN_0,
ALERT_HANDLER_LOC_ALERT_REGWEN_1,
ALERT_HANDLER_LOC_ALERT_REGWEN_2,
@@ -1053,7 +1061,7 @@
} alert_handler_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ALERT_HANDLER_PERMIT [250] = '{
+ parameter logic [3:0] ALERT_HANDLER_PERMIT [254] = '{
4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE
4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE
4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
@@ -1103,207 +1111,211 @@
4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_REGWEN_40
4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_REGWEN_41
4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_REGWEN_42
- 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_EN_0
- 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_EN_1
- 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_EN_2
- 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_EN_3
- 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_EN_4
- 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_5
- 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_6
- 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_7
- 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_8
- 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_9
- 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_10
- 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_11
- 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_12
- 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_13
- 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_14
- 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_15
- 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_16
- 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_17
- 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_18
- 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_19
- 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_20
- 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_21
- 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_22
- 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_23
- 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_24
- 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_25
- 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_26
- 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_27
- 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_28
- 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_29
- 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_30
- 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_31
- 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_32
- 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_33
- 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_34
- 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_35
- 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_36
- 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_37
- 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_38
- 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_39
- 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_40
- 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_41
- 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_42
- 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_CLASS_0
- 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_CLASS_1
- 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_CLASS_2
- 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_CLASS_3
- 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_CLASS_4
- 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_CLASS_5
- 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_CLASS_6
- 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_CLASS_7
- 4'b 0001, // index[100] ALERT_HANDLER_ALERT_CLASS_8
- 4'b 0001, // index[101] ALERT_HANDLER_ALERT_CLASS_9
- 4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_10
- 4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_11
- 4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_12
- 4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_13
- 4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_14
- 4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_15
- 4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_16
- 4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_17
- 4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_18
- 4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_19
- 4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_20
- 4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_21
- 4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_22
- 4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_23
- 4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_24
- 4'b 0001, // index[117] ALERT_HANDLER_ALERT_CLASS_25
- 4'b 0001, // index[118] ALERT_HANDLER_ALERT_CLASS_26
- 4'b 0001, // index[119] ALERT_HANDLER_ALERT_CLASS_27
- 4'b 0001, // index[120] ALERT_HANDLER_ALERT_CLASS_28
- 4'b 0001, // index[121] ALERT_HANDLER_ALERT_CLASS_29
- 4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_30
- 4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_31
- 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_32
- 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_33
- 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_34
- 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_35
- 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_36
- 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_37
- 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_38
- 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_39
- 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_40
- 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_41
- 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_42
- 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CAUSE_0
- 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CAUSE_1
- 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CAUSE_2
- 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CAUSE_3
- 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CAUSE_4
- 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CAUSE_5
- 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CAUSE_6
- 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CAUSE_7
- 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CAUSE_8
- 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CAUSE_9
- 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CAUSE_10
- 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CAUSE_11
- 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CAUSE_12
- 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CAUSE_13
- 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CAUSE_14
- 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CAUSE_15
- 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CAUSE_16
- 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CAUSE_17
- 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CAUSE_18
- 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CAUSE_19
- 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CAUSE_20
- 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CAUSE_21
- 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CAUSE_22
- 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CAUSE_23
- 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CAUSE_24
- 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CAUSE_25
- 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CAUSE_26
- 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CAUSE_27
- 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CAUSE_28
- 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CAUSE_29
- 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CAUSE_30
- 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CAUSE_31
- 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CAUSE_32
- 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CAUSE_33
- 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CAUSE_34
- 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CAUSE_35
- 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CAUSE_36
- 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CAUSE_37
- 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CAUSE_38
- 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CAUSE_39
- 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CAUSE_40
- 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CAUSE_41
- 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CAUSE_42
- 4'b 0001, // index[178] ALERT_HANDLER_LOC_ALERT_REGWEN_0
- 4'b 0001, // index[179] ALERT_HANDLER_LOC_ALERT_REGWEN_1
- 4'b 0001, // index[180] ALERT_HANDLER_LOC_ALERT_REGWEN_2
- 4'b 0001, // index[181] ALERT_HANDLER_LOC_ALERT_REGWEN_3
- 4'b 0001, // index[182] ALERT_HANDLER_LOC_ALERT_REGWEN_4
- 4'b 0001, // index[183] ALERT_HANDLER_LOC_ALERT_EN_0
- 4'b 0001, // index[184] ALERT_HANDLER_LOC_ALERT_EN_1
- 4'b 0001, // index[185] ALERT_HANDLER_LOC_ALERT_EN_2
- 4'b 0001, // index[186] ALERT_HANDLER_LOC_ALERT_EN_3
- 4'b 0001, // index[187] ALERT_HANDLER_LOC_ALERT_EN_4
- 4'b 0001, // index[188] ALERT_HANDLER_LOC_ALERT_CLASS_0
- 4'b 0001, // index[189] ALERT_HANDLER_LOC_ALERT_CLASS_1
- 4'b 0001, // index[190] ALERT_HANDLER_LOC_ALERT_CLASS_2
- 4'b 0001, // index[191] ALERT_HANDLER_LOC_ALERT_CLASS_3
- 4'b 0001, // index[192] ALERT_HANDLER_LOC_ALERT_CLASS_4
- 4'b 0001, // index[193] ALERT_HANDLER_LOC_ALERT_CAUSE_0
- 4'b 0001, // index[194] ALERT_HANDLER_LOC_ALERT_CAUSE_1
- 4'b 0001, // index[195] ALERT_HANDLER_LOC_ALERT_CAUSE_2
- 4'b 0001, // index[196] ALERT_HANDLER_LOC_ALERT_CAUSE_3
- 4'b 0001, // index[197] ALERT_HANDLER_LOC_ALERT_CAUSE_4
- 4'b 0001, // index[198] ALERT_HANDLER_CLASSA_REGWEN
- 4'b 0011, // index[199] ALERT_HANDLER_CLASSA_CTRL
- 4'b 0001, // index[200] ALERT_HANDLER_CLASSA_CLR_REGWEN
- 4'b 0001, // index[201] ALERT_HANDLER_CLASSA_CLR
- 4'b 0011, // index[202] ALERT_HANDLER_CLASSA_ACCUM_CNT
- 4'b 0011, // index[203] ALERT_HANDLER_CLASSA_ACCUM_THRESH
- 4'b 1111, // index[204] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
- 4'b 1111, // index[205] ALERT_HANDLER_CLASSA_PHASE0_CYC
- 4'b 1111, // index[206] ALERT_HANDLER_CLASSA_PHASE1_CYC
- 4'b 1111, // index[207] ALERT_HANDLER_CLASSA_PHASE2_CYC
- 4'b 1111, // index[208] ALERT_HANDLER_CLASSA_PHASE3_CYC
- 4'b 1111, // index[209] ALERT_HANDLER_CLASSA_ESC_CNT
- 4'b 0001, // index[210] ALERT_HANDLER_CLASSA_STATE
- 4'b 0001, // index[211] ALERT_HANDLER_CLASSB_REGWEN
- 4'b 0011, // index[212] ALERT_HANDLER_CLASSB_CTRL
- 4'b 0001, // index[213] ALERT_HANDLER_CLASSB_CLR_REGWEN
- 4'b 0001, // index[214] ALERT_HANDLER_CLASSB_CLR
- 4'b 0011, // index[215] ALERT_HANDLER_CLASSB_ACCUM_CNT
- 4'b 0011, // index[216] ALERT_HANDLER_CLASSB_ACCUM_THRESH
- 4'b 1111, // index[217] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
- 4'b 1111, // index[218] ALERT_HANDLER_CLASSB_PHASE0_CYC
- 4'b 1111, // index[219] ALERT_HANDLER_CLASSB_PHASE1_CYC
- 4'b 1111, // index[220] ALERT_HANDLER_CLASSB_PHASE2_CYC
- 4'b 1111, // index[221] ALERT_HANDLER_CLASSB_PHASE3_CYC
- 4'b 1111, // index[222] ALERT_HANDLER_CLASSB_ESC_CNT
- 4'b 0001, // index[223] ALERT_HANDLER_CLASSB_STATE
- 4'b 0001, // index[224] ALERT_HANDLER_CLASSC_REGWEN
- 4'b 0011, // index[225] ALERT_HANDLER_CLASSC_CTRL
- 4'b 0001, // index[226] ALERT_HANDLER_CLASSC_CLR_REGWEN
- 4'b 0001, // index[227] ALERT_HANDLER_CLASSC_CLR
- 4'b 0011, // index[228] ALERT_HANDLER_CLASSC_ACCUM_CNT
- 4'b 0011, // index[229] ALERT_HANDLER_CLASSC_ACCUM_THRESH
- 4'b 1111, // index[230] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
- 4'b 1111, // index[231] ALERT_HANDLER_CLASSC_PHASE0_CYC
- 4'b 1111, // index[232] ALERT_HANDLER_CLASSC_PHASE1_CYC
- 4'b 1111, // index[233] ALERT_HANDLER_CLASSC_PHASE2_CYC
- 4'b 1111, // index[234] ALERT_HANDLER_CLASSC_PHASE3_CYC
- 4'b 1111, // index[235] ALERT_HANDLER_CLASSC_ESC_CNT
- 4'b 0001, // index[236] ALERT_HANDLER_CLASSC_STATE
- 4'b 0001, // index[237] ALERT_HANDLER_CLASSD_REGWEN
- 4'b 0011, // index[238] ALERT_HANDLER_CLASSD_CTRL
- 4'b 0001, // index[239] ALERT_HANDLER_CLASSD_CLR_REGWEN
- 4'b 0001, // index[240] ALERT_HANDLER_CLASSD_CLR
- 4'b 0011, // index[241] ALERT_HANDLER_CLASSD_ACCUM_CNT
- 4'b 0011, // index[242] ALERT_HANDLER_CLASSD_ACCUM_THRESH
- 4'b 1111, // index[243] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
- 4'b 1111, // index[244] ALERT_HANDLER_CLASSD_PHASE0_CYC
- 4'b 1111, // index[245] ALERT_HANDLER_CLASSD_PHASE1_CYC
- 4'b 1111, // index[246] ALERT_HANDLER_CLASSD_PHASE2_CYC
- 4'b 1111, // index[247] ALERT_HANDLER_CLASSD_PHASE3_CYC
- 4'b 1111, // index[248] ALERT_HANDLER_CLASSD_ESC_CNT
- 4'b 0001 // index[249] ALERT_HANDLER_CLASSD_STATE
+ 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_REGWEN_43
+ 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_EN_0
+ 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_EN_1
+ 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_EN_2
+ 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_EN_3
+ 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_4
+ 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_5
+ 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_6
+ 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_7
+ 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_8
+ 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_9
+ 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_10
+ 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_11
+ 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_12
+ 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_13
+ 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_14
+ 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_15
+ 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_16
+ 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_17
+ 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_18
+ 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_19
+ 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_20
+ 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_21
+ 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_22
+ 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_23
+ 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_24
+ 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_25
+ 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_26
+ 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_27
+ 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_28
+ 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_29
+ 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_30
+ 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_31
+ 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_32
+ 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_33
+ 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_34
+ 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_35
+ 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_36
+ 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_37
+ 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_38
+ 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_39
+ 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_40
+ 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_41
+ 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_42
+ 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_43
+ 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_CLASS_0
+ 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_CLASS_1
+ 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_CLASS_2
+ 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_CLASS_3
+ 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_CLASS_4
+ 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_CLASS_5
+ 4'b 0001, // index[100] ALERT_HANDLER_ALERT_CLASS_6
+ 4'b 0001, // index[101] ALERT_HANDLER_ALERT_CLASS_7
+ 4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_8
+ 4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_9
+ 4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_10
+ 4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_11
+ 4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_12
+ 4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_13
+ 4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_14
+ 4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_15
+ 4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_16
+ 4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_17
+ 4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_18
+ 4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_19
+ 4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_20
+ 4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_21
+ 4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_22
+ 4'b 0001, // index[117] ALERT_HANDLER_ALERT_CLASS_23
+ 4'b 0001, // index[118] ALERT_HANDLER_ALERT_CLASS_24
+ 4'b 0001, // index[119] ALERT_HANDLER_ALERT_CLASS_25
+ 4'b 0001, // index[120] ALERT_HANDLER_ALERT_CLASS_26
+ 4'b 0001, // index[121] ALERT_HANDLER_ALERT_CLASS_27
+ 4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_28
+ 4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_29
+ 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_30
+ 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_31
+ 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_32
+ 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_33
+ 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_34
+ 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_35
+ 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_36
+ 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_37
+ 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_38
+ 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_39
+ 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_40
+ 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_41
+ 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_42
+ 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_43
+ 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CAUSE_0
+ 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CAUSE_1
+ 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CAUSE_2
+ 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CAUSE_3
+ 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CAUSE_4
+ 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CAUSE_5
+ 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CAUSE_6
+ 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CAUSE_7
+ 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CAUSE_8
+ 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CAUSE_9
+ 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CAUSE_10
+ 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CAUSE_11
+ 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CAUSE_12
+ 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CAUSE_13
+ 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CAUSE_14
+ 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CAUSE_15
+ 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CAUSE_16
+ 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CAUSE_17
+ 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CAUSE_18
+ 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CAUSE_19
+ 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CAUSE_20
+ 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CAUSE_21
+ 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CAUSE_22
+ 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CAUSE_23
+ 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CAUSE_24
+ 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CAUSE_25
+ 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CAUSE_26
+ 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CAUSE_27
+ 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CAUSE_28
+ 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CAUSE_29
+ 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CAUSE_30
+ 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CAUSE_31
+ 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CAUSE_32
+ 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CAUSE_33
+ 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CAUSE_34
+ 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CAUSE_35
+ 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CAUSE_36
+ 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CAUSE_37
+ 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CAUSE_38
+ 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CAUSE_39
+ 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CAUSE_40
+ 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CAUSE_41
+ 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CAUSE_42
+ 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CAUSE_43
+ 4'b 0001, // index[182] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+ 4'b 0001, // index[183] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+ 4'b 0001, // index[184] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+ 4'b 0001, // index[185] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+ 4'b 0001, // index[186] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+ 4'b 0001, // index[187] ALERT_HANDLER_LOC_ALERT_EN_0
+ 4'b 0001, // index[188] ALERT_HANDLER_LOC_ALERT_EN_1
+ 4'b 0001, // index[189] ALERT_HANDLER_LOC_ALERT_EN_2
+ 4'b 0001, // index[190] ALERT_HANDLER_LOC_ALERT_EN_3
+ 4'b 0001, // index[191] ALERT_HANDLER_LOC_ALERT_EN_4
+ 4'b 0001, // index[192] ALERT_HANDLER_LOC_ALERT_CLASS_0
+ 4'b 0001, // index[193] ALERT_HANDLER_LOC_ALERT_CLASS_1
+ 4'b 0001, // index[194] ALERT_HANDLER_LOC_ALERT_CLASS_2
+ 4'b 0001, // index[195] ALERT_HANDLER_LOC_ALERT_CLASS_3
+ 4'b 0001, // index[196] ALERT_HANDLER_LOC_ALERT_CLASS_4
+ 4'b 0001, // index[197] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+ 4'b 0001, // index[198] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+ 4'b 0001, // index[199] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+ 4'b 0001, // index[200] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+ 4'b 0001, // index[201] ALERT_HANDLER_LOC_ALERT_CAUSE_4
+ 4'b 0001, // index[202] ALERT_HANDLER_CLASSA_REGWEN
+ 4'b 0011, // index[203] ALERT_HANDLER_CLASSA_CTRL
+ 4'b 0001, // index[204] ALERT_HANDLER_CLASSA_CLR_REGWEN
+ 4'b 0001, // index[205] ALERT_HANDLER_CLASSA_CLR
+ 4'b 0011, // index[206] ALERT_HANDLER_CLASSA_ACCUM_CNT
+ 4'b 0011, // index[207] ALERT_HANDLER_CLASSA_ACCUM_THRESH
+ 4'b 1111, // index[208] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
+ 4'b 1111, // index[209] ALERT_HANDLER_CLASSA_PHASE0_CYC
+ 4'b 1111, // index[210] ALERT_HANDLER_CLASSA_PHASE1_CYC
+ 4'b 1111, // index[211] ALERT_HANDLER_CLASSA_PHASE2_CYC
+ 4'b 1111, // index[212] ALERT_HANDLER_CLASSA_PHASE3_CYC
+ 4'b 1111, // index[213] ALERT_HANDLER_CLASSA_ESC_CNT
+ 4'b 0001, // index[214] ALERT_HANDLER_CLASSA_STATE
+ 4'b 0001, // index[215] ALERT_HANDLER_CLASSB_REGWEN
+ 4'b 0011, // index[216] ALERT_HANDLER_CLASSB_CTRL
+ 4'b 0001, // index[217] ALERT_HANDLER_CLASSB_CLR_REGWEN
+ 4'b 0001, // index[218] ALERT_HANDLER_CLASSB_CLR
+ 4'b 0011, // index[219] ALERT_HANDLER_CLASSB_ACCUM_CNT
+ 4'b 0011, // index[220] ALERT_HANDLER_CLASSB_ACCUM_THRESH
+ 4'b 1111, // index[221] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
+ 4'b 1111, // index[222] ALERT_HANDLER_CLASSB_PHASE0_CYC
+ 4'b 1111, // index[223] ALERT_HANDLER_CLASSB_PHASE1_CYC
+ 4'b 1111, // index[224] ALERT_HANDLER_CLASSB_PHASE2_CYC
+ 4'b 1111, // index[225] ALERT_HANDLER_CLASSB_PHASE3_CYC
+ 4'b 1111, // index[226] ALERT_HANDLER_CLASSB_ESC_CNT
+ 4'b 0001, // index[227] ALERT_HANDLER_CLASSB_STATE
+ 4'b 0001, // index[228] ALERT_HANDLER_CLASSC_REGWEN
+ 4'b 0011, // index[229] ALERT_HANDLER_CLASSC_CTRL
+ 4'b 0001, // index[230] ALERT_HANDLER_CLASSC_CLR_REGWEN
+ 4'b 0001, // index[231] ALERT_HANDLER_CLASSC_CLR
+ 4'b 0011, // index[232] ALERT_HANDLER_CLASSC_ACCUM_CNT
+ 4'b 0011, // index[233] ALERT_HANDLER_CLASSC_ACCUM_THRESH
+ 4'b 1111, // index[234] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
+ 4'b 1111, // index[235] ALERT_HANDLER_CLASSC_PHASE0_CYC
+ 4'b 1111, // index[236] ALERT_HANDLER_CLASSC_PHASE1_CYC
+ 4'b 1111, // index[237] ALERT_HANDLER_CLASSC_PHASE2_CYC
+ 4'b 1111, // index[238] ALERT_HANDLER_CLASSC_PHASE3_CYC
+ 4'b 1111, // index[239] ALERT_HANDLER_CLASSC_ESC_CNT
+ 4'b 0001, // index[240] ALERT_HANDLER_CLASSC_STATE
+ 4'b 0001, // index[241] ALERT_HANDLER_CLASSD_REGWEN
+ 4'b 0011, // index[242] ALERT_HANDLER_CLASSD_CTRL
+ 4'b 0001, // index[243] ALERT_HANDLER_CLASSD_CLR_REGWEN
+ 4'b 0001, // index[244] ALERT_HANDLER_CLASSD_CLR
+ 4'b 0011, // index[245] ALERT_HANDLER_CLASSD_ACCUM_CNT
+ 4'b 0011, // index[246] ALERT_HANDLER_CLASSD_ACCUM_THRESH
+ 4'b 1111, // index[247] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
+ 4'b 1111, // index[248] ALERT_HANDLER_CLASSD_PHASE0_CYC
+ 4'b 1111, // index[249] ALERT_HANDLER_CLASSD_PHASE1_CYC
+ 4'b 1111, // index[250] ALERT_HANDLER_CLASSD_PHASE2_CYC
+ 4'b 1111, // index[251] ALERT_HANDLER_CLASSD_PHASE3_CYC
+ 4'b 1111, // index[252] ALERT_HANDLER_CLASSD_ESC_CNT
+ 4'b 0001 // index[253] ALERT_HANDLER_CLASSD_STATE
};
endpackage
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index 06e5b20..91a0332 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -274,6 +274,9 @@
logic alert_regwen_42_qs;
logic alert_regwen_42_wd;
logic alert_regwen_42_we;
+ logic alert_regwen_43_qs;
+ logic alert_regwen_43_wd;
+ logic alert_regwen_43_we;
logic alert_en_0_qs;
logic alert_en_0_wd;
logic alert_en_0_we;
@@ -403,6 +406,9 @@
logic alert_en_42_qs;
logic alert_en_42_wd;
logic alert_en_42_we;
+ logic alert_en_43_qs;
+ logic alert_en_43_wd;
+ logic alert_en_43_we;
logic [1:0] alert_class_0_qs;
logic [1:0] alert_class_0_wd;
logic alert_class_0_we;
@@ -532,6 +538,9 @@
logic [1:0] alert_class_42_qs;
logic [1:0] alert_class_42_wd;
logic alert_class_42_we;
+ logic [1:0] alert_class_43_qs;
+ logic [1:0] alert_class_43_wd;
+ logic alert_class_43_we;
logic alert_cause_0_qs;
logic alert_cause_0_wd;
logic alert_cause_0_we;
@@ -661,6 +670,9 @@
logic alert_cause_42_qs;
logic alert_cause_42_wd;
logic alert_cause_42_we;
+ logic alert_cause_43_qs;
+ logic alert_cause_43_wd;
+ logic alert_cause_43_we;
logic loc_alert_regwen_0_qs;
logic loc_alert_regwen_0_wd;
logic loc_alert_regwen_0_we;
@@ -2488,6 +2500,33 @@
.qs (alert_regwen_42_qs)
);
+ // Subregister 43 of Multireg alert_regwen
+ // R[alert_regwen_43]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_43_we),
+ .wd (alert_regwen_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[43].q),
+
+ // to register interface (read)
+ .qs (alert_regwen_43_qs)
+ );
+
// Subregister 0 of Multireg alert_en
@@ -3651,6 +3690,33 @@
.qs (alert_en_42_qs)
);
+ // Subregister 43 of Multireg alert_en
+ // R[alert_en_43]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_en_43_we & alert_regwen_43_qs),
+ .wd (alert_en_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[43].q),
+
+ // to register interface (read)
+ .qs (alert_en_43_qs)
+ );
+
// Subregister 0 of Multireg alert_class
@@ -4814,6 +4880,33 @@
.qs (alert_class_42_qs)
);
+ // Subregister 43 of Multireg alert_class
+ // R[alert_class_43]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_class_43_we & alert_regwen_43_qs),
+ .wd (alert_class_43_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[43].q),
+
+ // to register interface (read)
+ .qs (alert_class_43_qs)
+ );
+
// Subregister 0 of Multireg alert_cause
@@ -5977,6 +6070,33 @@
.qs (alert_cause_42_qs)
);
+ // Subregister 43 of Multireg alert_cause
+ // R[alert_cause_43]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_43 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_43_we),
+ .wd (alert_cause_43_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[43].de),
+ .d (hw2reg.alert_cause[43].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[43].q),
+
+ // to register interface (read)
+ .qs (alert_cause_43_qs)
+ );
+
// Subregister 0 of Multireg loc_alert_regwen
@@ -8740,7 +8860,7 @@
- logic [249:0] addr_hit;
+ logic [253:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
@@ -8792,207 +8912,211 @@
addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_40_OFFSET);
addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_41_OFFSET);
addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_42_OFFSET);
- addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
- addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
- addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
- addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
- addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
- addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
- addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
- addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
- addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
- addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
- addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
- addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
- addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
- addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
- addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
- addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
- addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
- addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
- addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
- addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
- addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
- addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
- addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
- addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
- addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
- addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
- addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
- addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
- addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
- addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
- addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
- addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
- addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
- addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
- addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
- addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
- addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
- addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET);
- addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET);
- addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET);
- addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET);
- addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET);
- addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET);
- addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
- addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
- addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
- addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
- addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
- addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
- addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
- addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
- addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
- addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
- addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
- addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
- addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
- addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
- addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
- addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
- addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
- addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
- addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
- addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
- addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
- addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
- addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
- addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
- addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
- addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
- addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
- addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
- addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
- addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
- addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
- addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
- addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
- addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
- addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
- addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
- addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
- addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET);
- addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET);
- addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET);
- addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET);
- addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET);
- addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET);
- addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
- addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
- addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
- addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
- addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
- addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
- addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
- addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
- addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
- addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
- addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
- addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
- addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
- addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
- addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
- addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
- addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
- addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
- addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
- addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
- addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
- addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
- addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
- addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
- addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
- addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
- addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
- addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
- addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
- addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
- addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
- addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
- addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
- addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
- addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
- addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
- addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
- addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
- addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
- addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
- addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
- addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
- addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
- addr_hit[178] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
- addr_hit[179] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
- addr_hit[180] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
- addr_hit[181] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
- addr_hit[182] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
- addr_hit[183] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
- addr_hit[184] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
- addr_hit[185] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
- addr_hit[186] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
- addr_hit[187] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET);
- addr_hit[188] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
- addr_hit[189] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
- addr_hit[190] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
- addr_hit[191] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
- addr_hit[192] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET);
- addr_hit[193] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
- addr_hit[194] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
- addr_hit[195] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
- addr_hit[196] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
- addr_hit[197] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
- addr_hit[198] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
- addr_hit[199] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
- addr_hit[200] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
- addr_hit[201] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
- addr_hit[202] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
- addr_hit[203] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
- addr_hit[204] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
- addr_hit[205] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
- addr_hit[206] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
- addr_hit[207] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
- addr_hit[208] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
- addr_hit[209] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
- addr_hit[210] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
- addr_hit[211] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
- addr_hit[212] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
- addr_hit[213] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
- addr_hit[214] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
- addr_hit[215] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
- addr_hit[216] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
- addr_hit[217] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
- addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
- addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
- addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
- addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
- addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
- addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
- addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
- addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
- addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
- addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
- addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
- addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
- addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
- addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
- addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
- addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
- addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
- addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
- addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
- addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
- addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
- addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
- addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
- addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
- addr_hit[242] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
- addr_hit[243] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
- addr_hit[244] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
- addr_hit[245] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
- addr_hit[246] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
- addr_hit[247] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
- addr_hit[248] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
- addr_hit[249] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+ addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_43_OFFSET);
+ addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
+ addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
+ addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
+ addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
+ addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
+ addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
+ addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
+ addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
+ addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
+ addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
+ addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
+ addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
+ addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
+ addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
+ addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
+ addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
+ addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
+ addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
+ addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
+ addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
+ addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
+ addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
+ addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
+ addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
+ addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
+ addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
+ addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
+ addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
+ addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
+ addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
+ addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
+ addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
+ addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
+ addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
+ addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
+ addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
+ addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
+ addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET);
+ addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET);
+ addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET);
+ addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET);
+ addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET);
+ addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET);
+ addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_43_OFFSET);
+ addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
+ addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
+ addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
+ addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
+ addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
+ addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
+ addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
+ addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
+ addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
+ addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
+ addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
+ addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
+ addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
+ addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
+ addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
+ addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
+ addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
+ addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
+ addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
+ addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
+ addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
+ addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
+ addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
+ addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
+ addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
+ addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
+ addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
+ addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
+ addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
+ addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
+ addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
+ addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
+ addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
+ addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
+ addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
+ addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
+ addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
+ addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET);
+ addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET);
+ addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET);
+ addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET);
+ addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET);
+ addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET);
+ addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_43_OFFSET);
+ addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+ addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+ addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+ addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+ addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+ addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+ addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+ addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+ addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+ addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+ addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+ addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+ addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+ addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+ addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+ addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+ addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+ addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+ addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+ addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+ addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+ addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+ addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+ addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+ addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+ addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+ addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+ addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+ addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+ addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+ addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+ addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+ addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+ addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+ addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+ addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+ addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+ addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+ addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+ addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
+ addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
+ addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
+ addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
+ addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
+ addr_hit[182] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+ addr_hit[183] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+ addr_hit[184] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+ addr_hit[185] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+ addr_hit[186] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+ addr_hit[187] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
+ addr_hit[188] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
+ addr_hit[189] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
+ addr_hit[190] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
+ addr_hit[191] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET);
+ addr_hit[192] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
+ addr_hit[193] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
+ addr_hit[194] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
+ addr_hit[195] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
+ addr_hit[196] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET);
+ addr_hit[197] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+ addr_hit[198] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+ addr_hit[199] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+ addr_hit[200] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+ addr_hit[201] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
+ addr_hit[202] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+ addr_hit[203] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
+ addr_hit[204] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+ addr_hit[205] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
+ addr_hit[206] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+ addr_hit[207] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
+ addr_hit[208] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
+ addr_hit[209] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
+ addr_hit[210] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
+ addr_hit[211] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
+ addr_hit[212] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
+ addr_hit[213] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+ addr_hit[214] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+ addr_hit[215] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+ addr_hit[216] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
+ addr_hit[217] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+ addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
+ addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+ addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
+ addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
+ addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
+ addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
+ addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
+ addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
+ addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+ addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+ addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+ addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
+ addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+ addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
+ addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+ addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
+ addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
+ addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
+ addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
+ addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
+ addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
+ addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+ addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+ addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+ addr_hit[242] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
+ addr_hit[243] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+ addr_hit[244] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
+ addr_hit[245] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+ addr_hit[246] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
+ addr_hit[247] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
+ addr_hit[248] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
+ addr_hit[249] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
+ addr_hit[250] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
+ addr_hit[251] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
+ addr_hit[252] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+ addr_hit[253] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -9249,7 +9373,11 @@
(addr_hit[246] & (|(ALERT_HANDLER_PERMIT[246] & ~reg_be))) |
(addr_hit[247] & (|(ALERT_HANDLER_PERMIT[247] & ~reg_be))) |
(addr_hit[248] & (|(ALERT_HANDLER_PERMIT[248] & ~reg_be))) |
- (addr_hit[249] & (|(ALERT_HANDLER_PERMIT[249] & ~reg_be)))));
+ (addr_hit[249] & (|(ALERT_HANDLER_PERMIT[249] & ~reg_be))) |
+ (addr_hit[250] & (|(ALERT_HANDLER_PERMIT[250] & ~reg_be))) |
+ (addr_hit[251] & (|(ALERT_HANDLER_PERMIT[251] & ~reg_be))) |
+ (addr_hit[252] & (|(ALERT_HANDLER_PERMIT[252] & ~reg_be))) |
+ (addr_hit[253] & (|(ALERT_HANDLER_PERMIT[253] & ~reg_be)))));
end
assign intr_state_classa_we = addr_hit[0] & reg_we & !reg_error;
@@ -9426,704 +9554,716 @@
assign alert_regwen_42_we = addr_hit[48] & reg_we & !reg_error;
assign alert_regwen_42_wd = reg_wdata[0];
- assign alert_en_0_we = addr_hit[49] & reg_we & !reg_error;
+ assign alert_regwen_43_we = addr_hit[49] & reg_we & !reg_error;
+ assign alert_regwen_43_wd = reg_wdata[0];
+
+ assign alert_en_0_we = addr_hit[50] & reg_we & !reg_error;
assign alert_en_0_wd = reg_wdata[0];
- assign alert_en_1_we = addr_hit[50] & reg_we & !reg_error;
+ assign alert_en_1_we = addr_hit[51] & reg_we & !reg_error;
assign alert_en_1_wd = reg_wdata[0];
- assign alert_en_2_we = addr_hit[51] & reg_we & !reg_error;
+ assign alert_en_2_we = addr_hit[52] & reg_we & !reg_error;
assign alert_en_2_wd = reg_wdata[0];
- assign alert_en_3_we = addr_hit[52] & reg_we & !reg_error;
+ assign alert_en_3_we = addr_hit[53] & reg_we & !reg_error;
assign alert_en_3_wd = reg_wdata[0];
- assign alert_en_4_we = addr_hit[53] & reg_we & !reg_error;
+ assign alert_en_4_we = addr_hit[54] & reg_we & !reg_error;
assign alert_en_4_wd = reg_wdata[0];
- assign alert_en_5_we = addr_hit[54] & reg_we & !reg_error;
+ assign alert_en_5_we = addr_hit[55] & reg_we & !reg_error;
assign alert_en_5_wd = reg_wdata[0];
- assign alert_en_6_we = addr_hit[55] & reg_we & !reg_error;
+ assign alert_en_6_we = addr_hit[56] & reg_we & !reg_error;
assign alert_en_6_wd = reg_wdata[0];
- assign alert_en_7_we = addr_hit[56] & reg_we & !reg_error;
+ assign alert_en_7_we = addr_hit[57] & reg_we & !reg_error;
assign alert_en_7_wd = reg_wdata[0];
- assign alert_en_8_we = addr_hit[57] & reg_we & !reg_error;
+ assign alert_en_8_we = addr_hit[58] & reg_we & !reg_error;
assign alert_en_8_wd = reg_wdata[0];
- assign alert_en_9_we = addr_hit[58] & reg_we & !reg_error;
+ assign alert_en_9_we = addr_hit[59] & reg_we & !reg_error;
assign alert_en_9_wd = reg_wdata[0];
- assign alert_en_10_we = addr_hit[59] & reg_we & !reg_error;
+ assign alert_en_10_we = addr_hit[60] & reg_we & !reg_error;
assign alert_en_10_wd = reg_wdata[0];
- assign alert_en_11_we = addr_hit[60] & reg_we & !reg_error;
+ assign alert_en_11_we = addr_hit[61] & reg_we & !reg_error;
assign alert_en_11_wd = reg_wdata[0];
- assign alert_en_12_we = addr_hit[61] & reg_we & !reg_error;
+ assign alert_en_12_we = addr_hit[62] & reg_we & !reg_error;
assign alert_en_12_wd = reg_wdata[0];
- assign alert_en_13_we = addr_hit[62] & reg_we & !reg_error;
+ assign alert_en_13_we = addr_hit[63] & reg_we & !reg_error;
assign alert_en_13_wd = reg_wdata[0];
- assign alert_en_14_we = addr_hit[63] & reg_we & !reg_error;
+ assign alert_en_14_we = addr_hit[64] & reg_we & !reg_error;
assign alert_en_14_wd = reg_wdata[0];
- assign alert_en_15_we = addr_hit[64] & reg_we & !reg_error;
+ assign alert_en_15_we = addr_hit[65] & reg_we & !reg_error;
assign alert_en_15_wd = reg_wdata[0];
- assign alert_en_16_we = addr_hit[65] & reg_we & !reg_error;
+ assign alert_en_16_we = addr_hit[66] & reg_we & !reg_error;
assign alert_en_16_wd = reg_wdata[0];
- assign alert_en_17_we = addr_hit[66] & reg_we & !reg_error;
+ assign alert_en_17_we = addr_hit[67] & reg_we & !reg_error;
assign alert_en_17_wd = reg_wdata[0];
- assign alert_en_18_we = addr_hit[67] & reg_we & !reg_error;
+ assign alert_en_18_we = addr_hit[68] & reg_we & !reg_error;
assign alert_en_18_wd = reg_wdata[0];
- assign alert_en_19_we = addr_hit[68] & reg_we & !reg_error;
+ assign alert_en_19_we = addr_hit[69] & reg_we & !reg_error;
assign alert_en_19_wd = reg_wdata[0];
- assign alert_en_20_we = addr_hit[69] & reg_we & !reg_error;
+ assign alert_en_20_we = addr_hit[70] & reg_we & !reg_error;
assign alert_en_20_wd = reg_wdata[0];
- assign alert_en_21_we = addr_hit[70] & reg_we & !reg_error;
+ assign alert_en_21_we = addr_hit[71] & reg_we & !reg_error;
assign alert_en_21_wd = reg_wdata[0];
- assign alert_en_22_we = addr_hit[71] & reg_we & !reg_error;
+ assign alert_en_22_we = addr_hit[72] & reg_we & !reg_error;
assign alert_en_22_wd = reg_wdata[0];
- assign alert_en_23_we = addr_hit[72] & reg_we & !reg_error;
+ assign alert_en_23_we = addr_hit[73] & reg_we & !reg_error;
assign alert_en_23_wd = reg_wdata[0];
- assign alert_en_24_we = addr_hit[73] & reg_we & !reg_error;
+ assign alert_en_24_we = addr_hit[74] & reg_we & !reg_error;
assign alert_en_24_wd = reg_wdata[0];
- assign alert_en_25_we = addr_hit[74] & reg_we & !reg_error;
+ assign alert_en_25_we = addr_hit[75] & reg_we & !reg_error;
assign alert_en_25_wd = reg_wdata[0];
- assign alert_en_26_we = addr_hit[75] & reg_we & !reg_error;
+ assign alert_en_26_we = addr_hit[76] & reg_we & !reg_error;
assign alert_en_26_wd = reg_wdata[0];
- assign alert_en_27_we = addr_hit[76] & reg_we & !reg_error;
+ assign alert_en_27_we = addr_hit[77] & reg_we & !reg_error;
assign alert_en_27_wd = reg_wdata[0];
- assign alert_en_28_we = addr_hit[77] & reg_we & !reg_error;
+ assign alert_en_28_we = addr_hit[78] & reg_we & !reg_error;
assign alert_en_28_wd = reg_wdata[0];
- assign alert_en_29_we = addr_hit[78] & reg_we & !reg_error;
+ assign alert_en_29_we = addr_hit[79] & reg_we & !reg_error;
assign alert_en_29_wd = reg_wdata[0];
- assign alert_en_30_we = addr_hit[79] & reg_we & !reg_error;
+ assign alert_en_30_we = addr_hit[80] & reg_we & !reg_error;
assign alert_en_30_wd = reg_wdata[0];
- assign alert_en_31_we = addr_hit[80] & reg_we & !reg_error;
+ assign alert_en_31_we = addr_hit[81] & reg_we & !reg_error;
assign alert_en_31_wd = reg_wdata[0];
- assign alert_en_32_we = addr_hit[81] & reg_we & !reg_error;
+ assign alert_en_32_we = addr_hit[82] & reg_we & !reg_error;
assign alert_en_32_wd = reg_wdata[0];
- assign alert_en_33_we = addr_hit[82] & reg_we & !reg_error;
+ assign alert_en_33_we = addr_hit[83] & reg_we & !reg_error;
assign alert_en_33_wd = reg_wdata[0];
- assign alert_en_34_we = addr_hit[83] & reg_we & !reg_error;
+ assign alert_en_34_we = addr_hit[84] & reg_we & !reg_error;
assign alert_en_34_wd = reg_wdata[0];
- assign alert_en_35_we = addr_hit[84] & reg_we & !reg_error;
+ assign alert_en_35_we = addr_hit[85] & reg_we & !reg_error;
assign alert_en_35_wd = reg_wdata[0];
- assign alert_en_36_we = addr_hit[85] & reg_we & !reg_error;
+ assign alert_en_36_we = addr_hit[86] & reg_we & !reg_error;
assign alert_en_36_wd = reg_wdata[0];
- assign alert_en_37_we = addr_hit[86] & reg_we & !reg_error;
+ assign alert_en_37_we = addr_hit[87] & reg_we & !reg_error;
assign alert_en_37_wd = reg_wdata[0];
- assign alert_en_38_we = addr_hit[87] & reg_we & !reg_error;
+ assign alert_en_38_we = addr_hit[88] & reg_we & !reg_error;
assign alert_en_38_wd = reg_wdata[0];
- assign alert_en_39_we = addr_hit[88] & reg_we & !reg_error;
+ assign alert_en_39_we = addr_hit[89] & reg_we & !reg_error;
assign alert_en_39_wd = reg_wdata[0];
- assign alert_en_40_we = addr_hit[89] & reg_we & !reg_error;
+ assign alert_en_40_we = addr_hit[90] & reg_we & !reg_error;
assign alert_en_40_wd = reg_wdata[0];
- assign alert_en_41_we = addr_hit[90] & reg_we & !reg_error;
+ assign alert_en_41_we = addr_hit[91] & reg_we & !reg_error;
assign alert_en_41_wd = reg_wdata[0];
- assign alert_en_42_we = addr_hit[91] & reg_we & !reg_error;
+ assign alert_en_42_we = addr_hit[92] & reg_we & !reg_error;
assign alert_en_42_wd = reg_wdata[0];
- assign alert_class_0_we = addr_hit[92] & reg_we & !reg_error;
+ assign alert_en_43_we = addr_hit[93] & reg_we & !reg_error;
+ assign alert_en_43_wd = reg_wdata[0];
+
+ assign alert_class_0_we = addr_hit[94] & reg_we & !reg_error;
assign alert_class_0_wd = reg_wdata[1:0];
- assign alert_class_1_we = addr_hit[93] & reg_we & !reg_error;
+ assign alert_class_1_we = addr_hit[95] & reg_we & !reg_error;
assign alert_class_1_wd = reg_wdata[1:0];
- assign alert_class_2_we = addr_hit[94] & reg_we & !reg_error;
+ assign alert_class_2_we = addr_hit[96] & reg_we & !reg_error;
assign alert_class_2_wd = reg_wdata[1:0];
- assign alert_class_3_we = addr_hit[95] & reg_we & !reg_error;
+ assign alert_class_3_we = addr_hit[97] & reg_we & !reg_error;
assign alert_class_3_wd = reg_wdata[1:0];
- assign alert_class_4_we = addr_hit[96] & reg_we & !reg_error;
+ assign alert_class_4_we = addr_hit[98] & reg_we & !reg_error;
assign alert_class_4_wd = reg_wdata[1:0];
- assign alert_class_5_we = addr_hit[97] & reg_we & !reg_error;
+ assign alert_class_5_we = addr_hit[99] & reg_we & !reg_error;
assign alert_class_5_wd = reg_wdata[1:0];
- assign alert_class_6_we = addr_hit[98] & reg_we & !reg_error;
+ assign alert_class_6_we = addr_hit[100] & reg_we & !reg_error;
assign alert_class_6_wd = reg_wdata[1:0];
- assign alert_class_7_we = addr_hit[99] & reg_we & !reg_error;
+ assign alert_class_7_we = addr_hit[101] & reg_we & !reg_error;
assign alert_class_7_wd = reg_wdata[1:0];
- assign alert_class_8_we = addr_hit[100] & reg_we & !reg_error;
+ assign alert_class_8_we = addr_hit[102] & reg_we & !reg_error;
assign alert_class_8_wd = reg_wdata[1:0];
- assign alert_class_9_we = addr_hit[101] & reg_we & !reg_error;
+ assign alert_class_9_we = addr_hit[103] & reg_we & !reg_error;
assign alert_class_9_wd = reg_wdata[1:0];
- assign alert_class_10_we = addr_hit[102] & reg_we & !reg_error;
+ assign alert_class_10_we = addr_hit[104] & reg_we & !reg_error;
assign alert_class_10_wd = reg_wdata[1:0];
- assign alert_class_11_we = addr_hit[103] & reg_we & !reg_error;
+ assign alert_class_11_we = addr_hit[105] & reg_we & !reg_error;
assign alert_class_11_wd = reg_wdata[1:0];
- assign alert_class_12_we = addr_hit[104] & reg_we & !reg_error;
+ assign alert_class_12_we = addr_hit[106] & reg_we & !reg_error;
assign alert_class_12_wd = reg_wdata[1:0];
- assign alert_class_13_we = addr_hit[105] & reg_we & !reg_error;
+ assign alert_class_13_we = addr_hit[107] & reg_we & !reg_error;
assign alert_class_13_wd = reg_wdata[1:0];
- assign alert_class_14_we = addr_hit[106] & reg_we & !reg_error;
+ assign alert_class_14_we = addr_hit[108] & reg_we & !reg_error;
assign alert_class_14_wd = reg_wdata[1:0];
- assign alert_class_15_we = addr_hit[107] & reg_we & !reg_error;
+ assign alert_class_15_we = addr_hit[109] & reg_we & !reg_error;
assign alert_class_15_wd = reg_wdata[1:0];
- assign alert_class_16_we = addr_hit[108] & reg_we & !reg_error;
+ assign alert_class_16_we = addr_hit[110] & reg_we & !reg_error;
assign alert_class_16_wd = reg_wdata[1:0];
- assign alert_class_17_we = addr_hit[109] & reg_we & !reg_error;
+ assign alert_class_17_we = addr_hit[111] & reg_we & !reg_error;
assign alert_class_17_wd = reg_wdata[1:0];
- assign alert_class_18_we = addr_hit[110] & reg_we & !reg_error;
+ assign alert_class_18_we = addr_hit[112] & reg_we & !reg_error;
assign alert_class_18_wd = reg_wdata[1:0];
- assign alert_class_19_we = addr_hit[111] & reg_we & !reg_error;
+ assign alert_class_19_we = addr_hit[113] & reg_we & !reg_error;
assign alert_class_19_wd = reg_wdata[1:0];
- assign alert_class_20_we = addr_hit[112] & reg_we & !reg_error;
+ assign alert_class_20_we = addr_hit[114] & reg_we & !reg_error;
assign alert_class_20_wd = reg_wdata[1:0];
- assign alert_class_21_we = addr_hit[113] & reg_we & !reg_error;
+ assign alert_class_21_we = addr_hit[115] & reg_we & !reg_error;
assign alert_class_21_wd = reg_wdata[1:0];
- assign alert_class_22_we = addr_hit[114] & reg_we & !reg_error;
+ assign alert_class_22_we = addr_hit[116] & reg_we & !reg_error;
assign alert_class_22_wd = reg_wdata[1:0];
- assign alert_class_23_we = addr_hit[115] & reg_we & !reg_error;
+ assign alert_class_23_we = addr_hit[117] & reg_we & !reg_error;
assign alert_class_23_wd = reg_wdata[1:0];
- assign alert_class_24_we = addr_hit[116] & reg_we & !reg_error;
+ assign alert_class_24_we = addr_hit[118] & reg_we & !reg_error;
assign alert_class_24_wd = reg_wdata[1:0];
- assign alert_class_25_we = addr_hit[117] & reg_we & !reg_error;
+ assign alert_class_25_we = addr_hit[119] & reg_we & !reg_error;
assign alert_class_25_wd = reg_wdata[1:0];
- assign alert_class_26_we = addr_hit[118] & reg_we & !reg_error;
+ assign alert_class_26_we = addr_hit[120] & reg_we & !reg_error;
assign alert_class_26_wd = reg_wdata[1:0];
- assign alert_class_27_we = addr_hit[119] & reg_we & !reg_error;
+ assign alert_class_27_we = addr_hit[121] & reg_we & !reg_error;
assign alert_class_27_wd = reg_wdata[1:0];
- assign alert_class_28_we = addr_hit[120] & reg_we & !reg_error;
+ assign alert_class_28_we = addr_hit[122] & reg_we & !reg_error;
assign alert_class_28_wd = reg_wdata[1:0];
- assign alert_class_29_we = addr_hit[121] & reg_we & !reg_error;
+ assign alert_class_29_we = addr_hit[123] & reg_we & !reg_error;
assign alert_class_29_wd = reg_wdata[1:0];
- assign alert_class_30_we = addr_hit[122] & reg_we & !reg_error;
+ assign alert_class_30_we = addr_hit[124] & reg_we & !reg_error;
assign alert_class_30_wd = reg_wdata[1:0];
- assign alert_class_31_we = addr_hit[123] & reg_we & !reg_error;
+ assign alert_class_31_we = addr_hit[125] & reg_we & !reg_error;
assign alert_class_31_wd = reg_wdata[1:0];
- assign alert_class_32_we = addr_hit[124] & reg_we & !reg_error;
+ assign alert_class_32_we = addr_hit[126] & reg_we & !reg_error;
assign alert_class_32_wd = reg_wdata[1:0];
- assign alert_class_33_we = addr_hit[125] & reg_we & !reg_error;
+ assign alert_class_33_we = addr_hit[127] & reg_we & !reg_error;
assign alert_class_33_wd = reg_wdata[1:0];
- assign alert_class_34_we = addr_hit[126] & reg_we & !reg_error;
+ assign alert_class_34_we = addr_hit[128] & reg_we & !reg_error;
assign alert_class_34_wd = reg_wdata[1:0];
- assign alert_class_35_we = addr_hit[127] & reg_we & !reg_error;
+ assign alert_class_35_we = addr_hit[129] & reg_we & !reg_error;
assign alert_class_35_wd = reg_wdata[1:0];
- assign alert_class_36_we = addr_hit[128] & reg_we & !reg_error;
+ assign alert_class_36_we = addr_hit[130] & reg_we & !reg_error;
assign alert_class_36_wd = reg_wdata[1:0];
- assign alert_class_37_we = addr_hit[129] & reg_we & !reg_error;
+ assign alert_class_37_we = addr_hit[131] & reg_we & !reg_error;
assign alert_class_37_wd = reg_wdata[1:0];
- assign alert_class_38_we = addr_hit[130] & reg_we & !reg_error;
+ assign alert_class_38_we = addr_hit[132] & reg_we & !reg_error;
assign alert_class_38_wd = reg_wdata[1:0];
- assign alert_class_39_we = addr_hit[131] & reg_we & !reg_error;
+ assign alert_class_39_we = addr_hit[133] & reg_we & !reg_error;
assign alert_class_39_wd = reg_wdata[1:0];
- assign alert_class_40_we = addr_hit[132] & reg_we & !reg_error;
+ assign alert_class_40_we = addr_hit[134] & reg_we & !reg_error;
assign alert_class_40_wd = reg_wdata[1:0];
- assign alert_class_41_we = addr_hit[133] & reg_we & !reg_error;
+ assign alert_class_41_we = addr_hit[135] & reg_we & !reg_error;
assign alert_class_41_wd = reg_wdata[1:0];
- assign alert_class_42_we = addr_hit[134] & reg_we & !reg_error;
+ assign alert_class_42_we = addr_hit[136] & reg_we & !reg_error;
assign alert_class_42_wd = reg_wdata[1:0];
- assign alert_cause_0_we = addr_hit[135] & reg_we & !reg_error;
+ assign alert_class_43_we = addr_hit[137] & reg_we & !reg_error;
+ assign alert_class_43_wd = reg_wdata[1:0];
+
+ assign alert_cause_0_we = addr_hit[138] & reg_we & !reg_error;
assign alert_cause_0_wd = reg_wdata[0];
- assign alert_cause_1_we = addr_hit[136] & reg_we & !reg_error;
+ assign alert_cause_1_we = addr_hit[139] & reg_we & !reg_error;
assign alert_cause_1_wd = reg_wdata[0];
- assign alert_cause_2_we = addr_hit[137] & reg_we & !reg_error;
+ assign alert_cause_2_we = addr_hit[140] & reg_we & !reg_error;
assign alert_cause_2_wd = reg_wdata[0];
- assign alert_cause_3_we = addr_hit[138] & reg_we & !reg_error;
+ assign alert_cause_3_we = addr_hit[141] & reg_we & !reg_error;
assign alert_cause_3_wd = reg_wdata[0];
- assign alert_cause_4_we = addr_hit[139] & reg_we & !reg_error;
+ assign alert_cause_4_we = addr_hit[142] & reg_we & !reg_error;
assign alert_cause_4_wd = reg_wdata[0];
- assign alert_cause_5_we = addr_hit[140] & reg_we & !reg_error;
+ assign alert_cause_5_we = addr_hit[143] & reg_we & !reg_error;
assign alert_cause_5_wd = reg_wdata[0];
- assign alert_cause_6_we = addr_hit[141] & reg_we & !reg_error;
+ assign alert_cause_6_we = addr_hit[144] & reg_we & !reg_error;
assign alert_cause_6_wd = reg_wdata[0];
- assign alert_cause_7_we = addr_hit[142] & reg_we & !reg_error;
+ assign alert_cause_7_we = addr_hit[145] & reg_we & !reg_error;
assign alert_cause_7_wd = reg_wdata[0];
- assign alert_cause_8_we = addr_hit[143] & reg_we & !reg_error;
+ assign alert_cause_8_we = addr_hit[146] & reg_we & !reg_error;
assign alert_cause_8_wd = reg_wdata[0];
- assign alert_cause_9_we = addr_hit[144] & reg_we & !reg_error;
+ assign alert_cause_9_we = addr_hit[147] & reg_we & !reg_error;
assign alert_cause_9_wd = reg_wdata[0];
- assign alert_cause_10_we = addr_hit[145] & reg_we & !reg_error;
+ assign alert_cause_10_we = addr_hit[148] & reg_we & !reg_error;
assign alert_cause_10_wd = reg_wdata[0];
- assign alert_cause_11_we = addr_hit[146] & reg_we & !reg_error;
+ assign alert_cause_11_we = addr_hit[149] & reg_we & !reg_error;
assign alert_cause_11_wd = reg_wdata[0];
- assign alert_cause_12_we = addr_hit[147] & reg_we & !reg_error;
+ assign alert_cause_12_we = addr_hit[150] & reg_we & !reg_error;
assign alert_cause_12_wd = reg_wdata[0];
- assign alert_cause_13_we = addr_hit[148] & reg_we & !reg_error;
+ assign alert_cause_13_we = addr_hit[151] & reg_we & !reg_error;
assign alert_cause_13_wd = reg_wdata[0];
- assign alert_cause_14_we = addr_hit[149] & reg_we & !reg_error;
+ assign alert_cause_14_we = addr_hit[152] & reg_we & !reg_error;
assign alert_cause_14_wd = reg_wdata[0];
- assign alert_cause_15_we = addr_hit[150] & reg_we & !reg_error;
+ assign alert_cause_15_we = addr_hit[153] & reg_we & !reg_error;
assign alert_cause_15_wd = reg_wdata[0];
- assign alert_cause_16_we = addr_hit[151] & reg_we & !reg_error;
+ assign alert_cause_16_we = addr_hit[154] & reg_we & !reg_error;
assign alert_cause_16_wd = reg_wdata[0];
- assign alert_cause_17_we = addr_hit[152] & reg_we & !reg_error;
+ assign alert_cause_17_we = addr_hit[155] & reg_we & !reg_error;
assign alert_cause_17_wd = reg_wdata[0];
- assign alert_cause_18_we = addr_hit[153] & reg_we & !reg_error;
+ assign alert_cause_18_we = addr_hit[156] & reg_we & !reg_error;
assign alert_cause_18_wd = reg_wdata[0];
- assign alert_cause_19_we = addr_hit[154] & reg_we & !reg_error;
+ assign alert_cause_19_we = addr_hit[157] & reg_we & !reg_error;
assign alert_cause_19_wd = reg_wdata[0];
- assign alert_cause_20_we = addr_hit[155] & reg_we & !reg_error;
+ assign alert_cause_20_we = addr_hit[158] & reg_we & !reg_error;
assign alert_cause_20_wd = reg_wdata[0];
- assign alert_cause_21_we = addr_hit[156] & reg_we & !reg_error;
+ assign alert_cause_21_we = addr_hit[159] & reg_we & !reg_error;
assign alert_cause_21_wd = reg_wdata[0];
- assign alert_cause_22_we = addr_hit[157] & reg_we & !reg_error;
+ assign alert_cause_22_we = addr_hit[160] & reg_we & !reg_error;
assign alert_cause_22_wd = reg_wdata[0];
- assign alert_cause_23_we = addr_hit[158] & reg_we & !reg_error;
+ assign alert_cause_23_we = addr_hit[161] & reg_we & !reg_error;
assign alert_cause_23_wd = reg_wdata[0];
- assign alert_cause_24_we = addr_hit[159] & reg_we & !reg_error;
+ assign alert_cause_24_we = addr_hit[162] & reg_we & !reg_error;
assign alert_cause_24_wd = reg_wdata[0];
- assign alert_cause_25_we = addr_hit[160] & reg_we & !reg_error;
+ assign alert_cause_25_we = addr_hit[163] & reg_we & !reg_error;
assign alert_cause_25_wd = reg_wdata[0];
- assign alert_cause_26_we = addr_hit[161] & reg_we & !reg_error;
+ assign alert_cause_26_we = addr_hit[164] & reg_we & !reg_error;
assign alert_cause_26_wd = reg_wdata[0];
- assign alert_cause_27_we = addr_hit[162] & reg_we & !reg_error;
+ assign alert_cause_27_we = addr_hit[165] & reg_we & !reg_error;
assign alert_cause_27_wd = reg_wdata[0];
- assign alert_cause_28_we = addr_hit[163] & reg_we & !reg_error;
+ assign alert_cause_28_we = addr_hit[166] & reg_we & !reg_error;
assign alert_cause_28_wd = reg_wdata[0];
- assign alert_cause_29_we = addr_hit[164] & reg_we & !reg_error;
+ assign alert_cause_29_we = addr_hit[167] & reg_we & !reg_error;
assign alert_cause_29_wd = reg_wdata[0];
- assign alert_cause_30_we = addr_hit[165] & reg_we & !reg_error;
+ assign alert_cause_30_we = addr_hit[168] & reg_we & !reg_error;
assign alert_cause_30_wd = reg_wdata[0];
- assign alert_cause_31_we = addr_hit[166] & reg_we & !reg_error;
+ assign alert_cause_31_we = addr_hit[169] & reg_we & !reg_error;
assign alert_cause_31_wd = reg_wdata[0];
- assign alert_cause_32_we = addr_hit[167] & reg_we & !reg_error;
+ assign alert_cause_32_we = addr_hit[170] & reg_we & !reg_error;
assign alert_cause_32_wd = reg_wdata[0];
- assign alert_cause_33_we = addr_hit[168] & reg_we & !reg_error;
+ assign alert_cause_33_we = addr_hit[171] & reg_we & !reg_error;
assign alert_cause_33_wd = reg_wdata[0];
- assign alert_cause_34_we = addr_hit[169] & reg_we & !reg_error;
+ assign alert_cause_34_we = addr_hit[172] & reg_we & !reg_error;
assign alert_cause_34_wd = reg_wdata[0];
- assign alert_cause_35_we = addr_hit[170] & reg_we & !reg_error;
+ assign alert_cause_35_we = addr_hit[173] & reg_we & !reg_error;
assign alert_cause_35_wd = reg_wdata[0];
- assign alert_cause_36_we = addr_hit[171] & reg_we & !reg_error;
+ assign alert_cause_36_we = addr_hit[174] & reg_we & !reg_error;
assign alert_cause_36_wd = reg_wdata[0];
- assign alert_cause_37_we = addr_hit[172] & reg_we & !reg_error;
+ assign alert_cause_37_we = addr_hit[175] & reg_we & !reg_error;
assign alert_cause_37_wd = reg_wdata[0];
- assign alert_cause_38_we = addr_hit[173] & reg_we & !reg_error;
+ assign alert_cause_38_we = addr_hit[176] & reg_we & !reg_error;
assign alert_cause_38_wd = reg_wdata[0];
- assign alert_cause_39_we = addr_hit[174] & reg_we & !reg_error;
+ assign alert_cause_39_we = addr_hit[177] & reg_we & !reg_error;
assign alert_cause_39_wd = reg_wdata[0];
- assign alert_cause_40_we = addr_hit[175] & reg_we & !reg_error;
+ assign alert_cause_40_we = addr_hit[178] & reg_we & !reg_error;
assign alert_cause_40_wd = reg_wdata[0];
- assign alert_cause_41_we = addr_hit[176] & reg_we & !reg_error;
+ assign alert_cause_41_we = addr_hit[179] & reg_we & !reg_error;
assign alert_cause_41_wd = reg_wdata[0];
- assign alert_cause_42_we = addr_hit[177] & reg_we & !reg_error;
+ assign alert_cause_42_we = addr_hit[180] & reg_we & !reg_error;
assign alert_cause_42_wd = reg_wdata[0];
- assign loc_alert_regwen_0_we = addr_hit[178] & reg_we & !reg_error;
+ assign alert_cause_43_we = addr_hit[181] & reg_we & !reg_error;
+ assign alert_cause_43_wd = reg_wdata[0];
+
+ assign loc_alert_regwen_0_we = addr_hit[182] & reg_we & !reg_error;
assign loc_alert_regwen_0_wd = reg_wdata[0];
- assign loc_alert_regwen_1_we = addr_hit[179] & reg_we & !reg_error;
+ assign loc_alert_regwen_1_we = addr_hit[183] & reg_we & !reg_error;
assign loc_alert_regwen_1_wd = reg_wdata[0];
- assign loc_alert_regwen_2_we = addr_hit[180] & reg_we & !reg_error;
+ assign loc_alert_regwen_2_we = addr_hit[184] & reg_we & !reg_error;
assign loc_alert_regwen_2_wd = reg_wdata[0];
- assign loc_alert_regwen_3_we = addr_hit[181] & reg_we & !reg_error;
+ assign loc_alert_regwen_3_we = addr_hit[185] & reg_we & !reg_error;
assign loc_alert_regwen_3_wd = reg_wdata[0];
- assign loc_alert_regwen_4_we = addr_hit[182] & reg_we & !reg_error;
+ assign loc_alert_regwen_4_we = addr_hit[186] & reg_we & !reg_error;
assign loc_alert_regwen_4_wd = reg_wdata[0];
- assign loc_alert_en_0_we = addr_hit[183] & reg_we & !reg_error;
+ assign loc_alert_en_0_we = addr_hit[187] & reg_we & !reg_error;
assign loc_alert_en_0_wd = reg_wdata[0];
- assign loc_alert_en_1_we = addr_hit[184] & reg_we & !reg_error;
+ assign loc_alert_en_1_we = addr_hit[188] & reg_we & !reg_error;
assign loc_alert_en_1_wd = reg_wdata[0];
- assign loc_alert_en_2_we = addr_hit[185] & reg_we & !reg_error;
+ assign loc_alert_en_2_we = addr_hit[189] & reg_we & !reg_error;
assign loc_alert_en_2_wd = reg_wdata[0];
- assign loc_alert_en_3_we = addr_hit[186] & reg_we & !reg_error;
+ assign loc_alert_en_3_we = addr_hit[190] & reg_we & !reg_error;
assign loc_alert_en_3_wd = reg_wdata[0];
- assign loc_alert_en_4_we = addr_hit[187] & reg_we & !reg_error;
+ assign loc_alert_en_4_we = addr_hit[191] & reg_we & !reg_error;
assign loc_alert_en_4_wd = reg_wdata[0];
- assign loc_alert_class_0_we = addr_hit[188] & reg_we & !reg_error;
+ assign loc_alert_class_0_we = addr_hit[192] & reg_we & !reg_error;
assign loc_alert_class_0_wd = reg_wdata[1:0];
- assign loc_alert_class_1_we = addr_hit[189] & reg_we & !reg_error;
+ assign loc_alert_class_1_we = addr_hit[193] & reg_we & !reg_error;
assign loc_alert_class_1_wd = reg_wdata[1:0];
- assign loc_alert_class_2_we = addr_hit[190] & reg_we & !reg_error;
+ assign loc_alert_class_2_we = addr_hit[194] & reg_we & !reg_error;
assign loc_alert_class_2_wd = reg_wdata[1:0];
- assign loc_alert_class_3_we = addr_hit[191] & reg_we & !reg_error;
+ assign loc_alert_class_3_we = addr_hit[195] & reg_we & !reg_error;
assign loc_alert_class_3_wd = reg_wdata[1:0];
- assign loc_alert_class_4_we = addr_hit[192] & reg_we & !reg_error;
+ assign loc_alert_class_4_we = addr_hit[196] & reg_we & !reg_error;
assign loc_alert_class_4_wd = reg_wdata[1:0];
- assign loc_alert_cause_0_we = addr_hit[193] & reg_we & !reg_error;
+ assign loc_alert_cause_0_we = addr_hit[197] & reg_we & !reg_error;
assign loc_alert_cause_0_wd = reg_wdata[0];
- assign loc_alert_cause_1_we = addr_hit[194] & reg_we & !reg_error;
+ assign loc_alert_cause_1_we = addr_hit[198] & reg_we & !reg_error;
assign loc_alert_cause_1_wd = reg_wdata[0];
- assign loc_alert_cause_2_we = addr_hit[195] & reg_we & !reg_error;
+ assign loc_alert_cause_2_we = addr_hit[199] & reg_we & !reg_error;
assign loc_alert_cause_2_wd = reg_wdata[0];
- assign loc_alert_cause_3_we = addr_hit[196] & reg_we & !reg_error;
+ assign loc_alert_cause_3_we = addr_hit[200] & reg_we & !reg_error;
assign loc_alert_cause_3_wd = reg_wdata[0];
- assign loc_alert_cause_4_we = addr_hit[197] & reg_we & !reg_error;
+ assign loc_alert_cause_4_we = addr_hit[201] & reg_we & !reg_error;
assign loc_alert_cause_4_wd = reg_wdata[0];
- assign classa_regwen_we = addr_hit[198] & reg_we & !reg_error;
+ assign classa_regwen_we = addr_hit[202] & reg_we & !reg_error;
assign classa_regwen_wd = reg_wdata[0];
- assign classa_ctrl_en_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_en_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_en_wd = reg_wdata[0];
- assign classa_ctrl_lock_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_lock_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_lock_wd = reg_wdata[1];
- assign classa_ctrl_en_e0_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_en_e0_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_en_e0_wd = reg_wdata[2];
- assign classa_ctrl_en_e1_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_en_e1_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_en_e1_wd = reg_wdata[3];
- assign classa_ctrl_en_e2_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_en_e2_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_en_e2_wd = reg_wdata[4];
- assign classa_ctrl_en_e3_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_en_e3_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_en_e3_wd = reg_wdata[5];
- assign classa_ctrl_map_e0_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_map_e0_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classa_ctrl_map_e1_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_map_e1_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classa_ctrl_map_e2_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_map_e2_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classa_ctrl_map_e3_we = addr_hit[199] & reg_we & !reg_error;
+ assign classa_ctrl_map_e3_we = addr_hit[203] & reg_we & !reg_error;
assign classa_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classa_clr_regwen_we = addr_hit[200] & reg_we & !reg_error;
+ assign classa_clr_regwen_we = addr_hit[204] & reg_we & !reg_error;
assign classa_clr_regwen_wd = reg_wdata[0];
- assign classa_clr_we = addr_hit[201] & reg_we & !reg_error;
+ assign classa_clr_we = addr_hit[205] & reg_we & !reg_error;
assign classa_clr_wd = reg_wdata[0];
- assign classa_accum_cnt_re = addr_hit[202] & reg_re & !reg_error;
+ assign classa_accum_cnt_re = addr_hit[206] & reg_re & !reg_error;
- assign classa_accum_thresh_we = addr_hit[203] & reg_we & !reg_error;
+ assign classa_accum_thresh_we = addr_hit[207] & reg_we & !reg_error;
assign classa_accum_thresh_wd = reg_wdata[15:0];
- assign classa_timeout_cyc_we = addr_hit[204] & reg_we & !reg_error;
+ assign classa_timeout_cyc_we = addr_hit[208] & reg_we & !reg_error;
assign classa_timeout_cyc_wd = reg_wdata[31:0];
- assign classa_phase0_cyc_we = addr_hit[205] & reg_we & !reg_error;
+ assign classa_phase0_cyc_we = addr_hit[209] & reg_we & !reg_error;
assign classa_phase0_cyc_wd = reg_wdata[31:0];
- assign classa_phase1_cyc_we = addr_hit[206] & reg_we & !reg_error;
+ assign classa_phase1_cyc_we = addr_hit[210] & reg_we & !reg_error;
assign classa_phase1_cyc_wd = reg_wdata[31:0];
- assign classa_phase2_cyc_we = addr_hit[207] & reg_we & !reg_error;
+ assign classa_phase2_cyc_we = addr_hit[211] & reg_we & !reg_error;
assign classa_phase2_cyc_wd = reg_wdata[31:0];
- assign classa_phase3_cyc_we = addr_hit[208] & reg_we & !reg_error;
+ assign classa_phase3_cyc_we = addr_hit[212] & reg_we & !reg_error;
assign classa_phase3_cyc_wd = reg_wdata[31:0];
- assign classa_esc_cnt_re = addr_hit[209] & reg_re & !reg_error;
+ assign classa_esc_cnt_re = addr_hit[213] & reg_re & !reg_error;
- assign classa_state_re = addr_hit[210] & reg_re & !reg_error;
+ assign classa_state_re = addr_hit[214] & reg_re & !reg_error;
- assign classb_regwen_we = addr_hit[211] & reg_we & !reg_error;
+ assign classb_regwen_we = addr_hit[215] & reg_we & !reg_error;
assign classb_regwen_wd = reg_wdata[0];
- assign classb_ctrl_en_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_en_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_en_wd = reg_wdata[0];
- assign classb_ctrl_lock_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_lock_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_lock_wd = reg_wdata[1];
- assign classb_ctrl_en_e0_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_en_e0_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_en_e0_wd = reg_wdata[2];
- assign classb_ctrl_en_e1_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_en_e1_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_en_e1_wd = reg_wdata[3];
- assign classb_ctrl_en_e2_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_en_e2_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_en_e2_wd = reg_wdata[4];
- assign classb_ctrl_en_e3_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_en_e3_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_en_e3_wd = reg_wdata[5];
- assign classb_ctrl_map_e0_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_map_e0_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classb_ctrl_map_e1_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_map_e1_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classb_ctrl_map_e2_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_map_e2_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classb_ctrl_map_e3_we = addr_hit[212] & reg_we & !reg_error;
+ assign classb_ctrl_map_e3_we = addr_hit[216] & reg_we & !reg_error;
assign classb_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classb_clr_regwen_we = addr_hit[213] & reg_we & !reg_error;
+ assign classb_clr_regwen_we = addr_hit[217] & reg_we & !reg_error;
assign classb_clr_regwen_wd = reg_wdata[0];
- assign classb_clr_we = addr_hit[214] & reg_we & !reg_error;
+ assign classb_clr_we = addr_hit[218] & reg_we & !reg_error;
assign classb_clr_wd = reg_wdata[0];
- assign classb_accum_cnt_re = addr_hit[215] & reg_re & !reg_error;
+ assign classb_accum_cnt_re = addr_hit[219] & reg_re & !reg_error;
- assign classb_accum_thresh_we = addr_hit[216] & reg_we & !reg_error;
+ assign classb_accum_thresh_we = addr_hit[220] & reg_we & !reg_error;
assign classb_accum_thresh_wd = reg_wdata[15:0];
- assign classb_timeout_cyc_we = addr_hit[217] & reg_we & !reg_error;
+ assign classb_timeout_cyc_we = addr_hit[221] & reg_we & !reg_error;
assign classb_timeout_cyc_wd = reg_wdata[31:0];
- assign classb_phase0_cyc_we = addr_hit[218] & reg_we & !reg_error;
+ assign classb_phase0_cyc_we = addr_hit[222] & reg_we & !reg_error;
assign classb_phase0_cyc_wd = reg_wdata[31:0];
- assign classb_phase1_cyc_we = addr_hit[219] & reg_we & !reg_error;
+ assign classb_phase1_cyc_we = addr_hit[223] & reg_we & !reg_error;
assign classb_phase1_cyc_wd = reg_wdata[31:0];
- assign classb_phase2_cyc_we = addr_hit[220] & reg_we & !reg_error;
+ assign classb_phase2_cyc_we = addr_hit[224] & reg_we & !reg_error;
assign classb_phase2_cyc_wd = reg_wdata[31:0];
- assign classb_phase3_cyc_we = addr_hit[221] & reg_we & !reg_error;
+ assign classb_phase3_cyc_we = addr_hit[225] & reg_we & !reg_error;
assign classb_phase3_cyc_wd = reg_wdata[31:0];
- assign classb_esc_cnt_re = addr_hit[222] & reg_re & !reg_error;
+ assign classb_esc_cnt_re = addr_hit[226] & reg_re & !reg_error;
- assign classb_state_re = addr_hit[223] & reg_re & !reg_error;
+ assign classb_state_re = addr_hit[227] & reg_re & !reg_error;
- assign classc_regwen_we = addr_hit[224] & reg_we & !reg_error;
+ assign classc_regwen_we = addr_hit[228] & reg_we & !reg_error;
assign classc_regwen_wd = reg_wdata[0];
- assign classc_ctrl_en_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_en_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_en_wd = reg_wdata[0];
- assign classc_ctrl_lock_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_lock_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_lock_wd = reg_wdata[1];
- assign classc_ctrl_en_e0_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_en_e0_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_en_e0_wd = reg_wdata[2];
- assign classc_ctrl_en_e1_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_en_e1_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_en_e1_wd = reg_wdata[3];
- assign classc_ctrl_en_e2_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_en_e2_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_en_e2_wd = reg_wdata[4];
- assign classc_ctrl_en_e3_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_en_e3_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_en_e3_wd = reg_wdata[5];
- assign classc_ctrl_map_e0_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_map_e0_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classc_ctrl_map_e1_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_map_e1_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classc_ctrl_map_e2_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_map_e2_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classc_ctrl_map_e3_we = addr_hit[225] & reg_we & !reg_error;
+ assign classc_ctrl_map_e3_we = addr_hit[229] & reg_we & !reg_error;
assign classc_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classc_clr_regwen_we = addr_hit[226] & reg_we & !reg_error;
+ assign classc_clr_regwen_we = addr_hit[230] & reg_we & !reg_error;
assign classc_clr_regwen_wd = reg_wdata[0];
- assign classc_clr_we = addr_hit[227] & reg_we & !reg_error;
+ assign classc_clr_we = addr_hit[231] & reg_we & !reg_error;
assign classc_clr_wd = reg_wdata[0];
- assign classc_accum_cnt_re = addr_hit[228] & reg_re & !reg_error;
+ assign classc_accum_cnt_re = addr_hit[232] & reg_re & !reg_error;
- assign classc_accum_thresh_we = addr_hit[229] & reg_we & !reg_error;
+ assign classc_accum_thresh_we = addr_hit[233] & reg_we & !reg_error;
assign classc_accum_thresh_wd = reg_wdata[15:0];
- assign classc_timeout_cyc_we = addr_hit[230] & reg_we & !reg_error;
+ assign classc_timeout_cyc_we = addr_hit[234] & reg_we & !reg_error;
assign classc_timeout_cyc_wd = reg_wdata[31:0];
- assign classc_phase0_cyc_we = addr_hit[231] & reg_we & !reg_error;
+ assign classc_phase0_cyc_we = addr_hit[235] & reg_we & !reg_error;
assign classc_phase0_cyc_wd = reg_wdata[31:0];
- assign classc_phase1_cyc_we = addr_hit[232] & reg_we & !reg_error;
+ assign classc_phase1_cyc_we = addr_hit[236] & reg_we & !reg_error;
assign classc_phase1_cyc_wd = reg_wdata[31:0];
- assign classc_phase2_cyc_we = addr_hit[233] & reg_we & !reg_error;
+ assign classc_phase2_cyc_we = addr_hit[237] & reg_we & !reg_error;
assign classc_phase2_cyc_wd = reg_wdata[31:0];
- assign classc_phase3_cyc_we = addr_hit[234] & reg_we & !reg_error;
+ assign classc_phase3_cyc_we = addr_hit[238] & reg_we & !reg_error;
assign classc_phase3_cyc_wd = reg_wdata[31:0];
- assign classc_esc_cnt_re = addr_hit[235] & reg_re & !reg_error;
+ assign classc_esc_cnt_re = addr_hit[239] & reg_re & !reg_error;
- assign classc_state_re = addr_hit[236] & reg_re & !reg_error;
+ assign classc_state_re = addr_hit[240] & reg_re & !reg_error;
- assign classd_regwen_we = addr_hit[237] & reg_we & !reg_error;
+ assign classd_regwen_we = addr_hit[241] & reg_we & !reg_error;
assign classd_regwen_wd = reg_wdata[0];
- assign classd_ctrl_en_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_en_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_en_wd = reg_wdata[0];
- assign classd_ctrl_lock_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_lock_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_lock_wd = reg_wdata[1];
- assign classd_ctrl_en_e0_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_en_e0_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_en_e0_wd = reg_wdata[2];
- assign classd_ctrl_en_e1_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_en_e1_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_en_e1_wd = reg_wdata[3];
- assign classd_ctrl_en_e2_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_en_e2_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_en_e2_wd = reg_wdata[4];
- assign classd_ctrl_en_e3_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_en_e3_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_en_e3_wd = reg_wdata[5];
- assign classd_ctrl_map_e0_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_map_e0_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classd_ctrl_map_e1_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_map_e1_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classd_ctrl_map_e2_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_map_e2_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classd_ctrl_map_e3_we = addr_hit[238] & reg_we & !reg_error;
+ assign classd_ctrl_map_e3_we = addr_hit[242] & reg_we & !reg_error;
assign classd_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classd_clr_regwen_we = addr_hit[239] & reg_we & !reg_error;
+ assign classd_clr_regwen_we = addr_hit[243] & reg_we & !reg_error;
assign classd_clr_regwen_wd = reg_wdata[0];
- assign classd_clr_we = addr_hit[240] & reg_we & !reg_error;
+ assign classd_clr_we = addr_hit[244] & reg_we & !reg_error;
assign classd_clr_wd = reg_wdata[0];
- assign classd_accum_cnt_re = addr_hit[241] & reg_re & !reg_error;
+ assign classd_accum_cnt_re = addr_hit[245] & reg_re & !reg_error;
- assign classd_accum_thresh_we = addr_hit[242] & reg_we & !reg_error;
+ assign classd_accum_thresh_we = addr_hit[246] & reg_we & !reg_error;
assign classd_accum_thresh_wd = reg_wdata[15:0];
- assign classd_timeout_cyc_we = addr_hit[243] & reg_we & !reg_error;
+ assign classd_timeout_cyc_we = addr_hit[247] & reg_we & !reg_error;
assign classd_timeout_cyc_wd = reg_wdata[31:0];
- assign classd_phase0_cyc_we = addr_hit[244] & reg_we & !reg_error;
+ assign classd_phase0_cyc_we = addr_hit[248] & reg_we & !reg_error;
assign classd_phase0_cyc_wd = reg_wdata[31:0];
- assign classd_phase1_cyc_we = addr_hit[245] & reg_we & !reg_error;
+ assign classd_phase1_cyc_we = addr_hit[249] & reg_we & !reg_error;
assign classd_phase1_cyc_wd = reg_wdata[31:0];
- assign classd_phase2_cyc_we = addr_hit[246] & reg_we & !reg_error;
+ assign classd_phase2_cyc_we = addr_hit[250] & reg_we & !reg_error;
assign classd_phase2_cyc_wd = reg_wdata[31:0];
- assign classd_phase3_cyc_we = addr_hit[247] & reg_we & !reg_error;
+ assign classd_phase3_cyc_we = addr_hit[251] & reg_we & !reg_error;
assign classd_phase3_cyc_wd = reg_wdata[31:0];
- assign classd_esc_cnt_re = addr_hit[248] & reg_re & !reg_error;
+ assign classd_esc_cnt_re = addr_hit[252] & reg_re & !reg_error;
- assign classd_state_re = addr_hit[249] & reg_re & !reg_error;
+ assign classd_state_re = addr_hit[253] & reg_re & !reg_error;
// Read data return
always_comb begin
@@ -10335,606 +10475,622 @@
end
addr_hit[49]: begin
- reg_rdata_next[0] = alert_en_0_qs;
+ reg_rdata_next[0] = alert_regwen_43_qs;
end
addr_hit[50]: begin
- reg_rdata_next[0] = alert_en_1_qs;
+ reg_rdata_next[0] = alert_en_0_qs;
end
addr_hit[51]: begin
- reg_rdata_next[0] = alert_en_2_qs;
+ reg_rdata_next[0] = alert_en_1_qs;
end
addr_hit[52]: begin
- reg_rdata_next[0] = alert_en_3_qs;
+ reg_rdata_next[0] = alert_en_2_qs;
end
addr_hit[53]: begin
- reg_rdata_next[0] = alert_en_4_qs;
+ reg_rdata_next[0] = alert_en_3_qs;
end
addr_hit[54]: begin
- reg_rdata_next[0] = alert_en_5_qs;
+ reg_rdata_next[0] = alert_en_4_qs;
end
addr_hit[55]: begin
- reg_rdata_next[0] = alert_en_6_qs;
+ reg_rdata_next[0] = alert_en_5_qs;
end
addr_hit[56]: begin
- reg_rdata_next[0] = alert_en_7_qs;
+ reg_rdata_next[0] = alert_en_6_qs;
end
addr_hit[57]: begin
- reg_rdata_next[0] = alert_en_8_qs;
+ reg_rdata_next[0] = alert_en_7_qs;
end
addr_hit[58]: begin
- reg_rdata_next[0] = alert_en_9_qs;
+ reg_rdata_next[0] = alert_en_8_qs;
end
addr_hit[59]: begin
- reg_rdata_next[0] = alert_en_10_qs;
+ reg_rdata_next[0] = alert_en_9_qs;
end
addr_hit[60]: begin
- reg_rdata_next[0] = alert_en_11_qs;
+ reg_rdata_next[0] = alert_en_10_qs;
end
addr_hit[61]: begin
- reg_rdata_next[0] = alert_en_12_qs;
+ reg_rdata_next[0] = alert_en_11_qs;
end
addr_hit[62]: begin
- reg_rdata_next[0] = alert_en_13_qs;
+ reg_rdata_next[0] = alert_en_12_qs;
end
addr_hit[63]: begin
- reg_rdata_next[0] = alert_en_14_qs;
+ reg_rdata_next[0] = alert_en_13_qs;
end
addr_hit[64]: begin
- reg_rdata_next[0] = alert_en_15_qs;
+ reg_rdata_next[0] = alert_en_14_qs;
end
addr_hit[65]: begin
- reg_rdata_next[0] = alert_en_16_qs;
+ reg_rdata_next[0] = alert_en_15_qs;
end
addr_hit[66]: begin
- reg_rdata_next[0] = alert_en_17_qs;
+ reg_rdata_next[0] = alert_en_16_qs;
end
addr_hit[67]: begin
- reg_rdata_next[0] = alert_en_18_qs;
+ reg_rdata_next[0] = alert_en_17_qs;
end
addr_hit[68]: begin
- reg_rdata_next[0] = alert_en_19_qs;
+ reg_rdata_next[0] = alert_en_18_qs;
end
addr_hit[69]: begin
- reg_rdata_next[0] = alert_en_20_qs;
+ reg_rdata_next[0] = alert_en_19_qs;
end
addr_hit[70]: begin
- reg_rdata_next[0] = alert_en_21_qs;
+ reg_rdata_next[0] = alert_en_20_qs;
end
addr_hit[71]: begin
- reg_rdata_next[0] = alert_en_22_qs;
+ reg_rdata_next[0] = alert_en_21_qs;
end
addr_hit[72]: begin
- reg_rdata_next[0] = alert_en_23_qs;
+ reg_rdata_next[0] = alert_en_22_qs;
end
addr_hit[73]: begin
- reg_rdata_next[0] = alert_en_24_qs;
+ reg_rdata_next[0] = alert_en_23_qs;
end
addr_hit[74]: begin
- reg_rdata_next[0] = alert_en_25_qs;
+ reg_rdata_next[0] = alert_en_24_qs;
end
addr_hit[75]: begin
- reg_rdata_next[0] = alert_en_26_qs;
+ reg_rdata_next[0] = alert_en_25_qs;
end
addr_hit[76]: begin
- reg_rdata_next[0] = alert_en_27_qs;
+ reg_rdata_next[0] = alert_en_26_qs;
end
addr_hit[77]: begin
- reg_rdata_next[0] = alert_en_28_qs;
+ reg_rdata_next[0] = alert_en_27_qs;
end
addr_hit[78]: begin
- reg_rdata_next[0] = alert_en_29_qs;
+ reg_rdata_next[0] = alert_en_28_qs;
end
addr_hit[79]: begin
- reg_rdata_next[0] = alert_en_30_qs;
+ reg_rdata_next[0] = alert_en_29_qs;
end
addr_hit[80]: begin
- reg_rdata_next[0] = alert_en_31_qs;
+ reg_rdata_next[0] = alert_en_30_qs;
end
addr_hit[81]: begin
- reg_rdata_next[0] = alert_en_32_qs;
+ reg_rdata_next[0] = alert_en_31_qs;
end
addr_hit[82]: begin
- reg_rdata_next[0] = alert_en_33_qs;
+ reg_rdata_next[0] = alert_en_32_qs;
end
addr_hit[83]: begin
- reg_rdata_next[0] = alert_en_34_qs;
+ reg_rdata_next[0] = alert_en_33_qs;
end
addr_hit[84]: begin
- reg_rdata_next[0] = alert_en_35_qs;
+ reg_rdata_next[0] = alert_en_34_qs;
end
addr_hit[85]: begin
- reg_rdata_next[0] = alert_en_36_qs;
+ reg_rdata_next[0] = alert_en_35_qs;
end
addr_hit[86]: begin
- reg_rdata_next[0] = alert_en_37_qs;
+ reg_rdata_next[0] = alert_en_36_qs;
end
addr_hit[87]: begin
- reg_rdata_next[0] = alert_en_38_qs;
+ reg_rdata_next[0] = alert_en_37_qs;
end
addr_hit[88]: begin
- reg_rdata_next[0] = alert_en_39_qs;
+ reg_rdata_next[0] = alert_en_38_qs;
end
addr_hit[89]: begin
- reg_rdata_next[0] = alert_en_40_qs;
+ reg_rdata_next[0] = alert_en_39_qs;
end
addr_hit[90]: begin
- reg_rdata_next[0] = alert_en_41_qs;
+ reg_rdata_next[0] = alert_en_40_qs;
end
addr_hit[91]: begin
- reg_rdata_next[0] = alert_en_42_qs;
+ reg_rdata_next[0] = alert_en_41_qs;
end
addr_hit[92]: begin
- reg_rdata_next[1:0] = alert_class_0_qs;
+ reg_rdata_next[0] = alert_en_42_qs;
end
addr_hit[93]: begin
- reg_rdata_next[1:0] = alert_class_1_qs;
+ reg_rdata_next[0] = alert_en_43_qs;
end
addr_hit[94]: begin
- reg_rdata_next[1:0] = alert_class_2_qs;
+ reg_rdata_next[1:0] = alert_class_0_qs;
end
addr_hit[95]: begin
- reg_rdata_next[1:0] = alert_class_3_qs;
+ reg_rdata_next[1:0] = alert_class_1_qs;
end
addr_hit[96]: begin
- reg_rdata_next[1:0] = alert_class_4_qs;
+ reg_rdata_next[1:0] = alert_class_2_qs;
end
addr_hit[97]: begin
- reg_rdata_next[1:0] = alert_class_5_qs;
+ reg_rdata_next[1:0] = alert_class_3_qs;
end
addr_hit[98]: begin
- reg_rdata_next[1:0] = alert_class_6_qs;
+ reg_rdata_next[1:0] = alert_class_4_qs;
end
addr_hit[99]: begin
- reg_rdata_next[1:0] = alert_class_7_qs;
+ reg_rdata_next[1:0] = alert_class_5_qs;
end
addr_hit[100]: begin
- reg_rdata_next[1:0] = alert_class_8_qs;
+ reg_rdata_next[1:0] = alert_class_6_qs;
end
addr_hit[101]: begin
- reg_rdata_next[1:0] = alert_class_9_qs;
+ reg_rdata_next[1:0] = alert_class_7_qs;
end
addr_hit[102]: begin
- reg_rdata_next[1:0] = alert_class_10_qs;
+ reg_rdata_next[1:0] = alert_class_8_qs;
end
addr_hit[103]: begin
- reg_rdata_next[1:0] = alert_class_11_qs;
+ reg_rdata_next[1:0] = alert_class_9_qs;
end
addr_hit[104]: begin
- reg_rdata_next[1:0] = alert_class_12_qs;
+ reg_rdata_next[1:0] = alert_class_10_qs;
end
addr_hit[105]: begin
- reg_rdata_next[1:0] = alert_class_13_qs;
+ reg_rdata_next[1:0] = alert_class_11_qs;
end
addr_hit[106]: begin
- reg_rdata_next[1:0] = alert_class_14_qs;
+ reg_rdata_next[1:0] = alert_class_12_qs;
end
addr_hit[107]: begin
- reg_rdata_next[1:0] = alert_class_15_qs;
+ reg_rdata_next[1:0] = alert_class_13_qs;
end
addr_hit[108]: begin
- reg_rdata_next[1:0] = alert_class_16_qs;
+ reg_rdata_next[1:0] = alert_class_14_qs;
end
addr_hit[109]: begin
- reg_rdata_next[1:0] = alert_class_17_qs;
+ reg_rdata_next[1:0] = alert_class_15_qs;
end
addr_hit[110]: begin
- reg_rdata_next[1:0] = alert_class_18_qs;
+ reg_rdata_next[1:0] = alert_class_16_qs;
end
addr_hit[111]: begin
- reg_rdata_next[1:0] = alert_class_19_qs;
+ reg_rdata_next[1:0] = alert_class_17_qs;
end
addr_hit[112]: begin
- reg_rdata_next[1:0] = alert_class_20_qs;
+ reg_rdata_next[1:0] = alert_class_18_qs;
end
addr_hit[113]: begin
- reg_rdata_next[1:0] = alert_class_21_qs;
+ reg_rdata_next[1:0] = alert_class_19_qs;
end
addr_hit[114]: begin
- reg_rdata_next[1:0] = alert_class_22_qs;
+ reg_rdata_next[1:0] = alert_class_20_qs;
end
addr_hit[115]: begin
- reg_rdata_next[1:0] = alert_class_23_qs;
+ reg_rdata_next[1:0] = alert_class_21_qs;
end
addr_hit[116]: begin
- reg_rdata_next[1:0] = alert_class_24_qs;
+ reg_rdata_next[1:0] = alert_class_22_qs;
end
addr_hit[117]: begin
- reg_rdata_next[1:0] = alert_class_25_qs;
+ reg_rdata_next[1:0] = alert_class_23_qs;
end
addr_hit[118]: begin
- reg_rdata_next[1:0] = alert_class_26_qs;
+ reg_rdata_next[1:0] = alert_class_24_qs;
end
addr_hit[119]: begin
- reg_rdata_next[1:0] = alert_class_27_qs;
+ reg_rdata_next[1:0] = alert_class_25_qs;
end
addr_hit[120]: begin
- reg_rdata_next[1:0] = alert_class_28_qs;
+ reg_rdata_next[1:0] = alert_class_26_qs;
end
addr_hit[121]: begin
- reg_rdata_next[1:0] = alert_class_29_qs;
+ reg_rdata_next[1:0] = alert_class_27_qs;
end
addr_hit[122]: begin
- reg_rdata_next[1:0] = alert_class_30_qs;
+ reg_rdata_next[1:0] = alert_class_28_qs;
end
addr_hit[123]: begin
- reg_rdata_next[1:0] = alert_class_31_qs;
+ reg_rdata_next[1:0] = alert_class_29_qs;
end
addr_hit[124]: begin
- reg_rdata_next[1:0] = alert_class_32_qs;
+ reg_rdata_next[1:0] = alert_class_30_qs;
end
addr_hit[125]: begin
- reg_rdata_next[1:0] = alert_class_33_qs;
+ reg_rdata_next[1:0] = alert_class_31_qs;
end
addr_hit[126]: begin
- reg_rdata_next[1:0] = alert_class_34_qs;
+ reg_rdata_next[1:0] = alert_class_32_qs;
end
addr_hit[127]: begin
- reg_rdata_next[1:0] = alert_class_35_qs;
+ reg_rdata_next[1:0] = alert_class_33_qs;
end
addr_hit[128]: begin
- reg_rdata_next[1:0] = alert_class_36_qs;
+ reg_rdata_next[1:0] = alert_class_34_qs;
end
addr_hit[129]: begin
- reg_rdata_next[1:0] = alert_class_37_qs;
+ reg_rdata_next[1:0] = alert_class_35_qs;
end
addr_hit[130]: begin
- reg_rdata_next[1:0] = alert_class_38_qs;
+ reg_rdata_next[1:0] = alert_class_36_qs;
end
addr_hit[131]: begin
- reg_rdata_next[1:0] = alert_class_39_qs;
+ reg_rdata_next[1:0] = alert_class_37_qs;
end
addr_hit[132]: begin
- reg_rdata_next[1:0] = alert_class_40_qs;
+ reg_rdata_next[1:0] = alert_class_38_qs;
end
addr_hit[133]: begin
- reg_rdata_next[1:0] = alert_class_41_qs;
+ reg_rdata_next[1:0] = alert_class_39_qs;
end
addr_hit[134]: begin
- reg_rdata_next[1:0] = alert_class_42_qs;
+ reg_rdata_next[1:0] = alert_class_40_qs;
end
addr_hit[135]: begin
- reg_rdata_next[0] = alert_cause_0_qs;
+ reg_rdata_next[1:0] = alert_class_41_qs;
end
addr_hit[136]: begin
- reg_rdata_next[0] = alert_cause_1_qs;
+ reg_rdata_next[1:0] = alert_class_42_qs;
end
addr_hit[137]: begin
- reg_rdata_next[0] = alert_cause_2_qs;
+ reg_rdata_next[1:0] = alert_class_43_qs;
end
addr_hit[138]: begin
- reg_rdata_next[0] = alert_cause_3_qs;
+ reg_rdata_next[0] = alert_cause_0_qs;
end
addr_hit[139]: begin
- reg_rdata_next[0] = alert_cause_4_qs;
+ reg_rdata_next[0] = alert_cause_1_qs;
end
addr_hit[140]: begin
- reg_rdata_next[0] = alert_cause_5_qs;
+ reg_rdata_next[0] = alert_cause_2_qs;
end
addr_hit[141]: begin
- reg_rdata_next[0] = alert_cause_6_qs;
+ reg_rdata_next[0] = alert_cause_3_qs;
end
addr_hit[142]: begin
- reg_rdata_next[0] = alert_cause_7_qs;
+ reg_rdata_next[0] = alert_cause_4_qs;
end
addr_hit[143]: begin
- reg_rdata_next[0] = alert_cause_8_qs;
+ reg_rdata_next[0] = alert_cause_5_qs;
end
addr_hit[144]: begin
- reg_rdata_next[0] = alert_cause_9_qs;
+ reg_rdata_next[0] = alert_cause_6_qs;
end
addr_hit[145]: begin
- reg_rdata_next[0] = alert_cause_10_qs;
+ reg_rdata_next[0] = alert_cause_7_qs;
end
addr_hit[146]: begin
- reg_rdata_next[0] = alert_cause_11_qs;
+ reg_rdata_next[0] = alert_cause_8_qs;
end
addr_hit[147]: begin
- reg_rdata_next[0] = alert_cause_12_qs;
+ reg_rdata_next[0] = alert_cause_9_qs;
end
addr_hit[148]: begin
- reg_rdata_next[0] = alert_cause_13_qs;
+ reg_rdata_next[0] = alert_cause_10_qs;
end
addr_hit[149]: begin
- reg_rdata_next[0] = alert_cause_14_qs;
+ reg_rdata_next[0] = alert_cause_11_qs;
end
addr_hit[150]: begin
- reg_rdata_next[0] = alert_cause_15_qs;
+ reg_rdata_next[0] = alert_cause_12_qs;
end
addr_hit[151]: begin
- reg_rdata_next[0] = alert_cause_16_qs;
+ reg_rdata_next[0] = alert_cause_13_qs;
end
addr_hit[152]: begin
- reg_rdata_next[0] = alert_cause_17_qs;
+ reg_rdata_next[0] = alert_cause_14_qs;
end
addr_hit[153]: begin
- reg_rdata_next[0] = alert_cause_18_qs;
+ reg_rdata_next[0] = alert_cause_15_qs;
end
addr_hit[154]: begin
- reg_rdata_next[0] = alert_cause_19_qs;
+ reg_rdata_next[0] = alert_cause_16_qs;
end
addr_hit[155]: begin
- reg_rdata_next[0] = alert_cause_20_qs;
+ reg_rdata_next[0] = alert_cause_17_qs;
end
addr_hit[156]: begin
- reg_rdata_next[0] = alert_cause_21_qs;
+ reg_rdata_next[0] = alert_cause_18_qs;
end
addr_hit[157]: begin
- reg_rdata_next[0] = alert_cause_22_qs;
+ reg_rdata_next[0] = alert_cause_19_qs;
end
addr_hit[158]: begin
- reg_rdata_next[0] = alert_cause_23_qs;
+ reg_rdata_next[0] = alert_cause_20_qs;
end
addr_hit[159]: begin
- reg_rdata_next[0] = alert_cause_24_qs;
+ reg_rdata_next[0] = alert_cause_21_qs;
end
addr_hit[160]: begin
- reg_rdata_next[0] = alert_cause_25_qs;
+ reg_rdata_next[0] = alert_cause_22_qs;
end
addr_hit[161]: begin
- reg_rdata_next[0] = alert_cause_26_qs;
+ reg_rdata_next[0] = alert_cause_23_qs;
end
addr_hit[162]: begin
- reg_rdata_next[0] = alert_cause_27_qs;
+ reg_rdata_next[0] = alert_cause_24_qs;
end
addr_hit[163]: begin
- reg_rdata_next[0] = alert_cause_28_qs;
+ reg_rdata_next[0] = alert_cause_25_qs;
end
addr_hit[164]: begin
- reg_rdata_next[0] = alert_cause_29_qs;
+ reg_rdata_next[0] = alert_cause_26_qs;
end
addr_hit[165]: begin
- reg_rdata_next[0] = alert_cause_30_qs;
+ reg_rdata_next[0] = alert_cause_27_qs;
end
addr_hit[166]: begin
- reg_rdata_next[0] = alert_cause_31_qs;
+ reg_rdata_next[0] = alert_cause_28_qs;
end
addr_hit[167]: begin
- reg_rdata_next[0] = alert_cause_32_qs;
+ reg_rdata_next[0] = alert_cause_29_qs;
end
addr_hit[168]: begin
- reg_rdata_next[0] = alert_cause_33_qs;
+ reg_rdata_next[0] = alert_cause_30_qs;
end
addr_hit[169]: begin
- reg_rdata_next[0] = alert_cause_34_qs;
+ reg_rdata_next[0] = alert_cause_31_qs;
end
addr_hit[170]: begin
- reg_rdata_next[0] = alert_cause_35_qs;
+ reg_rdata_next[0] = alert_cause_32_qs;
end
addr_hit[171]: begin
- reg_rdata_next[0] = alert_cause_36_qs;
+ reg_rdata_next[0] = alert_cause_33_qs;
end
addr_hit[172]: begin
- reg_rdata_next[0] = alert_cause_37_qs;
+ reg_rdata_next[0] = alert_cause_34_qs;
end
addr_hit[173]: begin
- reg_rdata_next[0] = alert_cause_38_qs;
+ reg_rdata_next[0] = alert_cause_35_qs;
end
addr_hit[174]: begin
- reg_rdata_next[0] = alert_cause_39_qs;
+ reg_rdata_next[0] = alert_cause_36_qs;
end
addr_hit[175]: begin
- reg_rdata_next[0] = alert_cause_40_qs;
+ reg_rdata_next[0] = alert_cause_37_qs;
end
addr_hit[176]: begin
- reg_rdata_next[0] = alert_cause_41_qs;
+ reg_rdata_next[0] = alert_cause_38_qs;
end
addr_hit[177]: begin
- reg_rdata_next[0] = alert_cause_42_qs;
+ reg_rdata_next[0] = alert_cause_39_qs;
end
addr_hit[178]: begin
- reg_rdata_next[0] = loc_alert_regwen_0_qs;
+ reg_rdata_next[0] = alert_cause_40_qs;
end
addr_hit[179]: begin
- reg_rdata_next[0] = loc_alert_regwen_1_qs;
+ reg_rdata_next[0] = alert_cause_41_qs;
end
addr_hit[180]: begin
- reg_rdata_next[0] = loc_alert_regwen_2_qs;
+ reg_rdata_next[0] = alert_cause_42_qs;
end
addr_hit[181]: begin
- reg_rdata_next[0] = loc_alert_regwen_3_qs;
+ reg_rdata_next[0] = alert_cause_43_qs;
end
addr_hit[182]: begin
- reg_rdata_next[0] = loc_alert_regwen_4_qs;
+ reg_rdata_next[0] = loc_alert_regwen_0_qs;
end
addr_hit[183]: begin
- reg_rdata_next[0] = loc_alert_en_0_qs;
+ reg_rdata_next[0] = loc_alert_regwen_1_qs;
end
addr_hit[184]: begin
- reg_rdata_next[0] = loc_alert_en_1_qs;
+ reg_rdata_next[0] = loc_alert_regwen_2_qs;
end
addr_hit[185]: begin
- reg_rdata_next[0] = loc_alert_en_2_qs;
+ reg_rdata_next[0] = loc_alert_regwen_3_qs;
end
addr_hit[186]: begin
- reg_rdata_next[0] = loc_alert_en_3_qs;
+ reg_rdata_next[0] = loc_alert_regwen_4_qs;
end
addr_hit[187]: begin
- reg_rdata_next[0] = loc_alert_en_4_qs;
+ reg_rdata_next[0] = loc_alert_en_0_qs;
end
addr_hit[188]: begin
- reg_rdata_next[1:0] = loc_alert_class_0_qs;
+ reg_rdata_next[0] = loc_alert_en_1_qs;
end
addr_hit[189]: begin
- reg_rdata_next[1:0] = loc_alert_class_1_qs;
+ reg_rdata_next[0] = loc_alert_en_2_qs;
end
addr_hit[190]: begin
- reg_rdata_next[1:0] = loc_alert_class_2_qs;
+ reg_rdata_next[0] = loc_alert_en_3_qs;
end
addr_hit[191]: begin
- reg_rdata_next[1:0] = loc_alert_class_3_qs;
+ reg_rdata_next[0] = loc_alert_en_4_qs;
end
addr_hit[192]: begin
- reg_rdata_next[1:0] = loc_alert_class_4_qs;
+ reg_rdata_next[1:0] = loc_alert_class_0_qs;
end
addr_hit[193]: begin
- reg_rdata_next[0] = loc_alert_cause_0_qs;
+ reg_rdata_next[1:0] = loc_alert_class_1_qs;
end
addr_hit[194]: begin
- reg_rdata_next[0] = loc_alert_cause_1_qs;
+ reg_rdata_next[1:0] = loc_alert_class_2_qs;
end
addr_hit[195]: begin
- reg_rdata_next[0] = loc_alert_cause_2_qs;
+ reg_rdata_next[1:0] = loc_alert_class_3_qs;
end
addr_hit[196]: begin
- reg_rdata_next[0] = loc_alert_cause_3_qs;
+ reg_rdata_next[1:0] = loc_alert_class_4_qs;
end
addr_hit[197]: begin
- reg_rdata_next[0] = loc_alert_cause_4_qs;
+ reg_rdata_next[0] = loc_alert_cause_0_qs;
end
addr_hit[198]: begin
- reg_rdata_next[0] = classa_regwen_qs;
+ reg_rdata_next[0] = loc_alert_cause_1_qs;
end
addr_hit[199]: begin
+ reg_rdata_next[0] = loc_alert_cause_2_qs;
+ end
+
+ addr_hit[200]: begin
+ reg_rdata_next[0] = loc_alert_cause_3_qs;
+ end
+
+ addr_hit[201]: begin
+ reg_rdata_next[0] = loc_alert_cause_4_qs;
+ end
+
+ addr_hit[202]: begin
+ reg_rdata_next[0] = classa_regwen_qs;
+ end
+
+ addr_hit[203]: begin
reg_rdata_next[0] = classa_ctrl_en_qs;
reg_rdata_next[1] = classa_ctrl_lock_qs;
reg_rdata_next[2] = classa_ctrl_en_e0_qs;
@@ -10947,55 +11103,55 @@
reg_rdata_next[13:12] = classa_ctrl_map_e3_qs;
end
- addr_hit[200]: begin
+ addr_hit[204]: begin
reg_rdata_next[0] = classa_clr_regwen_qs;
end
- addr_hit[201]: begin
+ addr_hit[205]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[202]: begin
+ addr_hit[206]: begin
reg_rdata_next[15:0] = classa_accum_cnt_qs;
end
- addr_hit[203]: begin
+ addr_hit[207]: begin
reg_rdata_next[15:0] = classa_accum_thresh_qs;
end
- addr_hit[204]: begin
+ addr_hit[208]: begin
reg_rdata_next[31:0] = classa_timeout_cyc_qs;
end
- addr_hit[205]: begin
+ addr_hit[209]: begin
reg_rdata_next[31:0] = classa_phase0_cyc_qs;
end
- addr_hit[206]: begin
+ addr_hit[210]: begin
reg_rdata_next[31:0] = classa_phase1_cyc_qs;
end
- addr_hit[207]: begin
+ addr_hit[211]: begin
reg_rdata_next[31:0] = classa_phase2_cyc_qs;
end
- addr_hit[208]: begin
+ addr_hit[212]: begin
reg_rdata_next[31:0] = classa_phase3_cyc_qs;
end
- addr_hit[209]: begin
+ addr_hit[213]: begin
reg_rdata_next[31:0] = classa_esc_cnt_qs;
end
- addr_hit[210]: begin
+ addr_hit[214]: begin
reg_rdata_next[2:0] = classa_state_qs;
end
- addr_hit[211]: begin
+ addr_hit[215]: begin
reg_rdata_next[0] = classb_regwen_qs;
end
- addr_hit[212]: begin
+ addr_hit[216]: begin
reg_rdata_next[0] = classb_ctrl_en_qs;
reg_rdata_next[1] = classb_ctrl_lock_qs;
reg_rdata_next[2] = classb_ctrl_en_e0_qs;
@@ -11008,55 +11164,55 @@
reg_rdata_next[13:12] = classb_ctrl_map_e3_qs;
end
- addr_hit[213]: begin
+ addr_hit[217]: begin
reg_rdata_next[0] = classb_clr_regwen_qs;
end
- addr_hit[214]: begin
+ addr_hit[218]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[215]: begin
+ addr_hit[219]: begin
reg_rdata_next[15:0] = classb_accum_cnt_qs;
end
- addr_hit[216]: begin
+ addr_hit[220]: begin
reg_rdata_next[15:0] = classb_accum_thresh_qs;
end
- addr_hit[217]: begin
+ addr_hit[221]: begin
reg_rdata_next[31:0] = classb_timeout_cyc_qs;
end
- addr_hit[218]: begin
+ addr_hit[222]: begin
reg_rdata_next[31:0] = classb_phase0_cyc_qs;
end
- addr_hit[219]: begin
+ addr_hit[223]: begin
reg_rdata_next[31:0] = classb_phase1_cyc_qs;
end
- addr_hit[220]: begin
+ addr_hit[224]: begin
reg_rdata_next[31:0] = classb_phase2_cyc_qs;
end
- addr_hit[221]: begin
+ addr_hit[225]: begin
reg_rdata_next[31:0] = classb_phase3_cyc_qs;
end
- addr_hit[222]: begin
+ addr_hit[226]: begin
reg_rdata_next[31:0] = classb_esc_cnt_qs;
end
- addr_hit[223]: begin
+ addr_hit[227]: begin
reg_rdata_next[2:0] = classb_state_qs;
end
- addr_hit[224]: begin
+ addr_hit[228]: begin
reg_rdata_next[0] = classc_regwen_qs;
end
- addr_hit[225]: begin
+ addr_hit[229]: begin
reg_rdata_next[0] = classc_ctrl_en_qs;
reg_rdata_next[1] = classc_ctrl_lock_qs;
reg_rdata_next[2] = classc_ctrl_en_e0_qs;
@@ -11069,55 +11225,55 @@
reg_rdata_next[13:12] = classc_ctrl_map_e3_qs;
end
- addr_hit[226]: begin
+ addr_hit[230]: begin
reg_rdata_next[0] = classc_clr_regwen_qs;
end
- addr_hit[227]: begin
+ addr_hit[231]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[228]: begin
+ addr_hit[232]: begin
reg_rdata_next[15:0] = classc_accum_cnt_qs;
end
- addr_hit[229]: begin
+ addr_hit[233]: begin
reg_rdata_next[15:0] = classc_accum_thresh_qs;
end
- addr_hit[230]: begin
+ addr_hit[234]: begin
reg_rdata_next[31:0] = classc_timeout_cyc_qs;
end
- addr_hit[231]: begin
+ addr_hit[235]: begin
reg_rdata_next[31:0] = classc_phase0_cyc_qs;
end
- addr_hit[232]: begin
+ addr_hit[236]: begin
reg_rdata_next[31:0] = classc_phase1_cyc_qs;
end
- addr_hit[233]: begin
+ addr_hit[237]: begin
reg_rdata_next[31:0] = classc_phase2_cyc_qs;
end
- addr_hit[234]: begin
+ addr_hit[238]: begin
reg_rdata_next[31:0] = classc_phase3_cyc_qs;
end
- addr_hit[235]: begin
+ addr_hit[239]: begin
reg_rdata_next[31:0] = classc_esc_cnt_qs;
end
- addr_hit[236]: begin
+ addr_hit[240]: begin
reg_rdata_next[2:0] = classc_state_qs;
end
- addr_hit[237]: begin
+ addr_hit[241]: begin
reg_rdata_next[0] = classd_regwen_qs;
end
- addr_hit[238]: begin
+ addr_hit[242]: begin
reg_rdata_next[0] = classd_ctrl_en_qs;
reg_rdata_next[1] = classd_ctrl_lock_qs;
reg_rdata_next[2] = classd_ctrl_en_e0_qs;
@@ -11130,47 +11286,47 @@
reg_rdata_next[13:12] = classd_ctrl_map_e3_qs;
end
- addr_hit[239]: begin
+ addr_hit[243]: begin
reg_rdata_next[0] = classd_clr_regwen_qs;
end
- addr_hit[240]: begin
+ addr_hit[244]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[241]: begin
+ addr_hit[245]: begin
reg_rdata_next[15:0] = classd_accum_cnt_qs;
end
- addr_hit[242]: begin
+ addr_hit[246]: begin
reg_rdata_next[15:0] = classd_accum_thresh_qs;
end
- addr_hit[243]: begin
+ addr_hit[247]: begin
reg_rdata_next[31:0] = classd_timeout_cyc_qs;
end
- addr_hit[244]: begin
+ addr_hit[248]: begin
reg_rdata_next[31:0] = classd_phase0_cyc_qs;
end
- addr_hit[245]: begin
+ addr_hit[249]: begin
reg_rdata_next[31:0] = classd_phase1_cyc_qs;
end
- addr_hit[246]: begin
+ addr_hit[250]: begin
reg_rdata_next[31:0] = classd_phase2_cyc_qs;
end
- addr_hit[247]: begin
+ addr_hit[251]: begin
reg_rdata_next[31:0] = classd_phase3_cyc_qs;
end
- addr_hit[248]: begin
+ addr_hit[252]: begin
reg_rdata_next[31:0] = classd_esc_cnt_qs;
end
- addr_hit[249]: begin
+ addr_hit[253]: begin
reg_rdata_next[2:0] = classd_state_qs;
end
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
index cf72271..3856ac5 100644
--- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
+++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -27,6 +27,14 @@
regwidth: "32",
scan: "true",
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the PINMUX unit.
+ '''
+ }
+ ],
+
wakeup_list: [
{ name: "aon_wkup_req",
desc: "pin wake request"
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
index 4eb74ea..ac4b347 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -14,6 +14,7 @@
parameter int NDioPads = 24;
parameter int NWkupDetect = 8;
parameter int WkupCntWidth = 8;
+ parameter int NumAlerts = 1;
// Address widths within the block
parameter int BlockAw = 12;
@@ -23,6 +24,11 @@
////////////////////////////
typedef struct packed {
+ logic q;
+ logic qe;
+ } pinmux_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
logic [5:0] q;
} pinmux_reg2hw_mio_periph_insel_mreg_t;
@@ -117,6 +123,7 @@
// Register -> HW type
typedef struct packed {
+ pinmux_reg2hw_alert_test_reg_t alert_test; // [2114:2113]
pinmux_reg2hw_mio_periph_insel_mreg_t [54:0] mio_periph_insel; // [2112:1783]
pinmux_reg2hw_mio_outsel_mreg_t [46:0] mio_outsel; // [1782:1454]
pinmux_reg2hw_mio_pad_attr_mreg_t [46:0] mio_pad_attr; // [1453:796]
@@ -144,611 +151,614 @@
} pinmux_hw2reg_t;
// Register offsets
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET = 12'h 0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET = 12'h 4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET = 12'h 8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET = 12'h c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET = 12'h 10;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET = 12'h 14;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET = 12'h 18;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET = 12'h 1c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET = 12'h 20;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET = 12'h 24;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET = 12'h 28;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET = 12'h 2c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET = 12'h 30;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET = 12'h 34;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET = 12'h 38;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET = 12'h 3c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET = 12'h 40;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET = 12'h 44;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET = 12'h 48;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET = 12'h 4c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET = 12'h 50;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET = 12'h 54;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET = 12'h 58;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET = 12'h 5c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET = 12'h 60;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET = 12'h 64;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET = 12'h 68;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET = 12'h 6c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET = 12'h 70;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET = 12'h 74;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET = 12'h 78;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET = 12'h 7c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET = 12'h 80;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET = 12'h 84;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET = 12'h 88;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET = 12'h 8c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET = 12'h 90;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET = 12'h 94;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET = 12'h 98;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET = 12'h 9c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET = 12'h a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET = 12'h a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET = 12'h a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET = 12'h ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET = 12'h b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET = 12'h b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_46_OFFSET = 12'h b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_47_OFFSET = 12'h bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_48_OFFSET = 12'h c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_49_OFFSET = 12'h c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_50_OFFSET = 12'h c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_51_OFFSET = 12'h cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_52_OFFSET = 12'h d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_53_OFFSET = 12'h d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET = 12'h d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 100;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 104;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 108;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 10c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 110;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 114;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 118;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 11c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 120;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 124;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 128;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 12c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 130;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 134;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 138;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 13c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 140;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 144;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 148;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 14c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 150;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 154;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 158;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 15c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 160;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 164;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 168;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 16c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 170;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 174;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 178;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 17c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 180;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 184;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 188;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 18c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 190;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 194;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 198;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 19c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 1d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 1d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 1dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 1e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 1e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 1e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 1ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 1f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 1f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 1f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 1fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 200;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 204;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 208;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 20c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 210;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 214;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 218;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 21c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 220;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 224;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 228;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 22c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 230;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 234;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 238;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 23c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 240;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 244;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 248;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 24c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 250;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 254;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 258;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 25c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 260;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 264;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 268;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 26c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 270;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 274;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 278;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 27c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 280;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 284;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 288;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 28c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 290;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 294;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 298;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 29c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 2cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 2d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 2d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 2d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 2dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 2e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 2e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 2e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 2ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 2f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 2f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 2f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 2fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 300;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 304;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 308;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 30c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 310;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 314;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 318;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 31c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 320;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 324;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 328;
- parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 32c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 330;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 334;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 338;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 33c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 340;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 344;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 348;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 34c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 350;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 354;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 358;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 35c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 360;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 364;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 368;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 36c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 370;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 374;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 378;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 37c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 380;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 384;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 388;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 38c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 390;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 394;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 398;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 39c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 3d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 3d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 3d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 3dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 3e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 3e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 3e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 3ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 3f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 3f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 3f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 3fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 400;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 404;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 408;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 40c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 410;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 414;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 418;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 41c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 420;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 424;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 428;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 42c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 430;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 434;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 438;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 43c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 440;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 444;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 448;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 44c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 450;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 454;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 458;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 45c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 460;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 464;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 468;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 46c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 470;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 474;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 478;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 47c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 480;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 484;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 488;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 48c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 490;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 494;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 498;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 49c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4a4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4a8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4ac;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4b0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4b4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4b8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4bc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4c0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4c4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4c8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4cc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4d0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 4d4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 4d8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 4dc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 4e0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 4e4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 4e8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 4ec;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 4f0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 4f4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 4f8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 4fc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 500;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 504;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 508;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 50c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 510;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 514;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 518;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 51c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 520;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 524;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 528;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 52c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 530;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 534;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 538;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 53c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 540;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 544;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_16_OFFSET = 12'h 548;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_17_OFFSET = 12'h 54c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_18_OFFSET = 12'h 550;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_19_OFFSET = 12'h 554;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_20_OFFSET = 12'h 558;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_21_OFFSET = 12'h 55c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_22_OFFSET = 12'h 560;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_23_OFFSET = 12'h 564;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 568;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 56c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 570;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 574;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 578;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 57c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 580;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 584;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 588;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 58c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 590;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 594;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 598;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 59c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 5a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 5a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 5a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 5ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 5b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 5b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 5b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 5bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 5c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 5c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 5c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 5cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 5d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 5d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 5d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 5dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 5e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 5e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 5e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 5ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 5f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 5f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 5f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 5fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 600;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 604;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 608;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 60c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 610;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 614;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 618;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 61c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 620;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 624;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 628;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 62c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 630;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 634;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 638;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 63c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 640;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 644;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 648;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 64c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 650;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 654;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 658;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 65c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 660;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 664;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 668;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 66c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 670;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 674;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 678;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 67c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 680;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 684;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 688;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 68c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 690;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 694;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 698;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 69c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 6a0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 6a4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 6a8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 6ac;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 6b0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 6b4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 6b8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 6bc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 6c0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 6c4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 6c8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 6cc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 6d0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 6d4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 6d8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 6dc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 6e0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 6e4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 6e8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 6ec;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 6f0;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 6f4;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 6f8;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 6fc;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 700;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 704;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 708;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 70c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 710;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 714;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 718;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 71c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 720;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 724;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 728;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 72c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 730;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 734;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 738;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 73c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 740;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 744;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 748;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 74c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 750;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 754;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 758;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 75c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 760;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 764;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 768;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 76c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 770;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 774;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 778;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 77c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 780;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 784;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 788;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 78c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 790;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 794;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 798;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 79c;
- parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 7a0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 7a4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 7a8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 7ac;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 7b0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 7b4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 7b8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 7bc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 7c0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 7c4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 7c8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 7cc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 7d0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 7d4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 7d8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 7dc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 7e0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 7e4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 7e8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 7ec;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 7f0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 7f4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 7f8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 7fc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 800;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 804;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 808;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 80c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 810;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 814;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 818;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 81c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 820;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 824;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 828;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 82c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 830;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 834;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 838;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 83c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 840;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 844;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET = 12'h 848;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET = 12'h 84c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET = 12'h 850;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET = 12'h 854;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET = 12'h 858;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET = 12'h 85c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET = 12'h 860;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET = 12'h 864;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 868;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 86c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 870;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 874;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 878;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 87c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 880;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 884;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 888;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 88c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 890;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 894;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 898;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 89c;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 8a0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 8a4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 8a8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 8ac;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 8b0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 8b4;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 8b8;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 8bc;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 8c0;
- parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 8c4;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 8c8;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 8cc;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 8d0;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 8d4;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 8d8;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 8dc;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 8e0;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 8e4;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 8e8;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 8ec;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 8f0;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 8f4;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 8f8;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 8fc;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 900;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 904;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 908;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 90c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 910;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 914;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 918;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 91c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 920;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 924;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 928;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 92c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 930;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 934;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 938;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 93c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 940;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 944;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 948;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 94c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 950;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 954;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 958;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 95c;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 960;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 964;
- parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 968;
+ parameter logic [BlockAw-1:0] PINMUX_ALERT_TEST_OFFSET = 12'h 0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET = 12'h 4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET = 12'h 8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET = 12'h c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET = 12'h 10;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET = 12'h 14;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET = 12'h 18;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET = 12'h 1c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET = 12'h 20;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET = 12'h 24;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET = 12'h 28;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET = 12'h 2c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET = 12'h 30;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET = 12'h 34;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET = 12'h 38;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET = 12'h 3c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET = 12'h 40;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET = 12'h 44;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET = 12'h 48;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET = 12'h 4c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET = 12'h 50;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET = 12'h 54;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET = 12'h 58;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET = 12'h 5c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET = 12'h 60;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET = 12'h 64;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET = 12'h 68;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET = 12'h 6c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET = 12'h 70;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET = 12'h 74;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET = 12'h 78;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET = 12'h 7c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET = 12'h 80;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET = 12'h 84;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET = 12'h 88;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET = 12'h 8c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET = 12'h 90;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET = 12'h 94;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET = 12'h 98;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET = 12'h 9c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET = 12'h a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET = 12'h a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET = 12'h a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET = 12'h ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET = 12'h b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET = 12'h b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET = 12'h b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_46_OFFSET = 12'h bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_47_OFFSET = 12'h c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_48_OFFSET = 12'h c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_49_OFFSET = 12'h c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_50_OFFSET = 12'h cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_51_OFFSET = 12'h d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_52_OFFSET = 12'h d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_53_OFFSET = 12'h d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET = 12'h dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h 100;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h 104;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h 108;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h 10c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h 110;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h 114;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h 118;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h 11c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h 120;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h 124;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h 128;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h 12c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h 130;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h 134;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h 138;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h 13c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h 140;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 144;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 148;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 14c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 150;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 154;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 158;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 15c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 160;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 164;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 168;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 16c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 170;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 174;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 12'h 178;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 12'h 17c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 12'h 180;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 12'h 184;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 12'h 188;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 12'h 18c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 12'h 190;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 12'h 194;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_46_OFFSET = 12'h 198;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_47_OFFSET = 12'h 19c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_48_OFFSET = 12'h 1a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_49_OFFSET = 12'h 1a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_50_OFFSET = 12'h 1a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_51_OFFSET = 12'h 1ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_52_OFFSET = 12'h 1b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_53_OFFSET = 12'h 1b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_54_OFFSET = 12'h 1b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 1bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 1c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 1c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 1c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 1cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 1d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 1d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 1d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 1dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 1e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 1e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 1e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 1ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 1f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 1f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 1f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 1fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 200;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 204;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 208;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 20c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 210;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 214;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 218;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 21c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 220;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 224;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 228;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 22c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 230;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 234;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 238;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 23c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 240;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 244;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 248;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 24c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 250;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 254;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 258;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 25c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 260;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 264;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 268;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 26c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 270;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 274;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 278;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 27c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 280;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 284;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 288;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 28c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 290;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 294;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 298;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 29c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 2a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 2a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 2a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 2ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 2b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 2b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 2b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 2bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 2c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 2c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 2c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 2cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 2d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 2d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 2d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 2dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 2e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 2e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 2e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 2ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 2f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 2f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 2f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 2fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 300;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 304;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 308;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 30c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 310;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 314;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 318;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 31c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 320;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 324;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 328;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 32c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 330;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 334;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 338;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 33c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 340;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 344;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 348;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 34c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 350;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 354;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 358;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 35c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 360;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 364;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 368;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 36c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 370;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 374;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 378;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 37c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 380;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 384;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 388;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 38c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 390;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 394;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 398;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 39c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 3a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 3a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 3a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 3ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 3b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 3b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 3b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 3bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 3c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 3c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 3c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 3cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 3d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 3d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 3d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 3dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 3e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 3e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 3e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 3ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 3f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 3f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 3f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 3fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 400;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 404;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 408;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 40c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 410;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 414;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 418;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 41c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 420;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 424;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 428;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 42c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 430;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 434;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 438;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 43c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 440;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 444;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 448;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 44c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 450;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 454;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 458;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 45c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 460;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 464;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 468;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 46c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 470;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 474;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 478;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 47c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 480;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 484;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 488;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 48c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 490;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 494;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 498;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 49c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 4a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 4a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 4a8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 4ac;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 4b0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 4b4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 4b8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 4bc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 4c0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 4c4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 4c8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 4cc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 4d0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 4d4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 4d8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 4dc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 4e0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 4e4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 4e8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 4ec;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 4f0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 4f4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 4f8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 4fc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 500;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 504;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 508;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 50c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 510;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 514;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 518;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 51c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 520;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 524;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 528;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 52c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 530;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 534;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 538;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 53c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 540;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 12'h 544;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 12'h 548;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_16_OFFSET = 12'h 54c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_17_OFFSET = 12'h 550;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_18_OFFSET = 12'h 554;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_19_OFFSET = 12'h 558;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_20_OFFSET = 12'h 55c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_21_OFFSET = 12'h 560;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_22_OFFSET = 12'h 564;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_23_OFFSET = 12'h 568;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 56c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 570;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 574;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 578;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 57c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 580;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 584;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 588;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 58c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 590;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 594;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 598;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 59c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 5a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 5a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 5a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 5ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 5b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 5b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 5b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 5bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 5c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 5c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 5c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 5cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 5d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 5d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 5d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 5dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 5e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 5e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 5e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 5ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 5f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 5f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 5f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 5fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 600;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 604;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 608;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 60c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 610;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 614;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 618;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 61c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 620;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 624;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 628;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 62c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 630;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 634;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 638;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 63c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 640;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 644;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 648;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 64c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 650;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 654;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 658;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 65c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 660;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 664;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 668;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 66c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 670;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 674;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 678;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 67c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 680;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 684;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 688;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 68c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 690;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 694;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 698;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 69c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 6a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 6a4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 6a8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 6ac;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 6b0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 6b4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 6b8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 6bc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 6c0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 6c4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 6c8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 6cc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 6d0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 6d4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 6d8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 6dc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 6e0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 6e4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 6e8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 6ec;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 6f0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 6f4;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 6f8;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 6fc;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 700;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 704;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 708;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 70c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 710;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 714;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 718;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 71c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 720;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 724;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 728;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 72c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 730;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 734;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 738;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 73c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 740;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 744;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 748;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 74c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 750;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 754;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 758;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 75c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 760;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 764;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 768;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 76c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 770;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 774;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 778;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 77c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 780;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 784;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 788;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 78c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 790;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 794;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 798;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 79c;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 7a0;
+ parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 7a4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 7a8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 7ac;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 7b0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 7b4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 7b8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 7bc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 7c0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 7c4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 7c8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 7cc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 7d0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 7d4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 7d8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 7dc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 7e0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 7e4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 7e8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 7ec;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 7f0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 7f4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 7f8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 7fc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 800;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 804;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 808;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 80c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 810;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 814;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 818;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 81c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 820;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 824;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 828;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 82c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 830;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 834;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 838;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 83c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 840;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 12'h 844;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 12'h 848;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET = 12'h 84c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET = 12'h 850;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET = 12'h 854;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET = 12'h 858;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET = 12'h 85c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET = 12'h 860;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET = 12'h 864;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET = 12'h 868;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 86c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 870;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 874;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 878;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 87c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 880;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 884;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 888;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 88c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 890;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 894;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 898;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 89c;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 8a0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 8a4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 8a8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 8ac;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 8b0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 8b4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 8b8;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 8bc;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 8c0;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 8c4;
+ parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 8c8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 8cc;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 8d0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 8d4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 8d8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 8dc;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 8e0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 8e4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 8e8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 8ec;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 8f0;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 8f4;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 8f8;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 8fc;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 900;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 904;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 908;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 90c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 910;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 914;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 918;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 91c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 920;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 924;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 928;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 92c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 930;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 934;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 938;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 93c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 940;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 944;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 948;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 94c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 950;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 954;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 958;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 95c;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 960;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 964;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 968;
+ parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 96c;
// Reset values for hwext registers and their fields
+ parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0;
+ parameter logic [0:0] PINMUX_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
parameter logic [12:0] PINMUX_MIO_PAD_ATTR_0_RESVAL = 13'h 0;
parameter logic [12:0] PINMUX_MIO_PAD_ATTR_0_ATTR_0_RESVAL = 13'h 0;
parameter logic [12:0] PINMUX_MIO_PAD_ATTR_1_RESVAL = 13'h 0;
@@ -903,6 +913,7 @@
// Register index
typedef enum int {
+ PINMUX_ALERT_TEST,
PINMUX_MIO_PERIPH_INSEL_REGWEN_0,
PINMUX_MIO_PERIPH_INSEL_REGWEN_1,
PINMUX_MIO_PERIPH_INSEL_REGWEN_2,
@@ -1509,610 +1520,611 @@
} pinmux_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] PINMUX_PERMIT [603] = '{
- 4'b 0001, // index[ 0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0
- 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_1
- 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_2
- 4'b 0001, // index[ 3] PINMUX_MIO_PERIPH_INSEL_REGWEN_3
- 4'b 0001, // index[ 4] PINMUX_MIO_PERIPH_INSEL_REGWEN_4
- 4'b 0001, // index[ 5] PINMUX_MIO_PERIPH_INSEL_REGWEN_5
- 4'b 0001, // index[ 6] PINMUX_MIO_PERIPH_INSEL_REGWEN_6
- 4'b 0001, // index[ 7] PINMUX_MIO_PERIPH_INSEL_REGWEN_7
- 4'b 0001, // index[ 8] PINMUX_MIO_PERIPH_INSEL_REGWEN_8
- 4'b 0001, // index[ 9] PINMUX_MIO_PERIPH_INSEL_REGWEN_9
- 4'b 0001, // index[ 10] PINMUX_MIO_PERIPH_INSEL_REGWEN_10
- 4'b 0001, // index[ 11] PINMUX_MIO_PERIPH_INSEL_REGWEN_11
- 4'b 0001, // index[ 12] PINMUX_MIO_PERIPH_INSEL_REGWEN_12
- 4'b 0001, // index[ 13] PINMUX_MIO_PERIPH_INSEL_REGWEN_13
- 4'b 0001, // index[ 14] PINMUX_MIO_PERIPH_INSEL_REGWEN_14
- 4'b 0001, // index[ 15] PINMUX_MIO_PERIPH_INSEL_REGWEN_15
- 4'b 0001, // index[ 16] PINMUX_MIO_PERIPH_INSEL_REGWEN_16
- 4'b 0001, // index[ 17] PINMUX_MIO_PERIPH_INSEL_REGWEN_17
- 4'b 0001, // index[ 18] PINMUX_MIO_PERIPH_INSEL_REGWEN_18
- 4'b 0001, // index[ 19] PINMUX_MIO_PERIPH_INSEL_REGWEN_19
- 4'b 0001, // index[ 20] PINMUX_MIO_PERIPH_INSEL_REGWEN_20
- 4'b 0001, // index[ 21] PINMUX_MIO_PERIPH_INSEL_REGWEN_21
- 4'b 0001, // index[ 22] PINMUX_MIO_PERIPH_INSEL_REGWEN_22
- 4'b 0001, // index[ 23] PINMUX_MIO_PERIPH_INSEL_REGWEN_23
- 4'b 0001, // index[ 24] PINMUX_MIO_PERIPH_INSEL_REGWEN_24
- 4'b 0001, // index[ 25] PINMUX_MIO_PERIPH_INSEL_REGWEN_25
- 4'b 0001, // index[ 26] PINMUX_MIO_PERIPH_INSEL_REGWEN_26
- 4'b 0001, // index[ 27] PINMUX_MIO_PERIPH_INSEL_REGWEN_27
- 4'b 0001, // index[ 28] PINMUX_MIO_PERIPH_INSEL_REGWEN_28
- 4'b 0001, // index[ 29] PINMUX_MIO_PERIPH_INSEL_REGWEN_29
- 4'b 0001, // index[ 30] PINMUX_MIO_PERIPH_INSEL_REGWEN_30
- 4'b 0001, // index[ 31] PINMUX_MIO_PERIPH_INSEL_REGWEN_31
- 4'b 0001, // index[ 32] PINMUX_MIO_PERIPH_INSEL_REGWEN_32
- 4'b 0001, // index[ 33] PINMUX_MIO_PERIPH_INSEL_REGWEN_33
- 4'b 0001, // index[ 34] PINMUX_MIO_PERIPH_INSEL_REGWEN_34
- 4'b 0001, // index[ 35] PINMUX_MIO_PERIPH_INSEL_REGWEN_35
- 4'b 0001, // index[ 36] PINMUX_MIO_PERIPH_INSEL_REGWEN_36
- 4'b 0001, // index[ 37] PINMUX_MIO_PERIPH_INSEL_REGWEN_37
- 4'b 0001, // index[ 38] PINMUX_MIO_PERIPH_INSEL_REGWEN_38
- 4'b 0001, // index[ 39] PINMUX_MIO_PERIPH_INSEL_REGWEN_39
- 4'b 0001, // index[ 40] PINMUX_MIO_PERIPH_INSEL_REGWEN_40
- 4'b 0001, // index[ 41] PINMUX_MIO_PERIPH_INSEL_REGWEN_41
- 4'b 0001, // index[ 42] PINMUX_MIO_PERIPH_INSEL_REGWEN_42
- 4'b 0001, // index[ 43] PINMUX_MIO_PERIPH_INSEL_REGWEN_43
- 4'b 0001, // index[ 44] PINMUX_MIO_PERIPH_INSEL_REGWEN_44
- 4'b 0001, // index[ 45] PINMUX_MIO_PERIPH_INSEL_REGWEN_45
- 4'b 0001, // index[ 46] PINMUX_MIO_PERIPH_INSEL_REGWEN_46
- 4'b 0001, // index[ 47] PINMUX_MIO_PERIPH_INSEL_REGWEN_47
- 4'b 0001, // index[ 48] PINMUX_MIO_PERIPH_INSEL_REGWEN_48
- 4'b 0001, // index[ 49] PINMUX_MIO_PERIPH_INSEL_REGWEN_49
- 4'b 0001, // index[ 50] PINMUX_MIO_PERIPH_INSEL_REGWEN_50
- 4'b 0001, // index[ 51] PINMUX_MIO_PERIPH_INSEL_REGWEN_51
- 4'b 0001, // index[ 52] PINMUX_MIO_PERIPH_INSEL_REGWEN_52
- 4'b 0001, // index[ 53] PINMUX_MIO_PERIPH_INSEL_REGWEN_53
- 4'b 0001, // index[ 54] PINMUX_MIO_PERIPH_INSEL_REGWEN_54
- 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_0
- 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_1
- 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_2
- 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_3
- 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_4
- 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_5
- 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_6
- 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_7
- 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_8
- 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_9
- 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_10
- 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_11
- 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_12
- 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_13
- 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_14
- 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_15
- 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_16
- 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_17
- 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_18
- 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_19
- 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_20
- 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_21
- 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_22
- 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_23
- 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_24
- 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_25
- 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_26
- 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_27
- 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_28
- 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_29
- 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_30
- 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_31
- 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_32
- 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_33
- 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_34
- 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_35
- 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_36
- 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_37
- 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_38
- 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_39
- 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_40
- 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_41
- 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_42
- 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_43
- 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_44
- 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_45
- 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_46
- 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_47
- 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_48
- 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_49
- 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_50
- 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_51
- 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_52
- 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_53
- 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_54
- 4'b 0001, // index[110] PINMUX_MIO_OUTSEL_REGWEN_0
- 4'b 0001, // index[111] PINMUX_MIO_OUTSEL_REGWEN_1
- 4'b 0001, // index[112] PINMUX_MIO_OUTSEL_REGWEN_2
- 4'b 0001, // index[113] PINMUX_MIO_OUTSEL_REGWEN_3
- 4'b 0001, // index[114] PINMUX_MIO_OUTSEL_REGWEN_4
- 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_REGWEN_5
- 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_REGWEN_6
- 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_7
- 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_REGWEN_8
- 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_9
- 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_10
- 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_11
- 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_12
- 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_13
- 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_14
- 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_15
- 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_16
- 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_17
- 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_18
- 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_19
- 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_20
- 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_21
- 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_22
- 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_23
- 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_24
- 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_25
- 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_26
- 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_27
- 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_28
- 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_29
- 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_30
- 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_31
- 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_32
- 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_33
- 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_34
- 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_35
- 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_36
- 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_37
- 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_38
- 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_39
- 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_40
- 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_41
- 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_42
- 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_43
- 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_44
- 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_45
- 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_46
- 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_0
- 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_1
- 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_2
- 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_3
- 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_4
- 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_5
- 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_6
- 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_7
- 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_8
- 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_9
- 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_10
- 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_11
- 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_12
- 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_13
- 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_14
- 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_15
- 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_16
- 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_17
- 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_18
- 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_19
- 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_20
- 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_21
- 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_22
- 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_23
- 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_24
- 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_25
- 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_26
- 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_27
- 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_28
- 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_29
- 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_30
- 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_31
- 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_32
- 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_33
- 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_34
- 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_35
- 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_36
- 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_37
- 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_38
- 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_39
- 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_40
- 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_41
- 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_42
- 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_43
- 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_44
- 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_45
- 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_46
- 4'b 0001, // index[204] PINMUX_MIO_PAD_ATTR_REGWEN_0
- 4'b 0001, // index[205] PINMUX_MIO_PAD_ATTR_REGWEN_1
- 4'b 0001, // index[206] PINMUX_MIO_PAD_ATTR_REGWEN_2
- 4'b 0001, // index[207] PINMUX_MIO_PAD_ATTR_REGWEN_3
- 4'b 0001, // index[208] PINMUX_MIO_PAD_ATTR_REGWEN_4
- 4'b 0001, // index[209] PINMUX_MIO_PAD_ATTR_REGWEN_5
- 4'b 0001, // index[210] PINMUX_MIO_PAD_ATTR_REGWEN_6
- 4'b 0001, // index[211] PINMUX_MIO_PAD_ATTR_REGWEN_7
- 4'b 0001, // index[212] PINMUX_MIO_PAD_ATTR_REGWEN_8
- 4'b 0001, // index[213] PINMUX_MIO_PAD_ATTR_REGWEN_9
- 4'b 0001, // index[214] PINMUX_MIO_PAD_ATTR_REGWEN_10
- 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_11
- 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_12
- 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_13
- 4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_14
- 4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_15
- 4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_16
- 4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_17
- 4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_18
- 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_19
- 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_20
- 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_21
- 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_22
- 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_23
- 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_24
- 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_25
- 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_26
- 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_27
- 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_28
- 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_29
- 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_30
- 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_31
- 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_32
- 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_33
- 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_34
- 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_35
- 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_36
- 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_37
- 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_38
- 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_39
- 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_40
- 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_41
- 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_42
- 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_43
- 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_44
- 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_45
- 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_46
- 4'b 0011, // index[251] PINMUX_MIO_PAD_ATTR_0
- 4'b 0011, // index[252] PINMUX_MIO_PAD_ATTR_1
- 4'b 0011, // index[253] PINMUX_MIO_PAD_ATTR_2
- 4'b 0011, // index[254] PINMUX_MIO_PAD_ATTR_3
- 4'b 0011, // index[255] PINMUX_MIO_PAD_ATTR_4
- 4'b 0011, // index[256] PINMUX_MIO_PAD_ATTR_5
- 4'b 0011, // index[257] PINMUX_MIO_PAD_ATTR_6
- 4'b 0011, // index[258] PINMUX_MIO_PAD_ATTR_7
- 4'b 0011, // index[259] PINMUX_MIO_PAD_ATTR_8
- 4'b 0011, // index[260] PINMUX_MIO_PAD_ATTR_9
- 4'b 0011, // index[261] PINMUX_MIO_PAD_ATTR_10
- 4'b 0011, // index[262] PINMUX_MIO_PAD_ATTR_11
- 4'b 0011, // index[263] PINMUX_MIO_PAD_ATTR_12
- 4'b 0011, // index[264] PINMUX_MIO_PAD_ATTR_13
- 4'b 0011, // index[265] PINMUX_MIO_PAD_ATTR_14
- 4'b 0011, // index[266] PINMUX_MIO_PAD_ATTR_15
- 4'b 0011, // index[267] PINMUX_MIO_PAD_ATTR_16
- 4'b 0011, // index[268] PINMUX_MIO_PAD_ATTR_17
- 4'b 0011, // index[269] PINMUX_MIO_PAD_ATTR_18
- 4'b 0011, // index[270] PINMUX_MIO_PAD_ATTR_19
- 4'b 0011, // index[271] PINMUX_MIO_PAD_ATTR_20
- 4'b 0011, // index[272] PINMUX_MIO_PAD_ATTR_21
- 4'b 0011, // index[273] PINMUX_MIO_PAD_ATTR_22
- 4'b 0011, // index[274] PINMUX_MIO_PAD_ATTR_23
- 4'b 0011, // index[275] PINMUX_MIO_PAD_ATTR_24
- 4'b 0011, // index[276] PINMUX_MIO_PAD_ATTR_25
- 4'b 0011, // index[277] PINMUX_MIO_PAD_ATTR_26
- 4'b 0011, // index[278] PINMUX_MIO_PAD_ATTR_27
- 4'b 0011, // index[279] PINMUX_MIO_PAD_ATTR_28
- 4'b 0011, // index[280] PINMUX_MIO_PAD_ATTR_29
- 4'b 0011, // index[281] PINMUX_MIO_PAD_ATTR_30
- 4'b 0011, // index[282] PINMUX_MIO_PAD_ATTR_31
- 4'b 0011, // index[283] PINMUX_MIO_PAD_ATTR_32
- 4'b 0011, // index[284] PINMUX_MIO_PAD_ATTR_33
- 4'b 0011, // index[285] PINMUX_MIO_PAD_ATTR_34
- 4'b 0011, // index[286] PINMUX_MIO_PAD_ATTR_35
- 4'b 0011, // index[287] PINMUX_MIO_PAD_ATTR_36
- 4'b 0011, // index[288] PINMUX_MIO_PAD_ATTR_37
- 4'b 0011, // index[289] PINMUX_MIO_PAD_ATTR_38
- 4'b 0011, // index[290] PINMUX_MIO_PAD_ATTR_39
- 4'b 0011, // index[291] PINMUX_MIO_PAD_ATTR_40
- 4'b 0011, // index[292] PINMUX_MIO_PAD_ATTR_41
- 4'b 0011, // index[293] PINMUX_MIO_PAD_ATTR_42
- 4'b 0011, // index[294] PINMUX_MIO_PAD_ATTR_43
- 4'b 0011, // index[295] PINMUX_MIO_PAD_ATTR_44
- 4'b 0011, // index[296] PINMUX_MIO_PAD_ATTR_45
- 4'b 0011, // index[297] PINMUX_MIO_PAD_ATTR_46
- 4'b 0001, // index[298] PINMUX_DIO_PAD_ATTR_REGWEN_0
- 4'b 0001, // index[299] PINMUX_DIO_PAD_ATTR_REGWEN_1
- 4'b 0001, // index[300] PINMUX_DIO_PAD_ATTR_REGWEN_2
- 4'b 0001, // index[301] PINMUX_DIO_PAD_ATTR_REGWEN_3
- 4'b 0001, // index[302] PINMUX_DIO_PAD_ATTR_REGWEN_4
- 4'b 0001, // index[303] PINMUX_DIO_PAD_ATTR_REGWEN_5
- 4'b 0001, // index[304] PINMUX_DIO_PAD_ATTR_REGWEN_6
- 4'b 0001, // index[305] PINMUX_DIO_PAD_ATTR_REGWEN_7
- 4'b 0001, // index[306] PINMUX_DIO_PAD_ATTR_REGWEN_8
- 4'b 0001, // index[307] PINMUX_DIO_PAD_ATTR_REGWEN_9
- 4'b 0001, // index[308] PINMUX_DIO_PAD_ATTR_REGWEN_10
- 4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_11
- 4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_12
- 4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_13
- 4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_14
- 4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_15
- 4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_16
- 4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_17
- 4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_18
- 4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_19
- 4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_20
- 4'b 0001, // index[319] PINMUX_DIO_PAD_ATTR_REGWEN_21
- 4'b 0001, // index[320] PINMUX_DIO_PAD_ATTR_REGWEN_22
- 4'b 0001, // index[321] PINMUX_DIO_PAD_ATTR_REGWEN_23
- 4'b 0011, // index[322] PINMUX_DIO_PAD_ATTR_0
- 4'b 0011, // index[323] PINMUX_DIO_PAD_ATTR_1
- 4'b 0011, // index[324] PINMUX_DIO_PAD_ATTR_2
- 4'b 0011, // index[325] PINMUX_DIO_PAD_ATTR_3
- 4'b 0011, // index[326] PINMUX_DIO_PAD_ATTR_4
- 4'b 0011, // index[327] PINMUX_DIO_PAD_ATTR_5
- 4'b 0011, // index[328] PINMUX_DIO_PAD_ATTR_6
- 4'b 0011, // index[329] PINMUX_DIO_PAD_ATTR_7
- 4'b 0011, // index[330] PINMUX_DIO_PAD_ATTR_8
- 4'b 0011, // index[331] PINMUX_DIO_PAD_ATTR_9
- 4'b 0011, // index[332] PINMUX_DIO_PAD_ATTR_10
- 4'b 0011, // index[333] PINMUX_DIO_PAD_ATTR_11
- 4'b 0011, // index[334] PINMUX_DIO_PAD_ATTR_12
- 4'b 0011, // index[335] PINMUX_DIO_PAD_ATTR_13
- 4'b 0011, // index[336] PINMUX_DIO_PAD_ATTR_14
- 4'b 0011, // index[337] PINMUX_DIO_PAD_ATTR_15
- 4'b 0011, // index[338] PINMUX_DIO_PAD_ATTR_16
- 4'b 0011, // index[339] PINMUX_DIO_PAD_ATTR_17
- 4'b 0011, // index[340] PINMUX_DIO_PAD_ATTR_18
- 4'b 0011, // index[341] PINMUX_DIO_PAD_ATTR_19
- 4'b 0011, // index[342] PINMUX_DIO_PAD_ATTR_20
- 4'b 0011, // index[343] PINMUX_DIO_PAD_ATTR_21
- 4'b 0011, // index[344] PINMUX_DIO_PAD_ATTR_22
- 4'b 0011, // index[345] PINMUX_DIO_PAD_ATTR_23
- 4'b 1111, // index[346] PINMUX_MIO_PAD_SLEEP_STATUS_0
- 4'b 0011, // index[347] PINMUX_MIO_PAD_SLEEP_STATUS_1
- 4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_REGWEN_0
- 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_REGWEN_1
- 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_REGWEN_2
- 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_REGWEN_3
- 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_REGWEN_4
- 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_REGWEN_5
- 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_REGWEN_6
- 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_REGWEN_7
- 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_REGWEN_8
- 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_REGWEN_9
- 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_REGWEN_10
- 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_REGWEN_11
- 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_REGWEN_12
- 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_REGWEN_13
- 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_REGWEN_14
- 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_REGWEN_15
- 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_REGWEN_16
- 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_REGWEN_17
- 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_18
- 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_19
- 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_20
- 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_21
- 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_22
- 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_23
- 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_24
- 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_25
- 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_26
- 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_27
- 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_28
- 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_29
- 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_30
- 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_31
- 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_32
- 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_33
- 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_34
- 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_35
- 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_REGWEN_36
- 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_REGWEN_37
- 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_REGWEN_38
- 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_REGWEN_39
- 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_REGWEN_40
- 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_REGWEN_41
- 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_REGWEN_42
- 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_REGWEN_43
- 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_REGWEN_44
- 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_REGWEN_45
- 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_REGWEN_46
- 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_EN_0
- 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_EN_1
- 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_EN_2
- 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_EN_3
- 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_EN_4
- 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_EN_5
- 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_EN_6
- 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_EN_7
- 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_EN_8
- 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_EN_9
- 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_EN_10
- 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_EN_11
- 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_EN_12
- 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_EN_13
- 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_EN_14
- 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_EN_15
- 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_EN_16
- 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_EN_17
- 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_18
- 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_19
- 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_20
- 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_21
- 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_22
- 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_23
- 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_24
- 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_25
- 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_26
- 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_27
- 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_28
- 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_29
- 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_30
- 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_31
- 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_32
- 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_33
- 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_34
- 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_35
- 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_EN_36
- 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_EN_37
- 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_EN_38
- 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_EN_39
- 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_EN_40
- 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_EN_41
- 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_EN_42
- 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_EN_43
- 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_EN_44
- 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_EN_45
- 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_EN_46
- 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_MODE_0
- 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_MODE_1
- 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_MODE_2
- 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_MODE_3
- 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_MODE_4
- 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_MODE_5
- 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_MODE_6
- 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_MODE_7
- 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_MODE_8
- 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_MODE_9
- 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_MODE_10
- 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_MODE_11
- 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_MODE_12
- 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_MODE_13
- 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_MODE_14
- 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_MODE_15
- 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_MODE_16
- 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_MODE_17
- 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_18
- 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_19
- 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_20
- 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_21
- 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_22
- 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_23
- 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_24
- 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_25
- 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_26
- 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_27
- 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_28
- 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_29
- 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_30
- 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_31
- 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_32
- 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_33
- 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_34
- 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_MODE_35
- 4'b 0001, // index[478] PINMUX_MIO_PAD_SLEEP_MODE_36
- 4'b 0001, // index[479] PINMUX_MIO_PAD_SLEEP_MODE_37
- 4'b 0001, // index[480] PINMUX_MIO_PAD_SLEEP_MODE_38
- 4'b 0001, // index[481] PINMUX_MIO_PAD_SLEEP_MODE_39
- 4'b 0001, // index[482] PINMUX_MIO_PAD_SLEEP_MODE_40
- 4'b 0001, // index[483] PINMUX_MIO_PAD_SLEEP_MODE_41
- 4'b 0001, // index[484] PINMUX_MIO_PAD_SLEEP_MODE_42
- 4'b 0001, // index[485] PINMUX_MIO_PAD_SLEEP_MODE_43
- 4'b 0001, // index[486] PINMUX_MIO_PAD_SLEEP_MODE_44
- 4'b 0001, // index[487] PINMUX_MIO_PAD_SLEEP_MODE_45
- 4'b 0001, // index[488] PINMUX_MIO_PAD_SLEEP_MODE_46
- 4'b 0111, // index[489] PINMUX_DIO_PAD_SLEEP_STATUS
- 4'b 0001, // index[490] PINMUX_DIO_PAD_SLEEP_REGWEN_0
- 4'b 0001, // index[491] PINMUX_DIO_PAD_SLEEP_REGWEN_1
- 4'b 0001, // index[492] PINMUX_DIO_PAD_SLEEP_REGWEN_2
- 4'b 0001, // index[493] PINMUX_DIO_PAD_SLEEP_REGWEN_3
- 4'b 0001, // index[494] PINMUX_DIO_PAD_SLEEP_REGWEN_4
- 4'b 0001, // index[495] PINMUX_DIO_PAD_SLEEP_REGWEN_5
- 4'b 0001, // index[496] PINMUX_DIO_PAD_SLEEP_REGWEN_6
- 4'b 0001, // index[497] PINMUX_DIO_PAD_SLEEP_REGWEN_7
- 4'b 0001, // index[498] PINMUX_DIO_PAD_SLEEP_REGWEN_8
- 4'b 0001, // index[499] PINMUX_DIO_PAD_SLEEP_REGWEN_9
- 4'b 0001, // index[500] PINMUX_DIO_PAD_SLEEP_REGWEN_10
- 4'b 0001, // index[501] PINMUX_DIO_PAD_SLEEP_REGWEN_11
- 4'b 0001, // index[502] PINMUX_DIO_PAD_SLEEP_REGWEN_12
- 4'b 0001, // index[503] PINMUX_DIO_PAD_SLEEP_REGWEN_13
- 4'b 0001, // index[504] PINMUX_DIO_PAD_SLEEP_REGWEN_14
- 4'b 0001, // index[505] PINMUX_DIO_PAD_SLEEP_REGWEN_15
- 4'b 0001, // index[506] PINMUX_DIO_PAD_SLEEP_REGWEN_16
- 4'b 0001, // index[507] PINMUX_DIO_PAD_SLEEP_REGWEN_17
- 4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_REGWEN_18
- 4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_REGWEN_19
- 4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_REGWEN_20
- 4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_REGWEN_21
- 4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_REGWEN_22
- 4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_REGWEN_23
- 4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_EN_0
- 4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_EN_1
- 4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_EN_2
- 4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_EN_3
- 4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_EN_4
- 4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_EN_5
- 4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_EN_6
- 4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_EN_7
- 4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_EN_8
- 4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_EN_9
- 4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_EN_10
- 4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_EN_11
- 4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_EN_12
- 4'b 0001, // index[527] PINMUX_DIO_PAD_SLEEP_EN_13
- 4'b 0001, // index[528] PINMUX_DIO_PAD_SLEEP_EN_14
- 4'b 0001, // index[529] PINMUX_DIO_PAD_SLEEP_EN_15
- 4'b 0001, // index[530] PINMUX_DIO_PAD_SLEEP_EN_16
- 4'b 0001, // index[531] PINMUX_DIO_PAD_SLEEP_EN_17
- 4'b 0001, // index[532] PINMUX_DIO_PAD_SLEEP_EN_18
- 4'b 0001, // index[533] PINMUX_DIO_PAD_SLEEP_EN_19
- 4'b 0001, // index[534] PINMUX_DIO_PAD_SLEEP_EN_20
- 4'b 0001, // index[535] PINMUX_DIO_PAD_SLEEP_EN_21
- 4'b 0001, // index[536] PINMUX_DIO_PAD_SLEEP_EN_22
- 4'b 0001, // index[537] PINMUX_DIO_PAD_SLEEP_EN_23
- 4'b 0001, // index[538] PINMUX_DIO_PAD_SLEEP_MODE_0
- 4'b 0001, // index[539] PINMUX_DIO_PAD_SLEEP_MODE_1
- 4'b 0001, // index[540] PINMUX_DIO_PAD_SLEEP_MODE_2
- 4'b 0001, // index[541] PINMUX_DIO_PAD_SLEEP_MODE_3
- 4'b 0001, // index[542] PINMUX_DIO_PAD_SLEEP_MODE_4
- 4'b 0001, // index[543] PINMUX_DIO_PAD_SLEEP_MODE_5
- 4'b 0001, // index[544] PINMUX_DIO_PAD_SLEEP_MODE_6
- 4'b 0001, // index[545] PINMUX_DIO_PAD_SLEEP_MODE_7
- 4'b 0001, // index[546] PINMUX_DIO_PAD_SLEEP_MODE_8
- 4'b 0001, // index[547] PINMUX_DIO_PAD_SLEEP_MODE_9
- 4'b 0001, // index[548] PINMUX_DIO_PAD_SLEEP_MODE_10
- 4'b 0001, // index[549] PINMUX_DIO_PAD_SLEEP_MODE_11
- 4'b 0001, // index[550] PINMUX_DIO_PAD_SLEEP_MODE_12
- 4'b 0001, // index[551] PINMUX_DIO_PAD_SLEEP_MODE_13
- 4'b 0001, // index[552] PINMUX_DIO_PAD_SLEEP_MODE_14
- 4'b 0001, // index[553] PINMUX_DIO_PAD_SLEEP_MODE_15
- 4'b 0001, // index[554] PINMUX_DIO_PAD_SLEEP_MODE_16
- 4'b 0001, // index[555] PINMUX_DIO_PAD_SLEEP_MODE_17
- 4'b 0001, // index[556] PINMUX_DIO_PAD_SLEEP_MODE_18
- 4'b 0001, // index[557] PINMUX_DIO_PAD_SLEEP_MODE_19
- 4'b 0001, // index[558] PINMUX_DIO_PAD_SLEEP_MODE_20
- 4'b 0001, // index[559] PINMUX_DIO_PAD_SLEEP_MODE_21
- 4'b 0001, // index[560] PINMUX_DIO_PAD_SLEEP_MODE_22
- 4'b 0001, // index[561] PINMUX_DIO_PAD_SLEEP_MODE_23
- 4'b 0001, // index[562] PINMUX_WKUP_DETECTOR_REGWEN_0
- 4'b 0001, // index[563] PINMUX_WKUP_DETECTOR_REGWEN_1
- 4'b 0001, // index[564] PINMUX_WKUP_DETECTOR_REGWEN_2
- 4'b 0001, // index[565] PINMUX_WKUP_DETECTOR_REGWEN_3
- 4'b 0001, // index[566] PINMUX_WKUP_DETECTOR_REGWEN_4
- 4'b 0001, // index[567] PINMUX_WKUP_DETECTOR_REGWEN_5
- 4'b 0001, // index[568] PINMUX_WKUP_DETECTOR_REGWEN_6
- 4'b 0001, // index[569] PINMUX_WKUP_DETECTOR_REGWEN_7
- 4'b 0001, // index[570] PINMUX_WKUP_DETECTOR_EN_0
- 4'b 0001, // index[571] PINMUX_WKUP_DETECTOR_EN_1
- 4'b 0001, // index[572] PINMUX_WKUP_DETECTOR_EN_2
- 4'b 0001, // index[573] PINMUX_WKUP_DETECTOR_EN_3
- 4'b 0001, // index[574] PINMUX_WKUP_DETECTOR_EN_4
- 4'b 0001, // index[575] PINMUX_WKUP_DETECTOR_EN_5
- 4'b 0001, // index[576] PINMUX_WKUP_DETECTOR_EN_6
- 4'b 0001, // index[577] PINMUX_WKUP_DETECTOR_EN_7
- 4'b 0001, // index[578] PINMUX_WKUP_DETECTOR_0
- 4'b 0001, // index[579] PINMUX_WKUP_DETECTOR_1
- 4'b 0001, // index[580] PINMUX_WKUP_DETECTOR_2
- 4'b 0001, // index[581] PINMUX_WKUP_DETECTOR_3
- 4'b 0001, // index[582] PINMUX_WKUP_DETECTOR_4
- 4'b 0001, // index[583] PINMUX_WKUP_DETECTOR_5
- 4'b 0001, // index[584] PINMUX_WKUP_DETECTOR_6
- 4'b 0001, // index[585] PINMUX_WKUP_DETECTOR_7
- 4'b 0001, // index[586] PINMUX_WKUP_DETECTOR_CNT_TH_0
- 4'b 0001, // index[587] PINMUX_WKUP_DETECTOR_CNT_TH_1
- 4'b 0001, // index[588] PINMUX_WKUP_DETECTOR_CNT_TH_2
- 4'b 0001, // index[589] PINMUX_WKUP_DETECTOR_CNT_TH_3
- 4'b 0001, // index[590] PINMUX_WKUP_DETECTOR_CNT_TH_4
- 4'b 0001, // index[591] PINMUX_WKUP_DETECTOR_CNT_TH_5
- 4'b 0001, // index[592] PINMUX_WKUP_DETECTOR_CNT_TH_6
- 4'b 0001, // index[593] PINMUX_WKUP_DETECTOR_CNT_TH_7
- 4'b 0001, // index[594] PINMUX_WKUP_DETECTOR_PADSEL_0
- 4'b 0001, // index[595] PINMUX_WKUP_DETECTOR_PADSEL_1
- 4'b 0001, // index[596] PINMUX_WKUP_DETECTOR_PADSEL_2
- 4'b 0001, // index[597] PINMUX_WKUP_DETECTOR_PADSEL_3
- 4'b 0001, // index[598] PINMUX_WKUP_DETECTOR_PADSEL_4
- 4'b 0001, // index[599] PINMUX_WKUP_DETECTOR_PADSEL_5
- 4'b 0001, // index[600] PINMUX_WKUP_DETECTOR_PADSEL_6
- 4'b 0001, // index[601] PINMUX_WKUP_DETECTOR_PADSEL_7
- 4'b 0001 // index[602] PINMUX_WKUP_CAUSE
+ parameter logic [3:0] PINMUX_PERMIT [604] = '{
+ 4'b 0001, // index[ 0] PINMUX_ALERT_TEST
+ 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0
+ 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1
+ 4'b 0001, // index[ 3] PINMUX_MIO_PERIPH_INSEL_REGWEN_2
+ 4'b 0001, // index[ 4] PINMUX_MIO_PERIPH_INSEL_REGWEN_3
+ 4'b 0001, // index[ 5] PINMUX_MIO_PERIPH_INSEL_REGWEN_4
+ 4'b 0001, // index[ 6] PINMUX_MIO_PERIPH_INSEL_REGWEN_5
+ 4'b 0001, // index[ 7] PINMUX_MIO_PERIPH_INSEL_REGWEN_6
+ 4'b 0001, // index[ 8] PINMUX_MIO_PERIPH_INSEL_REGWEN_7
+ 4'b 0001, // index[ 9] PINMUX_MIO_PERIPH_INSEL_REGWEN_8
+ 4'b 0001, // index[ 10] PINMUX_MIO_PERIPH_INSEL_REGWEN_9
+ 4'b 0001, // index[ 11] PINMUX_MIO_PERIPH_INSEL_REGWEN_10
+ 4'b 0001, // index[ 12] PINMUX_MIO_PERIPH_INSEL_REGWEN_11
+ 4'b 0001, // index[ 13] PINMUX_MIO_PERIPH_INSEL_REGWEN_12
+ 4'b 0001, // index[ 14] PINMUX_MIO_PERIPH_INSEL_REGWEN_13
+ 4'b 0001, // index[ 15] PINMUX_MIO_PERIPH_INSEL_REGWEN_14
+ 4'b 0001, // index[ 16] PINMUX_MIO_PERIPH_INSEL_REGWEN_15
+ 4'b 0001, // index[ 17] PINMUX_MIO_PERIPH_INSEL_REGWEN_16
+ 4'b 0001, // index[ 18] PINMUX_MIO_PERIPH_INSEL_REGWEN_17
+ 4'b 0001, // index[ 19] PINMUX_MIO_PERIPH_INSEL_REGWEN_18
+ 4'b 0001, // index[ 20] PINMUX_MIO_PERIPH_INSEL_REGWEN_19
+ 4'b 0001, // index[ 21] PINMUX_MIO_PERIPH_INSEL_REGWEN_20
+ 4'b 0001, // index[ 22] PINMUX_MIO_PERIPH_INSEL_REGWEN_21
+ 4'b 0001, // index[ 23] PINMUX_MIO_PERIPH_INSEL_REGWEN_22
+ 4'b 0001, // index[ 24] PINMUX_MIO_PERIPH_INSEL_REGWEN_23
+ 4'b 0001, // index[ 25] PINMUX_MIO_PERIPH_INSEL_REGWEN_24
+ 4'b 0001, // index[ 26] PINMUX_MIO_PERIPH_INSEL_REGWEN_25
+ 4'b 0001, // index[ 27] PINMUX_MIO_PERIPH_INSEL_REGWEN_26
+ 4'b 0001, // index[ 28] PINMUX_MIO_PERIPH_INSEL_REGWEN_27
+ 4'b 0001, // index[ 29] PINMUX_MIO_PERIPH_INSEL_REGWEN_28
+ 4'b 0001, // index[ 30] PINMUX_MIO_PERIPH_INSEL_REGWEN_29
+ 4'b 0001, // index[ 31] PINMUX_MIO_PERIPH_INSEL_REGWEN_30
+ 4'b 0001, // index[ 32] PINMUX_MIO_PERIPH_INSEL_REGWEN_31
+ 4'b 0001, // index[ 33] PINMUX_MIO_PERIPH_INSEL_REGWEN_32
+ 4'b 0001, // index[ 34] PINMUX_MIO_PERIPH_INSEL_REGWEN_33
+ 4'b 0001, // index[ 35] PINMUX_MIO_PERIPH_INSEL_REGWEN_34
+ 4'b 0001, // index[ 36] PINMUX_MIO_PERIPH_INSEL_REGWEN_35
+ 4'b 0001, // index[ 37] PINMUX_MIO_PERIPH_INSEL_REGWEN_36
+ 4'b 0001, // index[ 38] PINMUX_MIO_PERIPH_INSEL_REGWEN_37
+ 4'b 0001, // index[ 39] PINMUX_MIO_PERIPH_INSEL_REGWEN_38
+ 4'b 0001, // index[ 40] PINMUX_MIO_PERIPH_INSEL_REGWEN_39
+ 4'b 0001, // index[ 41] PINMUX_MIO_PERIPH_INSEL_REGWEN_40
+ 4'b 0001, // index[ 42] PINMUX_MIO_PERIPH_INSEL_REGWEN_41
+ 4'b 0001, // index[ 43] PINMUX_MIO_PERIPH_INSEL_REGWEN_42
+ 4'b 0001, // index[ 44] PINMUX_MIO_PERIPH_INSEL_REGWEN_43
+ 4'b 0001, // index[ 45] PINMUX_MIO_PERIPH_INSEL_REGWEN_44
+ 4'b 0001, // index[ 46] PINMUX_MIO_PERIPH_INSEL_REGWEN_45
+ 4'b 0001, // index[ 47] PINMUX_MIO_PERIPH_INSEL_REGWEN_46
+ 4'b 0001, // index[ 48] PINMUX_MIO_PERIPH_INSEL_REGWEN_47
+ 4'b 0001, // index[ 49] PINMUX_MIO_PERIPH_INSEL_REGWEN_48
+ 4'b 0001, // index[ 50] PINMUX_MIO_PERIPH_INSEL_REGWEN_49
+ 4'b 0001, // index[ 51] PINMUX_MIO_PERIPH_INSEL_REGWEN_50
+ 4'b 0001, // index[ 52] PINMUX_MIO_PERIPH_INSEL_REGWEN_51
+ 4'b 0001, // index[ 53] PINMUX_MIO_PERIPH_INSEL_REGWEN_52
+ 4'b 0001, // index[ 54] PINMUX_MIO_PERIPH_INSEL_REGWEN_53
+ 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_REGWEN_54
+ 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_0
+ 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_1
+ 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_2
+ 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_3
+ 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_4
+ 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_5
+ 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_6
+ 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_7
+ 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_8
+ 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_9
+ 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_10
+ 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_11
+ 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_12
+ 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_13
+ 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_14
+ 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_15
+ 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_16
+ 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_17
+ 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_18
+ 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_19
+ 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_20
+ 4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_21
+ 4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_22
+ 4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_23
+ 4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_24
+ 4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_25
+ 4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_26
+ 4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_27
+ 4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_28
+ 4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_29
+ 4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_30
+ 4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_31
+ 4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_32
+ 4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_33
+ 4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_34
+ 4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_35
+ 4'b 0001, // index[ 92] PINMUX_MIO_PERIPH_INSEL_36
+ 4'b 0001, // index[ 93] PINMUX_MIO_PERIPH_INSEL_37
+ 4'b 0001, // index[ 94] PINMUX_MIO_PERIPH_INSEL_38
+ 4'b 0001, // index[ 95] PINMUX_MIO_PERIPH_INSEL_39
+ 4'b 0001, // index[ 96] PINMUX_MIO_PERIPH_INSEL_40
+ 4'b 0001, // index[ 97] PINMUX_MIO_PERIPH_INSEL_41
+ 4'b 0001, // index[ 98] PINMUX_MIO_PERIPH_INSEL_42
+ 4'b 0001, // index[ 99] PINMUX_MIO_PERIPH_INSEL_43
+ 4'b 0001, // index[100] PINMUX_MIO_PERIPH_INSEL_44
+ 4'b 0001, // index[101] PINMUX_MIO_PERIPH_INSEL_45
+ 4'b 0001, // index[102] PINMUX_MIO_PERIPH_INSEL_46
+ 4'b 0001, // index[103] PINMUX_MIO_PERIPH_INSEL_47
+ 4'b 0001, // index[104] PINMUX_MIO_PERIPH_INSEL_48
+ 4'b 0001, // index[105] PINMUX_MIO_PERIPH_INSEL_49
+ 4'b 0001, // index[106] PINMUX_MIO_PERIPH_INSEL_50
+ 4'b 0001, // index[107] PINMUX_MIO_PERIPH_INSEL_51
+ 4'b 0001, // index[108] PINMUX_MIO_PERIPH_INSEL_52
+ 4'b 0001, // index[109] PINMUX_MIO_PERIPH_INSEL_53
+ 4'b 0001, // index[110] PINMUX_MIO_PERIPH_INSEL_54
+ 4'b 0001, // index[111] PINMUX_MIO_OUTSEL_REGWEN_0
+ 4'b 0001, // index[112] PINMUX_MIO_OUTSEL_REGWEN_1
+ 4'b 0001, // index[113] PINMUX_MIO_OUTSEL_REGWEN_2
+ 4'b 0001, // index[114] PINMUX_MIO_OUTSEL_REGWEN_3
+ 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_REGWEN_4
+ 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_REGWEN_5
+ 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_6
+ 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_REGWEN_7
+ 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_8
+ 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_9
+ 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_10
+ 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_11
+ 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_12
+ 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_REGWEN_13
+ 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_REGWEN_14
+ 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_REGWEN_15
+ 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_REGWEN_16
+ 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_REGWEN_17
+ 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_REGWEN_18
+ 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_REGWEN_19
+ 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_REGWEN_20
+ 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_REGWEN_21
+ 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_REGWEN_22
+ 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_REGWEN_23
+ 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_REGWEN_24
+ 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_REGWEN_25
+ 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_REGWEN_26
+ 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_REGWEN_27
+ 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_REGWEN_28
+ 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_REGWEN_29
+ 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_REGWEN_30
+ 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_REGWEN_31
+ 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_REGWEN_32
+ 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_REGWEN_33
+ 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_REGWEN_34
+ 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_REGWEN_35
+ 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_REGWEN_36
+ 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_REGWEN_37
+ 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_REGWEN_38
+ 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_REGWEN_39
+ 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_REGWEN_40
+ 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_REGWEN_41
+ 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_REGWEN_42
+ 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_REGWEN_43
+ 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_REGWEN_44
+ 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_REGWEN_45
+ 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_REGWEN_46
+ 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_0
+ 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_1
+ 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_2
+ 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_3
+ 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_4
+ 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_5
+ 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_6
+ 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_7
+ 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_8
+ 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_9
+ 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_10
+ 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_11
+ 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_12
+ 4'b 0001, // index[171] PINMUX_MIO_OUTSEL_13
+ 4'b 0001, // index[172] PINMUX_MIO_OUTSEL_14
+ 4'b 0001, // index[173] PINMUX_MIO_OUTSEL_15
+ 4'b 0001, // index[174] PINMUX_MIO_OUTSEL_16
+ 4'b 0001, // index[175] PINMUX_MIO_OUTSEL_17
+ 4'b 0001, // index[176] PINMUX_MIO_OUTSEL_18
+ 4'b 0001, // index[177] PINMUX_MIO_OUTSEL_19
+ 4'b 0001, // index[178] PINMUX_MIO_OUTSEL_20
+ 4'b 0001, // index[179] PINMUX_MIO_OUTSEL_21
+ 4'b 0001, // index[180] PINMUX_MIO_OUTSEL_22
+ 4'b 0001, // index[181] PINMUX_MIO_OUTSEL_23
+ 4'b 0001, // index[182] PINMUX_MIO_OUTSEL_24
+ 4'b 0001, // index[183] PINMUX_MIO_OUTSEL_25
+ 4'b 0001, // index[184] PINMUX_MIO_OUTSEL_26
+ 4'b 0001, // index[185] PINMUX_MIO_OUTSEL_27
+ 4'b 0001, // index[186] PINMUX_MIO_OUTSEL_28
+ 4'b 0001, // index[187] PINMUX_MIO_OUTSEL_29
+ 4'b 0001, // index[188] PINMUX_MIO_OUTSEL_30
+ 4'b 0001, // index[189] PINMUX_MIO_OUTSEL_31
+ 4'b 0001, // index[190] PINMUX_MIO_OUTSEL_32
+ 4'b 0001, // index[191] PINMUX_MIO_OUTSEL_33
+ 4'b 0001, // index[192] PINMUX_MIO_OUTSEL_34
+ 4'b 0001, // index[193] PINMUX_MIO_OUTSEL_35
+ 4'b 0001, // index[194] PINMUX_MIO_OUTSEL_36
+ 4'b 0001, // index[195] PINMUX_MIO_OUTSEL_37
+ 4'b 0001, // index[196] PINMUX_MIO_OUTSEL_38
+ 4'b 0001, // index[197] PINMUX_MIO_OUTSEL_39
+ 4'b 0001, // index[198] PINMUX_MIO_OUTSEL_40
+ 4'b 0001, // index[199] PINMUX_MIO_OUTSEL_41
+ 4'b 0001, // index[200] PINMUX_MIO_OUTSEL_42
+ 4'b 0001, // index[201] PINMUX_MIO_OUTSEL_43
+ 4'b 0001, // index[202] PINMUX_MIO_OUTSEL_44
+ 4'b 0001, // index[203] PINMUX_MIO_OUTSEL_45
+ 4'b 0001, // index[204] PINMUX_MIO_OUTSEL_46
+ 4'b 0001, // index[205] PINMUX_MIO_PAD_ATTR_REGWEN_0
+ 4'b 0001, // index[206] PINMUX_MIO_PAD_ATTR_REGWEN_1
+ 4'b 0001, // index[207] PINMUX_MIO_PAD_ATTR_REGWEN_2
+ 4'b 0001, // index[208] PINMUX_MIO_PAD_ATTR_REGWEN_3
+ 4'b 0001, // index[209] PINMUX_MIO_PAD_ATTR_REGWEN_4
+ 4'b 0001, // index[210] PINMUX_MIO_PAD_ATTR_REGWEN_5
+ 4'b 0001, // index[211] PINMUX_MIO_PAD_ATTR_REGWEN_6
+ 4'b 0001, // index[212] PINMUX_MIO_PAD_ATTR_REGWEN_7
+ 4'b 0001, // index[213] PINMUX_MIO_PAD_ATTR_REGWEN_8
+ 4'b 0001, // index[214] PINMUX_MIO_PAD_ATTR_REGWEN_9
+ 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_10
+ 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_11
+ 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_12
+ 4'b 0001, // index[218] PINMUX_MIO_PAD_ATTR_REGWEN_13
+ 4'b 0001, // index[219] PINMUX_MIO_PAD_ATTR_REGWEN_14
+ 4'b 0001, // index[220] PINMUX_MIO_PAD_ATTR_REGWEN_15
+ 4'b 0001, // index[221] PINMUX_MIO_PAD_ATTR_REGWEN_16
+ 4'b 0001, // index[222] PINMUX_MIO_PAD_ATTR_REGWEN_17
+ 4'b 0001, // index[223] PINMUX_MIO_PAD_ATTR_REGWEN_18
+ 4'b 0001, // index[224] PINMUX_MIO_PAD_ATTR_REGWEN_19
+ 4'b 0001, // index[225] PINMUX_MIO_PAD_ATTR_REGWEN_20
+ 4'b 0001, // index[226] PINMUX_MIO_PAD_ATTR_REGWEN_21
+ 4'b 0001, // index[227] PINMUX_MIO_PAD_ATTR_REGWEN_22
+ 4'b 0001, // index[228] PINMUX_MIO_PAD_ATTR_REGWEN_23
+ 4'b 0001, // index[229] PINMUX_MIO_PAD_ATTR_REGWEN_24
+ 4'b 0001, // index[230] PINMUX_MIO_PAD_ATTR_REGWEN_25
+ 4'b 0001, // index[231] PINMUX_MIO_PAD_ATTR_REGWEN_26
+ 4'b 0001, // index[232] PINMUX_MIO_PAD_ATTR_REGWEN_27
+ 4'b 0001, // index[233] PINMUX_MIO_PAD_ATTR_REGWEN_28
+ 4'b 0001, // index[234] PINMUX_MIO_PAD_ATTR_REGWEN_29
+ 4'b 0001, // index[235] PINMUX_MIO_PAD_ATTR_REGWEN_30
+ 4'b 0001, // index[236] PINMUX_MIO_PAD_ATTR_REGWEN_31
+ 4'b 0001, // index[237] PINMUX_MIO_PAD_ATTR_REGWEN_32
+ 4'b 0001, // index[238] PINMUX_MIO_PAD_ATTR_REGWEN_33
+ 4'b 0001, // index[239] PINMUX_MIO_PAD_ATTR_REGWEN_34
+ 4'b 0001, // index[240] PINMUX_MIO_PAD_ATTR_REGWEN_35
+ 4'b 0001, // index[241] PINMUX_MIO_PAD_ATTR_REGWEN_36
+ 4'b 0001, // index[242] PINMUX_MIO_PAD_ATTR_REGWEN_37
+ 4'b 0001, // index[243] PINMUX_MIO_PAD_ATTR_REGWEN_38
+ 4'b 0001, // index[244] PINMUX_MIO_PAD_ATTR_REGWEN_39
+ 4'b 0001, // index[245] PINMUX_MIO_PAD_ATTR_REGWEN_40
+ 4'b 0001, // index[246] PINMUX_MIO_PAD_ATTR_REGWEN_41
+ 4'b 0001, // index[247] PINMUX_MIO_PAD_ATTR_REGWEN_42
+ 4'b 0001, // index[248] PINMUX_MIO_PAD_ATTR_REGWEN_43
+ 4'b 0001, // index[249] PINMUX_MIO_PAD_ATTR_REGWEN_44
+ 4'b 0001, // index[250] PINMUX_MIO_PAD_ATTR_REGWEN_45
+ 4'b 0001, // index[251] PINMUX_MIO_PAD_ATTR_REGWEN_46
+ 4'b 0011, // index[252] PINMUX_MIO_PAD_ATTR_0
+ 4'b 0011, // index[253] PINMUX_MIO_PAD_ATTR_1
+ 4'b 0011, // index[254] PINMUX_MIO_PAD_ATTR_2
+ 4'b 0011, // index[255] PINMUX_MIO_PAD_ATTR_3
+ 4'b 0011, // index[256] PINMUX_MIO_PAD_ATTR_4
+ 4'b 0011, // index[257] PINMUX_MIO_PAD_ATTR_5
+ 4'b 0011, // index[258] PINMUX_MIO_PAD_ATTR_6
+ 4'b 0011, // index[259] PINMUX_MIO_PAD_ATTR_7
+ 4'b 0011, // index[260] PINMUX_MIO_PAD_ATTR_8
+ 4'b 0011, // index[261] PINMUX_MIO_PAD_ATTR_9
+ 4'b 0011, // index[262] PINMUX_MIO_PAD_ATTR_10
+ 4'b 0011, // index[263] PINMUX_MIO_PAD_ATTR_11
+ 4'b 0011, // index[264] PINMUX_MIO_PAD_ATTR_12
+ 4'b 0011, // index[265] PINMUX_MIO_PAD_ATTR_13
+ 4'b 0011, // index[266] PINMUX_MIO_PAD_ATTR_14
+ 4'b 0011, // index[267] PINMUX_MIO_PAD_ATTR_15
+ 4'b 0011, // index[268] PINMUX_MIO_PAD_ATTR_16
+ 4'b 0011, // index[269] PINMUX_MIO_PAD_ATTR_17
+ 4'b 0011, // index[270] PINMUX_MIO_PAD_ATTR_18
+ 4'b 0011, // index[271] PINMUX_MIO_PAD_ATTR_19
+ 4'b 0011, // index[272] PINMUX_MIO_PAD_ATTR_20
+ 4'b 0011, // index[273] PINMUX_MIO_PAD_ATTR_21
+ 4'b 0011, // index[274] PINMUX_MIO_PAD_ATTR_22
+ 4'b 0011, // index[275] PINMUX_MIO_PAD_ATTR_23
+ 4'b 0011, // index[276] PINMUX_MIO_PAD_ATTR_24
+ 4'b 0011, // index[277] PINMUX_MIO_PAD_ATTR_25
+ 4'b 0011, // index[278] PINMUX_MIO_PAD_ATTR_26
+ 4'b 0011, // index[279] PINMUX_MIO_PAD_ATTR_27
+ 4'b 0011, // index[280] PINMUX_MIO_PAD_ATTR_28
+ 4'b 0011, // index[281] PINMUX_MIO_PAD_ATTR_29
+ 4'b 0011, // index[282] PINMUX_MIO_PAD_ATTR_30
+ 4'b 0011, // index[283] PINMUX_MIO_PAD_ATTR_31
+ 4'b 0011, // index[284] PINMUX_MIO_PAD_ATTR_32
+ 4'b 0011, // index[285] PINMUX_MIO_PAD_ATTR_33
+ 4'b 0011, // index[286] PINMUX_MIO_PAD_ATTR_34
+ 4'b 0011, // index[287] PINMUX_MIO_PAD_ATTR_35
+ 4'b 0011, // index[288] PINMUX_MIO_PAD_ATTR_36
+ 4'b 0011, // index[289] PINMUX_MIO_PAD_ATTR_37
+ 4'b 0011, // index[290] PINMUX_MIO_PAD_ATTR_38
+ 4'b 0011, // index[291] PINMUX_MIO_PAD_ATTR_39
+ 4'b 0011, // index[292] PINMUX_MIO_PAD_ATTR_40
+ 4'b 0011, // index[293] PINMUX_MIO_PAD_ATTR_41
+ 4'b 0011, // index[294] PINMUX_MIO_PAD_ATTR_42
+ 4'b 0011, // index[295] PINMUX_MIO_PAD_ATTR_43
+ 4'b 0011, // index[296] PINMUX_MIO_PAD_ATTR_44
+ 4'b 0011, // index[297] PINMUX_MIO_PAD_ATTR_45
+ 4'b 0011, // index[298] PINMUX_MIO_PAD_ATTR_46
+ 4'b 0001, // index[299] PINMUX_DIO_PAD_ATTR_REGWEN_0
+ 4'b 0001, // index[300] PINMUX_DIO_PAD_ATTR_REGWEN_1
+ 4'b 0001, // index[301] PINMUX_DIO_PAD_ATTR_REGWEN_2
+ 4'b 0001, // index[302] PINMUX_DIO_PAD_ATTR_REGWEN_3
+ 4'b 0001, // index[303] PINMUX_DIO_PAD_ATTR_REGWEN_4
+ 4'b 0001, // index[304] PINMUX_DIO_PAD_ATTR_REGWEN_5
+ 4'b 0001, // index[305] PINMUX_DIO_PAD_ATTR_REGWEN_6
+ 4'b 0001, // index[306] PINMUX_DIO_PAD_ATTR_REGWEN_7
+ 4'b 0001, // index[307] PINMUX_DIO_PAD_ATTR_REGWEN_8
+ 4'b 0001, // index[308] PINMUX_DIO_PAD_ATTR_REGWEN_9
+ 4'b 0001, // index[309] PINMUX_DIO_PAD_ATTR_REGWEN_10
+ 4'b 0001, // index[310] PINMUX_DIO_PAD_ATTR_REGWEN_11
+ 4'b 0001, // index[311] PINMUX_DIO_PAD_ATTR_REGWEN_12
+ 4'b 0001, // index[312] PINMUX_DIO_PAD_ATTR_REGWEN_13
+ 4'b 0001, // index[313] PINMUX_DIO_PAD_ATTR_REGWEN_14
+ 4'b 0001, // index[314] PINMUX_DIO_PAD_ATTR_REGWEN_15
+ 4'b 0001, // index[315] PINMUX_DIO_PAD_ATTR_REGWEN_16
+ 4'b 0001, // index[316] PINMUX_DIO_PAD_ATTR_REGWEN_17
+ 4'b 0001, // index[317] PINMUX_DIO_PAD_ATTR_REGWEN_18
+ 4'b 0001, // index[318] PINMUX_DIO_PAD_ATTR_REGWEN_19
+ 4'b 0001, // index[319] PINMUX_DIO_PAD_ATTR_REGWEN_20
+ 4'b 0001, // index[320] PINMUX_DIO_PAD_ATTR_REGWEN_21
+ 4'b 0001, // index[321] PINMUX_DIO_PAD_ATTR_REGWEN_22
+ 4'b 0001, // index[322] PINMUX_DIO_PAD_ATTR_REGWEN_23
+ 4'b 0011, // index[323] PINMUX_DIO_PAD_ATTR_0
+ 4'b 0011, // index[324] PINMUX_DIO_PAD_ATTR_1
+ 4'b 0011, // index[325] PINMUX_DIO_PAD_ATTR_2
+ 4'b 0011, // index[326] PINMUX_DIO_PAD_ATTR_3
+ 4'b 0011, // index[327] PINMUX_DIO_PAD_ATTR_4
+ 4'b 0011, // index[328] PINMUX_DIO_PAD_ATTR_5
+ 4'b 0011, // index[329] PINMUX_DIO_PAD_ATTR_6
+ 4'b 0011, // index[330] PINMUX_DIO_PAD_ATTR_7
+ 4'b 0011, // index[331] PINMUX_DIO_PAD_ATTR_8
+ 4'b 0011, // index[332] PINMUX_DIO_PAD_ATTR_9
+ 4'b 0011, // index[333] PINMUX_DIO_PAD_ATTR_10
+ 4'b 0011, // index[334] PINMUX_DIO_PAD_ATTR_11
+ 4'b 0011, // index[335] PINMUX_DIO_PAD_ATTR_12
+ 4'b 0011, // index[336] PINMUX_DIO_PAD_ATTR_13
+ 4'b 0011, // index[337] PINMUX_DIO_PAD_ATTR_14
+ 4'b 0011, // index[338] PINMUX_DIO_PAD_ATTR_15
+ 4'b 0011, // index[339] PINMUX_DIO_PAD_ATTR_16
+ 4'b 0011, // index[340] PINMUX_DIO_PAD_ATTR_17
+ 4'b 0011, // index[341] PINMUX_DIO_PAD_ATTR_18
+ 4'b 0011, // index[342] PINMUX_DIO_PAD_ATTR_19
+ 4'b 0011, // index[343] PINMUX_DIO_PAD_ATTR_20
+ 4'b 0011, // index[344] PINMUX_DIO_PAD_ATTR_21
+ 4'b 0011, // index[345] PINMUX_DIO_PAD_ATTR_22
+ 4'b 0011, // index[346] PINMUX_DIO_PAD_ATTR_23
+ 4'b 1111, // index[347] PINMUX_MIO_PAD_SLEEP_STATUS_0
+ 4'b 0011, // index[348] PINMUX_MIO_PAD_SLEEP_STATUS_1
+ 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_REGWEN_0
+ 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_REGWEN_1
+ 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_REGWEN_2
+ 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_REGWEN_3
+ 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_REGWEN_4
+ 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_REGWEN_5
+ 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_REGWEN_6
+ 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_REGWEN_7
+ 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_REGWEN_8
+ 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_REGWEN_9
+ 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_REGWEN_10
+ 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_REGWEN_11
+ 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_REGWEN_12
+ 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_REGWEN_13
+ 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_REGWEN_14
+ 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_REGWEN_15
+ 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_REGWEN_16
+ 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_REGWEN_17
+ 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_REGWEN_18
+ 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_REGWEN_19
+ 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_REGWEN_20
+ 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_REGWEN_21
+ 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_REGWEN_22
+ 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_REGWEN_23
+ 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_REGWEN_24
+ 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_REGWEN_25
+ 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_REGWEN_26
+ 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_REGWEN_27
+ 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_REGWEN_28
+ 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_REGWEN_29
+ 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_REGWEN_30
+ 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_REGWEN_31
+ 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_REGWEN_32
+ 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_REGWEN_33
+ 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_REGWEN_34
+ 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_REGWEN_35
+ 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_REGWEN_36
+ 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_REGWEN_37
+ 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_REGWEN_38
+ 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_REGWEN_39
+ 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_REGWEN_40
+ 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_REGWEN_41
+ 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_REGWEN_42
+ 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_REGWEN_43
+ 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_REGWEN_44
+ 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_REGWEN_45
+ 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_REGWEN_46
+ 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_EN_0
+ 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_EN_1
+ 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_EN_2
+ 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_EN_3
+ 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_EN_4
+ 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_EN_5
+ 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_EN_6
+ 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_EN_7
+ 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_EN_8
+ 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_EN_9
+ 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_EN_10
+ 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_EN_11
+ 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_EN_12
+ 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_EN_13
+ 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_EN_14
+ 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_EN_15
+ 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_EN_16
+ 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_EN_17
+ 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_EN_18
+ 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_EN_19
+ 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_EN_20
+ 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_EN_21
+ 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_EN_22
+ 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_EN_23
+ 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_EN_24
+ 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_EN_25
+ 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_EN_26
+ 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_EN_27
+ 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_EN_28
+ 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_EN_29
+ 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_EN_30
+ 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_EN_31
+ 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_EN_32
+ 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_EN_33
+ 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_EN_34
+ 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_EN_35
+ 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_EN_36
+ 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_EN_37
+ 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_EN_38
+ 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_EN_39
+ 4'b 0001, // index[436] PINMUX_MIO_PAD_SLEEP_EN_40
+ 4'b 0001, // index[437] PINMUX_MIO_PAD_SLEEP_EN_41
+ 4'b 0001, // index[438] PINMUX_MIO_PAD_SLEEP_EN_42
+ 4'b 0001, // index[439] PINMUX_MIO_PAD_SLEEP_EN_43
+ 4'b 0001, // index[440] PINMUX_MIO_PAD_SLEEP_EN_44
+ 4'b 0001, // index[441] PINMUX_MIO_PAD_SLEEP_EN_45
+ 4'b 0001, // index[442] PINMUX_MIO_PAD_SLEEP_EN_46
+ 4'b 0001, // index[443] PINMUX_MIO_PAD_SLEEP_MODE_0
+ 4'b 0001, // index[444] PINMUX_MIO_PAD_SLEEP_MODE_1
+ 4'b 0001, // index[445] PINMUX_MIO_PAD_SLEEP_MODE_2
+ 4'b 0001, // index[446] PINMUX_MIO_PAD_SLEEP_MODE_3
+ 4'b 0001, // index[447] PINMUX_MIO_PAD_SLEEP_MODE_4
+ 4'b 0001, // index[448] PINMUX_MIO_PAD_SLEEP_MODE_5
+ 4'b 0001, // index[449] PINMUX_MIO_PAD_SLEEP_MODE_6
+ 4'b 0001, // index[450] PINMUX_MIO_PAD_SLEEP_MODE_7
+ 4'b 0001, // index[451] PINMUX_MIO_PAD_SLEEP_MODE_8
+ 4'b 0001, // index[452] PINMUX_MIO_PAD_SLEEP_MODE_9
+ 4'b 0001, // index[453] PINMUX_MIO_PAD_SLEEP_MODE_10
+ 4'b 0001, // index[454] PINMUX_MIO_PAD_SLEEP_MODE_11
+ 4'b 0001, // index[455] PINMUX_MIO_PAD_SLEEP_MODE_12
+ 4'b 0001, // index[456] PINMUX_MIO_PAD_SLEEP_MODE_13
+ 4'b 0001, // index[457] PINMUX_MIO_PAD_SLEEP_MODE_14
+ 4'b 0001, // index[458] PINMUX_MIO_PAD_SLEEP_MODE_15
+ 4'b 0001, // index[459] PINMUX_MIO_PAD_SLEEP_MODE_16
+ 4'b 0001, // index[460] PINMUX_MIO_PAD_SLEEP_MODE_17
+ 4'b 0001, // index[461] PINMUX_MIO_PAD_SLEEP_MODE_18
+ 4'b 0001, // index[462] PINMUX_MIO_PAD_SLEEP_MODE_19
+ 4'b 0001, // index[463] PINMUX_MIO_PAD_SLEEP_MODE_20
+ 4'b 0001, // index[464] PINMUX_MIO_PAD_SLEEP_MODE_21
+ 4'b 0001, // index[465] PINMUX_MIO_PAD_SLEEP_MODE_22
+ 4'b 0001, // index[466] PINMUX_MIO_PAD_SLEEP_MODE_23
+ 4'b 0001, // index[467] PINMUX_MIO_PAD_SLEEP_MODE_24
+ 4'b 0001, // index[468] PINMUX_MIO_PAD_SLEEP_MODE_25
+ 4'b 0001, // index[469] PINMUX_MIO_PAD_SLEEP_MODE_26
+ 4'b 0001, // index[470] PINMUX_MIO_PAD_SLEEP_MODE_27
+ 4'b 0001, // index[471] PINMUX_MIO_PAD_SLEEP_MODE_28
+ 4'b 0001, // index[472] PINMUX_MIO_PAD_SLEEP_MODE_29
+ 4'b 0001, // index[473] PINMUX_MIO_PAD_SLEEP_MODE_30
+ 4'b 0001, // index[474] PINMUX_MIO_PAD_SLEEP_MODE_31
+ 4'b 0001, // index[475] PINMUX_MIO_PAD_SLEEP_MODE_32
+ 4'b 0001, // index[476] PINMUX_MIO_PAD_SLEEP_MODE_33
+ 4'b 0001, // index[477] PINMUX_MIO_PAD_SLEEP_MODE_34
+ 4'b 0001, // index[478] PINMUX_MIO_PAD_SLEEP_MODE_35
+ 4'b 0001, // index[479] PINMUX_MIO_PAD_SLEEP_MODE_36
+ 4'b 0001, // index[480] PINMUX_MIO_PAD_SLEEP_MODE_37
+ 4'b 0001, // index[481] PINMUX_MIO_PAD_SLEEP_MODE_38
+ 4'b 0001, // index[482] PINMUX_MIO_PAD_SLEEP_MODE_39
+ 4'b 0001, // index[483] PINMUX_MIO_PAD_SLEEP_MODE_40
+ 4'b 0001, // index[484] PINMUX_MIO_PAD_SLEEP_MODE_41
+ 4'b 0001, // index[485] PINMUX_MIO_PAD_SLEEP_MODE_42
+ 4'b 0001, // index[486] PINMUX_MIO_PAD_SLEEP_MODE_43
+ 4'b 0001, // index[487] PINMUX_MIO_PAD_SLEEP_MODE_44
+ 4'b 0001, // index[488] PINMUX_MIO_PAD_SLEEP_MODE_45
+ 4'b 0001, // index[489] PINMUX_MIO_PAD_SLEEP_MODE_46
+ 4'b 0111, // index[490] PINMUX_DIO_PAD_SLEEP_STATUS
+ 4'b 0001, // index[491] PINMUX_DIO_PAD_SLEEP_REGWEN_0
+ 4'b 0001, // index[492] PINMUX_DIO_PAD_SLEEP_REGWEN_1
+ 4'b 0001, // index[493] PINMUX_DIO_PAD_SLEEP_REGWEN_2
+ 4'b 0001, // index[494] PINMUX_DIO_PAD_SLEEP_REGWEN_3
+ 4'b 0001, // index[495] PINMUX_DIO_PAD_SLEEP_REGWEN_4
+ 4'b 0001, // index[496] PINMUX_DIO_PAD_SLEEP_REGWEN_5
+ 4'b 0001, // index[497] PINMUX_DIO_PAD_SLEEP_REGWEN_6
+ 4'b 0001, // index[498] PINMUX_DIO_PAD_SLEEP_REGWEN_7
+ 4'b 0001, // index[499] PINMUX_DIO_PAD_SLEEP_REGWEN_8
+ 4'b 0001, // index[500] PINMUX_DIO_PAD_SLEEP_REGWEN_9
+ 4'b 0001, // index[501] PINMUX_DIO_PAD_SLEEP_REGWEN_10
+ 4'b 0001, // index[502] PINMUX_DIO_PAD_SLEEP_REGWEN_11
+ 4'b 0001, // index[503] PINMUX_DIO_PAD_SLEEP_REGWEN_12
+ 4'b 0001, // index[504] PINMUX_DIO_PAD_SLEEP_REGWEN_13
+ 4'b 0001, // index[505] PINMUX_DIO_PAD_SLEEP_REGWEN_14
+ 4'b 0001, // index[506] PINMUX_DIO_PAD_SLEEP_REGWEN_15
+ 4'b 0001, // index[507] PINMUX_DIO_PAD_SLEEP_REGWEN_16
+ 4'b 0001, // index[508] PINMUX_DIO_PAD_SLEEP_REGWEN_17
+ 4'b 0001, // index[509] PINMUX_DIO_PAD_SLEEP_REGWEN_18
+ 4'b 0001, // index[510] PINMUX_DIO_PAD_SLEEP_REGWEN_19
+ 4'b 0001, // index[511] PINMUX_DIO_PAD_SLEEP_REGWEN_20
+ 4'b 0001, // index[512] PINMUX_DIO_PAD_SLEEP_REGWEN_21
+ 4'b 0001, // index[513] PINMUX_DIO_PAD_SLEEP_REGWEN_22
+ 4'b 0001, // index[514] PINMUX_DIO_PAD_SLEEP_REGWEN_23
+ 4'b 0001, // index[515] PINMUX_DIO_PAD_SLEEP_EN_0
+ 4'b 0001, // index[516] PINMUX_DIO_PAD_SLEEP_EN_1
+ 4'b 0001, // index[517] PINMUX_DIO_PAD_SLEEP_EN_2
+ 4'b 0001, // index[518] PINMUX_DIO_PAD_SLEEP_EN_3
+ 4'b 0001, // index[519] PINMUX_DIO_PAD_SLEEP_EN_4
+ 4'b 0001, // index[520] PINMUX_DIO_PAD_SLEEP_EN_5
+ 4'b 0001, // index[521] PINMUX_DIO_PAD_SLEEP_EN_6
+ 4'b 0001, // index[522] PINMUX_DIO_PAD_SLEEP_EN_7
+ 4'b 0001, // index[523] PINMUX_DIO_PAD_SLEEP_EN_8
+ 4'b 0001, // index[524] PINMUX_DIO_PAD_SLEEP_EN_9
+ 4'b 0001, // index[525] PINMUX_DIO_PAD_SLEEP_EN_10
+ 4'b 0001, // index[526] PINMUX_DIO_PAD_SLEEP_EN_11
+ 4'b 0001, // index[527] PINMUX_DIO_PAD_SLEEP_EN_12
+ 4'b 0001, // index[528] PINMUX_DIO_PAD_SLEEP_EN_13
+ 4'b 0001, // index[529] PINMUX_DIO_PAD_SLEEP_EN_14
+ 4'b 0001, // index[530] PINMUX_DIO_PAD_SLEEP_EN_15
+ 4'b 0001, // index[531] PINMUX_DIO_PAD_SLEEP_EN_16
+ 4'b 0001, // index[532] PINMUX_DIO_PAD_SLEEP_EN_17
+ 4'b 0001, // index[533] PINMUX_DIO_PAD_SLEEP_EN_18
+ 4'b 0001, // index[534] PINMUX_DIO_PAD_SLEEP_EN_19
+ 4'b 0001, // index[535] PINMUX_DIO_PAD_SLEEP_EN_20
+ 4'b 0001, // index[536] PINMUX_DIO_PAD_SLEEP_EN_21
+ 4'b 0001, // index[537] PINMUX_DIO_PAD_SLEEP_EN_22
+ 4'b 0001, // index[538] PINMUX_DIO_PAD_SLEEP_EN_23
+ 4'b 0001, // index[539] PINMUX_DIO_PAD_SLEEP_MODE_0
+ 4'b 0001, // index[540] PINMUX_DIO_PAD_SLEEP_MODE_1
+ 4'b 0001, // index[541] PINMUX_DIO_PAD_SLEEP_MODE_2
+ 4'b 0001, // index[542] PINMUX_DIO_PAD_SLEEP_MODE_3
+ 4'b 0001, // index[543] PINMUX_DIO_PAD_SLEEP_MODE_4
+ 4'b 0001, // index[544] PINMUX_DIO_PAD_SLEEP_MODE_5
+ 4'b 0001, // index[545] PINMUX_DIO_PAD_SLEEP_MODE_6
+ 4'b 0001, // index[546] PINMUX_DIO_PAD_SLEEP_MODE_7
+ 4'b 0001, // index[547] PINMUX_DIO_PAD_SLEEP_MODE_8
+ 4'b 0001, // index[548] PINMUX_DIO_PAD_SLEEP_MODE_9
+ 4'b 0001, // index[549] PINMUX_DIO_PAD_SLEEP_MODE_10
+ 4'b 0001, // index[550] PINMUX_DIO_PAD_SLEEP_MODE_11
+ 4'b 0001, // index[551] PINMUX_DIO_PAD_SLEEP_MODE_12
+ 4'b 0001, // index[552] PINMUX_DIO_PAD_SLEEP_MODE_13
+ 4'b 0001, // index[553] PINMUX_DIO_PAD_SLEEP_MODE_14
+ 4'b 0001, // index[554] PINMUX_DIO_PAD_SLEEP_MODE_15
+ 4'b 0001, // index[555] PINMUX_DIO_PAD_SLEEP_MODE_16
+ 4'b 0001, // index[556] PINMUX_DIO_PAD_SLEEP_MODE_17
+ 4'b 0001, // index[557] PINMUX_DIO_PAD_SLEEP_MODE_18
+ 4'b 0001, // index[558] PINMUX_DIO_PAD_SLEEP_MODE_19
+ 4'b 0001, // index[559] PINMUX_DIO_PAD_SLEEP_MODE_20
+ 4'b 0001, // index[560] PINMUX_DIO_PAD_SLEEP_MODE_21
+ 4'b 0001, // index[561] PINMUX_DIO_PAD_SLEEP_MODE_22
+ 4'b 0001, // index[562] PINMUX_DIO_PAD_SLEEP_MODE_23
+ 4'b 0001, // index[563] PINMUX_WKUP_DETECTOR_REGWEN_0
+ 4'b 0001, // index[564] PINMUX_WKUP_DETECTOR_REGWEN_1
+ 4'b 0001, // index[565] PINMUX_WKUP_DETECTOR_REGWEN_2
+ 4'b 0001, // index[566] PINMUX_WKUP_DETECTOR_REGWEN_3
+ 4'b 0001, // index[567] PINMUX_WKUP_DETECTOR_REGWEN_4
+ 4'b 0001, // index[568] PINMUX_WKUP_DETECTOR_REGWEN_5
+ 4'b 0001, // index[569] PINMUX_WKUP_DETECTOR_REGWEN_6
+ 4'b 0001, // index[570] PINMUX_WKUP_DETECTOR_REGWEN_7
+ 4'b 0001, // index[571] PINMUX_WKUP_DETECTOR_EN_0
+ 4'b 0001, // index[572] PINMUX_WKUP_DETECTOR_EN_1
+ 4'b 0001, // index[573] PINMUX_WKUP_DETECTOR_EN_2
+ 4'b 0001, // index[574] PINMUX_WKUP_DETECTOR_EN_3
+ 4'b 0001, // index[575] PINMUX_WKUP_DETECTOR_EN_4
+ 4'b 0001, // index[576] PINMUX_WKUP_DETECTOR_EN_5
+ 4'b 0001, // index[577] PINMUX_WKUP_DETECTOR_EN_6
+ 4'b 0001, // index[578] PINMUX_WKUP_DETECTOR_EN_7
+ 4'b 0001, // index[579] PINMUX_WKUP_DETECTOR_0
+ 4'b 0001, // index[580] PINMUX_WKUP_DETECTOR_1
+ 4'b 0001, // index[581] PINMUX_WKUP_DETECTOR_2
+ 4'b 0001, // index[582] PINMUX_WKUP_DETECTOR_3
+ 4'b 0001, // index[583] PINMUX_WKUP_DETECTOR_4
+ 4'b 0001, // index[584] PINMUX_WKUP_DETECTOR_5
+ 4'b 0001, // index[585] PINMUX_WKUP_DETECTOR_6
+ 4'b 0001, // index[586] PINMUX_WKUP_DETECTOR_7
+ 4'b 0001, // index[587] PINMUX_WKUP_DETECTOR_CNT_TH_0
+ 4'b 0001, // index[588] PINMUX_WKUP_DETECTOR_CNT_TH_1
+ 4'b 0001, // index[589] PINMUX_WKUP_DETECTOR_CNT_TH_2
+ 4'b 0001, // index[590] PINMUX_WKUP_DETECTOR_CNT_TH_3
+ 4'b 0001, // index[591] PINMUX_WKUP_DETECTOR_CNT_TH_4
+ 4'b 0001, // index[592] PINMUX_WKUP_DETECTOR_CNT_TH_5
+ 4'b 0001, // index[593] PINMUX_WKUP_DETECTOR_CNT_TH_6
+ 4'b 0001, // index[594] PINMUX_WKUP_DETECTOR_CNT_TH_7
+ 4'b 0001, // index[595] PINMUX_WKUP_DETECTOR_PADSEL_0
+ 4'b 0001, // index[596] PINMUX_WKUP_DETECTOR_PADSEL_1
+ 4'b 0001, // index[597] PINMUX_WKUP_DETECTOR_PADSEL_2
+ 4'b 0001, // index[598] PINMUX_WKUP_DETECTOR_PADSEL_3
+ 4'b 0001, // index[599] PINMUX_WKUP_DETECTOR_PADSEL_4
+ 4'b 0001, // index[600] PINMUX_WKUP_DETECTOR_PADSEL_5
+ 4'b 0001, // index[601] PINMUX_WKUP_DETECTOR_PADSEL_6
+ 4'b 0001, // index[602] PINMUX_WKUP_DETECTOR_PADSEL_7
+ 4'b 0001 // index[603] PINMUX_WKUP_CAUSE
};
endpackage
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
index 9da5bb7..b603183 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -104,6 +104,8 @@
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
+ logic alert_test_wd;
+ logic alert_test_we;
logic mio_periph_insel_regwen_0_qs;
logic mio_periph_insel_regwen_0_wd;
logic mio_periph_insel_regwen_0_we;
@@ -2267,6 +2269,22 @@
logic wkup_cause_cause_7_re;
// Register instances
+ // R[alert_test]: V(True)
+
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.qe),
+ .q (reg2hw.alert_test.q),
+ .qs ()
+ );
+
+
// Subregister 0 of Multireg mio_periph_insel_regwen
// R[mio_periph_insel_regwen_0]: V(False)
@@ -20115,612 +20133,613 @@
- logic [602:0] addr_hit;
+ logic [603:0] addr_hit;
always_comb begin
addr_hit = '0;
- addr_hit[ 0] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET);
- addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET);
- addr_hit[ 2] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET);
- addr_hit[ 3] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET);
- addr_hit[ 4] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET);
- addr_hit[ 5] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET);
- addr_hit[ 6] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET);
- addr_hit[ 7] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET);
- addr_hit[ 8] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET);
- addr_hit[ 9] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET);
- addr_hit[ 10] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET);
- addr_hit[ 11] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET);
- addr_hit[ 12] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET);
- addr_hit[ 13] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET);
- addr_hit[ 14] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET);
- addr_hit[ 15] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET);
- addr_hit[ 16] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET);
- addr_hit[ 17] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET);
- addr_hit[ 18] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET);
- addr_hit[ 19] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET);
- addr_hit[ 20] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET);
- addr_hit[ 21] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET);
- addr_hit[ 22] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET);
- addr_hit[ 23] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET);
- addr_hit[ 24] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET);
- addr_hit[ 25] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET);
- addr_hit[ 26] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET);
- addr_hit[ 27] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET);
- addr_hit[ 28] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET);
- addr_hit[ 29] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET);
- addr_hit[ 30] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET);
- addr_hit[ 31] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET);
- addr_hit[ 32] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET);
- addr_hit[ 33] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET);
- addr_hit[ 34] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET);
- addr_hit[ 35] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET);
- addr_hit[ 36] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET);
- addr_hit[ 37] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET);
- addr_hit[ 38] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET);
- addr_hit[ 39] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET);
- addr_hit[ 40] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET);
- addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET);
- addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET);
- addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET);
- addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET);
- addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET);
- addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_46_OFFSET);
- addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_47_OFFSET);
- addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_48_OFFSET);
- addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_49_OFFSET);
- addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_50_OFFSET);
- addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_51_OFFSET);
- addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_52_OFFSET);
- addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_53_OFFSET);
- addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET);
- addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET);
- addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET);
- addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET);
- addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET);
- addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET);
- addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET);
- addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET);
- addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET);
- addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET);
- addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET);
- addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET);
- addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET);
- addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET);
- addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET);
- addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET);
- addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET);
- addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET);
- addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET);
- addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET);
- addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET);
- addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET);
- addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET);
- addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET);
- addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET);
- addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET);
- addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET);
- addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET);
- addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET);
- addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET);
- addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET);
- addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET);
- addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET);
- addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET);
- addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET);
- addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET);
- addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET);
- addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET);
- addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET);
- addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET);
- addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET);
- addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET);
- addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET);
- addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET);
- addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET);
- addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET);
- addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET);
- addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET);
- addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET);
- addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET);
- addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET);
- addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET);
- addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET);
- addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET);
- addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET);
- addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET);
- addr_hit[110] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET);
- addr_hit[111] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET);
- addr_hit[112] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET);
- addr_hit[113] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET);
- addr_hit[114] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET);
- addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET);
- addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET);
- addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET);
- addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET);
- addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET);
- addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET);
- addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET);
- addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET);
- addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET);
- addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET);
- addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET);
- addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET);
- addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET);
- addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET);
- addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET);
- addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET);
- addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET);
- addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET);
- addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET);
- addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET);
- addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET);
- addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET);
- addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET);
- addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET);
- addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET);
- addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET);
- addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET);
- addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET);
- addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET);
- addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET);
- addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET);
- addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET);
- addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET);
- addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET);
- addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET);
- addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET);
- addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET);
- addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET);
- addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET);
- addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET);
- addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET);
- addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET);
- addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
- addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
- addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
- addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
- addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
- addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
- addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
- addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
- addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
- addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
- addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
- addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
- addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
- addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
- addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
- addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
- addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
- addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
- addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
- addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
- addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
- addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
- addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
- addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
- addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
- addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
- addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
- addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
- addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
- addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
- addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
- addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
- addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET);
- addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET);
- addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET);
- addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET);
- addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET);
- addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET);
- addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET);
- addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET);
- addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET);
- addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET);
- addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET);
- addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET);
- addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET);
- addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET);
- addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET);
- addr_hit[204] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
- addr_hit[205] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
- addr_hit[206] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
- addr_hit[207] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
- addr_hit[208] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
- addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
- addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
- addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
- addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
- addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
- addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
- addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
- addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
- addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
- addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
- addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
- addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
- addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
- addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
- addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
- addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
- addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
- addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
- addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
- addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
- addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
- addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
- addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
- addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
- addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
- addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
- addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
- addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET);
- addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET);
- addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET);
- addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET);
- addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET);
- addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET);
- addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET);
- addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET);
- addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET);
- addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET);
- addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET);
- addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET);
- addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET);
- addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET);
- addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET);
- addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
- addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
- addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
- addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
- addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
- addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
- addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
- addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
- addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
- addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
- addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
- addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
- addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
- addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
- addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
- addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
- addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
- addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
- addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
- addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
- addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
- addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
- addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
- addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
- addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
- addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
- addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
- addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
- addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
- addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
- addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
- addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
- addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET);
- addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET);
- addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET);
- addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET);
- addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET);
- addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET);
- addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET);
- addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET);
- addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET);
- addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET);
- addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET);
- addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET);
- addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET);
- addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET);
- addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET);
- addr_hit[298] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
- addr_hit[299] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
- addr_hit[300] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
- addr_hit[301] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
- addr_hit[302] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
- addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
- addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
- addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
- addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
- addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
- addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
- addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
- addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
- addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
- addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
- addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET);
- addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET);
- addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET);
- addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET);
- addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET);
- addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET);
- addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET);
- addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET);
- addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET);
- addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
- addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
- addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
- addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
- addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
- addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
- addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
- addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
- addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
- addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
- addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
- addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
- addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
- addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
- addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
- addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET);
- addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_ATTR_16_OFFSET);
- addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_ATTR_17_OFFSET);
- addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_ATTR_18_OFFSET);
- addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_ATTR_19_OFFSET);
- addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_ATTR_20_OFFSET);
- addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_ATTR_21_OFFSET);
- addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_ATTR_22_OFFSET);
- addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_ATTR_23_OFFSET);
- addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET);
- addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET);
- addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
- addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
- addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
- addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
- addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
- addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
- addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
- addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
- addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
- addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
- addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
- addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
- addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
- addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
- addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
- addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
- addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
- addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
- addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
- addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
- addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
- addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
- addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
- addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
- addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
- addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
- addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
- addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
- addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
- addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
- addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
- addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
- addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET);
- addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET);
- addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET);
- addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET);
- addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET);
- addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET);
- addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET);
- addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET);
- addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET);
- addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET);
- addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET);
- addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET);
- addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET);
- addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET);
- addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET);
- addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
- addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
- addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
- addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
- addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
- addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
- addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
- addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
- addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
- addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
- addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
- addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
- addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
- addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
- addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
- addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
- addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
- addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
- addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
- addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
- addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
- addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
- addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
- addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
- addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
- addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
- addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
- addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
- addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
- addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
- addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
- addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
- addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET);
- addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET);
- addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET);
- addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET);
- addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET);
- addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET);
- addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET);
- addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET);
- addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET);
- addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET);
- addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET);
- addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET);
- addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET);
- addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET);
- addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET);
- addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
- addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
- addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
- addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
- addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
- addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
- addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
- addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
- addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
- addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
- addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
- addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
- addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
- addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
- addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
- addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
- addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
- addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
- addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
- addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
- addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
- addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
- addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
- addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
- addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
- addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
- addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
- addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
- addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
- addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
- addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
- addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
- addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET);
- addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET);
- addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET);
- addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET);
- addr_hit[478] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET);
- addr_hit[479] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET);
- addr_hit[480] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET);
- addr_hit[481] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET);
- addr_hit[482] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET);
- addr_hit[483] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET);
- addr_hit[484] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET);
- addr_hit[485] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET);
- addr_hit[486] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET);
- addr_hit[487] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET);
- addr_hit[488] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET);
- addr_hit[489] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
- addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
- addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
- addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
- addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
- addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
- addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
- addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
- addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
- addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
- addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
- addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
- addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
- addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
- addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
- addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
- addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET);
- addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET);
- addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET);
- addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET);
- addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET);
- addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET);
- addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET);
- addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET);
- addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET);
- addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
- addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
- addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
- addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
- addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
- addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
- addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
- addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
- addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
- addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
- addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
- addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
- addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
- addr_hit[527] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
- addr_hit[528] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
- addr_hit[529] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET);
- addr_hit[530] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET);
- addr_hit[531] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET);
- addr_hit[532] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET);
- addr_hit[533] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET);
- addr_hit[534] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET);
- addr_hit[535] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET);
- addr_hit[536] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET);
- addr_hit[537] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET);
- addr_hit[538] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
- addr_hit[539] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
- addr_hit[540] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
- addr_hit[541] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
- addr_hit[542] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
- addr_hit[543] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
- addr_hit[544] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
- addr_hit[545] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
- addr_hit[546] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
- addr_hit[547] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
- addr_hit[548] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
- addr_hit[549] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
- addr_hit[550] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
- addr_hit[551] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
- addr_hit[552] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
- addr_hit[553] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET);
- addr_hit[554] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET);
- addr_hit[555] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET);
- addr_hit[556] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET);
- addr_hit[557] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET);
- addr_hit[558] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET);
- addr_hit[559] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET);
- addr_hit[560] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET);
- addr_hit[561] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET);
- addr_hit[562] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
- addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
- addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
- addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
- addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
- addr_hit[567] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
- addr_hit[568] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
- addr_hit[569] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
- addr_hit[570] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
- addr_hit[571] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
- addr_hit[572] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
- addr_hit[573] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
- addr_hit[574] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
- addr_hit[575] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
- addr_hit[576] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
- addr_hit[577] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
- addr_hit[578] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
- addr_hit[579] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
- addr_hit[580] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
- addr_hit[581] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
- addr_hit[582] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
- addr_hit[583] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
- addr_hit[584] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
- addr_hit[585] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
- addr_hit[586] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
- addr_hit[587] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
- addr_hit[588] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
- addr_hit[589] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
- addr_hit[590] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
- addr_hit[591] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
- addr_hit[592] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
- addr_hit[593] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
- addr_hit[594] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
- addr_hit[595] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
- addr_hit[596] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
- addr_hit[597] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
- addr_hit[598] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
- addr_hit[599] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
- addr_hit[600] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
- addr_hit[601] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
- addr_hit[602] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
+ addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET);
+ addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET);
+ addr_hit[ 2] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET);
+ addr_hit[ 3] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET);
+ addr_hit[ 4] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET);
+ addr_hit[ 5] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET);
+ addr_hit[ 6] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET);
+ addr_hit[ 7] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET);
+ addr_hit[ 8] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET);
+ addr_hit[ 9] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET);
+ addr_hit[ 10] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET);
+ addr_hit[ 11] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET);
+ addr_hit[ 12] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET);
+ addr_hit[ 13] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET);
+ addr_hit[ 14] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET);
+ addr_hit[ 15] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET);
+ addr_hit[ 16] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET);
+ addr_hit[ 17] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET);
+ addr_hit[ 18] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET);
+ addr_hit[ 19] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET);
+ addr_hit[ 20] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET);
+ addr_hit[ 21] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET);
+ addr_hit[ 22] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET);
+ addr_hit[ 23] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET);
+ addr_hit[ 24] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET);
+ addr_hit[ 25] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET);
+ addr_hit[ 26] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET);
+ addr_hit[ 27] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET);
+ addr_hit[ 28] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET);
+ addr_hit[ 29] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET);
+ addr_hit[ 30] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET);
+ addr_hit[ 31] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET);
+ addr_hit[ 32] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET);
+ addr_hit[ 33] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET);
+ addr_hit[ 34] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET);
+ addr_hit[ 35] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET);
+ addr_hit[ 36] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET);
+ addr_hit[ 37] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET);
+ addr_hit[ 38] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET);
+ addr_hit[ 39] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET);
+ addr_hit[ 40] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET);
+ addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET);
+ addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET);
+ addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET);
+ addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET);
+ addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET);
+ addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET);
+ addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_46_OFFSET);
+ addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_47_OFFSET);
+ addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_48_OFFSET);
+ addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_49_OFFSET);
+ addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_50_OFFSET);
+ addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_51_OFFSET);
+ addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_52_OFFSET);
+ addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_53_OFFSET);
+ addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET);
+ addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET);
+ addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET);
+ addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET);
+ addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET);
+ addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET);
+ addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET);
+ addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET);
+ addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET);
+ addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET);
+ addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET);
+ addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET);
+ addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET);
+ addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET);
+ addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET);
+ addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET);
+ addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET);
+ addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET);
+ addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET);
+ addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET);
+ addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET);
+ addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET);
+ addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET);
+ addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET);
+ addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET);
+ addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET);
+ addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET);
+ addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET);
+ addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET);
+ addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET);
+ addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET);
+ addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET);
+ addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET);
+ addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET);
+ addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET);
+ addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET);
+ addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET);
+ addr_hit[ 92] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET);
+ addr_hit[ 93] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET);
+ addr_hit[ 94] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET);
+ addr_hit[ 95] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET);
+ addr_hit[ 96] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET);
+ addr_hit[ 97] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET);
+ addr_hit[ 98] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET);
+ addr_hit[ 99] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET);
+ addr_hit[100] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET);
+ addr_hit[101] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET);
+ addr_hit[102] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_46_OFFSET);
+ addr_hit[103] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_47_OFFSET);
+ addr_hit[104] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_48_OFFSET);
+ addr_hit[105] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_49_OFFSET);
+ addr_hit[106] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_50_OFFSET);
+ addr_hit[107] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_51_OFFSET);
+ addr_hit[108] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_52_OFFSET);
+ addr_hit[109] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_53_OFFSET);
+ addr_hit[110] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_54_OFFSET);
+ addr_hit[111] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET);
+ addr_hit[112] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET);
+ addr_hit[113] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET);
+ addr_hit[114] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET);
+ addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET);
+ addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET);
+ addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET);
+ addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET);
+ addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET);
+ addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET);
+ addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET);
+ addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET);
+ addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET);
+ addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET);
+ addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET);
+ addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET);
+ addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET);
+ addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET);
+ addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET);
+ addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET);
+ addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET);
+ addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET);
+ addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET);
+ addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET);
+ addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET);
+ addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET);
+ addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET);
+ addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET);
+ addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET);
+ addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET);
+ addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET);
+ addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET);
+ addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET);
+ addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET);
+ addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET);
+ addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET);
+ addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET);
+ addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET);
+ addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET);
+ addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET);
+ addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET);
+ addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET);
+ addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET);
+ addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET);
+ addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET);
+ addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET);
+ addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET);
+ addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
+ addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
+ addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
+ addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
+ addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
+ addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
+ addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
+ addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
+ addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
+ addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
+ addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
+ addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
+ addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
+ addr_hit[171] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
+ addr_hit[172] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
+ addr_hit[173] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
+ addr_hit[174] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
+ addr_hit[175] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
+ addr_hit[176] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
+ addr_hit[177] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
+ addr_hit[178] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
+ addr_hit[179] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
+ addr_hit[180] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
+ addr_hit[181] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
+ addr_hit[182] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
+ addr_hit[183] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
+ addr_hit[184] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
+ addr_hit[185] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
+ addr_hit[186] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
+ addr_hit[187] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
+ addr_hit[188] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
+ addr_hit[189] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
+ addr_hit[190] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET);
+ addr_hit[191] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET);
+ addr_hit[192] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET);
+ addr_hit[193] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET);
+ addr_hit[194] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET);
+ addr_hit[195] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET);
+ addr_hit[196] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET);
+ addr_hit[197] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET);
+ addr_hit[198] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET);
+ addr_hit[199] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET);
+ addr_hit[200] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET);
+ addr_hit[201] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET);
+ addr_hit[202] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET);
+ addr_hit[203] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET);
+ addr_hit[204] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET);
+ addr_hit[205] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
+ addr_hit[206] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
+ addr_hit[207] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
+ addr_hit[208] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
+ addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
+ addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
+ addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
+ addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
+ addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
+ addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
+ addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
+ addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
+ addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
+ addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
+ addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
+ addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
+ addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
+ addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
+ addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
+ addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
+ addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
+ addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
+ addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
+ addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
+ addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
+ addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
+ addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
+ addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
+ addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
+ addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
+ addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
+ addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
+ addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET);
+ addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET);
+ addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET);
+ addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET);
+ addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET);
+ addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET);
+ addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET);
+ addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET);
+ addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET);
+ addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET);
+ addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET);
+ addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET);
+ addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET);
+ addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET);
+ addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET);
+ addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
+ addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
+ addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
+ addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
+ addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
+ addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
+ addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
+ addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
+ addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
+ addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
+ addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
+ addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
+ addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
+ addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
+ addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
+ addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
+ addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
+ addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
+ addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
+ addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
+ addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
+ addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
+ addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
+ addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
+ addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
+ addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
+ addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
+ addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
+ addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
+ addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
+ addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
+ addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
+ addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET);
+ addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET);
+ addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET);
+ addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET);
+ addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET);
+ addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET);
+ addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET);
+ addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET);
+ addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET);
+ addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET);
+ addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET);
+ addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET);
+ addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET);
+ addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET);
+ addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET);
+ addr_hit[299] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
+ addr_hit[300] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
+ addr_hit[301] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
+ addr_hit[302] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
+ addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
+ addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
+ addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
+ addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
+ addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
+ addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
+ addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
+ addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
+ addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
+ addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
+ addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
+ addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET);
+ addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET);
+ addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET);
+ addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET);
+ addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET);
+ addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET);
+ addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET);
+ addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET);
+ addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET);
+ addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
+ addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
+ addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
+ addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
+ addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
+ addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
+ addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
+ addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
+ addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
+ addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
+ addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
+ addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
+ addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
+ addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
+ addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
+ addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET);
+ addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_ATTR_16_OFFSET);
+ addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_ATTR_17_OFFSET);
+ addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_ATTR_18_OFFSET);
+ addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_ATTR_19_OFFSET);
+ addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_ATTR_20_OFFSET);
+ addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_ATTR_21_OFFSET);
+ addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_ATTR_22_OFFSET);
+ addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_ATTR_23_OFFSET);
+ addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET);
+ addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET);
+ addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
+ addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
+ addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
+ addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
+ addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
+ addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
+ addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
+ addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
+ addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
+ addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
+ addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
+ addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
+ addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
+ addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
+ addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
+ addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
+ addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
+ addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
+ addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
+ addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
+ addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
+ addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
+ addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
+ addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
+ addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
+ addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
+ addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
+ addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
+ addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
+ addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
+ addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
+ addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
+ addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET);
+ addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET);
+ addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET);
+ addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET);
+ addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET);
+ addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET);
+ addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET);
+ addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET);
+ addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET);
+ addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET);
+ addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET);
+ addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET);
+ addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET);
+ addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET);
+ addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET);
+ addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
+ addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
+ addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
+ addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
+ addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
+ addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
+ addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
+ addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
+ addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
+ addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
+ addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
+ addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
+ addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
+ addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
+ addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
+ addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
+ addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
+ addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
+ addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
+ addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
+ addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
+ addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
+ addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
+ addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
+ addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
+ addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
+ addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
+ addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
+ addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
+ addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
+ addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
+ addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
+ addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET);
+ addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET);
+ addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET);
+ addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET);
+ addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET);
+ addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET);
+ addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET);
+ addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET);
+ addr_hit[436] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET);
+ addr_hit[437] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET);
+ addr_hit[438] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET);
+ addr_hit[439] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET);
+ addr_hit[440] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET);
+ addr_hit[441] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET);
+ addr_hit[442] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET);
+ addr_hit[443] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
+ addr_hit[444] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
+ addr_hit[445] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
+ addr_hit[446] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
+ addr_hit[447] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
+ addr_hit[448] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
+ addr_hit[449] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
+ addr_hit[450] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
+ addr_hit[451] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
+ addr_hit[452] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
+ addr_hit[453] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
+ addr_hit[454] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
+ addr_hit[455] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
+ addr_hit[456] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
+ addr_hit[457] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
+ addr_hit[458] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
+ addr_hit[459] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
+ addr_hit[460] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
+ addr_hit[461] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
+ addr_hit[462] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
+ addr_hit[463] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
+ addr_hit[464] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
+ addr_hit[465] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
+ addr_hit[466] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
+ addr_hit[467] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
+ addr_hit[468] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
+ addr_hit[469] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
+ addr_hit[470] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
+ addr_hit[471] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
+ addr_hit[472] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
+ addr_hit[473] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
+ addr_hit[474] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
+ addr_hit[475] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET);
+ addr_hit[476] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET);
+ addr_hit[477] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET);
+ addr_hit[478] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET);
+ addr_hit[479] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET);
+ addr_hit[480] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET);
+ addr_hit[481] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET);
+ addr_hit[482] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET);
+ addr_hit[483] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET);
+ addr_hit[484] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET);
+ addr_hit[485] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET);
+ addr_hit[486] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET);
+ addr_hit[487] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET);
+ addr_hit[488] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET);
+ addr_hit[489] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET);
+ addr_hit[490] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
+ addr_hit[491] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
+ addr_hit[492] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
+ addr_hit[493] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
+ addr_hit[494] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
+ addr_hit[495] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
+ addr_hit[496] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
+ addr_hit[497] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
+ addr_hit[498] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
+ addr_hit[499] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
+ addr_hit[500] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
+ addr_hit[501] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
+ addr_hit[502] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
+ addr_hit[503] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
+ addr_hit[504] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
+ addr_hit[505] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
+ addr_hit[506] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET);
+ addr_hit[507] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET);
+ addr_hit[508] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET);
+ addr_hit[509] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET);
+ addr_hit[510] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET);
+ addr_hit[511] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET);
+ addr_hit[512] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET);
+ addr_hit[513] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET);
+ addr_hit[514] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET);
+ addr_hit[515] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
+ addr_hit[516] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
+ addr_hit[517] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
+ addr_hit[518] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
+ addr_hit[519] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
+ addr_hit[520] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
+ addr_hit[521] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
+ addr_hit[522] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
+ addr_hit[523] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
+ addr_hit[524] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
+ addr_hit[525] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
+ addr_hit[526] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
+ addr_hit[527] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
+ addr_hit[528] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
+ addr_hit[529] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
+ addr_hit[530] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET);
+ addr_hit[531] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET);
+ addr_hit[532] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET);
+ addr_hit[533] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET);
+ addr_hit[534] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET);
+ addr_hit[535] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET);
+ addr_hit[536] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET);
+ addr_hit[537] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET);
+ addr_hit[538] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET);
+ addr_hit[539] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
+ addr_hit[540] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
+ addr_hit[541] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
+ addr_hit[542] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
+ addr_hit[543] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
+ addr_hit[544] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
+ addr_hit[545] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
+ addr_hit[546] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
+ addr_hit[547] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
+ addr_hit[548] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
+ addr_hit[549] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
+ addr_hit[550] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
+ addr_hit[551] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
+ addr_hit[552] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
+ addr_hit[553] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
+ addr_hit[554] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET);
+ addr_hit[555] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET);
+ addr_hit[556] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET);
+ addr_hit[557] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET);
+ addr_hit[558] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET);
+ addr_hit[559] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET);
+ addr_hit[560] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET);
+ addr_hit[561] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET);
+ addr_hit[562] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET);
+ addr_hit[563] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
+ addr_hit[564] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
+ addr_hit[565] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
+ addr_hit[566] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
+ addr_hit[567] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
+ addr_hit[568] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
+ addr_hit[569] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
+ addr_hit[570] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
+ addr_hit[571] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
+ addr_hit[572] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
+ addr_hit[573] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
+ addr_hit[574] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
+ addr_hit[575] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
+ addr_hit[576] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
+ addr_hit[577] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
+ addr_hit[578] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
+ addr_hit[579] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
+ addr_hit[580] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
+ addr_hit[581] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
+ addr_hit[582] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
+ addr_hit[583] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
+ addr_hit[584] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
+ addr_hit[585] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
+ addr_hit[586] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
+ addr_hit[587] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
+ addr_hit[588] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
+ addr_hit[589] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
+ addr_hit[590] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
+ addr_hit[591] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
+ addr_hit[592] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
+ addr_hit[593] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
+ addr_hit[594] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
+ addr_hit[595] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
+ addr_hit[596] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
+ addr_hit[597] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
+ addr_hit[598] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
+ addr_hit[599] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
+ addr_hit[600] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
+ addr_hit[601] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
+ addr_hit[602] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
+ addr_hit[603] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -21330,3559 +21349,3567 @@
(addr_hit[599] & (|(PINMUX_PERMIT[599] & ~reg_be))) |
(addr_hit[600] & (|(PINMUX_PERMIT[600] & ~reg_be))) |
(addr_hit[601] & (|(PINMUX_PERMIT[601] & ~reg_be))) |
- (addr_hit[602] & (|(PINMUX_PERMIT[602] & ~reg_be)))));
+ (addr_hit[602] & (|(PINMUX_PERMIT[602] & ~reg_be))) |
+ (addr_hit[603] & (|(PINMUX_PERMIT[603] & ~reg_be)))));
end
- assign mio_periph_insel_regwen_0_we = addr_hit[0] & reg_we & !reg_error;
+ assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
+ assign alert_test_wd = reg_wdata[0];
+
+ assign mio_periph_insel_regwen_0_we = addr_hit[1] & reg_we & !reg_error;
assign mio_periph_insel_regwen_0_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_1_we = addr_hit[1] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_1_we = addr_hit[2] & reg_we & !reg_error;
assign mio_periph_insel_regwen_1_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_2_we = addr_hit[2] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_2_we = addr_hit[3] & reg_we & !reg_error;
assign mio_periph_insel_regwen_2_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_3_we = addr_hit[3] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_3_we = addr_hit[4] & reg_we & !reg_error;
assign mio_periph_insel_regwen_3_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_4_we = addr_hit[4] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_4_we = addr_hit[5] & reg_we & !reg_error;
assign mio_periph_insel_regwen_4_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_5_we = addr_hit[5] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_5_we = addr_hit[6] & reg_we & !reg_error;
assign mio_periph_insel_regwen_5_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_6_we = addr_hit[6] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_6_we = addr_hit[7] & reg_we & !reg_error;
assign mio_periph_insel_regwen_6_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_7_we = addr_hit[7] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_7_we = addr_hit[8] & reg_we & !reg_error;
assign mio_periph_insel_regwen_7_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_8_we = addr_hit[8] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_8_we = addr_hit[9] & reg_we & !reg_error;
assign mio_periph_insel_regwen_8_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_9_we = addr_hit[9] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_9_we = addr_hit[10] & reg_we & !reg_error;
assign mio_periph_insel_regwen_9_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_10_we = addr_hit[10] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_10_we = addr_hit[11] & reg_we & !reg_error;
assign mio_periph_insel_regwen_10_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_11_we = addr_hit[11] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_11_we = addr_hit[12] & reg_we & !reg_error;
assign mio_periph_insel_regwen_11_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_12_we = addr_hit[12] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_12_we = addr_hit[13] & reg_we & !reg_error;
assign mio_periph_insel_regwen_12_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_13_we = addr_hit[13] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_13_we = addr_hit[14] & reg_we & !reg_error;
assign mio_periph_insel_regwen_13_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_14_we = addr_hit[14] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_14_we = addr_hit[15] & reg_we & !reg_error;
assign mio_periph_insel_regwen_14_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_15_we = addr_hit[15] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_15_we = addr_hit[16] & reg_we & !reg_error;
assign mio_periph_insel_regwen_15_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_16_we = addr_hit[16] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_16_we = addr_hit[17] & reg_we & !reg_error;
assign mio_periph_insel_regwen_16_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_17_we = addr_hit[17] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_17_we = addr_hit[18] & reg_we & !reg_error;
assign mio_periph_insel_regwen_17_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_18_we = addr_hit[18] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_18_we = addr_hit[19] & reg_we & !reg_error;
assign mio_periph_insel_regwen_18_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_19_we = addr_hit[19] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_19_we = addr_hit[20] & reg_we & !reg_error;
assign mio_periph_insel_regwen_19_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_20_we = addr_hit[20] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_20_we = addr_hit[21] & reg_we & !reg_error;
assign mio_periph_insel_regwen_20_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_21_we = addr_hit[21] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_21_we = addr_hit[22] & reg_we & !reg_error;
assign mio_periph_insel_regwen_21_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_22_we = addr_hit[22] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_22_we = addr_hit[23] & reg_we & !reg_error;
assign mio_periph_insel_regwen_22_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_23_we = addr_hit[23] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_23_we = addr_hit[24] & reg_we & !reg_error;
assign mio_periph_insel_regwen_23_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_24_we = addr_hit[24] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_24_we = addr_hit[25] & reg_we & !reg_error;
assign mio_periph_insel_regwen_24_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_25_we = addr_hit[25] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_25_we = addr_hit[26] & reg_we & !reg_error;
assign mio_periph_insel_regwen_25_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_26_we = addr_hit[26] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_26_we = addr_hit[27] & reg_we & !reg_error;
assign mio_periph_insel_regwen_26_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_27_we = addr_hit[27] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_27_we = addr_hit[28] & reg_we & !reg_error;
assign mio_periph_insel_regwen_27_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_28_we = addr_hit[28] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_28_we = addr_hit[29] & reg_we & !reg_error;
assign mio_periph_insel_regwen_28_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_29_we = addr_hit[29] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_29_we = addr_hit[30] & reg_we & !reg_error;
assign mio_periph_insel_regwen_29_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_30_we = addr_hit[30] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_30_we = addr_hit[31] & reg_we & !reg_error;
assign mio_periph_insel_regwen_30_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_31_we = addr_hit[31] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_31_we = addr_hit[32] & reg_we & !reg_error;
assign mio_periph_insel_regwen_31_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_32_we = addr_hit[32] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_32_we = addr_hit[33] & reg_we & !reg_error;
assign mio_periph_insel_regwen_32_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_33_we = addr_hit[33] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_33_we = addr_hit[34] & reg_we & !reg_error;
assign mio_periph_insel_regwen_33_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_34_we = addr_hit[34] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_34_we = addr_hit[35] & reg_we & !reg_error;
assign mio_periph_insel_regwen_34_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_35_we = addr_hit[35] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_35_we = addr_hit[36] & reg_we & !reg_error;
assign mio_periph_insel_regwen_35_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_36_we = addr_hit[36] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_36_we = addr_hit[37] & reg_we & !reg_error;
assign mio_periph_insel_regwen_36_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_37_we = addr_hit[37] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_37_we = addr_hit[38] & reg_we & !reg_error;
assign mio_periph_insel_regwen_37_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_38_we = addr_hit[38] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_38_we = addr_hit[39] & reg_we & !reg_error;
assign mio_periph_insel_regwen_38_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_39_we = addr_hit[39] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_39_we = addr_hit[40] & reg_we & !reg_error;
assign mio_periph_insel_regwen_39_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_40_we = addr_hit[40] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_40_we = addr_hit[41] & reg_we & !reg_error;
assign mio_periph_insel_regwen_40_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_41_we = addr_hit[41] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_41_we = addr_hit[42] & reg_we & !reg_error;
assign mio_periph_insel_regwen_41_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_42_we = addr_hit[42] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_42_we = addr_hit[43] & reg_we & !reg_error;
assign mio_periph_insel_regwen_42_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_43_we = addr_hit[43] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_43_we = addr_hit[44] & reg_we & !reg_error;
assign mio_periph_insel_regwen_43_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_44_we = addr_hit[44] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_44_we = addr_hit[45] & reg_we & !reg_error;
assign mio_periph_insel_regwen_44_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_45_we = addr_hit[45] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_45_we = addr_hit[46] & reg_we & !reg_error;
assign mio_periph_insel_regwen_45_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_46_we = addr_hit[46] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_46_we = addr_hit[47] & reg_we & !reg_error;
assign mio_periph_insel_regwen_46_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_47_we = addr_hit[47] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_47_we = addr_hit[48] & reg_we & !reg_error;
assign mio_periph_insel_regwen_47_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_48_we = addr_hit[48] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_48_we = addr_hit[49] & reg_we & !reg_error;
assign mio_periph_insel_regwen_48_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_49_we = addr_hit[49] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_49_we = addr_hit[50] & reg_we & !reg_error;
assign mio_periph_insel_regwen_49_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_50_we = addr_hit[50] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_50_we = addr_hit[51] & reg_we & !reg_error;
assign mio_periph_insel_regwen_50_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_51_we = addr_hit[51] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_51_we = addr_hit[52] & reg_we & !reg_error;
assign mio_periph_insel_regwen_51_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_52_we = addr_hit[52] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_52_we = addr_hit[53] & reg_we & !reg_error;
assign mio_periph_insel_regwen_52_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_53_we = addr_hit[53] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_53_we = addr_hit[54] & reg_we & !reg_error;
assign mio_periph_insel_regwen_53_wd = reg_wdata[0];
- assign mio_periph_insel_regwen_54_we = addr_hit[54] & reg_we & !reg_error;
+ assign mio_periph_insel_regwen_54_we = addr_hit[55] & reg_we & !reg_error;
assign mio_periph_insel_regwen_54_wd = reg_wdata[0];
- assign mio_periph_insel_0_we = addr_hit[55] & reg_we & !reg_error;
+ assign mio_periph_insel_0_we = addr_hit[56] & reg_we & !reg_error;
assign mio_periph_insel_0_wd = reg_wdata[5:0];
- assign mio_periph_insel_1_we = addr_hit[56] & reg_we & !reg_error;
+ assign mio_periph_insel_1_we = addr_hit[57] & reg_we & !reg_error;
assign mio_periph_insel_1_wd = reg_wdata[5:0];
- assign mio_periph_insel_2_we = addr_hit[57] & reg_we & !reg_error;
+ assign mio_periph_insel_2_we = addr_hit[58] & reg_we & !reg_error;
assign mio_periph_insel_2_wd = reg_wdata[5:0];
- assign mio_periph_insel_3_we = addr_hit[58] & reg_we & !reg_error;
+ assign mio_periph_insel_3_we = addr_hit[59] & reg_we & !reg_error;
assign mio_periph_insel_3_wd = reg_wdata[5:0];
- assign mio_periph_insel_4_we = addr_hit[59] & reg_we & !reg_error;
+ assign mio_periph_insel_4_we = addr_hit[60] & reg_we & !reg_error;
assign mio_periph_insel_4_wd = reg_wdata[5:0];
- assign mio_periph_insel_5_we = addr_hit[60] & reg_we & !reg_error;
+ assign mio_periph_insel_5_we = addr_hit[61] & reg_we & !reg_error;
assign mio_periph_insel_5_wd = reg_wdata[5:0];
- assign mio_periph_insel_6_we = addr_hit[61] & reg_we & !reg_error;
+ assign mio_periph_insel_6_we = addr_hit[62] & reg_we & !reg_error;
assign mio_periph_insel_6_wd = reg_wdata[5:0];
- assign mio_periph_insel_7_we = addr_hit[62] & reg_we & !reg_error;
+ assign mio_periph_insel_7_we = addr_hit[63] & reg_we & !reg_error;
assign mio_periph_insel_7_wd = reg_wdata[5:0];
- assign mio_periph_insel_8_we = addr_hit[63] & reg_we & !reg_error;
+ assign mio_periph_insel_8_we = addr_hit[64] & reg_we & !reg_error;
assign mio_periph_insel_8_wd = reg_wdata[5:0];
- assign mio_periph_insel_9_we = addr_hit[64] & reg_we & !reg_error;
+ assign mio_periph_insel_9_we = addr_hit[65] & reg_we & !reg_error;
assign mio_periph_insel_9_wd = reg_wdata[5:0];
- assign mio_periph_insel_10_we = addr_hit[65] & reg_we & !reg_error;
+ assign mio_periph_insel_10_we = addr_hit[66] & reg_we & !reg_error;
assign mio_periph_insel_10_wd = reg_wdata[5:0];
- assign mio_periph_insel_11_we = addr_hit[66] & reg_we & !reg_error;
+ assign mio_periph_insel_11_we = addr_hit[67] & reg_we & !reg_error;
assign mio_periph_insel_11_wd = reg_wdata[5:0];
- assign mio_periph_insel_12_we = addr_hit[67] & reg_we & !reg_error;
+ assign mio_periph_insel_12_we = addr_hit[68] & reg_we & !reg_error;
assign mio_periph_insel_12_wd = reg_wdata[5:0];
- assign mio_periph_insel_13_we = addr_hit[68] & reg_we & !reg_error;
+ assign mio_periph_insel_13_we = addr_hit[69] & reg_we & !reg_error;
assign mio_periph_insel_13_wd = reg_wdata[5:0];
- assign mio_periph_insel_14_we = addr_hit[69] & reg_we & !reg_error;
+ assign mio_periph_insel_14_we = addr_hit[70] & reg_we & !reg_error;
assign mio_periph_insel_14_wd = reg_wdata[5:0];
- assign mio_periph_insel_15_we = addr_hit[70] & reg_we & !reg_error;
+ assign mio_periph_insel_15_we = addr_hit[71] & reg_we & !reg_error;
assign mio_periph_insel_15_wd = reg_wdata[5:0];
- assign mio_periph_insel_16_we = addr_hit[71] & reg_we & !reg_error;
+ assign mio_periph_insel_16_we = addr_hit[72] & reg_we & !reg_error;
assign mio_periph_insel_16_wd = reg_wdata[5:0];
- assign mio_periph_insel_17_we = addr_hit[72] & reg_we & !reg_error;
+ assign mio_periph_insel_17_we = addr_hit[73] & reg_we & !reg_error;
assign mio_periph_insel_17_wd = reg_wdata[5:0];
- assign mio_periph_insel_18_we = addr_hit[73] & reg_we & !reg_error;
+ assign mio_periph_insel_18_we = addr_hit[74] & reg_we & !reg_error;
assign mio_periph_insel_18_wd = reg_wdata[5:0];
- assign mio_periph_insel_19_we = addr_hit[74] & reg_we & !reg_error;
+ assign mio_periph_insel_19_we = addr_hit[75] & reg_we & !reg_error;
assign mio_periph_insel_19_wd = reg_wdata[5:0];
- assign mio_periph_insel_20_we = addr_hit[75] & reg_we & !reg_error;
+ assign mio_periph_insel_20_we = addr_hit[76] & reg_we & !reg_error;
assign mio_periph_insel_20_wd = reg_wdata[5:0];
- assign mio_periph_insel_21_we = addr_hit[76] & reg_we & !reg_error;
+ assign mio_periph_insel_21_we = addr_hit[77] & reg_we & !reg_error;
assign mio_periph_insel_21_wd = reg_wdata[5:0];
- assign mio_periph_insel_22_we = addr_hit[77] & reg_we & !reg_error;
+ assign mio_periph_insel_22_we = addr_hit[78] & reg_we & !reg_error;
assign mio_periph_insel_22_wd = reg_wdata[5:0];
- assign mio_periph_insel_23_we = addr_hit[78] & reg_we & !reg_error;
+ assign mio_periph_insel_23_we = addr_hit[79] & reg_we & !reg_error;
assign mio_periph_insel_23_wd = reg_wdata[5:0];
- assign mio_periph_insel_24_we = addr_hit[79] & reg_we & !reg_error;
+ assign mio_periph_insel_24_we = addr_hit[80] & reg_we & !reg_error;
assign mio_periph_insel_24_wd = reg_wdata[5:0];
- assign mio_periph_insel_25_we = addr_hit[80] & reg_we & !reg_error;
+ assign mio_periph_insel_25_we = addr_hit[81] & reg_we & !reg_error;
assign mio_periph_insel_25_wd = reg_wdata[5:0];
- assign mio_periph_insel_26_we = addr_hit[81] & reg_we & !reg_error;
+ assign mio_periph_insel_26_we = addr_hit[82] & reg_we & !reg_error;
assign mio_periph_insel_26_wd = reg_wdata[5:0];
- assign mio_periph_insel_27_we = addr_hit[82] & reg_we & !reg_error;
+ assign mio_periph_insel_27_we = addr_hit[83] & reg_we & !reg_error;
assign mio_periph_insel_27_wd = reg_wdata[5:0];
- assign mio_periph_insel_28_we = addr_hit[83] & reg_we & !reg_error;
+ assign mio_periph_insel_28_we = addr_hit[84] & reg_we & !reg_error;
assign mio_periph_insel_28_wd = reg_wdata[5:0];
- assign mio_periph_insel_29_we = addr_hit[84] & reg_we & !reg_error;
+ assign mio_periph_insel_29_we = addr_hit[85] & reg_we & !reg_error;
assign mio_periph_insel_29_wd = reg_wdata[5:0];
- assign mio_periph_insel_30_we = addr_hit[85] & reg_we & !reg_error;
+ assign mio_periph_insel_30_we = addr_hit[86] & reg_we & !reg_error;
assign mio_periph_insel_30_wd = reg_wdata[5:0];
- assign mio_periph_insel_31_we = addr_hit[86] & reg_we & !reg_error;
+ assign mio_periph_insel_31_we = addr_hit[87] & reg_we & !reg_error;
assign mio_periph_insel_31_wd = reg_wdata[5:0];
- assign mio_periph_insel_32_we = addr_hit[87] & reg_we & !reg_error;
+ assign mio_periph_insel_32_we = addr_hit[88] & reg_we & !reg_error;
assign mio_periph_insel_32_wd = reg_wdata[5:0];
- assign mio_periph_insel_33_we = addr_hit[88] & reg_we & !reg_error;
+ assign mio_periph_insel_33_we = addr_hit[89] & reg_we & !reg_error;
assign mio_periph_insel_33_wd = reg_wdata[5:0];
- assign mio_periph_insel_34_we = addr_hit[89] & reg_we & !reg_error;
+ assign mio_periph_insel_34_we = addr_hit[90] & reg_we & !reg_error;
assign mio_periph_insel_34_wd = reg_wdata[5:0];
- assign mio_periph_insel_35_we = addr_hit[90] & reg_we & !reg_error;
+ assign mio_periph_insel_35_we = addr_hit[91] & reg_we & !reg_error;
assign mio_periph_insel_35_wd = reg_wdata[5:0];
- assign mio_periph_insel_36_we = addr_hit[91] & reg_we & !reg_error;
+ assign mio_periph_insel_36_we = addr_hit[92] & reg_we & !reg_error;
assign mio_periph_insel_36_wd = reg_wdata[5:0];
- assign mio_periph_insel_37_we = addr_hit[92] & reg_we & !reg_error;
+ assign mio_periph_insel_37_we = addr_hit[93] & reg_we & !reg_error;
assign mio_periph_insel_37_wd = reg_wdata[5:0];
- assign mio_periph_insel_38_we = addr_hit[93] & reg_we & !reg_error;
+ assign mio_periph_insel_38_we = addr_hit[94] & reg_we & !reg_error;
assign mio_periph_insel_38_wd = reg_wdata[5:0];
- assign mio_periph_insel_39_we = addr_hit[94] & reg_we & !reg_error;
+ assign mio_periph_insel_39_we = addr_hit[95] & reg_we & !reg_error;
assign mio_periph_insel_39_wd = reg_wdata[5:0];
- assign mio_periph_insel_40_we = addr_hit[95] & reg_we & !reg_error;
+ assign mio_periph_insel_40_we = addr_hit[96] & reg_we & !reg_error;
assign mio_periph_insel_40_wd = reg_wdata[5:0];
- assign mio_periph_insel_41_we = addr_hit[96] & reg_we & !reg_error;
+ assign mio_periph_insel_41_we = addr_hit[97] & reg_we & !reg_error;
assign mio_periph_insel_41_wd = reg_wdata[5:0];
- assign mio_periph_insel_42_we = addr_hit[97] & reg_we & !reg_error;
+ assign mio_periph_insel_42_we = addr_hit[98] & reg_we & !reg_error;
assign mio_periph_insel_42_wd = reg_wdata[5:0];
- assign mio_periph_insel_43_we = addr_hit[98] & reg_we & !reg_error;
+ assign mio_periph_insel_43_we = addr_hit[99] & reg_we & !reg_error;
assign mio_periph_insel_43_wd = reg_wdata[5:0];
- assign mio_periph_insel_44_we = addr_hit[99] & reg_we & !reg_error;
+ assign mio_periph_insel_44_we = addr_hit[100] & reg_we & !reg_error;
assign mio_periph_insel_44_wd = reg_wdata[5:0];
- assign mio_periph_insel_45_we = addr_hit[100] & reg_we & !reg_error;
+ assign mio_periph_insel_45_we = addr_hit[101] & reg_we & !reg_error;
assign mio_periph_insel_45_wd = reg_wdata[5:0];
- assign mio_periph_insel_46_we = addr_hit[101] & reg_we & !reg_error;
+ assign mio_periph_insel_46_we = addr_hit[102] & reg_we & !reg_error;
assign mio_periph_insel_46_wd = reg_wdata[5:0];
- assign mio_periph_insel_47_we = addr_hit[102] & reg_we & !reg_error;
+ assign mio_periph_insel_47_we = addr_hit[103] & reg_we & !reg_error;
assign mio_periph_insel_47_wd = reg_wdata[5:0];
- assign mio_periph_insel_48_we = addr_hit[103] & reg_we & !reg_error;
+ assign mio_periph_insel_48_we = addr_hit[104] & reg_we & !reg_error;
assign mio_periph_insel_48_wd = reg_wdata[5:0];
- assign mio_periph_insel_49_we = addr_hit[104] & reg_we & !reg_error;
+ assign mio_periph_insel_49_we = addr_hit[105] & reg_we & !reg_error;
assign mio_periph_insel_49_wd = reg_wdata[5:0];
- assign mio_periph_insel_50_we = addr_hit[105] & reg_we & !reg_error;
+ assign mio_periph_insel_50_we = addr_hit[106] & reg_we & !reg_error;
assign mio_periph_insel_50_wd = reg_wdata[5:0];
- assign mio_periph_insel_51_we = addr_hit[106] & reg_we & !reg_error;
+ assign mio_periph_insel_51_we = addr_hit[107] & reg_we & !reg_error;
assign mio_periph_insel_51_wd = reg_wdata[5:0];
- assign mio_periph_insel_52_we = addr_hit[107] & reg_we & !reg_error;
+ assign mio_periph_insel_52_we = addr_hit[108] & reg_we & !reg_error;
assign mio_periph_insel_52_wd = reg_wdata[5:0];
- assign mio_periph_insel_53_we = addr_hit[108] & reg_we & !reg_error;
+ assign mio_periph_insel_53_we = addr_hit[109] & reg_we & !reg_error;
assign mio_periph_insel_53_wd = reg_wdata[5:0];
- assign mio_periph_insel_54_we = addr_hit[109] & reg_we & !reg_error;
+ assign mio_periph_insel_54_we = addr_hit[110] & reg_we & !reg_error;
assign mio_periph_insel_54_wd = reg_wdata[5:0];
- assign mio_outsel_regwen_0_we = addr_hit[110] & reg_we & !reg_error;
+ assign mio_outsel_regwen_0_we = addr_hit[111] & reg_we & !reg_error;
assign mio_outsel_regwen_0_wd = reg_wdata[0];
- assign mio_outsel_regwen_1_we = addr_hit[111] & reg_we & !reg_error;
+ assign mio_outsel_regwen_1_we = addr_hit[112] & reg_we & !reg_error;
assign mio_outsel_regwen_1_wd = reg_wdata[0];
- assign mio_outsel_regwen_2_we = addr_hit[112] & reg_we & !reg_error;
+ assign mio_outsel_regwen_2_we = addr_hit[113] & reg_we & !reg_error;
assign mio_outsel_regwen_2_wd = reg_wdata[0];
- assign mio_outsel_regwen_3_we = addr_hit[113] & reg_we & !reg_error;
+ assign mio_outsel_regwen_3_we = addr_hit[114] & reg_we & !reg_error;
assign mio_outsel_regwen_3_wd = reg_wdata[0];
- assign mio_outsel_regwen_4_we = addr_hit[114] & reg_we & !reg_error;
+ assign mio_outsel_regwen_4_we = addr_hit[115] & reg_we & !reg_error;
assign mio_outsel_regwen_4_wd = reg_wdata[0];
- assign mio_outsel_regwen_5_we = addr_hit[115] & reg_we & !reg_error;
+ assign mio_outsel_regwen_5_we = addr_hit[116] & reg_we & !reg_error;
assign mio_outsel_regwen_5_wd = reg_wdata[0];
- assign mio_outsel_regwen_6_we = addr_hit[116] & reg_we & !reg_error;
+ assign mio_outsel_regwen_6_we = addr_hit[117] & reg_we & !reg_error;
assign mio_outsel_regwen_6_wd = reg_wdata[0];
- assign mio_outsel_regwen_7_we = addr_hit[117] & reg_we & !reg_error;
+ assign mio_outsel_regwen_7_we = addr_hit[118] & reg_we & !reg_error;
assign mio_outsel_regwen_7_wd = reg_wdata[0];
- assign mio_outsel_regwen_8_we = addr_hit[118] & reg_we & !reg_error;
+ assign mio_outsel_regwen_8_we = addr_hit[119] & reg_we & !reg_error;
assign mio_outsel_regwen_8_wd = reg_wdata[0];
- assign mio_outsel_regwen_9_we = addr_hit[119] & reg_we & !reg_error;
+ assign mio_outsel_regwen_9_we = addr_hit[120] & reg_we & !reg_error;
assign mio_outsel_regwen_9_wd = reg_wdata[0];
- assign mio_outsel_regwen_10_we = addr_hit[120] & reg_we & !reg_error;
+ assign mio_outsel_regwen_10_we = addr_hit[121] & reg_we & !reg_error;
assign mio_outsel_regwen_10_wd = reg_wdata[0];
- assign mio_outsel_regwen_11_we = addr_hit[121] & reg_we & !reg_error;
+ assign mio_outsel_regwen_11_we = addr_hit[122] & reg_we & !reg_error;
assign mio_outsel_regwen_11_wd = reg_wdata[0];
- assign mio_outsel_regwen_12_we = addr_hit[122] & reg_we & !reg_error;
+ assign mio_outsel_regwen_12_we = addr_hit[123] & reg_we & !reg_error;
assign mio_outsel_regwen_12_wd = reg_wdata[0];
- assign mio_outsel_regwen_13_we = addr_hit[123] & reg_we & !reg_error;
+ assign mio_outsel_regwen_13_we = addr_hit[124] & reg_we & !reg_error;
assign mio_outsel_regwen_13_wd = reg_wdata[0];
- assign mio_outsel_regwen_14_we = addr_hit[124] & reg_we & !reg_error;
+ assign mio_outsel_regwen_14_we = addr_hit[125] & reg_we & !reg_error;
assign mio_outsel_regwen_14_wd = reg_wdata[0];
- assign mio_outsel_regwen_15_we = addr_hit[125] & reg_we & !reg_error;
+ assign mio_outsel_regwen_15_we = addr_hit[126] & reg_we & !reg_error;
assign mio_outsel_regwen_15_wd = reg_wdata[0];
- assign mio_outsel_regwen_16_we = addr_hit[126] & reg_we & !reg_error;
+ assign mio_outsel_regwen_16_we = addr_hit[127] & reg_we & !reg_error;
assign mio_outsel_regwen_16_wd = reg_wdata[0];
- assign mio_outsel_regwen_17_we = addr_hit[127] & reg_we & !reg_error;
+ assign mio_outsel_regwen_17_we = addr_hit[128] & reg_we & !reg_error;
assign mio_outsel_regwen_17_wd = reg_wdata[0];
- assign mio_outsel_regwen_18_we = addr_hit[128] & reg_we & !reg_error;
+ assign mio_outsel_regwen_18_we = addr_hit[129] & reg_we & !reg_error;
assign mio_outsel_regwen_18_wd = reg_wdata[0];
- assign mio_outsel_regwen_19_we = addr_hit[129] & reg_we & !reg_error;
+ assign mio_outsel_regwen_19_we = addr_hit[130] & reg_we & !reg_error;
assign mio_outsel_regwen_19_wd = reg_wdata[0];
- assign mio_outsel_regwen_20_we = addr_hit[130] & reg_we & !reg_error;
+ assign mio_outsel_regwen_20_we = addr_hit[131] & reg_we & !reg_error;
assign mio_outsel_regwen_20_wd = reg_wdata[0];
- assign mio_outsel_regwen_21_we = addr_hit[131] & reg_we & !reg_error;
+ assign mio_outsel_regwen_21_we = addr_hit[132] & reg_we & !reg_error;
assign mio_outsel_regwen_21_wd = reg_wdata[0];
- assign mio_outsel_regwen_22_we = addr_hit[132] & reg_we & !reg_error;
+ assign mio_outsel_regwen_22_we = addr_hit[133] & reg_we & !reg_error;
assign mio_outsel_regwen_22_wd = reg_wdata[0];
- assign mio_outsel_regwen_23_we = addr_hit[133] & reg_we & !reg_error;
+ assign mio_outsel_regwen_23_we = addr_hit[134] & reg_we & !reg_error;
assign mio_outsel_regwen_23_wd = reg_wdata[0];
- assign mio_outsel_regwen_24_we = addr_hit[134] & reg_we & !reg_error;
+ assign mio_outsel_regwen_24_we = addr_hit[135] & reg_we & !reg_error;
assign mio_outsel_regwen_24_wd = reg_wdata[0];
- assign mio_outsel_regwen_25_we = addr_hit[135] & reg_we & !reg_error;
+ assign mio_outsel_regwen_25_we = addr_hit[136] & reg_we & !reg_error;
assign mio_outsel_regwen_25_wd = reg_wdata[0];
- assign mio_outsel_regwen_26_we = addr_hit[136] & reg_we & !reg_error;
+ assign mio_outsel_regwen_26_we = addr_hit[137] & reg_we & !reg_error;
assign mio_outsel_regwen_26_wd = reg_wdata[0];
- assign mio_outsel_regwen_27_we = addr_hit[137] & reg_we & !reg_error;
+ assign mio_outsel_regwen_27_we = addr_hit[138] & reg_we & !reg_error;
assign mio_outsel_regwen_27_wd = reg_wdata[0];
- assign mio_outsel_regwen_28_we = addr_hit[138] & reg_we & !reg_error;
+ assign mio_outsel_regwen_28_we = addr_hit[139] & reg_we & !reg_error;
assign mio_outsel_regwen_28_wd = reg_wdata[0];
- assign mio_outsel_regwen_29_we = addr_hit[139] & reg_we & !reg_error;
+ assign mio_outsel_regwen_29_we = addr_hit[140] & reg_we & !reg_error;
assign mio_outsel_regwen_29_wd = reg_wdata[0];
- assign mio_outsel_regwen_30_we = addr_hit[140] & reg_we & !reg_error;
+ assign mio_outsel_regwen_30_we = addr_hit[141] & reg_we & !reg_error;
assign mio_outsel_regwen_30_wd = reg_wdata[0];
- assign mio_outsel_regwen_31_we = addr_hit[141] & reg_we & !reg_error;
+ assign mio_outsel_regwen_31_we = addr_hit[142] & reg_we & !reg_error;
assign mio_outsel_regwen_31_wd = reg_wdata[0];
- assign mio_outsel_regwen_32_we = addr_hit[142] & reg_we & !reg_error;
+ assign mio_outsel_regwen_32_we = addr_hit[143] & reg_we & !reg_error;
assign mio_outsel_regwen_32_wd = reg_wdata[0];
- assign mio_outsel_regwen_33_we = addr_hit[143] & reg_we & !reg_error;
+ assign mio_outsel_regwen_33_we = addr_hit[144] & reg_we & !reg_error;
assign mio_outsel_regwen_33_wd = reg_wdata[0];
- assign mio_outsel_regwen_34_we = addr_hit[144] & reg_we & !reg_error;
+ assign mio_outsel_regwen_34_we = addr_hit[145] & reg_we & !reg_error;
assign mio_outsel_regwen_34_wd = reg_wdata[0];
- assign mio_outsel_regwen_35_we = addr_hit[145] & reg_we & !reg_error;
+ assign mio_outsel_regwen_35_we = addr_hit[146] & reg_we & !reg_error;
assign mio_outsel_regwen_35_wd = reg_wdata[0];
- assign mio_outsel_regwen_36_we = addr_hit[146] & reg_we & !reg_error;
+ assign mio_outsel_regwen_36_we = addr_hit[147] & reg_we & !reg_error;
assign mio_outsel_regwen_36_wd = reg_wdata[0];
- assign mio_outsel_regwen_37_we = addr_hit[147] & reg_we & !reg_error;
+ assign mio_outsel_regwen_37_we = addr_hit[148] & reg_we & !reg_error;
assign mio_outsel_regwen_37_wd = reg_wdata[0];
- assign mio_outsel_regwen_38_we = addr_hit[148] & reg_we & !reg_error;
+ assign mio_outsel_regwen_38_we = addr_hit[149] & reg_we & !reg_error;
assign mio_outsel_regwen_38_wd = reg_wdata[0];
- assign mio_outsel_regwen_39_we = addr_hit[149] & reg_we & !reg_error;
+ assign mio_outsel_regwen_39_we = addr_hit[150] & reg_we & !reg_error;
assign mio_outsel_regwen_39_wd = reg_wdata[0];
- assign mio_outsel_regwen_40_we = addr_hit[150] & reg_we & !reg_error;
+ assign mio_outsel_regwen_40_we = addr_hit[151] & reg_we & !reg_error;
assign mio_outsel_regwen_40_wd = reg_wdata[0];
- assign mio_outsel_regwen_41_we = addr_hit[151] & reg_we & !reg_error;
+ assign mio_outsel_regwen_41_we = addr_hit[152] & reg_we & !reg_error;
assign mio_outsel_regwen_41_wd = reg_wdata[0];
- assign mio_outsel_regwen_42_we = addr_hit[152] & reg_we & !reg_error;
+ assign mio_outsel_regwen_42_we = addr_hit[153] & reg_we & !reg_error;
assign mio_outsel_regwen_42_wd = reg_wdata[0];
- assign mio_outsel_regwen_43_we = addr_hit[153] & reg_we & !reg_error;
+ assign mio_outsel_regwen_43_we = addr_hit[154] & reg_we & !reg_error;
assign mio_outsel_regwen_43_wd = reg_wdata[0];
- assign mio_outsel_regwen_44_we = addr_hit[154] & reg_we & !reg_error;
+ assign mio_outsel_regwen_44_we = addr_hit[155] & reg_we & !reg_error;
assign mio_outsel_regwen_44_wd = reg_wdata[0];
- assign mio_outsel_regwen_45_we = addr_hit[155] & reg_we & !reg_error;
+ assign mio_outsel_regwen_45_we = addr_hit[156] & reg_we & !reg_error;
assign mio_outsel_regwen_45_wd = reg_wdata[0];
- assign mio_outsel_regwen_46_we = addr_hit[156] & reg_we & !reg_error;
+ assign mio_outsel_regwen_46_we = addr_hit[157] & reg_we & !reg_error;
assign mio_outsel_regwen_46_wd = reg_wdata[0];
- assign mio_outsel_0_we = addr_hit[157] & reg_we & !reg_error;
+ assign mio_outsel_0_we = addr_hit[158] & reg_we & !reg_error;
assign mio_outsel_0_wd = reg_wdata[6:0];
- assign mio_outsel_1_we = addr_hit[158] & reg_we & !reg_error;
+ assign mio_outsel_1_we = addr_hit[159] & reg_we & !reg_error;
assign mio_outsel_1_wd = reg_wdata[6:0];
- assign mio_outsel_2_we = addr_hit[159] & reg_we & !reg_error;
+ assign mio_outsel_2_we = addr_hit[160] & reg_we & !reg_error;
assign mio_outsel_2_wd = reg_wdata[6:0];
- assign mio_outsel_3_we = addr_hit[160] & reg_we & !reg_error;
+ assign mio_outsel_3_we = addr_hit[161] & reg_we & !reg_error;
assign mio_outsel_3_wd = reg_wdata[6:0];
- assign mio_outsel_4_we = addr_hit[161] & reg_we & !reg_error;
+ assign mio_outsel_4_we = addr_hit[162] & reg_we & !reg_error;
assign mio_outsel_4_wd = reg_wdata[6:0];
- assign mio_outsel_5_we = addr_hit[162] & reg_we & !reg_error;
+ assign mio_outsel_5_we = addr_hit[163] & reg_we & !reg_error;
assign mio_outsel_5_wd = reg_wdata[6:0];
- assign mio_outsel_6_we = addr_hit[163] & reg_we & !reg_error;
+ assign mio_outsel_6_we = addr_hit[164] & reg_we & !reg_error;
assign mio_outsel_6_wd = reg_wdata[6:0];
- assign mio_outsel_7_we = addr_hit[164] & reg_we & !reg_error;
+ assign mio_outsel_7_we = addr_hit[165] & reg_we & !reg_error;
assign mio_outsel_7_wd = reg_wdata[6:0];
- assign mio_outsel_8_we = addr_hit[165] & reg_we & !reg_error;
+ assign mio_outsel_8_we = addr_hit[166] & reg_we & !reg_error;
assign mio_outsel_8_wd = reg_wdata[6:0];
- assign mio_outsel_9_we = addr_hit[166] & reg_we & !reg_error;
+ assign mio_outsel_9_we = addr_hit[167] & reg_we & !reg_error;
assign mio_outsel_9_wd = reg_wdata[6:0];
- assign mio_outsel_10_we = addr_hit[167] & reg_we & !reg_error;
+ assign mio_outsel_10_we = addr_hit[168] & reg_we & !reg_error;
assign mio_outsel_10_wd = reg_wdata[6:0];
- assign mio_outsel_11_we = addr_hit[168] & reg_we & !reg_error;
+ assign mio_outsel_11_we = addr_hit[169] & reg_we & !reg_error;
assign mio_outsel_11_wd = reg_wdata[6:0];
- assign mio_outsel_12_we = addr_hit[169] & reg_we & !reg_error;
+ assign mio_outsel_12_we = addr_hit[170] & reg_we & !reg_error;
assign mio_outsel_12_wd = reg_wdata[6:0];
- assign mio_outsel_13_we = addr_hit[170] & reg_we & !reg_error;
+ assign mio_outsel_13_we = addr_hit[171] & reg_we & !reg_error;
assign mio_outsel_13_wd = reg_wdata[6:0];
- assign mio_outsel_14_we = addr_hit[171] & reg_we & !reg_error;
+ assign mio_outsel_14_we = addr_hit[172] & reg_we & !reg_error;
assign mio_outsel_14_wd = reg_wdata[6:0];
- assign mio_outsel_15_we = addr_hit[172] & reg_we & !reg_error;
+ assign mio_outsel_15_we = addr_hit[173] & reg_we & !reg_error;
assign mio_outsel_15_wd = reg_wdata[6:0];
- assign mio_outsel_16_we = addr_hit[173] & reg_we & !reg_error;
+ assign mio_outsel_16_we = addr_hit[174] & reg_we & !reg_error;
assign mio_outsel_16_wd = reg_wdata[6:0];
- assign mio_outsel_17_we = addr_hit[174] & reg_we & !reg_error;
+ assign mio_outsel_17_we = addr_hit[175] & reg_we & !reg_error;
assign mio_outsel_17_wd = reg_wdata[6:0];
- assign mio_outsel_18_we = addr_hit[175] & reg_we & !reg_error;
+ assign mio_outsel_18_we = addr_hit[176] & reg_we & !reg_error;
assign mio_outsel_18_wd = reg_wdata[6:0];
- assign mio_outsel_19_we = addr_hit[176] & reg_we & !reg_error;
+ assign mio_outsel_19_we = addr_hit[177] & reg_we & !reg_error;
assign mio_outsel_19_wd = reg_wdata[6:0];
- assign mio_outsel_20_we = addr_hit[177] & reg_we & !reg_error;
+ assign mio_outsel_20_we = addr_hit[178] & reg_we & !reg_error;
assign mio_outsel_20_wd = reg_wdata[6:0];
- assign mio_outsel_21_we = addr_hit[178] & reg_we & !reg_error;
+ assign mio_outsel_21_we = addr_hit[179] & reg_we & !reg_error;
assign mio_outsel_21_wd = reg_wdata[6:0];
- assign mio_outsel_22_we = addr_hit[179] & reg_we & !reg_error;
+ assign mio_outsel_22_we = addr_hit[180] & reg_we & !reg_error;
assign mio_outsel_22_wd = reg_wdata[6:0];
- assign mio_outsel_23_we = addr_hit[180] & reg_we & !reg_error;
+ assign mio_outsel_23_we = addr_hit[181] & reg_we & !reg_error;
assign mio_outsel_23_wd = reg_wdata[6:0];
- assign mio_outsel_24_we = addr_hit[181] & reg_we & !reg_error;
+ assign mio_outsel_24_we = addr_hit[182] & reg_we & !reg_error;
assign mio_outsel_24_wd = reg_wdata[6:0];
- assign mio_outsel_25_we = addr_hit[182] & reg_we & !reg_error;
+ assign mio_outsel_25_we = addr_hit[183] & reg_we & !reg_error;
assign mio_outsel_25_wd = reg_wdata[6:0];
- assign mio_outsel_26_we = addr_hit[183] & reg_we & !reg_error;
+ assign mio_outsel_26_we = addr_hit[184] & reg_we & !reg_error;
assign mio_outsel_26_wd = reg_wdata[6:0];
- assign mio_outsel_27_we = addr_hit[184] & reg_we & !reg_error;
+ assign mio_outsel_27_we = addr_hit[185] & reg_we & !reg_error;
assign mio_outsel_27_wd = reg_wdata[6:0];
- assign mio_outsel_28_we = addr_hit[185] & reg_we & !reg_error;
+ assign mio_outsel_28_we = addr_hit[186] & reg_we & !reg_error;
assign mio_outsel_28_wd = reg_wdata[6:0];
- assign mio_outsel_29_we = addr_hit[186] & reg_we & !reg_error;
+ assign mio_outsel_29_we = addr_hit[187] & reg_we & !reg_error;
assign mio_outsel_29_wd = reg_wdata[6:0];
- assign mio_outsel_30_we = addr_hit[187] & reg_we & !reg_error;
+ assign mio_outsel_30_we = addr_hit[188] & reg_we & !reg_error;
assign mio_outsel_30_wd = reg_wdata[6:0];
- assign mio_outsel_31_we = addr_hit[188] & reg_we & !reg_error;
+ assign mio_outsel_31_we = addr_hit[189] & reg_we & !reg_error;
assign mio_outsel_31_wd = reg_wdata[6:0];
- assign mio_outsel_32_we = addr_hit[189] & reg_we & !reg_error;
+ assign mio_outsel_32_we = addr_hit[190] & reg_we & !reg_error;
assign mio_outsel_32_wd = reg_wdata[6:0];
- assign mio_outsel_33_we = addr_hit[190] & reg_we & !reg_error;
+ assign mio_outsel_33_we = addr_hit[191] & reg_we & !reg_error;
assign mio_outsel_33_wd = reg_wdata[6:0];
- assign mio_outsel_34_we = addr_hit[191] & reg_we & !reg_error;
+ assign mio_outsel_34_we = addr_hit[192] & reg_we & !reg_error;
assign mio_outsel_34_wd = reg_wdata[6:0];
- assign mio_outsel_35_we = addr_hit[192] & reg_we & !reg_error;
+ assign mio_outsel_35_we = addr_hit[193] & reg_we & !reg_error;
assign mio_outsel_35_wd = reg_wdata[6:0];
- assign mio_outsel_36_we = addr_hit[193] & reg_we & !reg_error;
+ assign mio_outsel_36_we = addr_hit[194] & reg_we & !reg_error;
assign mio_outsel_36_wd = reg_wdata[6:0];
- assign mio_outsel_37_we = addr_hit[194] & reg_we & !reg_error;
+ assign mio_outsel_37_we = addr_hit[195] & reg_we & !reg_error;
assign mio_outsel_37_wd = reg_wdata[6:0];
- assign mio_outsel_38_we = addr_hit[195] & reg_we & !reg_error;
+ assign mio_outsel_38_we = addr_hit[196] & reg_we & !reg_error;
assign mio_outsel_38_wd = reg_wdata[6:0];
- assign mio_outsel_39_we = addr_hit[196] & reg_we & !reg_error;
+ assign mio_outsel_39_we = addr_hit[197] & reg_we & !reg_error;
assign mio_outsel_39_wd = reg_wdata[6:0];
- assign mio_outsel_40_we = addr_hit[197] & reg_we & !reg_error;
+ assign mio_outsel_40_we = addr_hit[198] & reg_we & !reg_error;
assign mio_outsel_40_wd = reg_wdata[6:0];
- assign mio_outsel_41_we = addr_hit[198] & reg_we & !reg_error;
+ assign mio_outsel_41_we = addr_hit[199] & reg_we & !reg_error;
assign mio_outsel_41_wd = reg_wdata[6:0];
- assign mio_outsel_42_we = addr_hit[199] & reg_we & !reg_error;
+ assign mio_outsel_42_we = addr_hit[200] & reg_we & !reg_error;
assign mio_outsel_42_wd = reg_wdata[6:0];
- assign mio_outsel_43_we = addr_hit[200] & reg_we & !reg_error;
+ assign mio_outsel_43_we = addr_hit[201] & reg_we & !reg_error;
assign mio_outsel_43_wd = reg_wdata[6:0];
- assign mio_outsel_44_we = addr_hit[201] & reg_we & !reg_error;
+ assign mio_outsel_44_we = addr_hit[202] & reg_we & !reg_error;
assign mio_outsel_44_wd = reg_wdata[6:0];
- assign mio_outsel_45_we = addr_hit[202] & reg_we & !reg_error;
+ assign mio_outsel_45_we = addr_hit[203] & reg_we & !reg_error;
assign mio_outsel_45_wd = reg_wdata[6:0];
- assign mio_outsel_46_we = addr_hit[203] & reg_we & !reg_error;
+ assign mio_outsel_46_we = addr_hit[204] & reg_we & !reg_error;
assign mio_outsel_46_wd = reg_wdata[6:0];
- assign mio_pad_attr_regwen_0_we = addr_hit[204] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_0_we = addr_hit[205] & reg_we & !reg_error;
assign mio_pad_attr_regwen_0_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_1_we = addr_hit[205] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_1_we = addr_hit[206] & reg_we & !reg_error;
assign mio_pad_attr_regwen_1_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_2_we = addr_hit[206] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_2_we = addr_hit[207] & reg_we & !reg_error;
assign mio_pad_attr_regwen_2_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_3_we = addr_hit[207] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_3_we = addr_hit[208] & reg_we & !reg_error;
assign mio_pad_attr_regwen_3_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_4_we = addr_hit[208] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_4_we = addr_hit[209] & reg_we & !reg_error;
assign mio_pad_attr_regwen_4_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_5_we = addr_hit[209] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_5_we = addr_hit[210] & reg_we & !reg_error;
assign mio_pad_attr_regwen_5_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_6_we = addr_hit[210] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_6_we = addr_hit[211] & reg_we & !reg_error;
assign mio_pad_attr_regwen_6_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_7_we = addr_hit[211] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_7_we = addr_hit[212] & reg_we & !reg_error;
assign mio_pad_attr_regwen_7_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_8_we = addr_hit[212] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_8_we = addr_hit[213] & reg_we & !reg_error;
assign mio_pad_attr_regwen_8_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_9_we = addr_hit[213] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_9_we = addr_hit[214] & reg_we & !reg_error;
assign mio_pad_attr_regwen_9_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_10_we = addr_hit[214] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_10_we = addr_hit[215] & reg_we & !reg_error;
assign mio_pad_attr_regwen_10_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_11_we = addr_hit[215] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_11_we = addr_hit[216] & reg_we & !reg_error;
assign mio_pad_attr_regwen_11_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_12_we = addr_hit[216] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_12_we = addr_hit[217] & reg_we & !reg_error;
assign mio_pad_attr_regwen_12_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_13_we = addr_hit[217] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_13_we = addr_hit[218] & reg_we & !reg_error;
assign mio_pad_attr_regwen_13_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_14_we = addr_hit[218] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_14_we = addr_hit[219] & reg_we & !reg_error;
assign mio_pad_attr_regwen_14_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_15_we = addr_hit[219] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_15_we = addr_hit[220] & reg_we & !reg_error;
assign mio_pad_attr_regwen_15_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_16_we = addr_hit[220] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_16_we = addr_hit[221] & reg_we & !reg_error;
assign mio_pad_attr_regwen_16_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_17_we = addr_hit[221] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_17_we = addr_hit[222] & reg_we & !reg_error;
assign mio_pad_attr_regwen_17_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_18_we = addr_hit[222] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_18_we = addr_hit[223] & reg_we & !reg_error;
assign mio_pad_attr_regwen_18_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_19_we = addr_hit[223] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_19_we = addr_hit[224] & reg_we & !reg_error;
assign mio_pad_attr_regwen_19_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_20_we = addr_hit[224] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_20_we = addr_hit[225] & reg_we & !reg_error;
assign mio_pad_attr_regwen_20_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_21_we = addr_hit[225] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_21_we = addr_hit[226] & reg_we & !reg_error;
assign mio_pad_attr_regwen_21_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_22_we = addr_hit[226] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_22_we = addr_hit[227] & reg_we & !reg_error;
assign mio_pad_attr_regwen_22_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_23_we = addr_hit[227] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_23_we = addr_hit[228] & reg_we & !reg_error;
assign mio_pad_attr_regwen_23_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_24_we = addr_hit[228] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_24_we = addr_hit[229] & reg_we & !reg_error;
assign mio_pad_attr_regwen_24_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_25_we = addr_hit[229] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_25_we = addr_hit[230] & reg_we & !reg_error;
assign mio_pad_attr_regwen_25_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_26_we = addr_hit[230] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_26_we = addr_hit[231] & reg_we & !reg_error;
assign mio_pad_attr_regwen_26_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_27_we = addr_hit[231] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_27_we = addr_hit[232] & reg_we & !reg_error;
assign mio_pad_attr_regwen_27_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_28_we = addr_hit[232] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_28_we = addr_hit[233] & reg_we & !reg_error;
assign mio_pad_attr_regwen_28_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_29_we = addr_hit[233] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_29_we = addr_hit[234] & reg_we & !reg_error;
assign mio_pad_attr_regwen_29_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_30_we = addr_hit[234] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_30_we = addr_hit[235] & reg_we & !reg_error;
assign mio_pad_attr_regwen_30_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_31_we = addr_hit[235] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_31_we = addr_hit[236] & reg_we & !reg_error;
assign mio_pad_attr_regwen_31_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_32_we = addr_hit[236] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_32_we = addr_hit[237] & reg_we & !reg_error;
assign mio_pad_attr_regwen_32_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_33_we = addr_hit[237] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_33_we = addr_hit[238] & reg_we & !reg_error;
assign mio_pad_attr_regwen_33_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_34_we = addr_hit[238] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_34_we = addr_hit[239] & reg_we & !reg_error;
assign mio_pad_attr_regwen_34_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_35_we = addr_hit[239] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_35_we = addr_hit[240] & reg_we & !reg_error;
assign mio_pad_attr_regwen_35_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_36_we = addr_hit[240] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_36_we = addr_hit[241] & reg_we & !reg_error;
assign mio_pad_attr_regwen_36_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_37_we = addr_hit[241] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_37_we = addr_hit[242] & reg_we & !reg_error;
assign mio_pad_attr_regwen_37_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_38_we = addr_hit[242] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_38_we = addr_hit[243] & reg_we & !reg_error;
assign mio_pad_attr_regwen_38_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_39_we = addr_hit[243] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_39_we = addr_hit[244] & reg_we & !reg_error;
assign mio_pad_attr_regwen_39_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_40_we = addr_hit[244] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_40_we = addr_hit[245] & reg_we & !reg_error;
assign mio_pad_attr_regwen_40_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_41_we = addr_hit[245] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_41_we = addr_hit[246] & reg_we & !reg_error;
assign mio_pad_attr_regwen_41_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_42_we = addr_hit[246] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_42_we = addr_hit[247] & reg_we & !reg_error;
assign mio_pad_attr_regwen_42_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_43_we = addr_hit[247] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_43_we = addr_hit[248] & reg_we & !reg_error;
assign mio_pad_attr_regwen_43_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_44_we = addr_hit[248] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_44_we = addr_hit[249] & reg_we & !reg_error;
assign mio_pad_attr_regwen_44_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_45_we = addr_hit[249] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_45_we = addr_hit[250] & reg_we & !reg_error;
assign mio_pad_attr_regwen_45_wd = reg_wdata[0];
- assign mio_pad_attr_regwen_46_we = addr_hit[250] & reg_we & !reg_error;
+ assign mio_pad_attr_regwen_46_we = addr_hit[251] & reg_we & !reg_error;
assign mio_pad_attr_regwen_46_wd = reg_wdata[0];
- assign mio_pad_attr_0_we = addr_hit[251] & reg_we & !reg_error;
+ assign mio_pad_attr_0_we = addr_hit[252] & reg_we & !reg_error;
assign mio_pad_attr_0_wd = reg_wdata[12:0];
- assign mio_pad_attr_0_re = addr_hit[251] & reg_re & !reg_error;
+ assign mio_pad_attr_0_re = addr_hit[252] & reg_re & !reg_error;
- assign mio_pad_attr_1_we = addr_hit[252] & reg_we & !reg_error;
+ assign mio_pad_attr_1_we = addr_hit[253] & reg_we & !reg_error;
assign mio_pad_attr_1_wd = reg_wdata[12:0];
- assign mio_pad_attr_1_re = addr_hit[252] & reg_re & !reg_error;
+ assign mio_pad_attr_1_re = addr_hit[253] & reg_re & !reg_error;
- assign mio_pad_attr_2_we = addr_hit[253] & reg_we & !reg_error;
+ assign mio_pad_attr_2_we = addr_hit[254] & reg_we & !reg_error;
assign mio_pad_attr_2_wd = reg_wdata[12:0];
- assign mio_pad_attr_2_re = addr_hit[253] & reg_re & !reg_error;
+ assign mio_pad_attr_2_re = addr_hit[254] & reg_re & !reg_error;
- assign mio_pad_attr_3_we = addr_hit[254] & reg_we & !reg_error;
+ assign mio_pad_attr_3_we = addr_hit[255] & reg_we & !reg_error;
assign mio_pad_attr_3_wd = reg_wdata[12:0];
- assign mio_pad_attr_3_re = addr_hit[254] & reg_re & !reg_error;
+ assign mio_pad_attr_3_re = addr_hit[255] & reg_re & !reg_error;
- assign mio_pad_attr_4_we = addr_hit[255] & reg_we & !reg_error;
+ assign mio_pad_attr_4_we = addr_hit[256] & reg_we & !reg_error;
assign mio_pad_attr_4_wd = reg_wdata[12:0];
- assign mio_pad_attr_4_re = addr_hit[255] & reg_re & !reg_error;
+ assign mio_pad_attr_4_re = addr_hit[256] & reg_re & !reg_error;
- assign mio_pad_attr_5_we = addr_hit[256] & reg_we & !reg_error;
+ assign mio_pad_attr_5_we = addr_hit[257] & reg_we & !reg_error;
assign mio_pad_attr_5_wd = reg_wdata[12:0];
- assign mio_pad_attr_5_re = addr_hit[256] & reg_re & !reg_error;
+ assign mio_pad_attr_5_re = addr_hit[257] & reg_re & !reg_error;
- assign mio_pad_attr_6_we = addr_hit[257] & reg_we & !reg_error;
+ assign mio_pad_attr_6_we = addr_hit[258] & reg_we & !reg_error;
assign mio_pad_attr_6_wd = reg_wdata[12:0];
- assign mio_pad_attr_6_re = addr_hit[257] & reg_re & !reg_error;
+ assign mio_pad_attr_6_re = addr_hit[258] & reg_re & !reg_error;
- assign mio_pad_attr_7_we = addr_hit[258] & reg_we & !reg_error;
+ assign mio_pad_attr_7_we = addr_hit[259] & reg_we & !reg_error;
assign mio_pad_attr_7_wd = reg_wdata[12:0];
- assign mio_pad_attr_7_re = addr_hit[258] & reg_re & !reg_error;
+ assign mio_pad_attr_7_re = addr_hit[259] & reg_re & !reg_error;
- assign mio_pad_attr_8_we = addr_hit[259] & reg_we & !reg_error;
+ assign mio_pad_attr_8_we = addr_hit[260] & reg_we & !reg_error;
assign mio_pad_attr_8_wd = reg_wdata[12:0];
- assign mio_pad_attr_8_re = addr_hit[259] & reg_re & !reg_error;
+ assign mio_pad_attr_8_re = addr_hit[260] & reg_re & !reg_error;
- assign mio_pad_attr_9_we = addr_hit[260] & reg_we & !reg_error;
+ assign mio_pad_attr_9_we = addr_hit[261] & reg_we & !reg_error;
assign mio_pad_attr_9_wd = reg_wdata[12:0];
- assign mio_pad_attr_9_re = addr_hit[260] & reg_re & !reg_error;
+ assign mio_pad_attr_9_re = addr_hit[261] & reg_re & !reg_error;
- assign mio_pad_attr_10_we = addr_hit[261] & reg_we & !reg_error;
+ assign mio_pad_attr_10_we = addr_hit[262] & reg_we & !reg_error;
assign mio_pad_attr_10_wd = reg_wdata[12:0];
- assign mio_pad_attr_10_re = addr_hit[261] & reg_re & !reg_error;
+ assign mio_pad_attr_10_re = addr_hit[262] & reg_re & !reg_error;
- assign mio_pad_attr_11_we = addr_hit[262] & reg_we & !reg_error;
+ assign mio_pad_attr_11_we = addr_hit[263] & reg_we & !reg_error;
assign mio_pad_attr_11_wd = reg_wdata[12:0];
- assign mio_pad_attr_11_re = addr_hit[262] & reg_re & !reg_error;
+ assign mio_pad_attr_11_re = addr_hit[263] & reg_re & !reg_error;
- assign mio_pad_attr_12_we = addr_hit[263] & reg_we & !reg_error;
+ assign mio_pad_attr_12_we = addr_hit[264] & reg_we & !reg_error;
assign mio_pad_attr_12_wd = reg_wdata[12:0];
- assign mio_pad_attr_12_re = addr_hit[263] & reg_re & !reg_error;
+ assign mio_pad_attr_12_re = addr_hit[264] & reg_re & !reg_error;
- assign mio_pad_attr_13_we = addr_hit[264] & reg_we & !reg_error;
+ assign mio_pad_attr_13_we = addr_hit[265] & reg_we & !reg_error;
assign mio_pad_attr_13_wd = reg_wdata[12:0];
- assign mio_pad_attr_13_re = addr_hit[264] & reg_re & !reg_error;
+ assign mio_pad_attr_13_re = addr_hit[265] & reg_re & !reg_error;
- assign mio_pad_attr_14_we = addr_hit[265] & reg_we & !reg_error;
+ assign mio_pad_attr_14_we = addr_hit[266] & reg_we & !reg_error;
assign mio_pad_attr_14_wd = reg_wdata[12:0];
- assign mio_pad_attr_14_re = addr_hit[265] & reg_re & !reg_error;
+ assign mio_pad_attr_14_re = addr_hit[266] & reg_re & !reg_error;
- assign mio_pad_attr_15_we = addr_hit[266] & reg_we & !reg_error;
+ assign mio_pad_attr_15_we = addr_hit[267] & reg_we & !reg_error;
assign mio_pad_attr_15_wd = reg_wdata[12:0];
- assign mio_pad_attr_15_re = addr_hit[266] & reg_re & !reg_error;
+ assign mio_pad_attr_15_re = addr_hit[267] & reg_re & !reg_error;
- assign mio_pad_attr_16_we = addr_hit[267] & reg_we & !reg_error;
+ assign mio_pad_attr_16_we = addr_hit[268] & reg_we & !reg_error;
assign mio_pad_attr_16_wd = reg_wdata[12:0];
- assign mio_pad_attr_16_re = addr_hit[267] & reg_re & !reg_error;
+ assign mio_pad_attr_16_re = addr_hit[268] & reg_re & !reg_error;
- assign mio_pad_attr_17_we = addr_hit[268] & reg_we & !reg_error;
+ assign mio_pad_attr_17_we = addr_hit[269] & reg_we & !reg_error;
assign mio_pad_attr_17_wd = reg_wdata[12:0];
- assign mio_pad_attr_17_re = addr_hit[268] & reg_re & !reg_error;
+ assign mio_pad_attr_17_re = addr_hit[269] & reg_re & !reg_error;
- assign mio_pad_attr_18_we = addr_hit[269] & reg_we & !reg_error;
+ assign mio_pad_attr_18_we = addr_hit[270] & reg_we & !reg_error;
assign mio_pad_attr_18_wd = reg_wdata[12:0];
- assign mio_pad_attr_18_re = addr_hit[269] & reg_re & !reg_error;
+ assign mio_pad_attr_18_re = addr_hit[270] & reg_re & !reg_error;
- assign mio_pad_attr_19_we = addr_hit[270] & reg_we & !reg_error;
+ assign mio_pad_attr_19_we = addr_hit[271] & reg_we & !reg_error;
assign mio_pad_attr_19_wd = reg_wdata[12:0];
- assign mio_pad_attr_19_re = addr_hit[270] & reg_re & !reg_error;
+ assign mio_pad_attr_19_re = addr_hit[271] & reg_re & !reg_error;
- assign mio_pad_attr_20_we = addr_hit[271] & reg_we & !reg_error;
+ assign mio_pad_attr_20_we = addr_hit[272] & reg_we & !reg_error;
assign mio_pad_attr_20_wd = reg_wdata[12:0];
- assign mio_pad_attr_20_re = addr_hit[271] & reg_re & !reg_error;
+ assign mio_pad_attr_20_re = addr_hit[272] & reg_re & !reg_error;
- assign mio_pad_attr_21_we = addr_hit[272] & reg_we & !reg_error;
+ assign mio_pad_attr_21_we = addr_hit[273] & reg_we & !reg_error;
assign mio_pad_attr_21_wd = reg_wdata[12:0];
- assign mio_pad_attr_21_re = addr_hit[272] & reg_re & !reg_error;
+ assign mio_pad_attr_21_re = addr_hit[273] & reg_re & !reg_error;
- assign mio_pad_attr_22_we = addr_hit[273] & reg_we & !reg_error;
+ assign mio_pad_attr_22_we = addr_hit[274] & reg_we & !reg_error;
assign mio_pad_attr_22_wd = reg_wdata[12:0];
- assign mio_pad_attr_22_re = addr_hit[273] & reg_re & !reg_error;
+ assign mio_pad_attr_22_re = addr_hit[274] & reg_re & !reg_error;
- assign mio_pad_attr_23_we = addr_hit[274] & reg_we & !reg_error;
+ assign mio_pad_attr_23_we = addr_hit[275] & reg_we & !reg_error;
assign mio_pad_attr_23_wd = reg_wdata[12:0];
- assign mio_pad_attr_23_re = addr_hit[274] & reg_re & !reg_error;
+ assign mio_pad_attr_23_re = addr_hit[275] & reg_re & !reg_error;
- assign mio_pad_attr_24_we = addr_hit[275] & reg_we & !reg_error;
+ assign mio_pad_attr_24_we = addr_hit[276] & reg_we & !reg_error;
assign mio_pad_attr_24_wd = reg_wdata[12:0];
- assign mio_pad_attr_24_re = addr_hit[275] & reg_re & !reg_error;
+ assign mio_pad_attr_24_re = addr_hit[276] & reg_re & !reg_error;
- assign mio_pad_attr_25_we = addr_hit[276] & reg_we & !reg_error;
+ assign mio_pad_attr_25_we = addr_hit[277] & reg_we & !reg_error;
assign mio_pad_attr_25_wd = reg_wdata[12:0];
- assign mio_pad_attr_25_re = addr_hit[276] & reg_re & !reg_error;
+ assign mio_pad_attr_25_re = addr_hit[277] & reg_re & !reg_error;
- assign mio_pad_attr_26_we = addr_hit[277] & reg_we & !reg_error;
+ assign mio_pad_attr_26_we = addr_hit[278] & reg_we & !reg_error;
assign mio_pad_attr_26_wd = reg_wdata[12:0];
- assign mio_pad_attr_26_re = addr_hit[277] & reg_re & !reg_error;
+ assign mio_pad_attr_26_re = addr_hit[278] & reg_re & !reg_error;
- assign mio_pad_attr_27_we = addr_hit[278] & reg_we & !reg_error;
+ assign mio_pad_attr_27_we = addr_hit[279] & reg_we & !reg_error;
assign mio_pad_attr_27_wd = reg_wdata[12:0];
- assign mio_pad_attr_27_re = addr_hit[278] & reg_re & !reg_error;
+ assign mio_pad_attr_27_re = addr_hit[279] & reg_re & !reg_error;
- assign mio_pad_attr_28_we = addr_hit[279] & reg_we & !reg_error;
+ assign mio_pad_attr_28_we = addr_hit[280] & reg_we & !reg_error;
assign mio_pad_attr_28_wd = reg_wdata[12:0];
- assign mio_pad_attr_28_re = addr_hit[279] & reg_re & !reg_error;
+ assign mio_pad_attr_28_re = addr_hit[280] & reg_re & !reg_error;
- assign mio_pad_attr_29_we = addr_hit[280] & reg_we & !reg_error;
+ assign mio_pad_attr_29_we = addr_hit[281] & reg_we & !reg_error;
assign mio_pad_attr_29_wd = reg_wdata[12:0];
- assign mio_pad_attr_29_re = addr_hit[280] & reg_re & !reg_error;
+ assign mio_pad_attr_29_re = addr_hit[281] & reg_re & !reg_error;
- assign mio_pad_attr_30_we = addr_hit[281] & reg_we & !reg_error;
+ assign mio_pad_attr_30_we = addr_hit[282] & reg_we & !reg_error;
assign mio_pad_attr_30_wd = reg_wdata[12:0];
- assign mio_pad_attr_30_re = addr_hit[281] & reg_re & !reg_error;
+ assign mio_pad_attr_30_re = addr_hit[282] & reg_re & !reg_error;
- assign mio_pad_attr_31_we = addr_hit[282] & reg_we & !reg_error;
+ assign mio_pad_attr_31_we = addr_hit[283] & reg_we & !reg_error;
assign mio_pad_attr_31_wd = reg_wdata[12:0];
- assign mio_pad_attr_31_re = addr_hit[282] & reg_re & !reg_error;
+ assign mio_pad_attr_31_re = addr_hit[283] & reg_re & !reg_error;
- assign mio_pad_attr_32_we = addr_hit[283] & reg_we & !reg_error;
+ assign mio_pad_attr_32_we = addr_hit[284] & reg_we & !reg_error;
assign mio_pad_attr_32_wd = reg_wdata[12:0];
- assign mio_pad_attr_32_re = addr_hit[283] & reg_re & !reg_error;
+ assign mio_pad_attr_32_re = addr_hit[284] & reg_re & !reg_error;
- assign mio_pad_attr_33_we = addr_hit[284] & reg_we & !reg_error;
+ assign mio_pad_attr_33_we = addr_hit[285] & reg_we & !reg_error;
assign mio_pad_attr_33_wd = reg_wdata[12:0];
- assign mio_pad_attr_33_re = addr_hit[284] & reg_re & !reg_error;
+ assign mio_pad_attr_33_re = addr_hit[285] & reg_re & !reg_error;
- assign mio_pad_attr_34_we = addr_hit[285] & reg_we & !reg_error;
+ assign mio_pad_attr_34_we = addr_hit[286] & reg_we & !reg_error;
assign mio_pad_attr_34_wd = reg_wdata[12:0];
- assign mio_pad_attr_34_re = addr_hit[285] & reg_re & !reg_error;
+ assign mio_pad_attr_34_re = addr_hit[286] & reg_re & !reg_error;
- assign mio_pad_attr_35_we = addr_hit[286] & reg_we & !reg_error;
+ assign mio_pad_attr_35_we = addr_hit[287] & reg_we & !reg_error;
assign mio_pad_attr_35_wd = reg_wdata[12:0];
- assign mio_pad_attr_35_re = addr_hit[286] & reg_re & !reg_error;
+ assign mio_pad_attr_35_re = addr_hit[287] & reg_re & !reg_error;
- assign mio_pad_attr_36_we = addr_hit[287] & reg_we & !reg_error;
+ assign mio_pad_attr_36_we = addr_hit[288] & reg_we & !reg_error;
assign mio_pad_attr_36_wd = reg_wdata[12:0];
- assign mio_pad_attr_36_re = addr_hit[287] & reg_re & !reg_error;
+ assign mio_pad_attr_36_re = addr_hit[288] & reg_re & !reg_error;
- assign mio_pad_attr_37_we = addr_hit[288] & reg_we & !reg_error;
+ assign mio_pad_attr_37_we = addr_hit[289] & reg_we & !reg_error;
assign mio_pad_attr_37_wd = reg_wdata[12:0];
- assign mio_pad_attr_37_re = addr_hit[288] & reg_re & !reg_error;
+ assign mio_pad_attr_37_re = addr_hit[289] & reg_re & !reg_error;
- assign mio_pad_attr_38_we = addr_hit[289] & reg_we & !reg_error;
+ assign mio_pad_attr_38_we = addr_hit[290] & reg_we & !reg_error;
assign mio_pad_attr_38_wd = reg_wdata[12:0];
- assign mio_pad_attr_38_re = addr_hit[289] & reg_re & !reg_error;
+ assign mio_pad_attr_38_re = addr_hit[290] & reg_re & !reg_error;
- assign mio_pad_attr_39_we = addr_hit[290] & reg_we & !reg_error;
+ assign mio_pad_attr_39_we = addr_hit[291] & reg_we & !reg_error;
assign mio_pad_attr_39_wd = reg_wdata[12:0];
- assign mio_pad_attr_39_re = addr_hit[290] & reg_re & !reg_error;
+ assign mio_pad_attr_39_re = addr_hit[291] & reg_re & !reg_error;
- assign mio_pad_attr_40_we = addr_hit[291] & reg_we & !reg_error;
+ assign mio_pad_attr_40_we = addr_hit[292] & reg_we & !reg_error;
assign mio_pad_attr_40_wd = reg_wdata[12:0];
- assign mio_pad_attr_40_re = addr_hit[291] & reg_re & !reg_error;
+ assign mio_pad_attr_40_re = addr_hit[292] & reg_re & !reg_error;
- assign mio_pad_attr_41_we = addr_hit[292] & reg_we & !reg_error;
+ assign mio_pad_attr_41_we = addr_hit[293] & reg_we & !reg_error;
assign mio_pad_attr_41_wd = reg_wdata[12:0];
- assign mio_pad_attr_41_re = addr_hit[292] & reg_re & !reg_error;
+ assign mio_pad_attr_41_re = addr_hit[293] & reg_re & !reg_error;
- assign mio_pad_attr_42_we = addr_hit[293] & reg_we & !reg_error;
+ assign mio_pad_attr_42_we = addr_hit[294] & reg_we & !reg_error;
assign mio_pad_attr_42_wd = reg_wdata[12:0];
- assign mio_pad_attr_42_re = addr_hit[293] & reg_re & !reg_error;
+ assign mio_pad_attr_42_re = addr_hit[294] & reg_re & !reg_error;
- assign mio_pad_attr_43_we = addr_hit[294] & reg_we & !reg_error;
+ assign mio_pad_attr_43_we = addr_hit[295] & reg_we & !reg_error;
assign mio_pad_attr_43_wd = reg_wdata[12:0];
- assign mio_pad_attr_43_re = addr_hit[294] & reg_re & !reg_error;
+ assign mio_pad_attr_43_re = addr_hit[295] & reg_re & !reg_error;
- assign mio_pad_attr_44_we = addr_hit[295] & reg_we & !reg_error;
+ assign mio_pad_attr_44_we = addr_hit[296] & reg_we & !reg_error;
assign mio_pad_attr_44_wd = reg_wdata[12:0];
- assign mio_pad_attr_44_re = addr_hit[295] & reg_re & !reg_error;
+ assign mio_pad_attr_44_re = addr_hit[296] & reg_re & !reg_error;
- assign mio_pad_attr_45_we = addr_hit[296] & reg_we & !reg_error;
+ assign mio_pad_attr_45_we = addr_hit[297] & reg_we & !reg_error;
assign mio_pad_attr_45_wd = reg_wdata[12:0];
- assign mio_pad_attr_45_re = addr_hit[296] & reg_re & !reg_error;
+ assign mio_pad_attr_45_re = addr_hit[297] & reg_re & !reg_error;
- assign mio_pad_attr_46_we = addr_hit[297] & reg_we & !reg_error;
+ assign mio_pad_attr_46_we = addr_hit[298] & reg_we & !reg_error;
assign mio_pad_attr_46_wd = reg_wdata[12:0];
- assign mio_pad_attr_46_re = addr_hit[297] & reg_re & !reg_error;
+ assign mio_pad_attr_46_re = addr_hit[298] & reg_re & !reg_error;
- assign dio_pad_attr_regwen_0_we = addr_hit[298] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_0_we = addr_hit[299] & reg_we & !reg_error;
assign dio_pad_attr_regwen_0_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_1_we = addr_hit[299] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_1_we = addr_hit[300] & reg_we & !reg_error;
assign dio_pad_attr_regwen_1_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_2_we = addr_hit[300] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_2_we = addr_hit[301] & reg_we & !reg_error;
assign dio_pad_attr_regwen_2_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_3_we = addr_hit[301] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_3_we = addr_hit[302] & reg_we & !reg_error;
assign dio_pad_attr_regwen_3_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_4_we = addr_hit[302] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_4_we = addr_hit[303] & reg_we & !reg_error;
assign dio_pad_attr_regwen_4_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_5_we = addr_hit[303] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_5_we = addr_hit[304] & reg_we & !reg_error;
assign dio_pad_attr_regwen_5_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_6_we = addr_hit[304] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_6_we = addr_hit[305] & reg_we & !reg_error;
assign dio_pad_attr_regwen_6_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_7_we = addr_hit[305] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_7_we = addr_hit[306] & reg_we & !reg_error;
assign dio_pad_attr_regwen_7_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_8_we = addr_hit[306] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_8_we = addr_hit[307] & reg_we & !reg_error;
assign dio_pad_attr_regwen_8_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_9_we = addr_hit[307] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_9_we = addr_hit[308] & reg_we & !reg_error;
assign dio_pad_attr_regwen_9_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_10_we = addr_hit[308] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_10_we = addr_hit[309] & reg_we & !reg_error;
assign dio_pad_attr_regwen_10_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_11_we = addr_hit[309] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_11_we = addr_hit[310] & reg_we & !reg_error;
assign dio_pad_attr_regwen_11_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_12_we = addr_hit[310] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_12_we = addr_hit[311] & reg_we & !reg_error;
assign dio_pad_attr_regwen_12_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_13_we = addr_hit[311] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_13_we = addr_hit[312] & reg_we & !reg_error;
assign dio_pad_attr_regwen_13_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_14_we = addr_hit[312] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_14_we = addr_hit[313] & reg_we & !reg_error;
assign dio_pad_attr_regwen_14_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_15_we = addr_hit[313] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_15_we = addr_hit[314] & reg_we & !reg_error;
assign dio_pad_attr_regwen_15_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_16_we = addr_hit[314] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_16_we = addr_hit[315] & reg_we & !reg_error;
assign dio_pad_attr_regwen_16_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_17_we = addr_hit[315] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_17_we = addr_hit[316] & reg_we & !reg_error;
assign dio_pad_attr_regwen_17_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_18_we = addr_hit[316] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_18_we = addr_hit[317] & reg_we & !reg_error;
assign dio_pad_attr_regwen_18_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_19_we = addr_hit[317] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_19_we = addr_hit[318] & reg_we & !reg_error;
assign dio_pad_attr_regwen_19_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_20_we = addr_hit[318] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_20_we = addr_hit[319] & reg_we & !reg_error;
assign dio_pad_attr_regwen_20_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_21_we = addr_hit[319] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_21_we = addr_hit[320] & reg_we & !reg_error;
assign dio_pad_attr_regwen_21_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_22_we = addr_hit[320] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_22_we = addr_hit[321] & reg_we & !reg_error;
assign dio_pad_attr_regwen_22_wd = reg_wdata[0];
- assign dio_pad_attr_regwen_23_we = addr_hit[321] & reg_we & !reg_error;
+ assign dio_pad_attr_regwen_23_we = addr_hit[322] & reg_we & !reg_error;
assign dio_pad_attr_regwen_23_wd = reg_wdata[0];
- assign dio_pad_attr_0_we = addr_hit[322] & reg_we & !reg_error;
+ assign dio_pad_attr_0_we = addr_hit[323] & reg_we & !reg_error;
assign dio_pad_attr_0_wd = reg_wdata[12:0];
- assign dio_pad_attr_0_re = addr_hit[322] & reg_re & !reg_error;
+ assign dio_pad_attr_0_re = addr_hit[323] & reg_re & !reg_error;
- assign dio_pad_attr_1_we = addr_hit[323] & reg_we & !reg_error;
+ assign dio_pad_attr_1_we = addr_hit[324] & reg_we & !reg_error;
assign dio_pad_attr_1_wd = reg_wdata[12:0];
- assign dio_pad_attr_1_re = addr_hit[323] & reg_re & !reg_error;
+ assign dio_pad_attr_1_re = addr_hit[324] & reg_re & !reg_error;
- assign dio_pad_attr_2_we = addr_hit[324] & reg_we & !reg_error;
+ assign dio_pad_attr_2_we = addr_hit[325] & reg_we & !reg_error;
assign dio_pad_attr_2_wd = reg_wdata[12:0];
- assign dio_pad_attr_2_re = addr_hit[324] & reg_re & !reg_error;
+ assign dio_pad_attr_2_re = addr_hit[325] & reg_re & !reg_error;
- assign dio_pad_attr_3_we = addr_hit[325] & reg_we & !reg_error;
+ assign dio_pad_attr_3_we = addr_hit[326] & reg_we & !reg_error;
assign dio_pad_attr_3_wd = reg_wdata[12:0];
- assign dio_pad_attr_3_re = addr_hit[325] & reg_re & !reg_error;
+ assign dio_pad_attr_3_re = addr_hit[326] & reg_re & !reg_error;
- assign dio_pad_attr_4_we = addr_hit[326] & reg_we & !reg_error;
+ assign dio_pad_attr_4_we = addr_hit[327] & reg_we & !reg_error;
assign dio_pad_attr_4_wd = reg_wdata[12:0];
- assign dio_pad_attr_4_re = addr_hit[326] & reg_re & !reg_error;
+ assign dio_pad_attr_4_re = addr_hit[327] & reg_re & !reg_error;
- assign dio_pad_attr_5_we = addr_hit[327] & reg_we & !reg_error;
+ assign dio_pad_attr_5_we = addr_hit[328] & reg_we & !reg_error;
assign dio_pad_attr_5_wd = reg_wdata[12:0];
- assign dio_pad_attr_5_re = addr_hit[327] & reg_re & !reg_error;
+ assign dio_pad_attr_5_re = addr_hit[328] & reg_re & !reg_error;
- assign dio_pad_attr_6_we = addr_hit[328] & reg_we & !reg_error;
+ assign dio_pad_attr_6_we = addr_hit[329] & reg_we & !reg_error;
assign dio_pad_attr_6_wd = reg_wdata[12:0];
- assign dio_pad_attr_6_re = addr_hit[328] & reg_re & !reg_error;
+ assign dio_pad_attr_6_re = addr_hit[329] & reg_re & !reg_error;
- assign dio_pad_attr_7_we = addr_hit[329] & reg_we & !reg_error;
+ assign dio_pad_attr_7_we = addr_hit[330] & reg_we & !reg_error;
assign dio_pad_attr_7_wd = reg_wdata[12:0];
- assign dio_pad_attr_7_re = addr_hit[329] & reg_re & !reg_error;
+ assign dio_pad_attr_7_re = addr_hit[330] & reg_re & !reg_error;
- assign dio_pad_attr_8_we = addr_hit[330] & reg_we & !reg_error;
+ assign dio_pad_attr_8_we = addr_hit[331] & reg_we & !reg_error;
assign dio_pad_attr_8_wd = reg_wdata[12:0];
- assign dio_pad_attr_8_re = addr_hit[330] & reg_re & !reg_error;
+ assign dio_pad_attr_8_re = addr_hit[331] & reg_re & !reg_error;
- assign dio_pad_attr_9_we = addr_hit[331] & reg_we & !reg_error;
+ assign dio_pad_attr_9_we = addr_hit[332] & reg_we & !reg_error;
assign dio_pad_attr_9_wd = reg_wdata[12:0];
- assign dio_pad_attr_9_re = addr_hit[331] & reg_re & !reg_error;
+ assign dio_pad_attr_9_re = addr_hit[332] & reg_re & !reg_error;
- assign dio_pad_attr_10_we = addr_hit[332] & reg_we & !reg_error;
+ assign dio_pad_attr_10_we = addr_hit[333] & reg_we & !reg_error;
assign dio_pad_attr_10_wd = reg_wdata[12:0];
- assign dio_pad_attr_10_re = addr_hit[332] & reg_re & !reg_error;
+ assign dio_pad_attr_10_re = addr_hit[333] & reg_re & !reg_error;
- assign dio_pad_attr_11_we = addr_hit[333] & reg_we & !reg_error;
+ assign dio_pad_attr_11_we = addr_hit[334] & reg_we & !reg_error;
assign dio_pad_attr_11_wd = reg_wdata[12:0];
- assign dio_pad_attr_11_re = addr_hit[333] & reg_re & !reg_error;
+ assign dio_pad_attr_11_re = addr_hit[334] & reg_re & !reg_error;
- assign dio_pad_attr_12_we = addr_hit[334] & reg_we & !reg_error;
+ assign dio_pad_attr_12_we = addr_hit[335] & reg_we & !reg_error;
assign dio_pad_attr_12_wd = reg_wdata[12:0];
- assign dio_pad_attr_12_re = addr_hit[334] & reg_re & !reg_error;
+ assign dio_pad_attr_12_re = addr_hit[335] & reg_re & !reg_error;
- assign dio_pad_attr_13_we = addr_hit[335] & reg_we & !reg_error;
+ assign dio_pad_attr_13_we = addr_hit[336] & reg_we & !reg_error;
assign dio_pad_attr_13_wd = reg_wdata[12:0];
- assign dio_pad_attr_13_re = addr_hit[335] & reg_re & !reg_error;
+ assign dio_pad_attr_13_re = addr_hit[336] & reg_re & !reg_error;
- assign dio_pad_attr_14_we = addr_hit[336] & reg_we & !reg_error;
+ assign dio_pad_attr_14_we = addr_hit[337] & reg_we & !reg_error;
assign dio_pad_attr_14_wd = reg_wdata[12:0];
- assign dio_pad_attr_14_re = addr_hit[336] & reg_re & !reg_error;
+ assign dio_pad_attr_14_re = addr_hit[337] & reg_re & !reg_error;
- assign dio_pad_attr_15_we = addr_hit[337] & reg_we & !reg_error;
+ assign dio_pad_attr_15_we = addr_hit[338] & reg_we & !reg_error;
assign dio_pad_attr_15_wd = reg_wdata[12:0];
- assign dio_pad_attr_15_re = addr_hit[337] & reg_re & !reg_error;
+ assign dio_pad_attr_15_re = addr_hit[338] & reg_re & !reg_error;
- assign dio_pad_attr_16_we = addr_hit[338] & reg_we & !reg_error;
+ assign dio_pad_attr_16_we = addr_hit[339] & reg_we & !reg_error;
assign dio_pad_attr_16_wd = reg_wdata[12:0];
- assign dio_pad_attr_16_re = addr_hit[338] & reg_re & !reg_error;
+ assign dio_pad_attr_16_re = addr_hit[339] & reg_re & !reg_error;
- assign dio_pad_attr_17_we = addr_hit[339] & reg_we & !reg_error;
+ assign dio_pad_attr_17_we = addr_hit[340] & reg_we & !reg_error;
assign dio_pad_attr_17_wd = reg_wdata[12:0];
- assign dio_pad_attr_17_re = addr_hit[339] & reg_re & !reg_error;
+ assign dio_pad_attr_17_re = addr_hit[340] & reg_re & !reg_error;
- assign dio_pad_attr_18_we = addr_hit[340] & reg_we & !reg_error;
+ assign dio_pad_attr_18_we = addr_hit[341] & reg_we & !reg_error;
assign dio_pad_attr_18_wd = reg_wdata[12:0];
- assign dio_pad_attr_18_re = addr_hit[340] & reg_re & !reg_error;
+ assign dio_pad_attr_18_re = addr_hit[341] & reg_re & !reg_error;
- assign dio_pad_attr_19_we = addr_hit[341] & reg_we & !reg_error;
+ assign dio_pad_attr_19_we = addr_hit[342] & reg_we & !reg_error;
assign dio_pad_attr_19_wd = reg_wdata[12:0];
- assign dio_pad_attr_19_re = addr_hit[341] & reg_re & !reg_error;
+ assign dio_pad_attr_19_re = addr_hit[342] & reg_re & !reg_error;
- assign dio_pad_attr_20_we = addr_hit[342] & reg_we & !reg_error;
+ assign dio_pad_attr_20_we = addr_hit[343] & reg_we & !reg_error;
assign dio_pad_attr_20_wd = reg_wdata[12:0];
- assign dio_pad_attr_20_re = addr_hit[342] & reg_re & !reg_error;
+ assign dio_pad_attr_20_re = addr_hit[343] & reg_re & !reg_error;
- assign dio_pad_attr_21_we = addr_hit[343] & reg_we & !reg_error;
+ assign dio_pad_attr_21_we = addr_hit[344] & reg_we & !reg_error;
assign dio_pad_attr_21_wd = reg_wdata[12:0];
- assign dio_pad_attr_21_re = addr_hit[343] & reg_re & !reg_error;
+ assign dio_pad_attr_21_re = addr_hit[344] & reg_re & !reg_error;
- assign dio_pad_attr_22_we = addr_hit[344] & reg_we & !reg_error;
+ assign dio_pad_attr_22_we = addr_hit[345] & reg_we & !reg_error;
assign dio_pad_attr_22_wd = reg_wdata[12:0];
- assign dio_pad_attr_22_re = addr_hit[344] & reg_re & !reg_error;
+ assign dio_pad_attr_22_re = addr_hit[345] & reg_re & !reg_error;
- assign dio_pad_attr_23_we = addr_hit[345] & reg_we & !reg_error;
+ assign dio_pad_attr_23_we = addr_hit[346] & reg_we & !reg_error;
assign dio_pad_attr_23_wd = reg_wdata[12:0];
- assign dio_pad_attr_23_re = addr_hit[345] & reg_re & !reg_error;
+ assign dio_pad_attr_23_re = addr_hit[346] & reg_re & !reg_error;
- assign mio_pad_sleep_status_0_en_0_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_0_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_0_wd = reg_wdata[0];
- assign mio_pad_sleep_status_0_en_1_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_1_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_1_wd = reg_wdata[1];
- assign mio_pad_sleep_status_0_en_2_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_2_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_2_wd = reg_wdata[2];
- assign mio_pad_sleep_status_0_en_3_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_3_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_3_wd = reg_wdata[3];
- assign mio_pad_sleep_status_0_en_4_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_4_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_4_wd = reg_wdata[4];
- assign mio_pad_sleep_status_0_en_5_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_5_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_5_wd = reg_wdata[5];
- assign mio_pad_sleep_status_0_en_6_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_6_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_6_wd = reg_wdata[6];
- assign mio_pad_sleep_status_0_en_7_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_7_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_7_wd = reg_wdata[7];
- assign mio_pad_sleep_status_0_en_8_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_8_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_8_wd = reg_wdata[8];
- assign mio_pad_sleep_status_0_en_9_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_9_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_9_wd = reg_wdata[9];
- assign mio_pad_sleep_status_0_en_10_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_10_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_10_wd = reg_wdata[10];
- assign mio_pad_sleep_status_0_en_11_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_11_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_11_wd = reg_wdata[11];
- assign mio_pad_sleep_status_0_en_12_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_12_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_12_wd = reg_wdata[12];
- assign mio_pad_sleep_status_0_en_13_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_13_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_13_wd = reg_wdata[13];
- assign mio_pad_sleep_status_0_en_14_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_14_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_14_wd = reg_wdata[14];
- assign mio_pad_sleep_status_0_en_15_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_15_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_15_wd = reg_wdata[15];
- assign mio_pad_sleep_status_0_en_16_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_16_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_16_wd = reg_wdata[16];
- assign mio_pad_sleep_status_0_en_17_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_17_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_17_wd = reg_wdata[17];
- assign mio_pad_sleep_status_0_en_18_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_18_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_18_wd = reg_wdata[18];
- assign mio_pad_sleep_status_0_en_19_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_19_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_19_wd = reg_wdata[19];
- assign mio_pad_sleep_status_0_en_20_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_20_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_20_wd = reg_wdata[20];
- assign mio_pad_sleep_status_0_en_21_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_21_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_21_wd = reg_wdata[21];
- assign mio_pad_sleep_status_0_en_22_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_22_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_22_wd = reg_wdata[22];
- assign mio_pad_sleep_status_0_en_23_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_23_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_23_wd = reg_wdata[23];
- assign mio_pad_sleep_status_0_en_24_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_24_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_24_wd = reg_wdata[24];
- assign mio_pad_sleep_status_0_en_25_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_25_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_25_wd = reg_wdata[25];
- assign mio_pad_sleep_status_0_en_26_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_26_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_26_wd = reg_wdata[26];
- assign mio_pad_sleep_status_0_en_27_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_27_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_27_wd = reg_wdata[27];
- assign mio_pad_sleep_status_0_en_28_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_28_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_28_wd = reg_wdata[28];
- assign mio_pad_sleep_status_0_en_29_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_29_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_29_wd = reg_wdata[29];
- assign mio_pad_sleep_status_0_en_30_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_30_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_30_wd = reg_wdata[30];
- assign mio_pad_sleep_status_0_en_31_we = addr_hit[346] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_0_en_31_we = addr_hit[347] & reg_we & !reg_error;
assign mio_pad_sleep_status_0_en_31_wd = reg_wdata[31];
- assign mio_pad_sleep_status_1_en_32_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_32_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_32_wd = reg_wdata[0];
- assign mio_pad_sleep_status_1_en_33_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_33_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_33_wd = reg_wdata[1];
- assign mio_pad_sleep_status_1_en_34_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_34_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_34_wd = reg_wdata[2];
- assign mio_pad_sleep_status_1_en_35_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_35_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_35_wd = reg_wdata[3];
- assign mio_pad_sleep_status_1_en_36_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_36_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_36_wd = reg_wdata[4];
- assign mio_pad_sleep_status_1_en_37_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_37_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_37_wd = reg_wdata[5];
- assign mio_pad_sleep_status_1_en_38_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_38_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_38_wd = reg_wdata[6];
- assign mio_pad_sleep_status_1_en_39_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_39_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_39_wd = reg_wdata[7];
- assign mio_pad_sleep_status_1_en_40_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_40_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_40_wd = reg_wdata[8];
- assign mio_pad_sleep_status_1_en_41_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_41_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_41_wd = reg_wdata[9];
- assign mio_pad_sleep_status_1_en_42_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_42_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_42_wd = reg_wdata[10];
- assign mio_pad_sleep_status_1_en_43_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_43_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_43_wd = reg_wdata[11];
- assign mio_pad_sleep_status_1_en_44_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_44_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_44_wd = reg_wdata[12];
- assign mio_pad_sleep_status_1_en_45_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_45_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_45_wd = reg_wdata[13];
- assign mio_pad_sleep_status_1_en_46_we = addr_hit[347] & reg_we & !reg_error;
+ assign mio_pad_sleep_status_1_en_46_we = addr_hit[348] & reg_we & !reg_error;
assign mio_pad_sleep_status_1_en_46_wd = reg_wdata[14];
- assign mio_pad_sleep_regwen_0_we = addr_hit[348] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_0_we = addr_hit[349] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_0_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_1_we = addr_hit[349] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_1_we = addr_hit[350] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_1_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_2_we = addr_hit[350] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_2_we = addr_hit[351] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_2_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_3_we = addr_hit[351] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_3_we = addr_hit[352] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_3_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_4_we = addr_hit[352] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_4_we = addr_hit[353] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_4_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_5_we = addr_hit[353] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_5_we = addr_hit[354] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_5_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_6_we = addr_hit[354] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_6_we = addr_hit[355] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_6_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_7_we = addr_hit[355] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_7_we = addr_hit[356] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_7_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_8_we = addr_hit[356] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_8_we = addr_hit[357] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_8_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_9_we = addr_hit[357] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_9_we = addr_hit[358] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_9_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_10_we = addr_hit[358] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_10_we = addr_hit[359] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_10_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_11_we = addr_hit[359] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_11_we = addr_hit[360] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_11_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_12_we = addr_hit[360] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_12_we = addr_hit[361] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_12_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_13_we = addr_hit[361] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_13_we = addr_hit[362] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_13_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_14_we = addr_hit[362] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_14_we = addr_hit[363] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_14_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_15_we = addr_hit[363] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_15_we = addr_hit[364] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_15_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_16_we = addr_hit[364] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_16_we = addr_hit[365] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_16_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_17_we = addr_hit[365] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_17_we = addr_hit[366] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_17_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_18_we = addr_hit[366] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_18_we = addr_hit[367] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_18_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_19_we = addr_hit[367] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_19_we = addr_hit[368] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_19_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_20_we = addr_hit[368] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_20_we = addr_hit[369] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_20_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_21_we = addr_hit[369] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_21_we = addr_hit[370] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_21_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_22_we = addr_hit[370] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_22_we = addr_hit[371] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_22_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_23_we = addr_hit[371] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_23_we = addr_hit[372] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_23_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_24_we = addr_hit[372] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_24_we = addr_hit[373] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_24_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_25_we = addr_hit[373] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_25_we = addr_hit[374] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_25_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_26_we = addr_hit[374] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_26_we = addr_hit[375] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_26_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_27_we = addr_hit[375] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_27_we = addr_hit[376] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_27_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_28_we = addr_hit[376] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_28_we = addr_hit[377] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_28_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_29_we = addr_hit[377] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_29_we = addr_hit[378] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_29_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_30_we = addr_hit[378] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_30_we = addr_hit[379] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_30_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_31_we = addr_hit[379] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_31_we = addr_hit[380] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_31_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_32_we = addr_hit[380] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_32_we = addr_hit[381] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_32_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_33_we = addr_hit[381] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_33_we = addr_hit[382] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_33_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_34_we = addr_hit[382] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_34_we = addr_hit[383] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_34_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_35_we = addr_hit[383] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_35_we = addr_hit[384] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_35_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_36_we = addr_hit[384] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_36_we = addr_hit[385] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_36_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_37_we = addr_hit[385] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_37_we = addr_hit[386] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_37_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_38_we = addr_hit[386] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_38_we = addr_hit[387] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_38_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_39_we = addr_hit[387] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_39_we = addr_hit[388] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_39_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_40_we = addr_hit[388] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_40_we = addr_hit[389] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_40_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_41_we = addr_hit[389] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_41_we = addr_hit[390] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_41_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_42_we = addr_hit[390] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_42_we = addr_hit[391] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_42_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_43_we = addr_hit[391] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_43_we = addr_hit[392] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_43_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_44_we = addr_hit[392] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_44_we = addr_hit[393] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_44_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_45_we = addr_hit[393] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_45_we = addr_hit[394] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_45_wd = reg_wdata[0];
- assign mio_pad_sleep_regwen_46_we = addr_hit[394] & reg_we & !reg_error;
+ assign mio_pad_sleep_regwen_46_we = addr_hit[395] & reg_we & !reg_error;
assign mio_pad_sleep_regwen_46_wd = reg_wdata[0];
- assign mio_pad_sleep_en_0_we = addr_hit[395] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_0_we = addr_hit[396] & reg_we & !reg_error;
assign mio_pad_sleep_en_0_wd = reg_wdata[0];
- assign mio_pad_sleep_en_1_we = addr_hit[396] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_1_we = addr_hit[397] & reg_we & !reg_error;
assign mio_pad_sleep_en_1_wd = reg_wdata[0];
- assign mio_pad_sleep_en_2_we = addr_hit[397] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_2_we = addr_hit[398] & reg_we & !reg_error;
assign mio_pad_sleep_en_2_wd = reg_wdata[0];
- assign mio_pad_sleep_en_3_we = addr_hit[398] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_3_we = addr_hit[399] & reg_we & !reg_error;
assign mio_pad_sleep_en_3_wd = reg_wdata[0];
- assign mio_pad_sleep_en_4_we = addr_hit[399] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_4_we = addr_hit[400] & reg_we & !reg_error;
assign mio_pad_sleep_en_4_wd = reg_wdata[0];
- assign mio_pad_sleep_en_5_we = addr_hit[400] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_5_we = addr_hit[401] & reg_we & !reg_error;
assign mio_pad_sleep_en_5_wd = reg_wdata[0];
- assign mio_pad_sleep_en_6_we = addr_hit[401] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_6_we = addr_hit[402] & reg_we & !reg_error;
assign mio_pad_sleep_en_6_wd = reg_wdata[0];
- assign mio_pad_sleep_en_7_we = addr_hit[402] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_7_we = addr_hit[403] & reg_we & !reg_error;
assign mio_pad_sleep_en_7_wd = reg_wdata[0];
- assign mio_pad_sleep_en_8_we = addr_hit[403] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_8_we = addr_hit[404] & reg_we & !reg_error;
assign mio_pad_sleep_en_8_wd = reg_wdata[0];
- assign mio_pad_sleep_en_9_we = addr_hit[404] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_9_we = addr_hit[405] & reg_we & !reg_error;
assign mio_pad_sleep_en_9_wd = reg_wdata[0];
- assign mio_pad_sleep_en_10_we = addr_hit[405] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_10_we = addr_hit[406] & reg_we & !reg_error;
assign mio_pad_sleep_en_10_wd = reg_wdata[0];
- assign mio_pad_sleep_en_11_we = addr_hit[406] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_11_we = addr_hit[407] & reg_we & !reg_error;
assign mio_pad_sleep_en_11_wd = reg_wdata[0];
- assign mio_pad_sleep_en_12_we = addr_hit[407] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_12_we = addr_hit[408] & reg_we & !reg_error;
assign mio_pad_sleep_en_12_wd = reg_wdata[0];
- assign mio_pad_sleep_en_13_we = addr_hit[408] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_13_we = addr_hit[409] & reg_we & !reg_error;
assign mio_pad_sleep_en_13_wd = reg_wdata[0];
- assign mio_pad_sleep_en_14_we = addr_hit[409] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_14_we = addr_hit[410] & reg_we & !reg_error;
assign mio_pad_sleep_en_14_wd = reg_wdata[0];
- assign mio_pad_sleep_en_15_we = addr_hit[410] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_15_we = addr_hit[411] & reg_we & !reg_error;
assign mio_pad_sleep_en_15_wd = reg_wdata[0];
- assign mio_pad_sleep_en_16_we = addr_hit[411] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_16_we = addr_hit[412] & reg_we & !reg_error;
assign mio_pad_sleep_en_16_wd = reg_wdata[0];
- assign mio_pad_sleep_en_17_we = addr_hit[412] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_17_we = addr_hit[413] & reg_we & !reg_error;
assign mio_pad_sleep_en_17_wd = reg_wdata[0];
- assign mio_pad_sleep_en_18_we = addr_hit[413] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_18_we = addr_hit[414] & reg_we & !reg_error;
assign mio_pad_sleep_en_18_wd = reg_wdata[0];
- assign mio_pad_sleep_en_19_we = addr_hit[414] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_19_we = addr_hit[415] & reg_we & !reg_error;
assign mio_pad_sleep_en_19_wd = reg_wdata[0];
- assign mio_pad_sleep_en_20_we = addr_hit[415] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_20_we = addr_hit[416] & reg_we & !reg_error;
assign mio_pad_sleep_en_20_wd = reg_wdata[0];
- assign mio_pad_sleep_en_21_we = addr_hit[416] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_21_we = addr_hit[417] & reg_we & !reg_error;
assign mio_pad_sleep_en_21_wd = reg_wdata[0];
- assign mio_pad_sleep_en_22_we = addr_hit[417] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_22_we = addr_hit[418] & reg_we & !reg_error;
assign mio_pad_sleep_en_22_wd = reg_wdata[0];
- assign mio_pad_sleep_en_23_we = addr_hit[418] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_23_we = addr_hit[419] & reg_we & !reg_error;
assign mio_pad_sleep_en_23_wd = reg_wdata[0];
- assign mio_pad_sleep_en_24_we = addr_hit[419] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_24_we = addr_hit[420] & reg_we & !reg_error;
assign mio_pad_sleep_en_24_wd = reg_wdata[0];
- assign mio_pad_sleep_en_25_we = addr_hit[420] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_25_we = addr_hit[421] & reg_we & !reg_error;
assign mio_pad_sleep_en_25_wd = reg_wdata[0];
- assign mio_pad_sleep_en_26_we = addr_hit[421] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_26_we = addr_hit[422] & reg_we & !reg_error;
assign mio_pad_sleep_en_26_wd = reg_wdata[0];
- assign mio_pad_sleep_en_27_we = addr_hit[422] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_27_we = addr_hit[423] & reg_we & !reg_error;
assign mio_pad_sleep_en_27_wd = reg_wdata[0];
- assign mio_pad_sleep_en_28_we = addr_hit[423] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_28_we = addr_hit[424] & reg_we & !reg_error;
assign mio_pad_sleep_en_28_wd = reg_wdata[0];
- assign mio_pad_sleep_en_29_we = addr_hit[424] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_29_we = addr_hit[425] & reg_we & !reg_error;
assign mio_pad_sleep_en_29_wd = reg_wdata[0];
- assign mio_pad_sleep_en_30_we = addr_hit[425] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_30_we = addr_hit[426] & reg_we & !reg_error;
assign mio_pad_sleep_en_30_wd = reg_wdata[0];
- assign mio_pad_sleep_en_31_we = addr_hit[426] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_31_we = addr_hit[427] & reg_we & !reg_error;
assign mio_pad_sleep_en_31_wd = reg_wdata[0];
- assign mio_pad_sleep_en_32_we = addr_hit[427] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_32_we = addr_hit[428] & reg_we & !reg_error;
assign mio_pad_sleep_en_32_wd = reg_wdata[0];
- assign mio_pad_sleep_en_33_we = addr_hit[428] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_33_we = addr_hit[429] & reg_we & !reg_error;
assign mio_pad_sleep_en_33_wd = reg_wdata[0];
- assign mio_pad_sleep_en_34_we = addr_hit[429] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_34_we = addr_hit[430] & reg_we & !reg_error;
assign mio_pad_sleep_en_34_wd = reg_wdata[0];
- assign mio_pad_sleep_en_35_we = addr_hit[430] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_35_we = addr_hit[431] & reg_we & !reg_error;
assign mio_pad_sleep_en_35_wd = reg_wdata[0];
- assign mio_pad_sleep_en_36_we = addr_hit[431] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_36_we = addr_hit[432] & reg_we & !reg_error;
assign mio_pad_sleep_en_36_wd = reg_wdata[0];
- assign mio_pad_sleep_en_37_we = addr_hit[432] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_37_we = addr_hit[433] & reg_we & !reg_error;
assign mio_pad_sleep_en_37_wd = reg_wdata[0];
- assign mio_pad_sleep_en_38_we = addr_hit[433] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_38_we = addr_hit[434] & reg_we & !reg_error;
assign mio_pad_sleep_en_38_wd = reg_wdata[0];
- assign mio_pad_sleep_en_39_we = addr_hit[434] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_39_we = addr_hit[435] & reg_we & !reg_error;
assign mio_pad_sleep_en_39_wd = reg_wdata[0];
- assign mio_pad_sleep_en_40_we = addr_hit[435] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_40_we = addr_hit[436] & reg_we & !reg_error;
assign mio_pad_sleep_en_40_wd = reg_wdata[0];
- assign mio_pad_sleep_en_41_we = addr_hit[436] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_41_we = addr_hit[437] & reg_we & !reg_error;
assign mio_pad_sleep_en_41_wd = reg_wdata[0];
- assign mio_pad_sleep_en_42_we = addr_hit[437] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_42_we = addr_hit[438] & reg_we & !reg_error;
assign mio_pad_sleep_en_42_wd = reg_wdata[0];
- assign mio_pad_sleep_en_43_we = addr_hit[438] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_43_we = addr_hit[439] & reg_we & !reg_error;
assign mio_pad_sleep_en_43_wd = reg_wdata[0];
- assign mio_pad_sleep_en_44_we = addr_hit[439] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_44_we = addr_hit[440] & reg_we & !reg_error;
assign mio_pad_sleep_en_44_wd = reg_wdata[0];
- assign mio_pad_sleep_en_45_we = addr_hit[440] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_45_we = addr_hit[441] & reg_we & !reg_error;
assign mio_pad_sleep_en_45_wd = reg_wdata[0];
- assign mio_pad_sleep_en_46_we = addr_hit[441] & reg_we & !reg_error;
+ assign mio_pad_sleep_en_46_we = addr_hit[442] & reg_we & !reg_error;
assign mio_pad_sleep_en_46_wd = reg_wdata[0];
- assign mio_pad_sleep_mode_0_we = addr_hit[442] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_0_we = addr_hit[443] & reg_we & !reg_error;
assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_1_we = addr_hit[443] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_1_we = addr_hit[444] & reg_we & !reg_error;
assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_2_we = addr_hit[444] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_2_we = addr_hit[445] & reg_we & !reg_error;
assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_3_we = addr_hit[445] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_3_we = addr_hit[446] & reg_we & !reg_error;
assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_4_we = addr_hit[446] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_4_we = addr_hit[447] & reg_we & !reg_error;
assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_5_we = addr_hit[447] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_5_we = addr_hit[448] & reg_we & !reg_error;
assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_6_we = addr_hit[448] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_6_we = addr_hit[449] & reg_we & !reg_error;
assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_7_we = addr_hit[449] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_7_we = addr_hit[450] & reg_we & !reg_error;
assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_8_we = addr_hit[450] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_8_we = addr_hit[451] & reg_we & !reg_error;
assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_9_we = addr_hit[451] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_9_we = addr_hit[452] & reg_we & !reg_error;
assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_10_we = addr_hit[452] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_10_we = addr_hit[453] & reg_we & !reg_error;
assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_11_we = addr_hit[453] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_11_we = addr_hit[454] & reg_we & !reg_error;
assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_12_we = addr_hit[454] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_12_we = addr_hit[455] & reg_we & !reg_error;
assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_13_we = addr_hit[455] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_13_we = addr_hit[456] & reg_we & !reg_error;
assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_14_we = addr_hit[456] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_14_we = addr_hit[457] & reg_we & !reg_error;
assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_15_we = addr_hit[457] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_15_we = addr_hit[458] & reg_we & !reg_error;
assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_16_we = addr_hit[458] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_16_we = addr_hit[459] & reg_we & !reg_error;
assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_17_we = addr_hit[459] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_17_we = addr_hit[460] & reg_we & !reg_error;
assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_18_we = addr_hit[460] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_18_we = addr_hit[461] & reg_we & !reg_error;
assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_19_we = addr_hit[461] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_19_we = addr_hit[462] & reg_we & !reg_error;
assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_20_we = addr_hit[462] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_20_we = addr_hit[463] & reg_we & !reg_error;
assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_21_we = addr_hit[463] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_21_we = addr_hit[464] & reg_we & !reg_error;
assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_22_we = addr_hit[464] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_22_we = addr_hit[465] & reg_we & !reg_error;
assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_23_we = addr_hit[465] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_23_we = addr_hit[466] & reg_we & !reg_error;
assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_24_we = addr_hit[466] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_24_we = addr_hit[467] & reg_we & !reg_error;
assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_25_we = addr_hit[467] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_25_we = addr_hit[468] & reg_we & !reg_error;
assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_26_we = addr_hit[468] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_26_we = addr_hit[469] & reg_we & !reg_error;
assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_27_we = addr_hit[469] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_27_we = addr_hit[470] & reg_we & !reg_error;
assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_28_we = addr_hit[470] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_28_we = addr_hit[471] & reg_we & !reg_error;
assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_29_we = addr_hit[471] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_29_we = addr_hit[472] & reg_we & !reg_error;
assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_30_we = addr_hit[472] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_30_we = addr_hit[473] & reg_we & !reg_error;
assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_31_we = addr_hit[473] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_31_we = addr_hit[474] & reg_we & !reg_error;
assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_32_we = addr_hit[474] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_32_we = addr_hit[475] & reg_we & !reg_error;
assign mio_pad_sleep_mode_32_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_33_we = addr_hit[475] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_33_we = addr_hit[476] & reg_we & !reg_error;
assign mio_pad_sleep_mode_33_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_34_we = addr_hit[476] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_34_we = addr_hit[477] & reg_we & !reg_error;
assign mio_pad_sleep_mode_34_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_35_we = addr_hit[477] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_35_we = addr_hit[478] & reg_we & !reg_error;
assign mio_pad_sleep_mode_35_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_36_we = addr_hit[478] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_36_we = addr_hit[479] & reg_we & !reg_error;
assign mio_pad_sleep_mode_36_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_37_we = addr_hit[479] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_37_we = addr_hit[480] & reg_we & !reg_error;
assign mio_pad_sleep_mode_37_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_38_we = addr_hit[480] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_38_we = addr_hit[481] & reg_we & !reg_error;
assign mio_pad_sleep_mode_38_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_39_we = addr_hit[481] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_39_we = addr_hit[482] & reg_we & !reg_error;
assign mio_pad_sleep_mode_39_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_40_we = addr_hit[482] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_40_we = addr_hit[483] & reg_we & !reg_error;
assign mio_pad_sleep_mode_40_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_41_we = addr_hit[483] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_41_we = addr_hit[484] & reg_we & !reg_error;
assign mio_pad_sleep_mode_41_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_42_we = addr_hit[484] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_42_we = addr_hit[485] & reg_we & !reg_error;
assign mio_pad_sleep_mode_42_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_43_we = addr_hit[485] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_43_we = addr_hit[486] & reg_we & !reg_error;
assign mio_pad_sleep_mode_43_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_44_we = addr_hit[486] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_44_we = addr_hit[487] & reg_we & !reg_error;
assign mio_pad_sleep_mode_44_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_45_we = addr_hit[487] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_45_we = addr_hit[488] & reg_we & !reg_error;
assign mio_pad_sleep_mode_45_wd = reg_wdata[1:0];
- assign mio_pad_sleep_mode_46_we = addr_hit[488] & reg_we & !reg_error;
+ assign mio_pad_sleep_mode_46_we = addr_hit[489] & reg_we & !reg_error;
assign mio_pad_sleep_mode_46_wd = reg_wdata[1:0];
- assign dio_pad_sleep_status_en_0_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_0_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_0_wd = reg_wdata[0];
- assign dio_pad_sleep_status_en_1_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_1_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_1_wd = reg_wdata[1];
- assign dio_pad_sleep_status_en_2_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_2_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_2_wd = reg_wdata[2];
- assign dio_pad_sleep_status_en_3_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_3_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_3_wd = reg_wdata[3];
- assign dio_pad_sleep_status_en_4_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_4_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_4_wd = reg_wdata[4];
- assign dio_pad_sleep_status_en_5_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_5_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_5_wd = reg_wdata[5];
- assign dio_pad_sleep_status_en_6_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_6_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_6_wd = reg_wdata[6];
- assign dio_pad_sleep_status_en_7_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_7_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_7_wd = reg_wdata[7];
- assign dio_pad_sleep_status_en_8_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_8_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_8_wd = reg_wdata[8];
- assign dio_pad_sleep_status_en_9_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_9_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_9_wd = reg_wdata[9];
- assign dio_pad_sleep_status_en_10_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_10_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_10_wd = reg_wdata[10];
- assign dio_pad_sleep_status_en_11_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_11_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_11_wd = reg_wdata[11];
- assign dio_pad_sleep_status_en_12_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_12_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_12_wd = reg_wdata[12];
- assign dio_pad_sleep_status_en_13_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_13_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_13_wd = reg_wdata[13];
- assign dio_pad_sleep_status_en_14_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_14_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_14_wd = reg_wdata[14];
- assign dio_pad_sleep_status_en_15_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_15_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_15_wd = reg_wdata[15];
- assign dio_pad_sleep_status_en_16_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_16_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_16_wd = reg_wdata[16];
- assign dio_pad_sleep_status_en_17_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_17_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_17_wd = reg_wdata[17];
- assign dio_pad_sleep_status_en_18_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_18_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_18_wd = reg_wdata[18];
- assign dio_pad_sleep_status_en_19_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_19_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_19_wd = reg_wdata[19];
- assign dio_pad_sleep_status_en_20_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_20_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_20_wd = reg_wdata[20];
- assign dio_pad_sleep_status_en_21_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_21_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_21_wd = reg_wdata[21];
- assign dio_pad_sleep_status_en_22_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_22_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_22_wd = reg_wdata[22];
- assign dio_pad_sleep_status_en_23_we = addr_hit[489] & reg_we & !reg_error;
+ assign dio_pad_sleep_status_en_23_we = addr_hit[490] & reg_we & !reg_error;
assign dio_pad_sleep_status_en_23_wd = reg_wdata[23];
- assign dio_pad_sleep_regwen_0_we = addr_hit[490] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_0_we = addr_hit[491] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_0_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_1_we = addr_hit[491] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_1_we = addr_hit[492] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_1_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_2_we = addr_hit[492] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_2_we = addr_hit[493] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_2_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_3_we = addr_hit[493] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_3_we = addr_hit[494] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_3_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_4_we = addr_hit[494] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_4_we = addr_hit[495] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_4_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_5_we = addr_hit[495] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_5_we = addr_hit[496] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_5_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_6_we = addr_hit[496] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_6_we = addr_hit[497] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_6_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_7_we = addr_hit[497] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_7_we = addr_hit[498] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_7_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_8_we = addr_hit[498] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_8_we = addr_hit[499] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_8_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_9_we = addr_hit[499] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_9_we = addr_hit[500] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_9_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_10_we = addr_hit[500] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_10_we = addr_hit[501] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_10_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_11_we = addr_hit[501] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_11_we = addr_hit[502] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_11_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_12_we = addr_hit[502] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_12_we = addr_hit[503] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_12_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_13_we = addr_hit[503] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_13_we = addr_hit[504] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_13_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_14_we = addr_hit[504] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_14_we = addr_hit[505] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_14_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_15_we = addr_hit[505] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_15_we = addr_hit[506] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_15_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_16_we = addr_hit[506] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_16_we = addr_hit[507] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_16_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_17_we = addr_hit[507] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_17_we = addr_hit[508] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_17_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_18_we = addr_hit[508] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_18_we = addr_hit[509] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_18_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_19_we = addr_hit[509] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_19_we = addr_hit[510] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_19_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_20_we = addr_hit[510] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_20_we = addr_hit[511] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_20_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_21_we = addr_hit[511] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_21_we = addr_hit[512] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_21_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_22_we = addr_hit[512] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_22_we = addr_hit[513] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_22_wd = reg_wdata[0];
- assign dio_pad_sleep_regwen_23_we = addr_hit[513] & reg_we & !reg_error;
+ assign dio_pad_sleep_regwen_23_we = addr_hit[514] & reg_we & !reg_error;
assign dio_pad_sleep_regwen_23_wd = reg_wdata[0];
- assign dio_pad_sleep_en_0_we = addr_hit[514] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_0_we = addr_hit[515] & reg_we & !reg_error;
assign dio_pad_sleep_en_0_wd = reg_wdata[0];
- assign dio_pad_sleep_en_1_we = addr_hit[515] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_1_we = addr_hit[516] & reg_we & !reg_error;
assign dio_pad_sleep_en_1_wd = reg_wdata[0];
- assign dio_pad_sleep_en_2_we = addr_hit[516] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_2_we = addr_hit[517] & reg_we & !reg_error;
assign dio_pad_sleep_en_2_wd = reg_wdata[0];
- assign dio_pad_sleep_en_3_we = addr_hit[517] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_3_we = addr_hit[518] & reg_we & !reg_error;
assign dio_pad_sleep_en_3_wd = reg_wdata[0];
- assign dio_pad_sleep_en_4_we = addr_hit[518] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_4_we = addr_hit[519] & reg_we & !reg_error;
assign dio_pad_sleep_en_4_wd = reg_wdata[0];
- assign dio_pad_sleep_en_5_we = addr_hit[519] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_5_we = addr_hit[520] & reg_we & !reg_error;
assign dio_pad_sleep_en_5_wd = reg_wdata[0];
- assign dio_pad_sleep_en_6_we = addr_hit[520] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_6_we = addr_hit[521] & reg_we & !reg_error;
assign dio_pad_sleep_en_6_wd = reg_wdata[0];
- assign dio_pad_sleep_en_7_we = addr_hit[521] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_7_we = addr_hit[522] & reg_we & !reg_error;
assign dio_pad_sleep_en_7_wd = reg_wdata[0];
- assign dio_pad_sleep_en_8_we = addr_hit[522] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_8_we = addr_hit[523] & reg_we & !reg_error;
assign dio_pad_sleep_en_8_wd = reg_wdata[0];
- assign dio_pad_sleep_en_9_we = addr_hit[523] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_9_we = addr_hit[524] & reg_we & !reg_error;
assign dio_pad_sleep_en_9_wd = reg_wdata[0];
- assign dio_pad_sleep_en_10_we = addr_hit[524] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_10_we = addr_hit[525] & reg_we & !reg_error;
assign dio_pad_sleep_en_10_wd = reg_wdata[0];
- assign dio_pad_sleep_en_11_we = addr_hit[525] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_11_we = addr_hit[526] & reg_we & !reg_error;
assign dio_pad_sleep_en_11_wd = reg_wdata[0];
- assign dio_pad_sleep_en_12_we = addr_hit[526] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_12_we = addr_hit[527] & reg_we & !reg_error;
assign dio_pad_sleep_en_12_wd = reg_wdata[0];
- assign dio_pad_sleep_en_13_we = addr_hit[527] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_13_we = addr_hit[528] & reg_we & !reg_error;
assign dio_pad_sleep_en_13_wd = reg_wdata[0];
- assign dio_pad_sleep_en_14_we = addr_hit[528] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_14_we = addr_hit[529] & reg_we & !reg_error;
assign dio_pad_sleep_en_14_wd = reg_wdata[0];
- assign dio_pad_sleep_en_15_we = addr_hit[529] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_15_we = addr_hit[530] & reg_we & !reg_error;
assign dio_pad_sleep_en_15_wd = reg_wdata[0];
- assign dio_pad_sleep_en_16_we = addr_hit[530] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_16_we = addr_hit[531] & reg_we & !reg_error;
assign dio_pad_sleep_en_16_wd = reg_wdata[0];
- assign dio_pad_sleep_en_17_we = addr_hit[531] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_17_we = addr_hit[532] & reg_we & !reg_error;
assign dio_pad_sleep_en_17_wd = reg_wdata[0];
- assign dio_pad_sleep_en_18_we = addr_hit[532] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_18_we = addr_hit[533] & reg_we & !reg_error;
assign dio_pad_sleep_en_18_wd = reg_wdata[0];
- assign dio_pad_sleep_en_19_we = addr_hit[533] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_19_we = addr_hit[534] & reg_we & !reg_error;
assign dio_pad_sleep_en_19_wd = reg_wdata[0];
- assign dio_pad_sleep_en_20_we = addr_hit[534] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_20_we = addr_hit[535] & reg_we & !reg_error;
assign dio_pad_sleep_en_20_wd = reg_wdata[0];
- assign dio_pad_sleep_en_21_we = addr_hit[535] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_21_we = addr_hit[536] & reg_we & !reg_error;
assign dio_pad_sleep_en_21_wd = reg_wdata[0];
- assign dio_pad_sleep_en_22_we = addr_hit[536] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_22_we = addr_hit[537] & reg_we & !reg_error;
assign dio_pad_sleep_en_22_wd = reg_wdata[0];
- assign dio_pad_sleep_en_23_we = addr_hit[537] & reg_we & !reg_error;
+ assign dio_pad_sleep_en_23_we = addr_hit[538] & reg_we & !reg_error;
assign dio_pad_sleep_en_23_wd = reg_wdata[0];
- assign dio_pad_sleep_mode_0_we = addr_hit[538] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_0_we = addr_hit[539] & reg_we & !reg_error;
assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_1_we = addr_hit[539] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_1_we = addr_hit[540] & reg_we & !reg_error;
assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_2_we = addr_hit[540] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_2_we = addr_hit[541] & reg_we & !reg_error;
assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_3_we = addr_hit[541] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_3_we = addr_hit[542] & reg_we & !reg_error;
assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_4_we = addr_hit[542] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_4_we = addr_hit[543] & reg_we & !reg_error;
assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_5_we = addr_hit[543] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_5_we = addr_hit[544] & reg_we & !reg_error;
assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_6_we = addr_hit[544] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_6_we = addr_hit[545] & reg_we & !reg_error;
assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_7_we = addr_hit[545] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_7_we = addr_hit[546] & reg_we & !reg_error;
assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_8_we = addr_hit[546] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_8_we = addr_hit[547] & reg_we & !reg_error;
assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_9_we = addr_hit[547] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_9_we = addr_hit[548] & reg_we & !reg_error;
assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_10_we = addr_hit[548] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_10_we = addr_hit[549] & reg_we & !reg_error;
assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_11_we = addr_hit[549] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_11_we = addr_hit[550] & reg_we & !reg_error;
assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_12_we = addr_hit[550] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_12_we = addr_hit[551] & reg_we & !reg_error;
assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_13_we = addr_hit[551] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_13_we = addr_hit[552] & reg_we & !reg_error;
assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_14_we = addr_hit[552] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_14_we = addr_hit[553] & reg_we & !reg_error;
assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_15_we = addr_hit[553] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_15_we = addr_hit[554] & reg_we & !reg_error;
assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_16_we = addr_hit[554] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_16_we = addr_hit[555] & reg_we & !reg_error;
assign dio_pad_sleep_mode_16_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_17_we = addr_hit[555] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_17_we = addr_hit[556] & reg_we & !reg_error;
assign dio_pad_sleep_mode_17_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_18_we = addr_hit[556] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_18_we = addr_hit[557] & reg_we & !reg_error;
assign dio_pad_sleep_mode_18_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_19_we = addr_hit[557] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_19_we = addr_hit[558] & reg_we & !reg_error;
assign dio_pad_sleep_mode_19_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_20_we = addr_hit[558] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_20_we = addr_hit[559] & reg_we & !reg_error;
assign dio_pad_sleep_mode_20_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_21_we = addr_hit[559] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_21_we = addr_hit[560] & reg_we & !reg_error;
assign dio_pad_sleep_mode_21_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_22_we = addr_hit[560] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_22_we = addr_hit[561] & reg_we & !reg_error;
assign dio_pad_sleep_mode_22_wd = reg_wdata[1:0];
- assign dio_pad_sleep_mode_23_we = addr_hit[561] & reg_we & !reg_error;
+ assign dio_pad_sleep_mode_23_we = addr_hit[562] & reg_we & !reg_error;
assign dio_pad_sleep_mode_23_wd = reg_wdata[1:0];
- assign wkup_detector_regwen_0_we = addr_hit[562] & reg_we & !reg_error;
+ assign wkup_detector_regwen_0_we = addr_hit[563] & reg_we & !reg_error;
assign wkup_detector_regwen_0_wd = reg_wdata[0];
- assign wkup_detector_regwen_1_we = addr_hit[563] & reg_we & !reg_error;
+ assign wkup_detector_regwen_1_we = addr_hit[564] & reg_we & !reg_error;
assign wkup_detector_regwen_1_wd = reg_wdata[0];
- assign wkup_detector_regwen_2_we = addr_hit[564] & reg_we & !reg_error;
+ assign wkup_detector_regwen_2_we = addr_hit[565] & reg_we & !reg_error;
assign wkup_detector_regwen_2_wd = reg_wdata[0];
- assign wkup_detector_regwen_3_we = addr_hit[565] & reg_we & !reg_error;
+ assign wkup_detector_regwen_3_we = addr_hit[566] & reg_we & !reg_error;
assign wkup_detector_regwen_3_wd = reg_wdata[0];
- assign wkup_detector_regwen_4_we = addr_hit[566] & reg_we & !reg_error;
+ assign wkup_detector_regwen_4_we = addr_hit[567] & reg_we & !reg_error;
assign wkup_detector_regwen_4_wd = reg_wdata[0];
- assign wkup_detector_regwen_5_we = addr_hit[567] & reg_we & !reg_error;
+ assign wkup_detector_regwen_5_we = addr_hit[568] & reg_we & !reg_error;
assign wkup_detector_regwen_5_wd = reg_wdata[0];
- assign wkup_detector_regwen_6_we = addr_hit[568] & reg_we & !reg_error;
+ assign wkup_detector_regwen_6_we = addr_hit[569] & reg_we & !reg_error;
assign wkup_detector_regwen_6_wd = reg_wdata[0];
- assign wkup_detector_regwen_7_we = addr_hit[569] & reg_we & !reg_error;
+ assign wkup_detector_regwen_7_we = addr_hit[570] & reg_we & !reg_error;
assign wkup_detector_regwen_7_wd = reg_wdata[0];
- assign wkup_detector_en_0_we = addr_hit[570] & reg_we & !reg_error;
+ assign wkup_detector_en_0_we = addr_hit[571] & reg_we & !reg_error;
assign wkup_detector_en_0_wd = reg_wdata[0];
- assign wkup_detector_en_1_we = addr_hit[571] & reg_we & !reg_error;
+ assign wkup_detector_en_1_we = addr_hit[572] & reg_we & !reg_error;
assign wkup_detector_en_1_wd = reg_wdata[0];
- assign wkup_detector_en_2_we = addr_hit[572] & reg_we & !reg_error;
+ assign wkup_detector_en_2_we = addr_hit[573] & reg_we & !reg_error;
assign wkup_detector_en_2_wd = reg_wdata[0];
- assign wkup_detector_en_3_we = addr_hit[573] & reg_we & !reg_error;
+ assign wkup_detector_en_3_we = addr_hit[574] & reg_we & !reg_error;
assign wkup_detector_en_3_wd = reg_wdata[0];
- assign wkup_detector_en_4_we = addr_hit[574] & reg_we & !reg_error;
+ assign wkup_detector_en_4_we = addr_hit[575] & reg_we & !reg_error;
assign wkup_detector_en_4_wd = reg_wdata[0];
- assign wkup_detector_en_5_we = addr_hit[575] & reg_we & !reg_error;
+ assign wkup_detector_en_5_we = addr_hit[576] & reg_we & !reg_error;
assign wkup_detector_en_5_wd = reg_wdata[0];
- assign wkup_detector_en_6_we = addr_hit[576] & reg_we & !reg_error;
+ assign wkup_detector_en_6_we = addr_hit[577] & reg_we & !reg_error;
assign wkup_detector_en_6_wd = reg_wdata[0];
- assign wkup_detector_en_7_we = addr_hit[577] & reg_we & !reg_error;
+ assign wkup_detector_en_7_we = addr_hit[578] & reg_we & !reg_error;
assign wkup_detector_en_7_wd = reg_wdata[0];
- assign wkup_detector_0_mode_0_we = addr_hit[578] & reg_we & !reg_error;
+ assign wkup_detector_0_mode_0_we = addr_hit[579] & reg_we & !reg_error;
assign wkup_detector_0_mode_0_wd = reg_wdata[2:0];
- assign wkup_detector_0_filter_0_we = addr_hit[578] & reg_we & !reg_error;
+ assign wkup_detector_0_filter_0_we = addr_hit[579] & reg_we & !reg_error;
assign wkup_detector_0_filter_0_wd = reg_wdata[3];
- assign wkup_detector_0_miodio_0_we = addr_hit[578] & reg_we & !reg_error;
+ assign wkup_detector_0_miodio_0_we = addr_hit[579] & reg_we & !reg_error;
assign wkup_detector_0_miodio_0_wd = reg_wdata[4];
- assign wkup_detector_1_mode_1_we = addr_hit[579] & reg_we & !reg_error;
+ assign wkup_detector_1_mode_1_we = addr_hit[580] & reg_we & !reg_error;
assign wkup_detector_1_mode_1_wd = reg_wdata[2:0];
- assign wkup_detector_1_filter_1_we = addr_hit[579] & reg_we & !reg_error;
+ assign wkup_detector_1_filter_1_we = addr_hit[580] & reg_we & !reg_error;
assign wkup_detector_1_filter_1_wd = reg_wdata[3];
- assign wkup_detector_1_miodio_1_we = addr_hit[579] & reg_we & !reg_error;
+ assign wkup_detector_1_miodio_1_we = addr_hit[580] & reg_we & !reg_error;
assign wkup_detector_1_miodio_1_wd = reg_wdata[4];
- assign wkup_detector_2_mode_2_we = addr_hit[580] & reg_we & !reg_error;
+ assign wkup_detector_2_mode_2_we = addr_hit[581] & reg_we & !reg_error;
assign wkup_detector_2_mode_2_wd = reg_wdata[2:0];
- assign wkup_detector_2_filter_2_we = addr_hit[580] & reg_we & !reg_error;
+ assign wkup_detector_2_filter_2_we = addr_hit[581] & reg_we & !reg_error;
assign wkup_detector_2_filter_2_wd = reg_wdata[3];
- assign wkup_detector_2_miodio_2_we = addr_hit[580] & reg_we & !reg_error;
+ assign wkup_detector_2_miodio_2_we = addr_hit[581] & reg_we & !reg_error;
assign wkup_detector_2_miodio_2_wd = reg_wdata[4];
- assign wkup_detector_3_mode_3_we = addr_hit[581] & reg_we & !reg_error;
+ assign wkup_detector_3_mode_3_we = addr_hit[582] & reg_we & !reg_error;
assign wkup_detector_3_mode_3_wd = reg_wdata[2:0];
- assign wkup_detector_3_filter_3_we = addr_hit[581] & reg_we & !reg_error;
+ assign wkup_detector_3_filter_3_we = addr_hit[582] & reg_we & !reg_error;
assign wkup_detector_3_filter_3_wd = reg_wdata[3];
- assign wkup_detector_3_miodio_3_we = addr_hit[581] & reg_we & !reg_error;
+ assign wkup_detector_3_miodio_3_we = addr_hit[582] & reg_we & !reg_error;
assign wkup_detector_3_miodio_3_wd = reg_wdata[4];
- assign wkup_detector_4_mode_4_we = addr_hit[582] & reg_we & !reg_error;
+ assign wkup_detector_4_mode_4_we = addr_hit[583] & reg_we & !reg_error;
assign wkup_detector_4_mode_4_wd = reg_wdata[2:0];
- assign wkup_detector_4_filter_4_we = addr_hit[582] & reg_we & !reg_error;
+ assign wkup_detector_4_filter_4_we = addr_hit[583] & reg_we & !reg_error;
assign wkup_detector_4_filter_4_wd = reg_wdata[3];
- assign wkup_detector_4_miodio_4_we = addr_hit[582] & reg_we & !reg_error;
+ assign wkup_detector_4_miodio_4_we = addr_hit[583] & reg_we & !reg_error;
assign wkup_detector_4_miodio_4_wd = reg_wdata[4];
- assign wkup_detector_5_mode_5_we = addr_hit[583] & reg_we & !reg_error;
+ assign wkup_detector_5_mode_5_we = addr_hit[584] & reg_we & !reg_error;
assign wkup_detector_5_mode_5_wd = reg_wdata[2:0];
- assign wkup_detector_5_filter_5_we = addr_hit[583] & reg_we & !reg_error;
+ assign wkup_detector_5_filter_5_we = addr_hit[584] & reg_we & !reg_error;
assign wkup_detector_5_filter_5_wd = reg_wdata[3];
- assign wkup_detector_5_miodio_5_we = addr_hit[583] & reg_we & !reg_error;
+ assign wkup_detector_5_miodio_5_we = addr_hit[584] & reg_we & !reg_error;
assign wkup_detector_5_miodio_5_wd = reg_wdata[4];
- assign wkup_detector_6_mode_6_we = addr_hit[584] & reg_we & !reg_error;
+ assign wkup_detector_6_mode_6_we = addr_hit[585] & reg_we & !reg_error;
assign wkup_detector_6_mode_6_wd = reg_wdata[2:0];
- assign wkup_detector_6_filter_6_we = addr_hit[584] & reg_we & !reg_error;
+ assign wkup_detector_6_filter_6_we = addr_hit[585] & reg_we & !reg_error;
assign wkup_detector_6_filter_6_wd = reg_wdata[3];
- assign wkup_detector_6_miodio_6_we = addr_hit[584] & reg_we & !reg_error;
+ assign wkup_detector_6_miodio_6_we = addr_hit[585] & reg_we & !reg_error;
assign wkup_detector_6_miodio_6_wd = reg_wdata[4];
- assign wkup_detector_7_mode_7_we = addr_hit[585] & reg_we & !reg_error;
+ assign wkup_detector_7_mode_7_we = addr_hit[586] & reg_we & !reg_error;
assign wkup_detector_7_mode_7_wd = reg_wdata[2:0];
- assign wkup_detector_7_filter_7_we = addr_hit[585] & reg_we & !reg_error;
+ assign wkup_detector_7_filter_7_we = addr_hit[586] & reg_we & !reg_error;
assign wkup_detector_7_filter_7_wd = reg_wdata[3];
- assign wkup_detector_7_miodio_7_we = addr_hit[585] & reg_we & !reg_error;
+ assign wkup_detector_7_miodio_7_we = addr_hit[586] & reg_we & !reg_error;
assign wkup_detector_7_miodio_7_wd = reg_wdata[4];
- assign wkup_detector_cnt_th_0_we = addr_hit[586] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_0_we = addr_hit[587] & reg_we & !reg_error;
assign wkup_detector_cnt_th_0_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_1_we = addr_hit[587] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_1_we = addr_hit[588] & reg_we & !reg_error;
assign wkup_detector_cnt_th_1_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_2_we = addr_hit[588] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_2_we = addr_hit[589] & reg_we & !reg_error;
assign wkup_detector_cnt_th_2_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_3_we = addr_hit[589] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_3_we = addr_hit[590] & reg_we & !reg_error;
assign wkup_detector_cnt_th_3_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_4_we = addr_hit[590] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_4_we = addr_hit[591] & reg_we & !reg_error;
assign wkup_detector_cnt_th_4_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_5_we = addr_hit[591] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_5_we = addr_hit[592] & reg_we & !reg_error;
assign wkup_detector_cnt_th_5_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_6_we = addr_hit[592] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_6_we = addr_hit[593] & reg_we & !reg_error;
assign wkup_detector_cnt_th_6_wd = reg_wdata[7:0];
- assign wkup_detector_cnt_th_7_we = addr_hit[593] & reg_we & !reg_error;
+ assign wkup_detector_cnt_th_7_we = addr_hit[594] & reg_we & !reg_error;
assign wkup_detector_cnt_th_7_wd = reg_wdata[7:0];
- assign wkup_detector_padsel_0_we = addr_hit[594] & reg_we & !reg_error;
+ assign wkup_detector_padsel_0_we = addr_hit[595] & reg_we & !reg_error;
assign wkup_detector_padsel_0_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_1_we = addr_hit[595] & reg_we & !reg_error;
+ assign wkup_detector_padsel_1_we = addr_hit[596] & reg_we & !reg_error;
assign wkup_detector_padsel_1_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_2_we = addr_hit[596] & reg_we & !reg_error;
+ assign wkup_detector_padsel_2_we = addr_hit[597] & reg_we & !reg_error;
assign wkup_detector_padsel_2_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_3_we = addr_hit[597] & reg_we & !reg_error;
+ assign wkup_detector_padsel_3_we = addr_hit[598] & reg_we & !reg_error;
assign wkup_detector_padsel_3_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_4_we = addr_hit[598] & reg_we & !reg_error;
+ assign wkup_detector_padsel_4_we = addr_hit[599] & reg_we & !reg_error;
assign wkup_detector_padsel_4_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_5_we = addr_hit[599] & reg_we & !reg_error;
+ assign wkup_detector_padsel_5_we = addr_hit[600] & reg_we & !reg_error;
assign wkup_detector_padsel_5_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_6_we = addr_hit[600] & reg_we & !reg_error;
+ assign wkup_detector_padsel_6_we = addr_hit[601] & reg_we & !reg_error;
assign wkup_detector_padsel_6_wd = reg_wdata[5:0];
- assign wkup_detector_padsel_7_we = addr_hit[601] & reg_we & !reg_error;
+ assign wkup_detector_padsel_7_we = addr_hit[602] & reg_we & !reg_error;
assign wkup_detector_padsel_7_wd = reg_wdata[5:0];
- assign wkup_cause_cause_0_we = addr_hit[602] & reg_we & !reg_error;
+ assign wkup_cause_cause_0_we = addr_hit[603] & reg_we & !reg_error;
assign wkup_cause_cause_0_wd = reg_wdata[0];
- assign wkup_cause_cause_0_re = addr_hit[602] & reg_re & !reg_error;
+ assign wkup_cause_cause_0_re = addr_hit[603] & reg_re & !reg_error;
- assign wkup_cause_cause_1_we = addr_hit[602] & reg_we & !reg_error;
+ assign wkup_cause_cause_1_we = addr_hit[603] & reg_we & !reg_error;
assign wkup_cause_cause_1_wd = reg_wdata[1];
- assign wkup_cause_cause_1_re = addr_hit[602] & reg_re & !reg_error;
+ assign wkup_cause_cause_1_re = addr_hit[603] & reg_re & !reg_error;
- assign wkup_cause_cause_2_we = addr_hit[602] & reg_we & !reg_error;
+ assign wkup_cause_cause_2_we = addr_hit[603] & reg_we & !reg_error;
assign wkup_cause_cause_2_wd = reg_wdata[2];
- assign wkup_cause_cause_2_re = addr_hit[602] & reg_re & !reg_error;
+ assign wkup_cause_cause_2_re = addr_hit[603] & reg_re & !reg_error;
- assign wkup_cause_cause_3_we = addr_hit[602] & reg_we & !reg_error;
+ assign wkup_cause_cause_3_we = addr_hit[603] & reg_we & !reg_error;
assign wkup_cause_cause_3_wd = reg_wdata[3];
- assign wkup_cause_cause_3_re = addr_hit[602] & reg_re & !reg_error;
+ assign wkup_cause_cause_3_re = addr_hit[603] & reg_re & !reg_error;
- assign wkup_cause_cause_4_we = addr_hit[602] & reg_we & !reg_error;
+ assign wkup_cause_cause_4_we = addr_hit[603] & reg_we & !reg_error;
assign wkup_cause_cause_4_wd = reg_wdata[4];
- assign wkup_cause_cause_4_re = addr_hit[602] & reg_re & !reg_error;
+ assign wkup_cause_cause_4_re = addr_hit[603] & reg_re & !reg_error;
- assign wkup_cause_cause_5_we = addr_hit[602] & reg_we & !reg_error;
+ assign wkup_cause_cause_5_we = addr_hit[603] & reg_we & !reg_error;
assign wkup_cause_cause_5_wd = reg_wdata[5];
- assign wkup_cause_cause_5_re = addr_hit[602] & reg_re & !reg_error;
+ assign wkup_cause_cause_5_re = addr_hit[603] & reg_re & !reg_error;
- assign wkup_cause_cause_6_we = addr_hit[602] & reg_we & !reg_error;
+ assign wkup_cause_cause_6_we = addr_hit[603] & reg_we & !reg_error;
assign wkup_cause_cause_6_wd = reg_wdata[6];
- assign wkup_cause_cause_6_re = addr_hit[602] & reg_re & !reg_error;
+ assign wkup_cause_cause_6_re = addr_hit[603] & reg_re & !reg_error;
- assign wkup_cause_cause_7_we = addr_hit[602] & reg_we & !reg_error;
+ assign wkup_cause_cause_7_we = addr_hit[603] & reg_we & !reg_error;
assign wkup_cause_cause_7_wd = reg_wdata[7];
- assign wkup_cause_cause_7_re = addr_hit[602] & reg_re & !reg_error;
+ assign wkup_cause_cause_7_re = addr_hit[603] & reg_re & !reg_error;
// Read data return
always_comb begin
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_0_qs;
+ reg_rdata_next[0] = '0;
end
addr_hit[1]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_1_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_0_qs;
end
addr_hit[2]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_2_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_1_qs;
end
addr_hit[3]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_3_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_2_qs;
end
addr_hit[4]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_4_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_3_qs;
end
addr_hit[5]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_5_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_4_qs;
end
addr_hit[6]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_6_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_5_qs;
end
addr_hit[7]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_7_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_6_qs;
end
addr_hit[8]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_8_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_7_qs;
end
addr_hit[9]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_9_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_8_qs;
end
addr_hit[10]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_10_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_9_qs;
end
addr_hit[11]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_11_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_10_qs;
end
addr_hit[12]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_12_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_11_qs;
end
addr_hit[13]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_13_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_12_qs;
end
addr_hit[14]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_14_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_13_qs;
end
addr_hit[15]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_15_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_14_qs;
end
addr_hit[16]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_16_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_15_qs;
end
addr_hit[17]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_17_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_16_qs;
end
addr_hit[18]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_18_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_17_qs;
end
addr_hit[19]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_19_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_18_qs;
end
addr_hit[20]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_20_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_19_qs;
end
addr_hit[21]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_21_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_20_qs;
end
addr_hit[22]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_22_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_21_qs;
end
addr_hit[23]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_23_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_22_qs;
end
addr_hit[24]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_24_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_23_qs;
end
addr_hit[25]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_25_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_24_qs;
end
addr_hit[26]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_26_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_25_qs;
end
addr_hit[27]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_27_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_26_qs;
end
addr_hit[28]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_28_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_27_qs;
end
addr_hit[29]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_29_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_28_qs;
end
addr_hit[30]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_30_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_29_qs;
end
addr_hit[31]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_31_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_30_qs;
end
addr_hit[32]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_32_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_31_qs;
end
addr_hit[33]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_33_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_32_qs;
end
addr_hit[34]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_34_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_33_qs;
end
addr_hit[35]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_35_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_34_qs;
end
addr_hit[36]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_36_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_35_qs;
end
addr_hit[37]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_37_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_36_qs;
end
addr_hit[38]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_38_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_37_qs;
end
addr_hit[39]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_39_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_38_qs;
end
addr_hit[40]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_40_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_39_qs;
end
addr_hit[41]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_41_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_40_qs;
end
addr_hit[42]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_42_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_41_qs;
end
addr_hit[43]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_43_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_42_qs;
end
addr_hit[44]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_44_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_43_qs;
end
addr_hit[45]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_45_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_44_qs;
end
addr_hit[46]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_46_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_45_qs;
end
addr_hit[47]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_47_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_46_qs;
end
addr_hit[48]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_48_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_47_qs;
end
addr_hit[49]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_49_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_48_qs;
end
addr_hit[50]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_50_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_49_qs;
end
addr_hit[51]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_51_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_50_qs;
end
addr_hit[52]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_52_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_51_qs;
end
addr_hit[53]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_53_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_52_qs;
end
addr_hit[54]: begin
- reg_rdata_next[0] = mio_periph_insel_regwen_54_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_53_qs;
end
addr_hit[55]: begin
- reg_rdata_next[5:0] = mio_periph_insel_0_qs;
+ reg_rdata_next[0] = mio_periph_insel_regwen_54_qs;
end
addr_hit[56]: begin
- reg_rdata_next[5:0] = mio_periph_insel_1_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_0_qs;
end
addr_hit[57]: begin
- reg_rdata_next[5:0] = mio_periph_insel_2_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_1_qs;
end
addr_hit[58]: begin
- reg_rdata_next[5:0] = mio_periph_insel_3_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_2_qs;
end
addr_hit[59]: begin
- reg_rdata_next[5:0] = mio_periph_insel_4_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_3_qs;
end
addr_hit[60]: begin
- reg_rdata_next[5:0] = mio_periph_insel_5_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_4_qs;
end
addr_hit[61]: begin
- reg_rdata_next[5:0] = mio_periph_insel_6_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_5_qs;
end
addr_hit[62]: begin
- reg_rdata_next[5:0] = mio_periph_insel_7_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_6_qs;
end
addr_hit[63]: begin
- reg_rdata_next[5:0] = mio_periph_insel_8_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_7_qs;
end
addr_hit[64]: begin
- reg_rdata_next[5:0] = mio_periph_insel_9_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_8_qs;
end
addr_hit[65]: begin
- reg_rdata_next[5:0] = mio_periph_insel_10_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_9_qs;
end
addr_hit[66]: begin
- reg_rdata_next[5:0] = mio_periph_insel_11_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_10_qs;
end
addr_hit[67]: begin
- reg_rdata_next[5:0] = mio_periph_insel_12_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_11_qs;
end
addr_hit[68]: begin
- reg_rdata_next[5:0] = mio_periph_insel_13_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_12_qs;
end
addr_hit[69]: begin
- reg_rdata_next[5:0] = mio_periph_insel_14_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_13_qs;
end
addr_hit[70]: begin
- reg_rdata_next[5:0] = mio_periph_insel_15_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_14_qs;
end
addr_hit[71]: begin
- reg_rdata_next[5:0] = mio_periph_insel_16_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_15_qs;
end
addr_hit[72]: begin
- reg_rdata_next[5:0] = mio_periph_insel_17_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_16_qs;
end
addr_hit[73]: begin
- reg_rdata_next[5:0] = mio_periph_insel_18_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_17_qs;
end
addr_hit[74]: begin
- reg_rdata_next[5:0] = mio_periph_insel_19_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_18_qs;
end
addr_hit[75]: begin
- reg_rdata_next[5:0] = mio_periph_insel_20_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_19_qs;
end
addr_hit[76]: begin
- reg_rdata_next[5:0] = mio_periph_insel_21_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_20_qs;
end
addr_hit[77]: begin
- reg_rdata_next[5:0] = mio_periph_insel_22_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_21_qs;
end
addr_hit[78]: begin
- reg_rdata_next[5:0] = mio_periph_insel_23_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_22_qs;
end
addr_hit[79]: begin
- reg_rdata_next[5:0] = mio_periph_insel_24_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_23_qs;
end
addr_hit[80]: begin
- reg_rdata_next[5:0] = mio_periph_insel_25_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_24_qs;
end
addr_hit[81]: begin
- reg_rdata_next[5:0] = mio_periph_insel_26_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_25_qs;
end
addr_hit[82]: begin
- reg_rdata_next[5:0] = mio_periph_insel_27_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_26_qs;
end
addr_hit[83]: begin
- reg_rdata_next[5:0] = mio_periph_insel_28_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_27_qs;
end
addr_hit[84]: begin
- reg_rdata_next[5:0] = mio_periph_insel_29_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_28_qs;
end
addr_hit[85]: begin
- reg_rdata_next[5:0] = mio_periph_insel_30_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_29_qs;
end
addr_hit[86]: begin
- reg_rdata_next[5:0] = mio_periph_insel_31_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_30_qs;
end
addr_hit[87]: begin
- reg_rdata_next[5:0] = mio_periph_insel_32_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_31_qs;
end
addr_hit[88]: begin
- reg_rdata_next[5:0] = mio_periph_insel_33_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_32_qs;
end
addr_hit[89]: begin
- reg_rdata_next[5:0] = mio_periph_insel_34_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_33_qs;
end
addr_hit[90]: begin
- reg_rdata_next[5:0] = mio_periph_insel_35_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_34_qs;
end
addr_hit[91]: begin
- reg_rdata_next[5:0] = mio_periph_insel_36_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_35_qs;
end
addr_hit[92]: begin
- reg_rdata_next[5:0] = mio_periph_insel_37_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_36_qs;
end
addr_hit[93]: begin
- reg_rdata_next[5:0] = mio_periph_insel_38_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_37_qs;
end
addr_hit[94]: begin
- reg_rdata_next[5:0] = mio_periph_insel_39_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_38_qs;
end
addr_hit[95]: begin
- reg_rdata_next[5:0] = mio_periph_insel_40_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_39_qs;
end
addr_hit[96]: begin
- reg_rdata_next[5:0] = mio_periph_insel_41_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_40_qs;
end
addr_hit[97]: begin
- reg_rdata_next[5:0] = mio_periph_insel_42_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_41_qs;
end
addr_hit[98]: begin
- reg_rdata_next[5:0] = mio_periph_insel_43_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_42_qs;
end
addr_hit[99]: begin
- reg_rdata_next[5:0] = mio_periph_insel_44_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_43_qs;
end
addr_hit[100]: begin
- reg_rdata_next[5:0] = mio_periph_insel_45_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_44_qs;
end
addr_hit[101]: begin
- reg_rdata_next[5:0] = mio_periph_insel_46_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_45_qs;
end
addr_hit[102]: begin
- reg_rdata_next[5:0] = mio_periph_insel_47_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_46_qs;
end
addr_hit[103]: begin
- reg_rdata_next[5:0] = mio_periph_insel_48_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_47_qs;
end
addr_hit[104]: begin
- reg_rdata_next[5:0] = mio_periph_insel_49_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_48_qs;
end
addr_hit[105]: begin
- reg_rdata_next[5:0] = mio_periph_insel_50_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_49_qs;
end
addr_hit[106]: begin
- reg_rdata_next[5:0] = mio_periph_insel_51_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_50_qs;
end
addr_hit[107]: begin
- reg_rdata_next[5:0] = mio_periph_insel_52_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_51_qs;
end
addr_hit[108]: begin
- reg_rdata_next[5:0] = mio_periph_insel_53_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_52_qs;
end
addr_hit[109]: begin
- reg_rdata_next[5:0] = mio_periph_insel_54_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_53_qs;
end
addr_hit[110]: begin
- reg_rdata_next[0] = mio_outsel_regwen_0_qs;
+ reg_rdata_next[5:0] = mio_periph_insel_54_qs;
end
addr_hit[111]: begin
- reg_rdata_next[0] = mio_outsel_regwen_1_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_0_qs;
end
addr_hit[112]: begin
- reg_rdata_next[0] = mio_outsel_regwen_2_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_1_qs;
end
addr_hit[113]: begin
- reg_rdata_next[0] = mio_outsel_regwen_3_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_2_qs;
end
addr_hit[114]: begin
- reg_rdata_next[0] = mio_outsel_regwen_4_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_3_qs;
end
addr_hit[115]: begin
- reg_rdata_next[0] = mio_outsel_regwen_5_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_4_qs;
end
addr_hit[116]: begin
- reg_rdata_next[0] = mio_outsel_regwen_6_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_5_qs;
end
addr_hit[117]: begin
- reg_rdata_next[0] = mio_outsel_regwen_7_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_6_qs;
end
addr_hit[118]: begin
- reg_rdata_next[0] = mio_outsel_regwen_8_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_7_qs;
end
addr_hit[119]: begin
- reg_rdata_next[0] = mio_outsel_regwen_9_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_8_qs;
end
addr_hit[120]: begin
- reg_rdata_next[0] = mio_outsel_regwen_10_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_9_qs;
end
addr_hit[121]: begin
- reg_rdata_next[0] = mio_outsel_regwen_11_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_10_qs;
end
addr_hit[122]: begin
- reg_rdata_next[0] = mio_outsel_regwen_12_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_11_qs;
end
addr_hit[123]: begin
- reg_rdata_next[0] = mio_outsel_regwen_13_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_12_qs;
end
addr_hit[124]: begin
- reg_rdata_next[0] = mio_outsel_regwen_14_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_13_qs;
end
addr_hit[125]: begin
- reg_rdata_next[0] = mio_outsel_regwen_15_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_14_qs;
end
addr_hit[126]: begin
- reg_rdata_next[0] = mio_outsel_regwen_16_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_15_qs;
end
addr_hit[127]: begin
- reg_rdata_next[0] = mio_outsel_regwen_17_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_16_qs;
end
addr_hit[128]: begin
- reg_rdata_next[0] = mio_outsel_regwen_18_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_17_qs;
end
addr_hit[129]: begin
- reg_rdata_next[0] = mio_outsel_regwen_19_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_18_qs;
end
addr_hit[130]: begin
- reg_rdata_next[0] = mio_outsel_regwen_20_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_19_qs;
end
addr_hit[131]: begin
- reg_rdata_next[0] = mio_outsel_regwen_21_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_20_qs;
end
addr_hit[132]: begin
- reg_rdata_next[0] = mio_outsel_regwen_22_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_21_qs;
end
addr_hit[133]: begin
- reg_rdata_next[0] = mio_outsel_regwen_23_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_22_qs;
end
addr_hit[134]: begin
- reg_rdata_next[0] = mio_outsel_regwen_24_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_23_qs;
end
addr_hit[135]: begin
- reg_rdata_next[0] = mio_outsel_regwen_25_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_24_qs;
end
addr_hit[136]: begin
- reg_rdata_next[0] = mio_outsel_regwen_26_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_25_qs;
end
addr_hit[137]: begin
- reg_rdata_next[0] = mio_outsel_regwen_27_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_26_qs;
end
addr_hit[138]: begin
- reg_rdata_next[0] = mio_outsel_regwen_28_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_27_qs;
end
addr_hit[139]: begin
- reg_rdata_next[0] = mio_outsel_regwen_29_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_28_qs;
end
addr_hit[140]: begin
- reg_rdata_next[0] = mio_outsel_regwen_30_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_29_qs;
end
addr_hit[141]: begin
- reg_rdata_next[0] = mio_outsel_regwen_31_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_30_qs;
end
addr_hit[142]: begin
- reg_rdata_next[0] = mio_outsel_regwen_32_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_31_qs;
end
addr_hit[143]: begin
- reg_rdata_next[0] = mio_outsel_regwen_33_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_32_qs;
end
addr_hit[144]: begin
- reg_rdata_next[0] = mio_outsel_regwen_34_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_33_qs;
end
addr_hit[145]: begin
- reg_rdata_next[0] = mio_outsel_regwen_35_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_34_qs;
end
addr_hit[146]: begin
- reg_rdata_next[0] = mio_outsel_regwen_36_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_35_qs;
end
addr_hit[147]: begin
- reg_rdata_next[0] = mio_outsel_regwen_37_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_36_qs;
end
addr_hit[148]: begin
- reg_rdata_next[0] = mio_outsel_regwen_38_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_37_qs;
end
addr_hit[149]: begin
- reg_rdata_next[0] = mio_outsel_regwen_39_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_38_qs;
end
addr_hit[150]: begin
- reg_rdata_next[0] = mio_outsel_regwen_40_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_39_qs;
end
addr_hit[151]: begin
- reg_rdata_next[0] = mio_outsel_regwen_41_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_40_qs;
end
addr_hit[152]: begin
- reg_rdata_next[0] = mio_outsel_regwen_42_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_41_qs;
end
addr_hit[153]: begin
- reg_rdata_next[0] = mio_outsel_regwen_43_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_42_qs;
end
addr_hit[154]: begin
- reg_rdata_next[0] = mio_outsel_regwen_44_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_43_qs;
end
addr_hit[155]: begin
- reg_rdata_next[0] = mio_outsel_regwen_45_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_44_qs;
end
addr_hit[156]: begin
- reg_rdata_next[0] = mio_outsel_regwen_46_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_45_qs;
end
addr_hit[157]: begin
- reg_rdata_next[6:0] = mio_outsel_0_qs;
+ reg_rdata_next[0] = mio_outsel_regwen_46_qs;
end
addr_hit[158]: begin
- reg_rdata_next[6:0] = mio_outsel_1_qs;
+ reg_rdata_next[6:0] = mio_outsel_0_qs;
end
addr_hit[159]: begin
- reg_rdata_next[6:0] = mio_outsel_2_qs;
+ reg_rdata_next[6:0] = mio_outsel_1_qs;
end
addr_hit[160]: begin
- reg_rdata_next[6:0] = mio_outsel_3_qs;
+ reg_rdata_next[6:0] = mio_outsel_2_qs;
end
addr_hit[161]: begin
- reg_rdata_next[6:0] = mio_outsel_4_qs;
+ reg_rdata_next[6:0] = mio_outsel_3_qs;
end
addr_hit[162]: begin
- reg_rdata_next[6:0] = mio_outsel_5_qs;
+ reg_rdata_next[6:0] = mio_outsel_4_qs;
end
addr_hit[163]: begin
- reg_rdata_next[6:0] = mio_outsel_6_qs;
+ reg_rdata_next[6:0] = mio_outsel_5_qs;
end
addr_hit[164]: begin
- reg_rdata_next[6:0] = mio_outsel_7_qs;
+ reg_rdata_next[6:0] = mio_outsel_6_qs;
end
addr_hit[165]: begin
- reg_rdata_next[6:0] = mio_outsel_8_qs;
+ reg_rdata_next[6:0] = mio_outsel_7_qs;
end
addr_hit[166]: begin
- reg_rdata_next[6:0] = mio_outsel_9_qs;
+ reg_rdata_next[6:0] = mio_outsel_8_qs;
end
addr_hit[167]: begin
- reg_rdata_next[6:0] = mio_outsel_10_qs;
+ reg_rdata_next[6:0] = mio_outsel_9_qs;
end
addr_hit[168]: begin
- reg_rdata_next[6:0] = mio_outsel_11_qs;
+ reg_rdata_next[6:0] = mio_outsel_10_qs;
end
addr_hit[169]: begin
- reg_rdata_next[6:0] = mio_outsel_12_qs;
+ reg_rdata_next[6:0] = mio_outsel_11_qs;
end
addr_hit[170]: begin
- reg_rdata_next[6:0] = mio_outsel_13_qs;
+ reg_rdata_next[6:0] = mio_outsel_12_qs;
end
addr_hit[171]: begin
- reg_rdata_next[6:0] = mio_outsel_14_qs;
+ reg_rdata_next[6:0] = mio_outsel_13_qs;
end
addr_hit[172]: begin
- reg_rdata_next[6:0] = mio_outsel_15_qs;
+ reg_rdata_next[6:0] = mio_outsel_14_qs;
end
addr_hit[173]: begin
- reg_rdata_next[6:0] = mio_outsel_16_qs;
+ reg_rdata_next[6:0] = mio_outsel_15_qs;
end
addr_hit[174]: begin
- reg_rdata_next[6:0] = mio_outsel_17_qs;
+ reg_rdata_next[6:0] = mio_outsel_16_qs;
end
addr_hit[175]: begin
- reg_rdata_next[6:0] = mio_outsel_18_qs;
+ reg_rdata_next[6:0] = mio_outsel_17_qs;
end
addr_hit[176]: begin
- reg_rdata_next[6:0] = mio_outsel_19_qs;
+ reg_rdata_next[6:0] = mio_outsel_18_qs;
end
addr_hit[177]: begin
- reg_rdata_next[6:0] = mio_outsel_20_qs;
+ reg_rdata_next[6:0] = mio_outsel_19_qs;
end
addr_hit[178]: begin
- reg_rdata_next[6:0] = mio_outsel_21_qs;
+ reg_rdata_next[6:0] = mio_outsel_20_qs;
end
addr_hit[179]: begin
- reg_rdata_next[6:0] = mio_outsel_22_qs;
+ reg_rdata_next[6:0] = mio_outsel_21_qs;
end
addr_hit[180]: begin
- reg_rdata_next[6:0] = mio_outsel_23_qs;
+ reg_rdata_next[6:0] = mio_outsel_22_qs;
end
addr_hit[181]: begin
- reg_rdata_next[6:0] = mio_outsel_24_qs;
+ reg_rdata_next[6:0] = mio_outsel_23_qs;
end
addr_hit[182]: begin
- reg_rdata_next[6:0] = mio_outsel_25_qs;
+ reg_rdata_next[6:0] = mio_outsel_24_qs;
end
addr_hit[183]: begin
- reg_rdata_next[6:0] = mio_outsel_26_qs;
+ reg_rdata_next[6:0] = mio_outsel_25_qs;
end
addr_hit[184]: begin
- reg_rdata_next[6:0] = mio_outsel_27_qs;
+ reg_rdata_next[6:0] = mio_outsel_26_qs;
end
addr_hit[185]: begin
- reg_rdata_next[6:0] = mio_outsel_28_qs;
+ reg_rdata_next[6:0] = mio_outsel_27_qs;
end
addr_hit[186]: begin
- reg_rdata_next[6:0] = mio_outsel_29_qs;
+ reg_rdata_next[6:0] = mio_outsel_28_qs;
end
addr_hit[187]: begin
- reg_rdata_next[6:0] = mio_outsel_30_qs;
+ reg_rdata_next[6:0] = mio_outsel_29_qs;
end
addr_hit[188]: begin
- reg_rdata_next[6:0] = mio_outsel_31_qs;
+ reg_rdata_next[6:0] = mio_outsel_30_qs;
end
addr_hit[189]: begin
- reg_rdata_next[6:0] = mio_outsel_32_qs;
+ reg_rdata_next[6:0] = mio_outsel_31_qs;
end
addr_hit[190]: begin
- reg_rdata_next[6:0] = mio_outsel_33_qs;
+ reg_rdata_next[6:0] = mio_outsel_32_qs;
end
addr_hit[191]: begin
- reg_rdata_next[6:0] = mio_outsel_34_qs;
+ reg_rdata_next[6:0] = mio_outsel_33_qs;
end
addr_hit[192]: begin
- reg_rdata_next[6:0] = mio_outsel_35_qs;
+ reg_rdata_next[6:0] = mio_outsel_34_qs;
end
addr_hit[193]: begin
- reg_rdata_next[6:0] = mio_outsel_36_qs;
+ reg_rdata_next[6:0] = mio_outsel_35_qs;
end
addr_hit[194]: begin
- reg_rdata_next[6:0] = mio_outsel_37_qs;
+ reg_rdata_next[6:0] = mio_outsel_36_qs;
end
addr_hit[195]: begin
- reg_rdata_next[6:0] = mio_outsel_38_qs;
+ reg_rdata_next[6:0] = mio_outsel_37_qs;
end
addr_hit[196]: begin
- reg_rdata_next[6:0] = mio_outsel_39_qs;
+ reg_rdata_next[6:0] = mio_outsel_38_qs;
end
addr_hit[197]: begin
- reg_rdata_next[6:0] = mio_outsel_40_qs;
+ reg_rdata_next[6:0] = mio_outsel_39_qs;
end
addr_hit[198]: begin
- reg_rdata_next[6:0] = mio_outsel_41_qs;
+ reg_rdata_next[6:0] = mio_outsel_40_qs;
end
addr_hit[199]: begin
- reg_rdata_next[6:0] = mio_outsel_42_qs;
+ reg_rdata_next[6:0] = mio_outsel_41_qs;
end
addr_hit[200]: begin
- reg_rdata_next[6:0] = mio_outsel_43_qs;
+ reg_rdata_next[6:0] = mio_outsel_42_qs;
end
addr_hit[201]: begin
- reg_rdata_next[6:0] = mio_outsel_44_qs;
+ reg_rdata_next[6:0] = mio_outsel_43_qs;
end
addr_hit[202]: begin
- reg_rdata_next[6:0] = mio_outsel_45_qs;
+ reg_rdata_next[6:0] = mio_outsel_44_qs;
end
addr_hit[203]: begin
- reg_rdata_next[6:0] = mio_outsel_46_qs;
+ reg_rdata_next[6:0] = mio_outsel_45_qs;
end
addr_hit[204]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
+ reg_rdata_next[6:0] = mio_outsel_46_qs;
end
addr_hit[205]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
end
addr_hit[206]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
end
addr_hit[207]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
end
addr_hit[208]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
end
addr_hit[209]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
end
addr_hit[210]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
end
addr_hit[211]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
end
addr_hit[212]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
end
addr_hit[213]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
end
addr_hit[214]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
end
addr_hit[215]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
end
addr_hit[216]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
end
addr_hit[217]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
end
addr_hit[218]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
end
addr_hit[219]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
end
addr_hit[220]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
end
addr_hit[221]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
end
addr_hit[222]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
end
addr_hit[223]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
end
addr_hit[224]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
end
addr_hit[225]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
end
addr_hit[226]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
end
addr_hit[227]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
end
addr_hit[228]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
end
addr_hit[229]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
end
addr_hit[230]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
end
addr_hit[231]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
end
addr_hit[232]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
end
addr_hit[233]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
end
addr_hit[234]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
end
addr_hit[235]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
end
addr_hit[236]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_32_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
end
addr_hit[237]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_33_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_32_qs;
end
addr_hit[238]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_34_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_33_qs;
end
addr_hit[239]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_35_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_34_qs;
end
addr_hit[240]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_36_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_35_qs;
end
addr_hit[241]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_37_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_36_qs;
end
addr_hit[242]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_38_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_37_qs;
end
addr_hit[243]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_39_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_38_qs;
end
addr_hit[244]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_40_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_39_qs;
end
addr_hit[245]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_41_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_40_qs;
end
addr_hit[246]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_42_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_41_qs;
end
addr_hit[247]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_43_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_42_qs;
end
addr_hit[248]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_44_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_43_qs;
end
addr_hit[249]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_45_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_44_qs;
end
addr_hit[250]: begin
- reg_rdata_next[0] = mio_pad_attr_regwen_46_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_45_qs;
end
addr_hit[251]: begin
- reg_rdata_next[12:0] = mio_pad_attr_0_qs;
+ reg_rdata_next[0] = mio_pad_attr_regwen_46_qs;
end
addr_hit[252]: begin
- reg_rdata_next[12:0] = mio_pad_attr_1_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_0_qs;
end
addr_hit[253]: begin
- reg_rdata_next[12:0] = mio_pad_attr_2_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_1_qs;
end
addr_hit[254]: begin
- reg_rdata_next[12:0] = mio_pad_attr_3_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_2_qs;
end
addr_hit[255]: begin
- reg_rdata_next[12:0] = mio_pad_attr_4_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_3_qs;
end
addr_hit[256]: begin
- reg_rdata_next[12:0] = mio_pad_attr_5_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_4_qs;
end
addr_hit[257]: begin
- reg_rdata_next[12:0] = mio_pad_attr_6_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_5_qs;
end
addr_hit[258]: begin
- reg_rdata_next[12:0] = mio_pad_attr_7_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_6_qs;
end
addr_hit[259]: begin
- reg_rdata_next[12:0] = mio_pad_attr_8_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_7_qs;
end
addr_hit[260]: begin
- reg_rdata_next[12:0] = mio_pad_attr_9_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_8_qs;
end
addr_hit[261]: begin
- reg_rdata_next[12:0] = mio_pad_attr_10_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_9_qs;
end
addr_hit[262]: begin
- reg_rdata_next[12:0] = mio_pad_attr_11_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_10_qs;
end
addr_hit[263]: begin
- reg_rdata_next[12:0] = mio_pad_attr_12_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_11_qs;
end
addr_hit[264]: begin
- reg_rdata_next[12:0] = mio_pad_attr_13_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_12_qs;
end
addr_hit[265]: begin
- reg_rdata_next[12:0] = mio_pad_attr_14_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_13_qs;
end
addr_hit[266]: begin
- reg_rdata_next[12:0] = mio_pad_attr_15_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_14_qs;
end
addr_hit[267]: begin
- reg_rdata_next[12:0] = mio_pad_attr_16_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_15_qs;
end
addr_hit[268]: begin
- reg_rdata_next[12:0] = mio_pad_attr_17_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_16_qs;
end
addr_hit[269]: begin
- reg_rdata_next[12:0] = mio_pad_attr_18_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_17_qs;
end
addr_hit[270]: begin
- reg_rdata_next[12:0] = mio_pad_attr_19_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_18_qs;
end
addr_hit[271]: begin
- reg_rdata_next[12:0] = mio_pad_attr_20_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_19_qs;
end
addr_hit[272]: begin
- reg_rdata_next[12:0] = mio_pad_attr_21_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_20_qs;
end
addr_hit[273]: begin
- reg_rdata_next[12:0] = mio_pad_attr_22_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_21_qs;
end
addr_hit[274]: begin
- reg_rdata_next[12:0] = mio_pad_attr_23_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_22_qs;
end
addr_hit[275]: begin
- reg_rdata_next[12:0] = mio_pad_attr_24_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_23_qs;
end
addr_hit[276]: begin
- reg_rdata_next[12:0] = mio_pad_attr_25_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_24_qs;
end
addr_hit[277]: begin
- reg_rdata_next[12:0] = mio_pad_attr_26_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_25_qs;
end
addr_hit[278]: begin
- reg_rdata_next[12:0] = mio_pad_attr_27_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_26_qs;
end
addr_hit[279]: begin
- reg_rdata_next[12:0] = mio_pad_attr_28_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_27_qs;
end
addr_hit[280]: begin
- reg_rdata_next[12:0] = mio_pad_attr_29_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_28_qs;
end
addr_hit[281]: begin
- reg_rdata_next[12:0] = mio_pad_attr_30_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_29_qs;
end
addr_hit[282]: begin
- reg_rdata_next[12:0] = mio_pad_attr_31_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_30_qs;
end
addr_hit[283]: begin
- reg_rdata_next[12:0] = mio_pad_attr_32_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_31_qs;
end
addr_hit[284]: begin
- reg_rdata_next[12:0] = mio_pad_attr_33_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_32_qs;
end
addr_hit[285]: begin
- reg_rdata_next[12:0] = mio_pad_attr_34_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_33_qs;
end
addr_hit[286]: begin
- reg_rdata_next[12:0] = mio_pad_attr_35_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_34_qs;
end
addr_hit[287]: begin
- reg_rdata_next[12:0] = mio_pad_attr_36_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_35_qs;
end
addr_hit[288]: begin
- reg_rdata_next[12:0] = mio_pad_attr_37_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_36_qs;
end
addr_hit[289]: begin
- reg_rdata_next[12:0] = mio_pad_attr_38_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_37_qs;
end
addr_hit[290]: begin
- reg_rdata_next[12:0] = mio_pad_attr_39_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_38_qs;
end
addr_hit[291]: begin
- reg_rdata_next[12:0] = mio_pad_attr_40_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_39_qs;
end
addr_hit[292]: begin
- reg_rdata_next[12:0] = mio_pad_attr_41_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_40_qs;
end
addr_hit[293]: begin
- reg_rdata_next[12:0] = mio_pad_attr_42_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_41_qs;
end
addr_hit[294]: begin
- reg_rdata_next[12:0] = mio_pad_attr_43_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_42_qs;
end
addr_hit[295]: begin
- reg_rdata_next[12:0] = mio_pad_attr_44_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_43_qs;
end
addr_hit[296]: begin
- reg_rdata_next[12:0] = mio_pad_attr_45_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_44_qs;
end
addr_hit[297]: begin
- reg_rdata_next[12:0] = mio_pad_attr_46_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_45_qs;
end
addr_hit[298]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
+ reg_rdata_next[12:0] = mio_pad_attr_46_qs;
end
addr_hit[299]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
end
addr_hit[300]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
end
addr_hit[301]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
end
addr_hit[302]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
end
addr_hit[303]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
end
addr_hit[304]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
end
addr_hit[305]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
end
addr_hit[306]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
end
addr_hit[307]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
end
addr_hit[308]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
end
addr_hit[309]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
end
addr_hit[310]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
end
addr_hit[311]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
end
addr_hit[312]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
end
addr_hit[313]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_15_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
end
addr_hit[314]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_16_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_15_qs;
end
addr_hit[315]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_17_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_16_qs;
end
addr_hit[316]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_18_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_17_qs;
end
addr_hit[317]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_19_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_18_qs;
end
addr_hit[318]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_20_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_19_qs;
end
addr_hit[319]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_21_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_20_qs;
end
addr_hit[320]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_22_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_21_qs;
end
addr_hit[321]: begin
- reg_rdata_next[0] = dio_pad_attr_regwen_23_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_22_qs;
end
addr_hit[322]: begin
- reg_rdata_next[12:0] = dio_pad_attr_0_qs;
+ reg_rdata_next[0] = dio_pad_attr_regwen_23_qs;
end
addr_hit[323]: begin
- reg_rdata_next[12:0] = dio_pad_attr_1_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_0_qs;
end
addr_hit[324]: begin
- reg_rdata_next[12:0] = dio_pad_attr_2_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_1_qs;
end
addr_hit[325]: begin
- reg_rdata_next[12:0] = dio_pad_attr_3_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_2_qs;
end
addr_hit[326]: begin
- reg_rdata_next[12:0] = dio_pad_attr_4_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_3_qs;
end
addr_hit[327]: begin
- reg_rdata_next[12:0] = dio_pad_attr_5_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_4_qs;
end
addr_hit[328]: begin
- reg_rdata_next[12:0] = dio_pad_attr_6_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_5_qs;
end
addr_hit[329]: begin
- reg_rdata_next[12:0] = dio_pad_attr_7_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_6_qs;
end
addr_hit[330]: begin
- reg_rdata_next[12:0] = dio_pad_attr_8_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_7_qs;
end
addr_hit[331]: begin
- reg_rdata_next[12:0] = dio_pad_attr_9_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_8_qs;
end
addr_hit[332]: begin
- reg_rdata_next[12:0] = dio_pad_attr_10_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_9_qs;
end
addr_hit[333]: begin
- reg_rdata_next[12:0] = dio_pad_attr_11_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_10_qs;
end
addr_hit[334]: begin
- reg_rdata_next[12:0] = dio_pad_attr_12_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_11_qs;
end
addr_hit[335]: begin
- reg_rdata_next[12:0] = dio_pad_attr_13_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_12_qs;
end
addr_hit[336]: begin
- reg_rdata_next[12:0] = dio_pad_attr_14_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_13_qs;
end
addr_hit[337]: begin
- reg_rdata_next[12:0] = dio_pad_attr_15_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_14_qs;
end
addr_hit[338]: begin
- reg_rdata_next[12:0] = dio_pad_attr_16_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_15_qs;
end
addr_hit[339]: begin
- reg_rdata_next[12:0] = dio_pad_attr_17_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_16_qs;
end
addr_hit[340]: begin
- reg_rdata_next[12:0] = dio_pad_attr_18_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_17_qs;
end
addr_hit[341]: begin
- reg_rdata_next[12:0] = dio_pad_attr_19_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_18_qs;
end
addr_hit[342]: begin
- reg_rdata_next[12:0] = dio_pad_attr_20_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_19_qs;
end
addr_hit[343]: begin
- reg_rdata_next[12:0] = dio_pad_attr_21_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_20_qs;
end
addr_hit[344]: begin
- reg_rdata_next[12:0] = dio_pad_attr_22_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_21_qs;
end
addr_hit[345]: begin
- reg_rdata_next[12:0] = dio_pad_attr_23_qs;
+ reg_rdata_next[12:0] = dio_pad_attr_22_qs;
end
addr_hit[346]: begin
+ reg_rdata_next[12:0] = dio_pad_attr_23_qs;
+ end
+
+ addr_hit[347]: begin
reg_rdata_next[0] = mio_pad_sleep_status_0_en_0_qs;
reg_rdata_next[1] = mio_pad_sleep_status_0_en_1_qs;
reg_rdata_next[2] = mio_pad_sleep_status_0_en_2_qs;
@@ -24917,7 +24944,7 @@
reg_rdata_next[31] = mio_pad_sleep_status_0_en_31_qs;
end
- addr_hit[347]: begin
+ addr_hit[348]: begin
reg_rdata_next[0] = mio_pad_sleep_status_1_en_32_qs;
reg_rdata_next[1] = mio_pad_sleep_status_1_en_33_qs;
reg_rdata_next[2] = mio_pad_sleep_status_1_en_34_qs;
@@ -24935,571 +24962,571 @@
reg_rdata_next[14] = mio_pad_sleep_status_1_en_46_qs;
end
- addr_hit[348]: begin
+ addr_hit[349]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs;
end
- addr_hit[349]: begin
+ addr_hit[350]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs;
end
- addr_hit[350]: begin
+ addr_hit[351]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs;
end
- addr_hit[351]: begin
+ addr_hit[352]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs;
end
- addr_hit[352]: begin
+ addr_hit[353]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs;
end
- addr_hit[353]: begin
+ addr_hit[354]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs;
end
- addr_hit[354]: begin
+ addr_hit[355]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs;
end
- addr_hit[355]: begin
+ addr_hit[356]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs;
end
- addr_hit[356]: begin
+ addr_hit[357]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs;
end
- addr_hit[357]: begin
+ addr_hit[358]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs;
end
- addr_hit[358]: begin
+ addr_hit[359]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs;
end
- addr_hit[359]: begin
+ addr_hit[360]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs;
end
- addr_hit[360]: begin
+ addr_hit[361]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs;
end
- addr_hit[361]: begin
+ addr_hit[362]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs;
end
- addr_hit[362]: begin
+ addr_hit[363]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs;
end
- addr_hit[363]: begin
+ addr_hit[364]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs;
end
- addr_hit[364]: begin
+ addr_hit[365]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs;
end
- addr_hit[365]: begin
+ addr_hit[366]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs;
end
- addr_hit[366]: begin
+ addr_hit[367]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs;
end
- addr_hit[367]: begin
+ addr_hit[368]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs;
end
- addr_hit[368]: begin
+ addr_hit[369]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs;
end
- addr_hit[369]: begin
+ addr_hit[370]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs;
end
- addr_hit[370]: begin
+ addr_hit[371]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs;
end
- addr_hit[371]: begin
+ addr_hit[372]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs;
end
- addr_hit[372]: begin
+ addr_hit[373]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs;
end
- addr_hit[373]: begin
+ addr_hit[374]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs;
end
- addr_hit[374]: begin
+ addr_hit[375]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs;
end
- addr_hit[375]: begin
+ addr_hit[376]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs;
end
- addr_hit[376]: begin
+ addr_hit[377]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs;
end
- addr_hit[377]: begin
+ addr_hit[378]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs;
end
- addr_hit[378]: begin
+ addr_hit[379]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs;
end
- addr_hit[379]: begin
+ addr_hit[380]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs;
end
- addr_hit[380]: begin
+ addr_hit[381]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs;
end
- addr_hit[381]: begin
+ addr_hit[382]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs;
end
- addr_hit[382]: begin
+ addr_hit[383]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs;
end
- addr_hit[383]: begin
+ addr_hit[384]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs;
end
- addr_hit[384]: begin
+ addr_hit[385]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs;
end
- addr_hit[385]: begin
+ addr_hit[386]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs;
end
- addr_hit[386]: begin
+ addr_hit[387]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs;
end
- addr_hit[387]: begin
+ addr_hit[388]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs;
end
- addr_hit[388]: begin
+ addr_hit[389]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs;
end
- addr_hit[389]: begin
+ addr_hit[390]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs;
end
- addr_hit[390]: begin
+ addr_hit[391]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs;
end
- addr_hit[391]: begin
+ addr_hit[392]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_43_qs;
end
- addr_hit[392]: begin
+ addr_hit[393]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_44_qs;
end
- addr_hit[393]: begin
+ addr_hit[394]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_45_qs;
end
- addr_hit[394]: begin
+ addr_hit[395]: begin
reg_rdata_next[0] = mio_pad_sleep_regwen_46_qs;
end
- addr_hit[395]: begin
+ addr_hit[396]: begin
reg_rdata_next[0] = mio_pad_sleep_en_0_qs;
end
- addr_hit[396]: begin
+ addr_hit[397]: begin
reg_rdata_next[0] = mio_pad_sleep_en_1_qs;
end
- addr_hit[397]: begin
+ addr_hit[398]: begin
reg_rdata_next[0] = mio_pad_sleep_en_2_qs;
end
- addr_hit[398]: begin
+ addr_hit[399]: begin
reg_rdata_next[0] = mio_pad_sleep_en_3_qs;
end
- addr_hit[399]: begin
+ addr_hit[400]: begin
reg_rdata_next[0] = mio_pad_sleep_en_4_qs;
end
- addr_hit[400]: begin
+ addr_hit[401]: begin
reg_rdata_next[0] = mio_pad_sleep_en_5_qs;
end
- addr_hit[401]: begin
+ addr_hit[402]: begin
reg_rdata_next[0] = mio_pad_sleep_en_6_qs;
end
- addr_hit[402]: begin
+ addr_hit[403]: begin
reg_rdata_next[0] = mio_pad_sleep_en_7_qs;
end
- addr_hit[403]: begin
+ addr_hit[404]: begin
reg_rdata_next[0] = mio_pad_sleep_en_8_qs;
end
- addr_hit[404]: begin
+ addr_hit[405]: begin
reg_rdata_next[0] = mio_pad_sleep_en_9_qs;
end
- addr_hit[405]: begin
+ addr_hit[406]: begin
reg_rdata_next[0] = mio_pad_sleep_en_10_qs;
end
- addr_hit[406]: begin
+ addr_hit[407]: begin
reg_rdata_next[0] = mio_pad_sleep_en_11_qs;
end
- addr_hit[407]: begin
+ addr_hit[408]: begin
reg_rdata_next[0] = mio_pad_sleep_en_12_qs;
end
- addr_hit[408]: begin
+ addr_hit[409]: begin
reg_rdata_next[0] = mio_pad_sleep_en_13_qs;
end
- addr_hit[409]: begin
+ addr_hit[410]: begin
reg_rdata_next[0] = mio_pad_sleep_en_14_qs;
end
- addr_hit[410]: begin
+ addr_hit[411]: begin
reg_rdata_next[0] = mio_pad_sleep_en_15_qs;
end
- addr_hit[411]: begin
+ addr_hit[412]: begin
reg_rdata_next[0] = mio_pad_sleep_en_16_qs;
end
- addr_hit[412]: begin
+ addr_hit[413]: begin
reg_rdata_next[0] = mio_pad_sleep_en_17_qs;
end
- addr_hit[413]: begin
+ addr_hit[414]: begin
reg_rdata_next[0] = mio_pad_sleep_en_18_qs;
end
- addr_hit[414]: begin
+ addr_hit[415]: begin
reg_rdata_next[0] = mio_pad_sleep_en_19_qs;
end
- addr_hit[415]: begin
+ addr_hit[416]: begin
reg_rdata_next[0] = mio_pad_sleep_en_20_qs;
end
- addr_hit[416]: begin
+ addr_hit[417]: begin
reg_rdata_next[0] = mio_pad_sleep_en_21_qs;
end
- addr_hit[417]: begin
+ addr_hit[418]: begin
reg_rdata_next[0] = mio_pad_sleep_en_22_qs;
end
- addr_hit[418]: begin
+ addr_hit[419]: begin
reg_rdata_next[0] = mio_pad_sleep_en_23_qs;
end
- addr_hit[419]: begin
+ addr_hit[420]: begin
reg_rdata_next[0] = mio_pad_sleep_en_24_qs;
end
- addr_hit[420]: begin
+ addr_hit[421]: begin
reg_rdata_next[0] = mio_pad_sleep_en_25_qs;
end
- addr_hit[421]: begin
+ addr_hit[422]: begin
reg_rdata_next[0] = mio_pad_sleep_en_26_qs;
end
- addr_hit[422]: begin
+ addr_hit[423]: begin
reg_rdata_next[0] = mio_pad_sleep_en_27_qs;
end
- addr_hit[423]: begin
+ addr_hit[424]: begin
reg_rdata_next[0] = mio_pad_sleep_en_28_qs;
end
- addr_hit[424]: begin
+ addr_hit[425]: begin
reg_rdata_next[0] = mio_pad_sleep_en_29_qs;
end
- addr_hit[425]: begin
+ addr_hit[426]: begin
reg_rdata_next[0] = mio_pad_sleep_en_30_qs;
end
- addr_hit[426]: begin
+ addr_hit[427]: begin
reg_rdata_next[0] = mio_pad_sleep_en_31_qs;
end
- addr_hit[427]: begin
+ addr_hit[428]: begin
reg_rdata_next[0] = mio_pad_sleep_en_32_qs;
end
- addr_hit[428]: begin
+ addr_hit[429]: begin
reg_rdata_next[0] = mio_pad_sleep_en_33_qs;
end
- addr_hit[429]: begin
+ addr_hit[430]: begin
reg_rdata_next[0] = mio_pad_sleep_en_34_qs;
end
- addr_hit[430]: begin
+ addr_hit[431]: begin
reg_rdata_next[0] = mio_pad_sleep_en_35_qs;
end
- addr_hit[431]: begin
+ addr_hit[432]: begin
reg_rdata_next[0] = mio_pad_sleep_en_36_qs;
end
- addr_hit[432]: begin
+ addr_hit[433]: begin
reg_rdata_next[0] = mio_pad_sleep_en_37_qs;
end
- addr_hit[433]: begin
+ addr_hit[434]: begin
reg_rdata_next[0] = mio_pad_sleep_en_38_qs;
end
- addr_hit[434]: begin
+ addr_hit[435]: begin
reg_rdata_next[0] = mio_pad_sleep_en_39_qs;
end
- addr_hit[435]: begin
+ addr_hit[436]: begin
reg_rdata_next[0] = mio_pad_sleep_en_40_qs;
end
- addr_hit[436]: begin
+ addr_hit[437]: begin
reg_rdata_next[0] = mio_pad_sleep_en_41_qs;
end
- addr_hit[437]: begin
+ addr_hit[438]: begin
reg_rdata_next[0] = mio_pad_sleep_en_42_qs;
end
- addr_hit[438]: begin
+ addr_hit[439]: begin
reg_rdata_next[0] = mio_pad_sleep_en_43_qs;
end
- addr_hit[439]: begin
+ addr_hit[440]: begin
reg_rdata_next[0] = mio_pad_sleep_en_44_qs;
end
- addr_hit[440]: begin
+ addr_hit[441]: begin
reg_rdata_next[0] = mio_pad_sleep_en_45_qs;
end
- addr_hit[441]: begin
+ addr_hit[442]: begin
reg_rdata_next[0] = mio_pad_sleep_en_46_qs;
end
- addr_hit[442]: begin
+ addr_hit[443]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs;
end
- addr_hit[443]: begin
+ addr_hit[444]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs;
end
- addr_hit[444]: begin
+ addr_hit[445]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs;
end
- addr_hit[445]: begin
+ addr_hit[446]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs;
end
- addr_hit[446]: begin
+ addr_hit[447]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs;
end
- addr_hit[447]: begin
+ addr_hit[448]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs;
end
- addr_hit[448]: begin
+ addr_hit[449]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs;
end
- addr_hit[449]: begin
+ addr_hit[450]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs;
end
- addr_hit[450]: begin
+ addr_hit[451]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs;
end
- addr_hit[451]: begin
+ addr_hit[452]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs;
end
- addr_hit[452]: begin
+ addr_hit[453]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs;
end
- addr_hit[453]: begin
+ addr_hit[454]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs;
end
- addr_hit[454]: begin
+ addr_hit[455]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs;
end
- addr_hit[455]: begin
+ addr_hit[456]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs;
end
- addr_hit[456]: begin
+ addr_hit[457]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs;
end
- addr_hit[457]: begin
+ addr_hit[458]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs;
end
- addr_hit[458]: begin
+ addr_hit[459]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs;
end
- addr_hit[459]: begin
+ addr_hit[460]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs;
end
- addr_hit[460]: begin
+ addr_hit[461]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs;
end
- addr_hit[461]: begin
+ addr_hit[462]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs;
end
- addr_hit[462]: begin
+ addr_hit[463]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs;
end
- addr_hit[463]: begin
+ addr_hit[464]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs;
end
- addr_hit[464]: begin
+ addr_hit[465]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs;
end
- addr_hit[465]: begin
+ addr_hit[466]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs;
end
- addr_hit[466]: begin
+ addr_hit[467]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs;
end
- addr_hit[467]: begin
+ addr_hit[468]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs;
end
- addr_hit[468]: begin
+ addr_hit[469]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs;
end
- addr_hit[469]: begin
+ addr_hit[470]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs;
end
- addr_hit[470]: begin
+ addr_hit[471]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs;
end
- addr_hit[471]: begin
+ addr_hit[472]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs;
end
- addr_hit[472]: begin
+ addr_hit[473]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs;
end
- addr_hit[473]: begin
+ addr_hit[474]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs;
end
- addr_hit[474]: begin
+ addr_hit[475]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs;
end
- addr_hit[475]: begin
+ addr_hit[476]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs;
end
- addr_hit[476]: begin
+ addr_hit[477]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs;
end
- addr_hit[477]: begin
+ addr_hit[478]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs;
end
- addr_hit[478]: begin
+ addr_hit[479]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs;
end
- addr_hit[479]: begin
+ addr_hit[480]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs;
end
- addr_hit[480]: begin
+ addr_hit[481]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs;
end
- addr_hit[481]: begin
+ addr_hit[482]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs;
end
- addr_hit[482]: begin
+ addr_hit[483]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs;
end
- addr_hit[483]: begin
+ addr_hit[484]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs;
end
- addr_hit[484]: begin
+ addr_hit[485]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs;
end
- addr_hit[485]: begin
+ addr_hit[486]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_43_qs;
end
- addr_hit[486]: begin
+ addr_hit[487]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_44_qs;
end
- addr_hit[487]: begin
+ addr_hit[488]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_45_qs;
end
- addr_hit[488]: begin
+ addr_hit[489]: begin
reg_rdata_next[1:0] = mio_pad_sleep_mode_46_qs;
end
- addr_hit[489]: begin
+ addr_hit[490]: begin
reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs;
reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs;
reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs;
@@ -25526,471 +25553,471 @@
reg_rdata_next[23] = dio_pad_sleep_status_en_23_qs;
end
- addr_hit[490]: begin
+ addr_hit[491]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs;
end
- addr_hit[491]: begin
+ addr_hit[492]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs;
end
- addr_hit[492]: begin
+ addr_hit[493]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs;
end
- addr_hit[493]: begin
+ addr_hit[494]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs;
end
- addr_hit[494]: begin
+ addr_hit[495]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs;
end
- addr_hit[495]: begin
+ addr_hit[496]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs;
end
- addr_hit[496]: begin
+ addr_hit[497]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs;
end
- addr_hit[497]: begin
+ addr_hit[498]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs;
end
- addr_hit[498]: begin
+ addr_hit[499]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs;
end
- addr_hit[499]: begin
+ addr_hit[500]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs;
end
- addr_hit[500]: begin
+ addr_hit[501]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs;
end
- addr_hit[501]: begin
+ addr_hit[502]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs;
end
- addr_hit[502]: begin
+ addr_hit[503]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs;
end
- addr_hit[503]: begin
+ addr_hit[504]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs;
end
- addr_hit[504]: begin
+ addr_hit[505]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs;
end
- addr_hit[505]: begin
+ addr_hit[506]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs;
end
- addr_hit[506]: begin
+ addr_hit[507]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_16_qs;
end
- addr_hit[507]: begin
+ addr_hit[508]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_17_qs;
end
- addr_hit[508]: begin
+ addr_hit[509]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_18_qs;
end
- addr_hit[509]: begin
+ addr_hit[510]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_19_qs;
end
- addr_hit[510]: begin
+ addr_hit[511]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_20_qs;
end
- addr_hit[511]: begin
+ addr_hit[512]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_21_qs;
end
- addr_hit[512]: begin
+ addr_hit[513]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_22_qs;
end
- addr_hit[513]: begin
+ addr_hit[514]: begin
reg_rdata_next[0] = dio_pad_sleep_regwen_23_qs;
end
- addr_hit[514]: begin
+ addr_hit[515]: begin
reg_rdata_next[0] = dio_pad_sleep_en_0_qs;
end
- addr_hit[515]: begin
+ addr_hit[516]: begin
reg_rdata_next[0] = dio_pad_sleep_en_1_qs;
end
- addr_hit[516]: begin
+ addr_hit[517]: begin
reg_rdata_next[0] = dio_pad_sleep_en_2_qs;
end
- addr_hit[517]: begin
+ addr_hit[518]: begin
reg_rdata_next[0] = dio_pad_sleep_en_3_qs;
end
- addr_hit[518]: begin
+ addr_hit[519]: begin
reg_rdata_next[0] = dio_pad_sleep_en_4_qs;
end
- addr_hit[519]: begin
+ addr_hit[520]: begin
reg_rdata_next[0] = dio_pad_sleep_en_5_qs;
end
- addr_hit[520]: begin
+ addr_hit[521]: begin
reg_rdata_next[0] = dio_pad_sleep_en_6_qs;
end
- addr_hit[521]: begin
+ addr_hit[522]: begin
reg_rdata_next[0] = dio_pad_sleep_en_7_qs;
end
- addr_hit[522]: begin
+ addr_hit[523]: begin
reg_rdata_next[0] = dio_pad_sleep_en_8_qs;
end
- addr_hit[523]: begin
+ addr_hit[524]: begin
reg_rdata_next[0] = dio_pad_sleep_en_9_qs;
end
- addr_hit[524]: begin
+ addr_hit[525]: begin
reg_rdata_next[0] = dio_pad_sleep_en_10_qs;
end
- addr_hit[525]: begin
+ addr_hit[526]: begin
reg_rdata_next[0] = dio_pad_sleep_en_11_qs;
end
- addr_hit[526]: begin
+ addr_hit[527]: begin
reg_rdata_next[0] = dio_pad_sleep_en_12_qs;
end
- addr_hit[527]: begin
+ addr_hit[528]: begin
reg_rdata_next[0] = dio_pad_sleep_en_13_qs;
end
- addr_hit[528]: begin
+ addr_hit[529]: begin
reg_rdata_next[0] = dio_pad_sleep_en_14_qs;
end
- addr_hit[529]: begin
+ addr_hit[530]: begin
reg_rdata_next[0] = dio_pad_sleep_en_15_qs;
end
- addr_hit[530]: begin
+ addr_hit[531]: begin
reg_rdata_next[0] = dio_pad_sleep_en_16_qs;
end
- addr_hit[531]: begin
+ addr_hit[532]: begin
reg_rdata_next[0] = dio_pad_sleep_en_17_qs;
end
- addr_hit[532]: begin
+ addr_hit[533]: begin
reg_rdata_next[0] = dio_pad_sleep_en_18_qs;
end
- addr_hit[533]: begin
+ addr_hit[534]: begin
reg_rdata_next[0] = dio_pad_sleep_en_19_qs;
end
- addr_hit[534]: begin
+ addr_hit[535]: begin
reg_rdata_next[0] = dio_pad_sleep_en_20_qs;
end
- addr_hit[535]: begin
+ addr_hit[536]: begin
reg_rdata_next[0] = dio_pad_sleep_en_21_qs;
end
- addr_hit[536]: begin
+ addr_hit[537]: begin
reg_rdata_next[0] = dio_pad_sleep_en_22_qs;
end
- addr_hit[537]: begin
+ addr_hit[538]: begin
reg_rdata_next[0] = dio_pad_sleep_en_23_qs;
end
- addr_hit[538]: begin
+ addr_hit[539]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs;
end
- addr_hit[539]: begin
+ addr_hit[540]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs;
end
- addr_hit[540]: begin
+ addr_hit[541]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs;
end
- addr_hit[541]: begin
+ addr_hit[542]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs;
end
- addr_hit[542]: begin
+ addr_hit[543]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs;
end
- addr_hit[543]: begin
+ addr_hit[544]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs;
end
- addr_hit[544]: begin
+ addr_hit[545]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs;
end
- addr_hit[545]: begin
+ addr_hit[546]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs;
end
- addr_hit[546]: begin
+ addr_hit[547]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs;
end
- addr_hit[547]: begin
+ addr_hit[548]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs;
end
- addr_hit[548]: begin
+ addr_hit[549]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs;
end
- addr_hit[549]: begin
+ addr_hit[550]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs;
end
- addr_hit[550]: begin
+ addr_hit[551]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs;
end
- addr_hit[551]: begin
+ addr_hit[552]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs;
end
- addr_hit[552]: begin
+ addr_hit[553]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs;
end
- addr_hit[553]: begin
+ addr_hit[554]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs;
end
- addr_hit[554]: begin
+ addr_hit[555]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_16_qs;
end
- addr_hit[555]: begin
+ addr_hit[556]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_17_qs;
end
- addr_hit[556]: begin
+ addr_hit[557]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_18_qs;
end
- addr_hit[557]: begin
+ addr_hit[558]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_19_qs;
end
- addr_hit[558]: begin
+ addr_hit[559]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_20_qs;
end
- addr_hit[559]: begin
+ addr_hit[560]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_21_qs;
end
- addr_hit[560]: begin
+ addr_hit[561]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_22_qs;
end
- addr_hit[561]: begin
+ addr_hit[562]: begin
reg_rdata_next[1:0] = dio_pad_sleep_mode_23_qs;
end
- addr_hit[562]: begin
+ addr_hit[563]: begin
reg_rdata_next[0] = wkup_detector_regwen_0_qs;
end
- addr_hit[563]: begin
+ addr_hit[564]: begin
reg_rdata_next[0] = wkup_detector_regwen_1_qs;
end
- addr_hit[564]: begin
+ addr_hit[565]: begin
reg_rdata_next[0] = wkup_detector_regwen_2_qs;
end
- addr_hit[565]: begin
+ addr_hit[566]: begin
reg_rdata_next[0] = wkup_detector_regwen_3_qs;
end
- addr_hit[566]: begin
+ addr_hit[567]: begin
reg_rdata_next[0] = wkup_detector_regwen_4_qs;
end
- addr_hit[567]: begin
+ addr_hit[568]: begin
reg_rdata_next[0] = wkup_detector_regwen_5_qs;
end
- addr_hit[568]: begin
+ addr_hit[569]: begin
reg_rdata_next[0] = wkup_detector_regwen_6_qs;
end
- addr_hit[569]: begin
+ addr_hit[570]: begin
reg_rdata_next[0] = wkup_detector_regwen_7_qs;
end
- addr_hit[570]: begin
+ addr_hit[571]: begin
reg_rdata_next[0] = wkup_detector_en_0_qs;
end
- addr_hit[571]: begin
+ addr_hit[572]: begin
reg_rdata_next[0] = wkup_detector_en_1_qs;
end
- addr_hit[572]: begin
+ addr_hit[573]: begin
reg_rdata_next[0] = wkup_detector_en_2_qs;
end
- addr_hit[573]: begin
+ addr_hit[574]: begin
reg_rdata_next[0] = wkup_detector_en_3_qs;
end
- addr_hit[574]: begin
+ addr_hit[575]: begin
reg_rdata_next[0] = wkup_detector_en_4_qs;
end
- addr_hit[575]: begin
+ addr_hit[576]: begin
reg_rdata_next[0] = wkup_detector_en_5_qs;
end
- addr_hit[576]: begin
+ addr_hit[577]: begin
reg_rdata_next[0] = wkup_detector_en_6_qs;
end
- addr_hit[577]: begin
+ addr_hit[578]: begin
reg_rdata_next[0] = wkup_detector_en_7_qs;
end
- addr_hit[578]: begin
+ addr_hit[579]: begin
reg_rdata_next[2:0] = wkup_detector_0_mode_0_qs;
reg_rdata_next[3] = wkup_detector_0_filter_0_qs;
reg_rdata_next[4] = wkup_detector_0_miodio_0_qs;
end
- addr_hit[579]: begin
+ addr_hit[580]: begin
reg_rdata_next[2:0] = wkup_detector_1_mode_1_qs;
reg_rdata_next[3] = wkup_detector_1_filter_1_qs;
reg_rdata_next[4] = wkup_detector_1_miodio_1_qs;
end
- addr_hit[580]: begin
+ addr_hit[581]: begin
reg_rdata_next[2:0] = wkup_detector_2_mode_2_qs;
reg_rdata_next[3] = wkup_detector_2_filter_2_qs;
reg_rdata_next[4] = wkup_detector_2_miodio_2_qs;
end
- addr_hit[581]: begin
+ addr_hit[582]: begin
reg_rdata_next[2:0] = wkup_detector_3_mode_3_qs;
reg_rdata_next[3] = wkup_detector_3_filter_3_qs;
reg_rdata_next[4] = wkup_detector_3_miodio_3_qs;
end
- addr_hit[582]: begin
+ addr_hit[583]: begin
reg_rdata_next[2:0] = wkup_detector_4_mode_4_qs;
reg_rdata_next[3] = wkup_detector_4_filter_4_qs;
reg_rdata_next[4] = wkup_detector_4_miodio_4_qs;
end
- addr_hit[583]: begin
+ addr_hit[584]: begin
reg_rdata_next[2:0] = wkup_detector_5_mode_5_qs;
reg_rdata_next[3] = wkup_detector_5_filter_5_qs;
reg_rdata_next[4] = wkup_detector_5_miodio_5_qs;
end
- addr_hit[584]: begin
+ addr_hit[585]: begin
reg_rdata_next[2:0] = wkup_detector_6_mode_6_qs;
reg_rdata_next[3] = wkup_detector_6_filter_6_qs;
reg_rdata_next[4] = wkup_detector_6_miodio_6_qs;
end
- addr_hit[585]: begin
+ addr_hit[586]: begin
reg_rdata_next[2:0] = wkup_detector_7_mode_7_qs;
reg_rdata_next[3] = wkup_detector_7_filter_7_qs;
reg_rdata_next[4] = wkup_detector_7_miodio_7_qs;
end
- addr_hit[586]: begin
+ addr_hit[587]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_0_qs;
end
- addr_hit[587]: begin
+ addr_hit[588]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_1_qs;
end
- addr_hit[588]: begin
+ addr_hit[589]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_2_qs;
end
- addr_hit[589]: begin
+ addr_hit[590]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_3_qs;
end
- addr_hit[590]: begin
+ addr_hit[591]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_4_qs;
end
- addr_hit[591]: begin
+ addr_hit[592]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_5_qs;
end
- addr_hit[592]: begin
+ addr_hit[593]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_6_qs;
end
- addr_hit[593]: begin
+ addr_hit[594]: begin
reg_rdata_next[7:0] = wkup_detector_cnt_th_7_qs;
end
- addr_hit[594]: begin
+ addr_hit[595]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_0_qs;
end
- addr_hit[595]: begin
+ addr_hit[596]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_1_qs;
end
- addr_hit[596]: begin
+ addr_hit[597]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_2_qs;
end
- addr_hit[597]: begin
+ addr_hit[598]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_3_qs;
end
- addr_hit[598]: begin
+ addr_hit[599]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_4_qs;
end
- addr_hit[599]: begin
+ addr_hit[600]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_5_qs;
end
- addr_hit[600]: begin
+ addr_hit[601]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_6_qs;
end
- addr_hit[601]: begin
+ addr_hit[602]: begin
reg_rdata_next[5:0] = wkup_detector_padsel_7_qs;
end
- addr_hit[602]: begin
+ addr_hit[603]: begin
reg_rdata_next[0] = wkup_cause_cause_0_qs;
reg_rdata_next[1] = wkup_cause_cause_1_qs;
reg_rdata_next[2] = wkup_cause_cause_2_qs;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 3ed55a9..5a5558f 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -1851,8 +1851,12 @@
);
pinmux #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10]),
.TargetCfg(PinmuxAonTargetCfg)
) u_pinmux_aon (
+ // [10]: fatal_fault
+ .alert_tx_o ( alert_tx[10:10] ),
+ .alert_rx_i ( alert_rx[10:10] ),
// Inter-module signals
.lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
@@ -1926,25 +1930,25 @@
);
sensor_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:10])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:11])
) u_sensor_ctrl_aon (
// Output
.cio_ast_debug_out_o (cio_sensor_ctrl_aon_ast_debug_out_d2p),
.cio_ast_debug_out_en_o (cio_sensor_ctrl_aon_ast_debug_out_en_d2p),
- // [10]: recov_as
- // [11]: recov_cg
- // [12]: recov_gd
- // [13]: recov_ts_hi
- // [14]: recov_ts_lo
- // [15]: recov_fla
- // [16]: recov_otp
- // [17]: recov_ot0
- // [18]: recov_ot1
- // [19]: recov_ot2
- // [20]: recov_ot3
- .alert_tx_o ( alert_tx[20:10] ),
- .alert_rx_i ( alert_rx[20:10] ),
+ // [11]: recov_as
+ // [12]: recov_cg
+ // [13]: recov_gd
+ // [14]: recov_ts_hi
+ // [15]: recov_ts_lo
+ // [16]: recov_fla
+ // [17]: recov_otp
+ // [18]: recov_ot0
+ // [19]: recov_ot1
+ // [20]: recov_ot2
+ // [21]: recov_ot3
+ .alert_tx_o ( alert_tx[21:11] ),
+ .alert_rx_i ( alert_rx[21:11] ),
// Inter-module signals
.ast_alert_i(sensor_ctrl_ast_alert_req_i),
@@ -1961,16 +1965,16 @@
);
sram_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:21]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:22]),
.RndCnstSramKey(RndCnstSramCtrlRetAonSramKey),
.RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce),
.RndCnstSramLfsrPerm(RndCnstSramCtrlRetAonSramLfsrPerm),
.InstrExec(SramCtrlRetAonInstrExec)
) u_sram_ctrl_ret_aon (
- // [21]: fatal_intg_error
- // [22]: fatal_parity_error
- .alert_tx_o ( alert_tx[22:21] ),
- .alert_rx_i ( alert_rx[22:21] ),
+ // [22]: fatal_intg_error
+ // [23]: fatal_parity_error
+ .alert_tx_o ( alert_tx[23:22] ),
+ .alert_rx_i ( alert_rx[23:22] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]),
@@ -1995,7 +1999,7 @@
);
flash_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:23]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:24]),
.RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
.RndCnstDataKey(RndCnstFlashCtrlDataKey),
.RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
@@ -2018,12 +2022,12 @@
.intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
.intr_op_done_o (intr_flash_ctrl_op_done),
.intr_err_o (intr_flash_ctrl_err),
- // [23]: recov_err
- // [24]: recov_mp_err
- // [25]: recov_ecc_err
- // [26]: fatal_intg_err
- .alert_tx_o ( alert_tx[26:23] ),
- .alert_rx_i ( alert_rx[26:23] ),
+ // [24]: recov_err
+ // [25]: recov_mp_err
+ // [26]: recov_ecc_err
+ // [27]: fatal_intg_err
+ .alert_tx_o ( alert_tx[27:24] ),
+ .alert_rx_i ( alert_rx[27:24] ),
// Inter-module signals
.flash_o(flash_ctrl_flash_req),
@@ -2069,7 +2073,7 @@
);
aes #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:27]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:28]),
.AES192Enable(1'b1),
.Masking(AesMasking),
.SBoxImpl(AesSBoxImpl),
@@ -2082,10 +2086,10 @@
.RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
.RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm)
) u_aes (
- // [27]: recov_ctrl_update_err
- // [28]: fatal_fault
- .alert_tx_o ( alert_tx[28:27] ),
- .alert_rx_i ( alert_rx[28:27] ),
+ // [28]: recov_ctrl_update_err
+ // [29]: fatal_fault
+ .alert_tx_o ( alert_tx[29:28] ),
+ .alert_rx_i ( alert_rx[29:28] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[0]),
@@ -2103,16 +2107,16 @@
);
hmac #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30])
) u_hmac (
// Interrupt
.intr_hmac_done_o (intr_hmac_hmac_done),
.intr_fifo_empty_o (intr_hmac_fifo_empty),
.intr_hmac_err_o (intr_hmac_hmac_err),
- // [29]: fatal_fault
- .alert_tx_o ( alert_tx[29:29] ),
- .alert_rx_i ( alert_rx[29:29] ),
+ // [30]: fatal_fault
+ .alert_tx_o ( alert_tx[30:30] ),
+ .alert_rx_i ( alert_rx[30:30] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[1]),
@@ -2125,7 +2129,7 @@
);
kmac #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31]),
.EnMasking(KmacEnMasking),
.ReuseShare(KmacReuseShare)
) u_kmac (
@@ -2134,9 +2138,9 @@
.intr_kmac_done_o (intr_kmac_kmac_done),
.intr_fifo_empty_o (intr_kmac_fifo_empty),
.intr_kmac_err_o (intr_kmac_kmac_err),
- // [30]: fatal_fault
- .alert_tx_o ( alert_tx[30:30] ),
- .alert_rx_i ( alert_rx[30:30] ),
+ // [31]: fatal_fault
+ .alert_tx_o ( alert_tx[31:31] ),
+ .alert_rx_i ( alert_rx[31:31] ),
// Inter-module signals
.keymgr_key_i(keymgr_kmac_key),
@@ -2156,7 +2160,7 @@
);
keymgr #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[32:31]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]),
.RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
.RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
.RndCnstRandPerm(RndCnstKeymgrRandPerm),
@@ -2174,10 +2178,10 @@
// Interrupt
.intr_op_done_o (intr_keymgr_op_done),
- // [31]: fatal_fault_err
- // [32]: recov_operation_err
- .alert_tx_o ( alert_tx[32:31] ),
- .alert_rx_i ( alert_rx[32:31] ),
+ // [32]: fatal_fault_err
+ // [33]: recov_operation_err
+ .alert_tx_o ( alert_tx[33:32] ),
+ .alert_rx_i ( alert_rx[33:32] ),
// Inter-module signals
.edn_o(edn0_edn_req[0]),
@@ -2204,7 +2208,7 @@
);
csrng #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:33]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34]),
.SBoxImpl(CsrngSBoxImpl)
) u_csrng (
@@ -2213,9 +2217,9 @@
.intr_cs_entropy_req_o (intr_csrng_cs_entropy_req),
.intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc),
.intr_cs_fatal_err_o (intr_csrng_cs_fatal_err),
- // [33]: fatal_alert
- .alert_tx_o ( alert_tx[33:33] ),
- .alert_rx_i ( alert_rx[33:33] ),
+ // [34]: fatal_alert
+ .alert_tx_o ( alert_tx[34:34] ),
+ .alert_rx_i ( alert_rx[34:34] ),
// Inter-module signals
.csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2235,7 +2239,7 @@
);
entropy_src #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:34]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[36:35]),
.Stub(EntropySrcStub)
) u_entropy_src (
@@ -2244,10 +2248,10 @@
.intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
.intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
.intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
- // [34]: recov_alert
- // [35]: fatal_alert
- .alert_tx_o ( alert_tx[35:34] ),
- .alert_rx_i ( alert_rx[35:34] ),
+ // [35]: recov_alert
+ // [36]: fatal_alert
+ .alert_tx_o ( alert_tx[36:35] ),
+ .alert_rx_i ( alert_rx[36:35] ),
// Inter-module signals
.entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2270,15 +2274,15 @@
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[36:36])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:37])
) u_edn0 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn0_edn_fatal_err),
- // [36]: fatal_alert
- .alert_tx_o ( alert_tx[36:36] ),
- .alert_rx_i ( alert_rx[36:36] ),
+ // [37]: fatal_alert
+ .alert_tx_o ( alert_tx[37:37] ),
+ .alert_rx_i ( alert_rx[37:37] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2294,15 +2298,15 @@
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:37])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:38])
) u_edn1 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn1_edn_fatal_err),
- // [37]: fatal_alert
- .alert_tx_o ( alert_tx[37:37] ),
- .alert_rx_i ( alert_rx[37:37] ),
+ // [38]: fatal_alert
+ .alert_tx_o ( alert_tx[38:38] ),
+ .alert_rx_i ( alert_rx[38:38] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2318,16 +2322,16 @@
);
sram_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:38]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:39]),
.RndCnstSramKey(RndCnstSramCtrlMainSramKey),
.RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
.RndCnstSramLfsrPerm(RndCnstSramCtrlMainSramLfsrPerm),
.InstrExec(SramCtrlMainInstrExec)
) u_sram_ctrl_main (
- // [38]: fatal_intg_error
- // [39]: fatal_parity_error
- .alert_tx_o ( alert_tx[39:38] ),
- .alert_rx_i ( alert_rx[39:38] ),
+ // [39]: fatal_intg_error
+ // [40]: fatal_parity_error
+ .alert_tx_o ( alert_tx[40:39] ),
+ .alert_rx_i ( alert_rx[40:39] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2352,7 +2356,7 @@
);
otbn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:40]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:41]),
.Stub(OtbnStub),
.RegFile(OtbnRegFile),
.RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed),
@@ -2361,10 +2365,10 @@
// Interrupt
.intr_done_o (intr_otbn_done),
- // [40]: fatal
- // [41]: recov
- .alert_tx_o ( alert_tx[41:40] ),
- .alert_rx_i ( alert_rx[41:40] ),
+ // [41]: fatal
+ // [42]: recov
+ .alert_tx_o ( alert_tx[42:41] ),
+ .alert_rx_i ( alert_rx[42:41] ),
// Inter-module signals
.edn_rnd_o(edn1_edn_req[0]),
@@ -2384,14 +2388,14 @@
);
rom_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:42]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:43]),
.BootRomInitFile(RomCtrlBootRomInitFile),
.RndCnstScrNonce(RndCnstRomCtrlScrNonce),
.RndCnstScrKey(RndCnstRomCtrlScrKey)
) u_rom_ctrl (
- // [42]: fatal
- .alert_tx_o ( alert_tx[42:42] ),
- .alert_rx_i ( alert_rx[42:42] ),
+ // [43]: fatal
+ .alert_tx_o ( alert_tx[43:43] ),
+ .alert_rx_i ( alert_rx[43:43] ),
// Inter-module signals
.rom_cfg_i(ast_rom_cfg),
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index f2a00ad..c646b5f 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -202,7 +202,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[43] = {
+ top_earlgrey_alert_for_peripheral[44] = {
[kTopEarlgreyAlertIdGpioFatalFault] = kTopEarlgreyAlertPeripheralGpio,
[kTopEarlgreyAlertIdSpiDeviceFatalFault] = kTopEarlgreyAlertPeripheralSpiDevice,
[kTopEarlgreyAlertIdSpiHost0FatalFault] = kTopEarlgreyAlertPeripheralSpiHost0,
@@ -213,6 +213,7 @@
[kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl,
[kTopEarlgreyAlertIdLcCtrlFatalStateError] = kTopEarlgreyAlertPeripheralLcCtrl,
[kTopEarlgreyAlertIdLcCtrlFatalBusIntegError] = kTopEarlgreyAlertPeripheralLcCtrl,
+ [kTopEarlgreyAlertIdPinmuxAonFatalFault] = kTopEarlgreyAlertPeripheralPinmuxAon,
[kTopEarlgreyAlertIdSensorCtrlAonRecovAs] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
[kTopEarlgreyAlertIdSensorCtrlAonRecovCg] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
[kTopEarlgreyAlertIdSensorCtrlAonRecovGd] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 94dc16c..c9754e1 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1095,21 +1095,22 @@
kTopEarlgreyAlertPeripheralPattgen = 4, /**< pattgen */
kTopEarlgreyAlertPeripheralOtpCtrl = 5, /**< otp_ctrl */
kTopEarlgreyAlertPeripheralLcCtrl = 6, /**< lc_ctrl */
- kTopEarlgreyAlertPeripheralSensorCtrlAon = 7, /**< sensor_ctrl_aon */
- kTopEarlgreyAlertPeripheralSramCtrlRetAon = 8, /**< sram_ctrl_ret_aon */
- kTopEarlgreyAlertPeripheralFlashCtrl = 9, /**< flash_ctrl */
- kTopEarlgreyAlertPeripheralAes = 10, /**< aes */
- kTopEarlgreyAlertPeripheralHmac = 11, /**< hmac */
- kTopEarlgreyAlertPeripheralKmac = 12, /**< kmac */
- kTopEarlgreyAlertPeripheralKeymgr = 13, /**< keymgr */
- kTopEarlgreyAlertPeripheralCsrng = 14, /**< csrng */
- kTopEarlgreyAlertPeripheralEntropySrc = 15, /**< entropy_src */
- kTopEarlgreyAlertPeripheralEdn0 = 16, /**< edn0 */
- kTopEarlgreyAlertPeripheralEdn1 = 17, /**< edn1 */
- kTopEarlgreyAlertPeripheralSramCtrlMain = 18, /**< sram_ctrl_main */
- kTopEarlgreyAlertPeripheralOtbn = 19, /**< otbn */
- kTopEarlgreyAlertPeripheralRomCtrl = 20, /**< rom_ctrl */
- kTopEarlgreyAlertPeripheralLast = 20, /**< \internal Final Alert peripheral */
+ kTopEarlgreyAlertPeripheralPinmuxAon = 7, /**< pinmux_aon */
+ kTopEarlgreyAlertPeripheralSensorCtrlAon = 8, /**< sensor_ctrl_aon */
+ kTopEarlgreyAlertPeripheralSramCtrlRetAon = 9, /**< sram_ctrl_ret_aon */
+ kTopEarlgreyAlertPeripheralFlashCtrl = 10, /**< flash_ctrl */
+ kTopEarlgreyAlertPeripheralAes = 11, /**< aes */
+ kTopEarlgreyAlertPeripheralHmac = 12, /**< hmac */
+ kTopEarlgreyAlertPeripheralKmac = 13, /**< kmac */
+ kTopEarlgreyAlertPeripheralKeymgr = 14, /**< keymgr */
+ kTopEarlgreyAlertPeripheralCsrng = 15, /**< csrng */
+ kTopEarlgreyAlertPeripheralEntropySrc = 16, /**< entropy_src */
+ kTopEarlgreyAlertPeripheralEdn0 = 17, /**< edn0 */
+ kTopEarlgreyAlertPeripheralEdn1 = 18, /**< edn1 */
+ kTopEarlgreyAlertPeripheralSramCtrlMain = 19, /**< sram_ctrl_main */
+ kTopEarlgreyAlertPeripheralOtbn = 20, /**< otbn */
+ kTopEarlgreyAlertPeripheralRomCtrl = 21, /**< rom_ctrl */
+ kTopEarlgreyAlertPeripheralLast = 21, /**< \internal Final Alert peripheral */
} top_earlgrey_alert_peripheral_t;
/**
@@ -1129,40 +1130,41 @@
kTopEarlgreyAlertIdLcCtrlFatalProgError = 7, /**< lc_ctrl_fatal_prog_error */
kTopEarlgreyAlertIdLcCtrlFatalStateError = 8, /**< lc_ctrl_fatal_state_error */
kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 9, /**< lc_ctrl_fatal_bus_integ_error */
- kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 10, /**< sensor_ctrl_aon_recov_as */
- kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 11, /**< sensor_ctrl_aon_recov_cg */
- kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 12, /**< sensor_ctrl_aon_recov_gd */
- kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 13, /**< sensor_ctrl_aon_recov_ts_hi */
- kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 14, /**< sensor_ctrl_aon_recov_ts_lo */
- kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 15, /**< sensor_ctrl_aon_recov_fla */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 16, /**< sensor_ctrl_aon_recov_otp */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 17, /**< sensor_ctrl_aon_recov_ot0 */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 18, /**< sensor_ctrl_aon_recov_ot1 */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 19, /**< sensor_ctrl_aon_recov_ot2 */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 20, /**< sensor_ctrl_aon_recov_ot3 */
- kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 21, /**< sram_ctrl_ret_aon_fatal_intg_error */
- kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 22, /**< sram_ctrl_ret_aon_fatal_parity_error */
- kTopEarlgreyAlertIdFlashCtrlRecovErr = 23, /**< flash_ctrl_recov_err */
- kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 24, /**< flash_ctrl_recov_mp_err */
- kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 25, /**< flash_ctrl_recov_ecc_err */
- kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 26, /**< flash_ctrl_fatal_intg_err */
- kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 27, /**< aes_recov_ctrl_update_err */
- kTopEarlgreyAlertIdAesFatalFault = 28, /**< aes_fatal_fault */
- kTopEarlgreyAlertIdHmacFatalFault = 29, /**< hmac_fatal_fault */
- kTopEarlgreyAlertIdKmacFatalFault = 30, /**< kmac_fatal_fault */
- kTopEarlgreyAlertIdKeymgrFatalFaultErr = 31, /**< keymgr_fatal_fault_err */
- kTopEarlgreyAlertIdKeymgrRecovOperationErr = 32, /**< keymgr_recov_operation_err */
- kTopEarlgreyAlertIdCsrngFatalAlert = 33, /**< csrng_fatal_alert */
- kTopEarlgreyAlertIdEntropySrcRecovAlert = 34, /**< entropy_src_recov_alert */
- kTopEarlgreyAlertIdEntropySrcFatalAlert = 35, /**< entropy_src_fatal_alert */
- kTopEarlgreyAlertIdEdn0FatalAlert = 36, /**< edn0_fatal_alert */
- kTopEarlgreyAlertIdEdn1FatalAlert = 37, /**< edn1_fatal_alert */
- kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 38, /**< sram_ctrl_main_fatal_intg_error */
- kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 39, /**< sram_ctrl_main_fatal_parity_error */
- kTopEarlgreyAlertIdOtbnFatal = 40, /**< otbn_fatal */
- kTopEarlgreyAlertIdOtbnRecov = 41, /**< otbn_recov */
- kTopEarlgreyAlertIdRomCtrlFatal = 42, /**< rom_ctrl_fatal */
- kTopEarlgreyAlertIdLast = 42, /**< \internal The Last Valid Alert ID. */
+ kTopEarlgreyAlertIdPinmuxAonFatalFault = 10, /**< pinmux_aon_fatal_fault */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 11, /**< sensor_ctrl_aon_recov_as */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 12, /**< sensor_ctrl_aon_recov_cg */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 13, /**< sensor_ctrl_aon_recov_gd */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 14, /**< sensor_ctrl_aon_recov_ts_hi */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 15, /**< sensor_ctrl_aon_recov_ts_lo */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 16, /**< sensor_ctrl_aon_recov_fla */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 17, /**< sensor_ctrl_aon_recov_otp */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 18, /**< sensor_ctrl_aon_recov_ot0 */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 19, /**< sensor_ctrl_aon_recov_ot1 */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 20, /**< sensor_ctrl_aon_recov_ot2 */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 21, /**< sensor_ctrl_aon_recov_ot3 */
+ kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 22, /**< sram_ctrl_ret_aon_fatal_intg_error */
+ kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 23, /**< sram_ctrl_ret_aon_fatal_parity_error */
+ kTopEarlgreyAlertIdFlashCtrlRecovErr = 24, /**< flash_ctrl_recov_err */
+ kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 25, /**< flash_ctrl_recov_mp_err */
+ kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 26, /**< flash_ctrl_recov_ecc_err */
+ kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 27, /**< flash_ctrl_fatal_intg_err */
+ kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 28, /**< aes_recov_ctrl_update_err */
+ kTopEarlgreyAlertIdAesFatalFault = 29, /**< aes_fatal_fault */
+ kTopEarlgreyAlertIdHmacFatalFault = 30, /**< hmac_fatal_fault */
+ kTopEarlgreyAlertIdKmacFatalFault = 31, /**< kmac_fatal_fault */
+ kTopEarlgreyAlertIdKeymgrFatalFaultErr = 32, /**< keymgr_fatal_fault_err */
+ kTopEarlgreyAlertIdKeymgrRecovOperationErr = 33, /**< keymgr_recov_operation_err */
+ kTopEarlgreyAlertIdCsrngFatalAlert = 34, /**< csrng_fatal_alert */
+ kTopEarlgreyAlertIdEntropySrcRecovAlert = 35, /**< entropy_src_recov_alert */
+ kTopEarlgreyAlertIdEntropySrcFatalAlert = 36, /**< entropy_src_fatal_alert */
+ kTopEarlgreyAlertIdEdn0FatalAlert = 37, /**< edn0_fatal_alert */
+ kTopEarlgreyAlertIdEdn1FatalAlert = 38, /**< edn1_fatal_alert */
+ kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 39, /**< sram_ctrl_main_fatal_intg_error */
+ kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 40, /**< sram_ctrl_main_fatal_parity_error */
+ kTopEarlgreyAlertIdOtbnFatal = 41, /**< otbn_fatal */
+ kTopEarlgreyAlertIdOtbnRecov = 42, /**< otbn_recov */
+ kTopEarlgreyAlertIdRomCtrlFatal = 43, /**< rom_ctrl_fatal */
+ kTopEarlgreyAlertIdLast = 43, /**< \internal The Last Valid Alert ID. */
} top_earlgrey_alert_id_t;
/**
@@ -1172,7 +1174,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
extern const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[43];
+ top_earlgrey_alert_for_peripheral[44];
#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
