[hw, top_earlgrey] Align peripherals in different domains to PoT
This change would make it possible to describe peripherals using less
ePMP regions.
`ram_ret` base address `0x40520000` => `0x40600000` aligns the whole
peripherals in AON domain address space blob to PoT
2^21 (`0x40600000` - `0x40400000` = 0x200000).
`periph` clock domain peripherals start with `0x40000000` and end with
`0x40400000`, which is 2^22 (`0x40400000` - `0x40000000` =
`0x400000`), so it is already aligned.
The `main` clock domain peripheral address space blob starts with
`0x4100_0000` and the upper boundary is `u32` size, so no changes to
`.hjson`.
Signed-off-by: Silvestrs Timofejevs <silvestrst@lowrisc.org>
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index d2b8e89..a2053f9 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -568,7 +568,7 @@
reset_connections: {rst_ni: "sys_io_div4"},
domain: "Aon",
type: "ram_1p_scr",
- base_addr: "0x40520000",
+ base_addr: "0x40600000",
size: "0x1000",
byte_write: "true",
inter_signal_list: [
