[prim_mubi*_sync] Remove explicit mux prim to improve coverage
See #16586
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/ip/prim/rtl/prim_mubi12_sync.sv b/hw/ip/prim/rtl/prim_mubi12_sync.sv
index 956f40c..30ee2d6 100644
--- a/hw/ip/prim/rtl/prim_mubi12_sync.sv
+++ b/hw/ip/prim/rtl/prim_mubi12_sync.sv
@@ -90,15 +90,10 @@
);
// if any xor indicates signal is unstable, output the reset
- // value.
- prim_clock_mux2 #(
- .NoFpgaBufG(1'b1)
- ) u_mux (
- .clk0_i(mubi_q[k]),
- .clk1_i(reset_value[k]),
- .sel_i(|sig_unstable_buf),
- .clk_o(mubi[k])
- );
+ // value. note that the input and output signals of this mux
+ // are driven/read by constrained primitive cells (regs, buffers),
+ // hence this mux can be implemented behaviorally.
+ assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
end
// Note regarding SVAs below:
diff --git a/hw/ip/prim/rtl/prim_mubi16_sync.sv b/hw/ip/prim/rtl/prim_mubi16_sync.sv
index ab46fbc..02be5a0 100644
--- a/hw/ip/prim/rtl/prim_mubi16_sync.sv
+++ b/hw/ip/prim/rtl/prim_mubi16_sync.sv
@@ -90,15 +90,10 @@
);
// if any xor indicates signal is unstable, output the reset
- // value.
- prim_clock_mux2 #(
- .NoFpgaBufG(1'b1)
- ) u_mux (
- .clk0_i(mubi_q[k]),
- .clk1_i(reset_value[k]),
- .sel_i(|sig_unstable_buf),
- .clk_o(mubi[k])
- );
+ // value. note that the input and output signals of this mux
+ // are driven/read by constrained primitive cells (regs, buffers),
+ // hence this mux can be implemented behaviorally.
+ assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
end
// Note regarding SVAs below:
diff --git a/hw/ip/prim/rtl/prim_mubi4_sync.sv b/hw/ip/prim/rtl/prim_mubi4_sync.sv
index 264355c..0239540 100644
--- a/hw/ip/prim/rtl/prim_mubi4_sync.sv
+++ b/hw/ip/prim/rtl/prim_mubi4_sync.sv
@@ -90,15 +90,10 @@
);
// if any xor indicates signal is unstable, output the reset
- // value.
- prim_clock_mux2 #(
- .NoFpgaBufG(1'b1)
- ) u_mux (
- .clk0_i(mubi_q[k]),
- .clk1_i(reset_value[k]),
- .sel_i(|sig_unstable_buf),
- .clk_o(mubi[k])
- );
+ // value. note that the input and output signals of this mux
+ // are driven/read by constrained primitive cells (regs, buffers),
+ // hence this mux can be implemented behaviorally.
+ assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
end
// Note regarding SVAs below:
diff --git a/hw/ip/prim/rtl/prim_mubi8_sync.sv b/hw/ip/prim/rtl/prim_mubi8_sync.sv
index 51b1a32..14e9254 100644
--- a/hw/ip/prim/rtl/prim_mubi8_sync.sv
+++ b/hw/ip/prim/rtl/prim_mubi8_sync.sv
@@ -90,15 +90,10 @@
);
// if any xor indicates signal is unstable, output the reset
- // value.
- prim_clock_mux2 #(
- .NoFpgaBufG(1'b1)
- ) u_mux (
- .clk0_i(mubi_q[k]),
- .clk1_i(reset_value[k]),
- .sel_i(|sig_unstable_buf),
- .clk_o(mubi[k])
- );
+ // value. note that the input and output signals of this mux
+ // are driven/read by constrained primitive cells (regs, buffers),
+ // hence this mux can be implemented behaviorally.
+ assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
end
// Note regarding SVAs below:
diff --git a/util/design/data/prim_mubi_sync.sv.tpl b/util/design/data/prim_mubi_sync.sv.tpl
index da497fe..d1ca6b4 100644
--- a/util/design/data/prim_mubi_sync.sv.tpl
+++ b/util/design/data/prim_mubi_sync.sv.tpl
@@ -90,15 +90,10 @@
);
// if any xor indicates signal is unstable, output the reset
- // value.
- prim_clock_mux2 #(
- .NoFpgaBufG(1'b1)
- ) u_mux (
- .clk0_i(mubi_q[k]),
- .clk1_i(reset_value[k]),
- .sel_i(|sig_unstable_buf),
- .clk_o(mubi[k])
- );
+ // value. note that the input and output signals of this mux
+ // are driven/read by constrained primitive cells (regs, buffers),
+ // hence this mux can be implemented behaviorally.
+ assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
end
// Note regarding SVAs below:
