hw/top_earlgrey/dv/chip_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: chip

  // Top level dut name (sv module).
  dut: chip_earlgrey_asic

  // Top level testbench name (sv module).
  tb: tb

  // Default simulator used to sign off.
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:chip_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/top_earlgrey/data/chip_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/top_earlgrey/data/top_earlgrey.hjson"

  // Add additional tops for simulation.
  sim_tops: ["pwrmgr_bind",
             "xbar_main_bind",
             "xbar_peri_bind"]

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                // TODO #5484, comment these 2 lines out because spi host memory is dummy
                // "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                // xbar tests
                "{proj_root}/hw/ip/tlul/generic_dv/xbar_tests.hjson",
                // Config files to get the correct flags for otbn_memutil and otbn_tracer
                "{proj_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson",
                "{proj_root}/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson",
                "{proj_root}/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson",
                "{proj_root}/hw/top_earlgrey/dv/chip_dif_tests.hjson",
                "{proj_root}/hw/top_earlgrey/dv/chip_mask_rom_tests.hjson",
                ]

  // Override existing project defaults to supply chip-specific values.
  overrides: [
    // Chip level design is markedly different from our Comportable IPs (and so
    // is our coverage goals). The coverage goals also differ between 'default'
    // and the 'cover_reg_top' (used by common tests) builds. We override the
    // variables below to swap the coverage cfg files used for the Comportable
    // IPs with chip-specific ones. See `doc/ug/dv_methodology.md` for more
    // details.

    // Used by all chip level functional test. Collects coverage on the IO
    // boundary of all pre-verified IPs and full coverage on non-pre-verified
    // IPs. See `hw/dv/tools/dvsim/common_sim_cfg.hjson` for the default value.
    {
      name: default_vcs_cov_cfg_file
      value: "-cm_hier {proj_root}/hw/top_earlgrey/dv/cov/chip_cover.cfg"
    }
    // Used by 'cover_reg_top' only builds - we only cover the *_reg_top of
    // the non-pre-verified modules at the chip level. See
    // `hw/dv/tools/dvsim//common_sim_cfg.hjson` for the default value.
    {
      name: cover_reg_top_vcs_cov_cfg_file
      value: "-cm_hier {proj_root}/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg"
    }
    // Used by the UNR flow.
    {
      name: vcs_unr_cfg_file
      value: "{proj_root}/hw/top_earlgrey/dv/cov/unr.cfg"
    }

    // This defaults to 'ip' in `hw/data/common_project_cfg.hjson`.
    {
      name: design_level
      value: "top"
    }
  ]

  // Default iterations for all tests - each test entry can override this.
  reseed: 1

  // Default UVM test and seq class name.
  uvm_test: chip_base_test
  uvm_test_seq: chip_sw_base_vseq
  sw_build_device: sim_dv

  // Add build modes.
  build_modes: [
    {
      name: en_ibex_tracer
      build_opts: ["+define+RVFI=1"]
    }
  ]

  // Add options needed to compile against otbn_memutil, otbn_tracer, and
  // memutil_dpi_scrambled.
  en_build_modes: ["{tool}_otbn_memutil_build_opts",
                   "{tool}_otbn_tracer_build_opts",
                   "{tool}_memutil_dpi_scrambled_build_opts"]

  // Add run modes.
  run_modes: [
    { // This base mode initializes the OTP / life cycle with the DEV state
      name: base_otp_lc_dev_mode
      sw_images: ["sw/device/otp_img/otp_img:3"],
      run_opts: ["+sw_build_bin_dir={sw_build_dir}/build-bin",
                 "+sw_build_device={sw_build_device}",
                 // Separate individual SW images supplied to +sw_images plusarg by comma.
                 "+sw_images={eval_cmd} echo {sw_images} | sed -E 's/\\s+/,/g'"]
    }
    {
      name: sw_test_mode
      sw_images: ["sw/device/boot_rom/boot_rom:0"]
      en_run_modes: ["base_otp_lc_dev_mode"]
    }
    {
      name: stub_cpu_mode
      en_run_modes: ["base_otp_lc_dev_mode"]
      run_opts: ["+stub_cpu=1"]
    }
    {
      // Append stub cpu mode to csr_tests_mode, run with 20 reseeds.
      name: csr_tests_mode
      en_run_modes: ["stub_cpu_mode"]
      reseed: 20
    }
    {
      // Append stub cpu mode to mem_tests_mode, run with 20 reseeds.
      name: mem_tests_mode
      en_run_modes: ["stub_cpu_mode"]
      reseed: 20
    }
    {
      name: xbar_mode
      en_run_modes: ["base_otp_lc_dev_mode"]
      run_opts: ["+xbar_mode=1"]
      reseed: 100
    }
  ]

  // List of test specifications.
  //
  // If you are adding a test that has been generated from the `sw_tests`
  // dictionary declared in `sw/device/tests/meson.build`, the `sw_images` list
  // below should contain `sw/device/tests/<sw_test_name>` (without any more
  // subdirectories) because that is where the meson target is created. For
  // example `dif_plic_smoketest` is added to `sw_tests` in
  // `sw/device/tests/dif/meson.build`, but the final meson targets all start
  // `sw/device/tests/dif_plic_smoketest_`.
  //
  // Each entry in `sw_images` is followed by an index separated with ':' which
  // is used by the testbench to know what type of image is it:
  // - 0 for boot_rom,
  // - 1 for SW test,
  // - 2 for OTBN test,
  // - 3 for OTP and so on
  // This allows an arbitrary number of SW images to be supplied to the TB.
  tests: [
    {
      name: chip_sw_uart_tx_rx
      uvm_test_seq: chip_sw_uart_tx_rx_vseq
      sw_images: ["sw/device/tests/uart_tx_rx_test:1"]
      en_run_modes: ["sw_test_mode"]
      reseed: 10
    }
    {
      name: chip_sw_uart_tx_rx_idx1
      uvm_test_seq: chip_sw_uart_tx_rx_vseq
      sw_images: ["sw/device/tests/uart_tx_rx_test:1"]
      en_run_modes: ["sw_test_mode"]
      run_opts: ["+uart_idx=1"]
      reseed: 10
    }
    {
      name: chip_sw_uart_tx_rx_idx2
      uvm_test_seq: chip_sw_uart_tx_rx_vseq
      sw_images: ["sw/device/tests/uart_tx_rx_test:1"]
      en_run_modes: ["sw_test_mode"]
      run_opts: ["+uart_idx=2"]
      reseed: 10
    }
    {
      name: chip_sw_uart_tx_rx_idx3
      uvm_test_seq: chip_sw_uart_tx_rx_vseq
      sw_images: ["sw/device/tests/uart_tx_rx_test:1"]
      en_run_modes: ["sw_test_mode"]
      run_opts: ["+uart_idx=3"]
      reseed: 10
    }
    {
      name: chip_sw_uart_tx_rx_bootstrap
      uvm_test_seq: chip_sw_uart_tx_rx_vseq
      sw_images: ["sw/device/tests/uart_tx_rx_test:1"]
      en_run_modes: ["sw_test_mode"]
      run_opts: ["+use_spi_load_bootstrap=1"]
    }
    {
      name: chip_sw_spi_device_tx_rx
      uvm_test_seq: chip_sw_spi_tx_rx_vseq
      sw_images: ["sw/device/tests/spi_tx_rx_test:1"]
      en_run_modes: ["sw_test_mode"]
    }
    {
      name: chip_sw_gpio
      uvm_test_seq: chip_sw_gpio_vseq
      sw_images: ["sw/device/tests/gpio_test:1"]
      en_run_modes: ["sw_test_mode"]
    }
    {
      name: chip_sw_flash_ctrl_access
      uvm_test_seq: chip_sw_base_vseq
      sw_images: ["sw/device/tests/flash_ctrl_test:1"]
      en_run_modes: ["sw_test_mode"]
    }
    {
      name: chip_sw_lc_ctrl_otp_hw_cfg
      uvm_test_seq: chip_sw_base_vseq
      sw_images: ["sw/device/tests/lc_ctrl_otp_hw_cfg_test:1"]
      en_run_modes: ["sw_test_mode"]
    }
    {
      name: chip_sw_pwrmgr_usbdev_smoketest
      uvm_test_seq: chip_sw_base_vseq
      sw_images: ["sw/device/tests/pwrmgr_usbdev_smoketest:1"]
      en_run_modes: ["sw_test_mode"]
      run_opts: ["+sw_test_timeout_ns=2000000"]
    }
    {
      name: chip_sw_rv_timer_irq
      uvm_test_seq: chip_sw_base_vseq
      sw_images: ["sw/device/tests/dif_rv_timer_smoketest:1"]
      en_run_modes: ["sw_test_mode"]
    }

    {
      name: chip_sw_coremark
      uvm_test_seq: chip_sw_base_vseq
      sw_images: ["sw/device/benchmarks/coremark/coremark_top_earlgrey:1:external"]
      en_run_modes: ["sw_test_mode"]
      run_opts: ["+en_uart_logger=1",
                 "+sw_test_timeout_ns=22000000"]
    }
    // The test below is from tl_access_tests.hjson, but we don't need to include tl_intg_err,
    // which is also in tl_access_tests.hjson, as TLUL integrity is generated by design and we
    // include this block in the data path when we stub CPU to verify TL access
    // So copy chip_tl_errors here and append the stub_cpu_mode run mode.
    {
      name: chip_tl_errors
      build_mode: "cover_reg_top"
      uvm_test_seq: "{name}_common_vseq"
      run_opts: ["+run_tl_errors"]
      en_run_modes: ["stub_cpu_mode"]
      reseed: 20
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["chip_sw_uart_tx_rx"]
    }
  ]
}