| commit | acd168c15616e620a7ab30ebc5906520cc7161aa | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Nov 30 17:09:48 2021 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Thu Dec 02 10:15:36 2021 +0000 |
| tree | 5bdee2f69cb809efbe61b12338c6ff2234dba485 | |
| parent | 15daa83ee2abb7abecc0140bcbe043a013111dfd [diff] |
[dv] Only run registers through one csr_rw sequence at once
This is an issue up for blocks with multiple device interfaces. The
default behaviour of run_csr_vseq is to grab all of the registers
defined for the block. The run_tl_intg_err_vseq task runs in parallel
across the different ral_names, which means we do run_csr_vseq("rw")
for each of the interfaces in parallel.
It turns out that the csr_rw sequence isn't really "re-entrant". If
you've got two copies running at once then you can see a register R
with thread 0 writing it and thread 1 reading it at the same time.
This causes a UVM warning (and causes the test to fail).
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING and our documentation on project organization and processes for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).