[flash/top] Generated files and scrambling key connections - OTP does not exist yet in master, so the keys are hardwired Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv index 5a3e6f6..4c7081e 100644 --- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv +++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -105,6 +105,10 @@ } flash_ctrl_reg2hw_addr_reg_t; typedef struct packed { + logic q; + } flash_ctrl_reg2hw_scramble_en_reg_t; + + typedef struct packed { struct packed { logic q; } en; @@ -240,11 +244,12 @@ // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [312:307] - flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [306:301] - flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [300:289] - flash_ctrl_reg2hw_control_reg_t control; // [288:272] - flash_ctrl_reg2hw_addr_reg_t addr; // [271:240] + flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [313:308] + flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [307:302] + flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [301:290] + flash_ctrl_reg2hw_control_reg_t control; // [289:273] + flash_ctrl_reg2hw_addr_reg_t addr; // [272:241] + flash_ctrl_reg2hw_scramble_en_reg_t scramble_en; // [240:240] flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [239:48] flash_ctrl_reg2hw_default_region_reg_t default_region; // [47:45] flash_ctrl_reg2hw_mp_bank_cfg_mreg_t [1:0] mp_bank_cfg; // [44:43] @@ -271,28 +276,29 @@ parameter logic [6:0] FLASH_CTRL_CTRL_REGWEN_OFFSET = 7'h c; parameter logic [6:0] FLASH_CTRL_CONTROL_OFFSET = 7'h 10; parameter logic [6:0] FLASH_CTRL_ADDR_OFFSET = 7'h 14; - parameter logic [6:0] FLASH_CTRL_REGION_CFG_REGWEN_OFFSET = 7'h 18; - parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG0_OFFSET = 7'h 1c; - parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG1_OFFSET = 7'h 20; - parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG2_OFFSET = 7'h 24; - parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG3_OFFSET = 7'h 28; - parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG4_OFFSET = 7'h 2c; - parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG5_OFFSET = 7'h 30; - parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG6_OFFSET = 7'h 34; - parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG7_OFFSET = 7'h 38; - parameter logic [6:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 7'h 3c; - parameter logic [6:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 7'h 40; - parameter logic [6:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 7'h 44; - parameter logic [6:0] FLASH_CTRL_OP_STATUS_OFFSET = 7'h 48; - parameter logic [6:0] FLASH_CTRL_STATUS_OFFSET = 7'h 4c; - parameter logic [6:0] FLASH_CTRL_SCRATCH_OFFSET = 7'h 50; - parameter logic [6:0] FLASH_CTRL_FIFO_LVL_OFFSET = 7'h 54; - parameter logic [6:0] FLASH_CTRL_FIFO_RST_OFFSET = 7'h 58; + parameter logic [6:0] FLASH_CTRL_SCRAMBLE_EN_OFFSET = 7'h 18; + parameter logic [6:0] FLASH_CTRL_REGION_CFG_REGWEN_OFFSET = 7'h 1c; + parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG0_OFFSET = 7'h 20; + parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG1_OFFSET = 7'h 24; + parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG2_OFFSET = 7'h 28; + parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG3_OFFSET = 7'h 2c; + parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG4_OFFSET = 7'h 30; + parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG5_OFFSET = 7'h 34; + parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG6_OFFSET = 7'h 38; + parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG7_OFFSET = 7'h 3c; + parameter logic [6:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 7'h 40; + parameter logic [6:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 7'h 44; + parameter logic [6:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 7'h 48; + parameter logic [6:0] FLASH_CTRL_OP_STATUS_OFFSET = 7'h 4c; + parameter logic [6:0] FLASH_CTRL_STATUS_OFFSET = 7'h 50; + parameter logic [6:0] FLASH_CTRL_SCRATCH_OFFSET = 7'h 54; + parameter logic [6:0] FLASH_CTRL_FIFO_LVL_OFFSET = 7'h 58; + parameter logic [6:0] FLASH_CTRL_FIFO_RST_OFFSET = 7'h 5c; // Window parameter - parameter logic [6:0] FLASH_CTRL_PROG_FIFO_OFFSET = 7'h 5c; + parameter logic [6:0] FLASH_CTRL_PROG_FIFO_OFFSET = 7'h 60; parameter logic [6:0] FLASH_CTRL_PROG_FIFO_SIZE = 7'h 4; - parameter logic [6:0] FLASH_CTRL_RD_FIFO_OFFSET = 7'h 60; + parameter logic [6:0] FLASH_CTRL_RD_FIFO_OFFSET = 7'h 64; parameter logic [6:0] FLASH_CTRL_RD_FIFO_SIZE = 7'h 4; // Register Index @@ -303,6 +309,7 @@ FLASH_CTRL_CTRL_REGWEN, FLASH_CTRL_CONTROL, FLASH_CTRL_ADDR, + FLASH_CTRL_SCRAMBLE_EN, FLASH_CTRL_REGION_CFG_REGWEN, FLASH_CTRL_MP_REGION_CFG0, FLASH_CTRL_MP_REGION_CFG1, @@ -323,30 +330,31 @@ } flash_ctrl_id_e; // Register width information to check illegal writes - parameter logic [3:0] FLASH_CTRL_PERMIT [23] = '{ + parameter logic [3:0] FLASH_CTRL_PERMIT [24] = '{ 4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE 4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE 4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST 4'b 0001, // index[ 3] FLASH_CTRL_CTRL_REGWEN 4'b 1111, // index[ 4] FLASH_CTRL_CONTROL 4'b 1111, // index[ 5] FLASH_CTRL_ADDR - 4'b 0001, // index[ 6] FLASH_CTRL_REGION_CFG_REGWEN - 4'b 1111, // index[ 7] FLASH_CTRL_MP_REGION_CFG0 - 4'b 1111, // index[ 8] FLASH_CTRL_MP_REGION_CFG1 - 4'b 1111, // index[ 9] FLASH_CTRL_MP_REGION_CFG2 - 4'b 1111, // index[10] FLASH_CTRL_MP_REGION_CFG3 - 4'b 1111, // index[11] FLASH_CTRL_MP_REGION_CFG4 - 4'b 1111, // index[12] FLASH_CTRL_MP_REGION_CFG5 - 4'b 1111, // index[13] FLASH_CTRL_MP_REGION_CFG6 - 4'b 1111, // index[14] FLASH_CTRL_MP_REGION_CFG7 - 4'b 0001, // index[15] FLASH_CTRL_DEFAULT_REGION - 4'b 0001, // index[16] FLASH_CTRL_BANK_CFG_REGWEN - 4'b 0001, // index[17] FLASH_CTRL_MP_BANK_CFG - 4'b 0001, // index[18] FLASH_CTRL_OP_STATUS - 4'b 0111, // index[19] FLASH_CTRL_STATUS - 4'b 1111, // index[20] FLASH_CTRL_SCRATCH - 4'b 0011, // index[21] FLASH_CTRL_FIFO_LVL - 4'b 0001 // index[22] FLASH_CTRL_FIFO_RST + 4'b 0001, // index[ 6] FLASH_CTRL_SCRAMBLE_EN + 4'b 0001, // index[ 7] FLASH_CTRL_REGION_CFG_REGWEN + 4'b 1111, // index[ 8] FLASH_CTRL_MP_REGION_CFG0 + 4'b 1111, // index[ 9] FLASH_CTRL_MP_REGION_CFG1 + 4'b 1111, // index[10] FLASH_CTRL_MP_REGION_CFG2 + 4'b 1111, // index[11] FLASH_CTRL_MP_REGION_CFG3 + 4'b 1111, // index[12] FLASH_CTRL_MP_REGION_CFG4 + 4'b 1111, // index[13] FLASH_CTRL_MP_REGION_CFG5 + 4'b 1111, // index[14] FLASH_CTRL_MP_REGION_CFG6 + 4'b 1111, // index[15] FLASH_CTRL_MP_REGION_CFG7 + 4'b 0001, // index[16] FLASH_CTRL_DEFAULT_REGION + 4'b 0001, // index[17] FLASH_CTRL_BANK_CFG_REGWEN + 4'b 0001, // index[18] FLASH_CTRL_MP_BANK_CFG + 4'b 0001, // index[19] FLASH_CTRL_OP_STATUS + 4'b 0111, // index[20] FLASH_CTRL_STATUS + 4'b 1111, // index[21] FLASH_CTRL_SCRATCH + 4'b 0011, // index[22] FLASH_CTRL_FIFO_LVL + 4'b 0001 // index[23] FLASH_CTRL_FIFO_RST }; endpackage
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv index f7da02c..3bfc0f0 100644 --- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv +++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
@@ -88,10 +88,10 @@ reg_steer = 2; // Default set to register // TODO: Can below codes be unique case () inside ? - if (tl_i.a_address[AW-1:0] >= 92 && tl_i.a_address[AW-1:0] < 96) begin + if (tl_i.a_address[AW-1:0] >= 96 && tl_i.a_address[AW-1:0] < 100) begin reg_steer = 0; end - if (tl_i.a_address[AW-1:0] >= 96 && tl_i.a_address[AW-1:0] < 100) begin + if (tl_i.a_address[AW-1:0] >= 100 && tl_i.a_address[AW-1:0] < 104) begin reg_steer = 1; end end @@ -189,6 +189,9 @@ logic [31:0] addr_qs; logic [31:0] addr_wd; logic addr_we; + logic scramble_en_qs; + logic scramble_en_wd; + logic scramble_en_we; logic region_cfg_regwen_qs; logic region_cfg_regwen_wd; logic region_cfg_regwen_we; @@ -995,6 +998,33 @@ ); + // R[scramble_en]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_scramble_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (scramble_en_we), + .wd (scramble_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.scramble_en.q ), + + // to register interface (read) + .qs (scramble_en_qs) + ); + + // R[region_cfg_regwen]: V(False) prim_subreg #( @@ -2939,7 +2969,7 @@ - logic [22:0] addr_hit; + logic [23:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET); @@ -2948,23 +2978,24 @@ addr_hit[ 3] = (reg_addr == FLASH_CTRL_CTRL_REGWEN_OFFSET); addr_hit[ 4] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET); addr_hit[ 5] = (reg_addr == FLASH_CTRL_ADDR_OFFSET); - addr_hit[ 6] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_OFFSET); - addr_hit[ 7] = (reg_addr == FLASH_CTRL_MP_REGION_CFG0_OFFSET); - addr_hit[ 8] = (reg_addr == FLASH_CTRL_MP_REGION_CFG1_OFFSET); - addr_hit[ 9] = (reg_addr == FLASH_CTRL_MP_REGION_CFG2_OFFSET); - addr_hit[10] = (reg_addr == FLASH_CTRL_MP_REGION_CFG3_OFFSET); - addr_hit[11] = (reg_addr == FLASH_CTRL_MP_REGION_CFG4_OFFSET); - addr_hit[12] = (reg_addr == FLASH_CTRL_MP_REGION_CFG5_OFFSET); - addr_hit[13] = (reg_addr == FLASH_CTRL_MP_REGION_CFG6_OFFSET); - addr_hit[14] = (reg_addr == FLASH_CTRL_MP_REGION_CFG7_OFFSET); - addr_hit[15] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET); - addr_hit[16] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET); - addr_hit[17] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET); - addr_hit[18] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET); - addr_hit[19] = (reg_addr == FLASH_CTRL_STATUS_OFFSET); - addr_hit[20] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET); - addr_hit[21] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET); - addr_hit[22] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET); + addr_hit[ 6] = (reg_addr == FLASH_CTRL_SCRAMBLE_EN_OFFSET); + addr_hit[ 7] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_OFFSET); + addr_hit[ 8] = (reg_addr == FLASH_CTRL_MP_REGION_CFG0_OFFSET); + addr_hit[ 9] = (reg_addr == FLASH_CTRL_MP_REGION_CFG1_OFFSET); + addr_hit[10] = (reg_addr == FLASH_CTRL_MP_REGION_CFG2_OFFSET); + addr_hit[11] = (reg_addr == FLASH_CTRL_MP_REGION_CFG3_OFFSET); + addr_hit[12] = (reg_addr == FLASH_CTRL_MP_REGION_CFG4_OFFSET); + addr_hit[13] = (reg_addr == FLASH_CTRL_MP_REGION_CFG5_OFFSET); + addr_hit[14] = (reg_addr == FLASH_CTRL_MP_REGION_CFG6_OFFSET); + addr_hit[15] = (reg_addr == FLASH_CTRL_MP_REGION_CFG7_OFFSET); + addr_hit[16] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET); + addr_hit[17] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET); + addr_hit[18] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET); + addr_hit[19] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET); + addr_hit[20] = (reg_addr == FLASH_CTRL_STATUS_OFFSET); + addr_hit[21] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET); + addr_hit[22] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET); + addr_hit[23] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -2995,6 +3026,7 @@ if (addr_hit[20] && reg_we && (FLASH_CTRL_PERMIT[20] != (FLASH_CTRL_PERMIT[20] & reg_be))) wr_err = 1'b1 ; if (addr_hit[21] && reg_we && (FLASH_CTRL_PERMIT[21] != (FLASH_CTRL_PERMIT[21] & reg_be))) wr_err = 1'b1 ; if (addr_hit[22] && reg_we && (FLASH_CTRL_PERMIT[22] != (FLASH_CTRL_PERMIT[22] & reg_be))) wr_err = 1'b1 ; + if (addr_hit[23] && reg_we && (FLASH_CTRL_PERMIT[23] != (FLASH_CTRL_PERMIT[23] & reg_be))) wr_err = 1'b1 ; end assign intr_state_prog_empty_we = addr_hit[0] & reg_we & ~wr_err; @@ -3071,225 +3103,228 @@ assign addr_we = addr_hit[5] & reg_we & ~wr_err; assign addr_wd = reg_wdata[31:0]; - assign region_cfg_regwen_we = addr_hit[6] & reg_we & ~wr_err; + assign scramble_en_we = addr_hit[6] & reg_we & ~wr_err; + assign scramble_en_wd = reg_wdata[0]; + + assign region_cfg_regwen_we = addr_hit[7] & reg_we & ~wr_err; assign region_cfg_regwen_wd = reg_wdata[0]; - assign mp_region_cfg0_en0_we = addr_hit[7] & reg_we & ~wr_err; + assign mp_region_cfg0_en0_we = addr_hit[8] & reg_we & ~wr_err; assign mp_region_cfg0_en0_wd = reg_wdata[0]; - assign mp_region_cfg0_rd_en0_we = addr_hit[7] & reg_we & ~wr_err; + assign mp_region_cfg0_rd_en0_we = addr_hit[8] & reg_we & ~wr_err; assign mp_region_cfg0_rd_en0_wd = reg_wdata[1]; - assign mp_region_cfg0_prog_en0_we = addr_hit[7] & reg_we & ~wr_err; + assign mp_region_cfg0_prog_en0_we = addr_hit[8] & reg_we & ~wr_err; assign mp_region_cfg0_prog_en0_wd = reg_wdata[2]; - assign mp_region_cfg0_erase_en0_we = addr_hit[7] & reg_we & ~wr_err; + assign mp_region_cfg0_erase_en0_we = addr_hit[8] & reg_we & ~wr_err; assign mp_region_cfg0_erase_en0_wd = reg_wdata[3]; - assign mp_region_cfg0_base0_we = addr_hit[7] & reg_we & ~wr_err; + assign mp_region_cfg0_base0_we = addr_hit[8] & reg_we & ~wr_err; assign mp_region_cfg0_base0_wd = reg_wdata[12:4]; - assign mp_region_cfg0_size0_we = addr_hit[7] & reg_we & ~wr_err; + assign mp_region_cfg0_size0_we = addr_hit[8] & reg_we & ~wr_err; assign mp_region_cfg0_size0_wd = reg_wdata[25:16]; - assign mp_region_cfg0_partition0_we = addr_hit[7] & reg_we & ~wr_err; + assign mp_region_cfg0_partition0_we = addr_hit[8] & reg_we & ~wr_err; assign mp_region_cfg0_partition0_wd = reg_wdata[28]; - assign mp_region_cfg1_en1_we = addr_hit[8] & reg_we & ~wr_err; + assign mp_region_cfg1_en1_we = addr_hit[9] & reg_we & ~wr_err; assign mp_region_cfg1_en1_wd = reg_wdata[0]; - assign mp_region_cfg1_rd_en1_we = addr_hit[8] & reg_we & ~wr_err; + assign mp_region_cfg1_rd_en1_we = addr_hit[9] & reg_we & ~wr_err; assign mp_region_cfg1_rd_en1_wd = reg_wdata[1]; - assign mp_region_cfg1_prog_en1_we = addr_hit[8] & reg_we & ~wr_err; + assign mp_region_cfg1_prog_en1_we = addr_hit[9] & reg_we & ~wr_err; assign mp_region_cfg1_prog_en1_wd = reg_wdata[2]; - assign mp_region_cfg1_erase_en1_we = addr_hit[8] & reg_we & ~wr_err; + assign mp_region_cfg1_erase_en1_we = addr_hit[9] & reg_we & ~wr_err; assign mp_region_cfg1_erase_en1_wd = reg_wdata[3]; - assign mp_region_cfg1_base1_we = addr_hit[8] & reg_we & ~wr_err; + assign mp_region_cfg1_base1_we = addr_hit[9] & reg_we & ~wr_err; assign mp_region_cfg1_base1_wd = reg_wdata[12:4]; - assign mp_region_cfg1_size1_we = addr_hit[8] & reg_we & ~wr_err; + assign mp_region_cfg1_size1_we = addr_hit[9] & reg_we & ~wr_err; assign mp_region_cfg1_size1_wd = reg_wdata[25:16]; - assign mp_region_cfg1_partition1_we = addr_hit[8] & reg_we & ~wr_err; + assign mp_region_cfg1_partition1_we = addr_hit[9] & reg_we & ~wr_err; assign mp_region_cfg1_partition1_wd = reg_wdata[28]; - assign mp_region_cfg2_en2_we = addr_hit[9] & reg_we & ~wr_err; + assign mp_region_cfg2_en2_we = addr_hit[10] & reg_we & ~wr_err; assign mp_region_cfg2_en2_wd = reg_wdata[0]; - assign mp_region_cfg2_rd_en2_we = addr_hit[9] & reg_we & ~wr_err; + assign mp_region_cfg2_rd_en2_we = addr_hit[10] & reg_we & ~wr_err; assign mp_region_cfg2_rd_en2_wd = reg_wdata[1]; - assign mp_region_cfg2_prog_en2_we = addr_hit[9] & reg_we & ~wr_err; + assign mp_region_cfg2_prog_en2_we = addr_hit[10] & reg_we & ~wr_err; assign mp_region_cfg2_prog_en2_wd = reg_wdata[2]; - assign mp_region_cfg2_erase_en2_we = addr_hit[9] & reg_we & ~wr_err; + assign mp_region_cfg2_erase_en2_we = addr_hit[10] & reg_we & ~wr_err; assign mp_region_cfg2_erase_en2_wd = reg_wdata[3]; - assign mp_region_cfg2_base2_we = addr_hit[9] & reg_we & ~wr_err; + assign mp_region_cfg2_base2_we = addr_hit[10] & reg_we & ~wr_err; assign mp_region_cfg2_base2_wd = reg_wdata[12:4]; - assign mp_region_cfg2_size2_we = addr_hit[9] & reg_we & ~wr_err; + assign mp_region_cfg2_size2_we = addr_hit[10] & reg_we & ~wr_err; assign mp_region_cfg2_size2_wd = reg_wdata[25:16]; - assign mp_region_cfg2_partition2_we = addr_hit[9] & reg_we & ~wr_err; + assign mp_region_cfg2_partition2_we = addr_hit[10] & reg_we & ~wr_err; assign mp_region_cfg2_partition2_wd = reg_wdata[28]; - assign mp_region_cfg3_en3_we = addr_hit[10] & reg_we & ~wr_err; + assign mp_region_cfg3_en3_we = addr_hit[11] & reg_we & ~wr_err; assign mp_region_cfg3_en3_wd = reg_wdata[0]; - assign mp_region_cfg3_rd_en3_we = addr_hit[10] & reg_we & ~wr_err; + assign mp_region_cfg3_rd_en3_we = addr_hit[11] & reg_we & ~wr_err; assign mp_region_cfg3_rd_en3_wd = reg_wdata[1]; - assign mp_region_cfg3_prog_en3_we = addr_hit[10] & reg_we & ~wr_err; + assign mp_region_cfg3_prog_en3_we = addr_hit[11] & reg_we & ~wr_err; assign mp_region_cfg3_prog_en3_wd = reg_wdata[2]; - assign mp_region_cfg3_erase_en3_we = addr_hit[10] & reg_we & ~wr_err; + assign mp_region_cfg3_erase_en3_we = addr_hit[11] & reg_we & ~wr_err; assign mp_region_cfg3_erase_en3_wd = reg_wdata[3]; - assign mp_region_cfg3_base3_we = addr_hit[10] & reg_we & ~wr_err; + assign mp_region_cfg3_base3_we = addr_hit[11] & reg_we & ~wr_err; assign mp_region_cfg3_base3_wd = reg_wdata[12:4]; - assign mp_region_cfg3_size3_we = addr_hit[10] & reg_we & ~wr_err; + assign mp_region_cfg3_size3_we = addr_hit[11] & reg_we & ~wr_err; assign mp_region_cfg3_size3_wd = reg_wdata[25:16]; - assign mp_region_cfg3_partition3_we = addr_hit[10] & reg_we & ~wr_err; + assign mp_region_cfg3_partition3_we = addr_hit[11] & reg_we & ~wr_err; assign mp_region_cfg3_partition3_wd = reg_wdata[28]; - assign mp_region_cfg4_en4_we = addr_hit[11] & reg_we & ~wr_err; + assign mp_region_cfg4_en4_we = addr_hit[12] & reg_we & ~wr_err; assign mp_region_cfg4_en4_wd = reg_wdata[0]; - assign mp_region_cfg4_rd_en4_we = addr_hit[11] & reg_we & ~wr_err; + assign mp_region_cfg4_rd_en4_we = addr_hit[12] & reg_we & ~wr_err; assign mp_region_cfg4_rd_en4_wd = reg_wdata[1]; - assign mp_region_cfg4_prog_en4_we = addr_hit[11] & reg_we & ~wr_err; + assign mp_region_cfg4_prog_en4_we = addr_hit[12] & reg_we & ~wr_err; assign mp_region_cfg4_prog_en4_wd = reg_wdata[2]; - assign mp_region_cfg4_erase_en4_we = addr_hit[11] & reg_we & ~wr_err; + assign mp_region_cfg4_erase_en4_we = addr_hit[12] & reg_we & ~wr_err; assign mp_region_cfg4_erase_en4_wd = reg_wdata[3]; - assign mp_region_cfg4_base4_we = addr_hit[11] & reg_we & ~wr_err; + assign mp_region_cfg4_base4_we = addr_hit[12] & reg_we & ~wr_err; assign mp_region_cfg4_base4_wd = reg_wdata[12:4]; - assign mp_region_cfg4_size4_we = addr_hit[11] & reg_we & ~wr_err; + assign mp_region_cfg4_size4_we = addr_hit[12] & reg_we & ~wr_err; assign mp_region_cfg4_size4_wd = reg_wdata[25:16]; - assign mp_region_cfg4_partition4_we = addr_hit[11] & reg_we & ~wr_err; + assign mp_region_cfg4_partition4_we = addr_hit[12] & reg_we & ~wr_err; assign mp_region_cfg4_partition4_wd = reg_wdata[28]; - assign mp_region_cfg5_en5_we = addr_hit[12] & reg_we & ~wr_err; + assign mp_region_cfg5_en5_we = addr_hit[13] & reg_we & ~wr_err; assign mp_region_cfg5_en5_wd = reg_wdata[0]; - assign mp_region_cfg5_rd_en5_we = addr_hit[12] & reg_we & ~wr_err; + assign mp_region_cfg5_rd_en5_we = addr_hit[13] & reg_we & ~wr_err; assign mp_region_cfg5_rd_en5_wd = reg_wdata[1]; - assign mp_region_cfg5_prog_en5_we = addr_hit[12] & reg_we & ~wr_err; + assign mp_region_cfg5_prog_en5_we = addr_hit[13] & reg_we & ~wr_err; assign mp_region_cfg5_prog_en5_wd = reg_wdata[2]; - assign mp_region_cfg5_erase_en5_we = addr_hit[12] & reg_we & ~wr_err; + assign mp_region_cfg5_erase_en5_we = addr_hit[13] & reg_we & ~wr_err; assign mp_region_cfg5_erase_en5_wd = reg_wdata[3]; - assign mp_region_cfg5_base5_we = addr_hit[12] & reg_we & ~wr_err; + assign mp_region_cfg5_base5_we = addr_hit[13] & reg_we & ~wr_err; assign mp_region_cfg5_base5_wd = reg_wdata[12:4]; - assign mp_region_cfg5_size5_we = addr_hit[12] & reg_we & ~wr_err; + assign mp_region_cfg5_size5_we = addr_hit[13] & reg_we & ~wr_err; assign mp_region_cfg5_size5_wd = reg_wdata[25:16]; - assign mp_region_cfg5_partition5_we = addr_hit[12] & reg_we & ~wr_err; + assign mp_region_cfg5_partition5_we = addr_hit[13] & reg_we & ~wr_err; assign mp_region_cfg5_partition5_wd = reg_wdata[28]; - assign mp_region_cfg6_en6_we = addr_hit[13] & reg_we & ~wr_err; + assign mp_region_cfg6_en6_we = addr_hit[14] & reg_we & ~wr_err; assign mp_region_cfg6_en6_wd = reg_wdata[0]; - assign mp_region_cfg6_rd_en6_we = addr_hit[13] & reg_we & ~wr_err; + assign mp_region_cfg6_rd_en6_we = addr_hit[14] & reg_we & ~wr_err; assign mp_region_cfg6_rd_en6_wd = reg_wdata[1]; - assign mp_region_cfg6_prog_en6_we = addr_hit[13] & reg_we & ~wr_err; + assign mp_region_cfg6_prog_en6_we = addr_hit[14] & reg_we & ~wr_err; assign mp_region_cfg6_prog_en6_wd = reg_wdata[2]; - assign mp_region_cfg6_erase_en6_we = addr_hit[13] & reg_we & ~wr_err; + assign mp_region_cfg6_erase_en6_we = addr_hit[14] & reg_we & ~wr_err; assign mp_region_cfg6_erase_en6_wd = reg_wdata[3]; - assign mp_region_cfg6_base6_we = addr_hit[13] & reg_we & ~wr_err; + assign mp_region_cfg6_base6_we = addr_hit[14] & reg_we & ~wr_err; assign mp_region_cfg6_base6_wd = reg_wdata[12:4]; - assign mp_region_cfg6_size6_we = addr_hit[13] & reg_we & ~wr_err; + assign mp_region_cfg6_size6_we = addr_hit[14] & reg_we & ~wr_err; assign mp_region_cfg6_size6_wd = reg_wdata[25:16]; - assign mp_region_cfg6_partition6_we = addr_hit[13] & reg_we & ~wr_err; + assign mp_region_cfg6_partition6_we = addr_hit[14] & reg_we & ~wr_err; assign mp_region_cfg6_partition6_wd = reg_wdata[28]; - assign mp_region_cfg7_en7_we = addr_hit[14] & reg_we & ~wr_err; + assign mp_region_cfg7_en7_we = addr_hit[15] & reg_we & ~wr_err; assign mp_region_cfg7_en7_wd = reg_wdata[0]; - assign mp_region_cfg7_rd_en7_we = addr_hit[14] & reg_we & ~wr_err; + assign mp_region_cfg7_rd_en7_we = addr_hit[15] & reg_we & ~wr_err; assign mp_region_cfg7_rd_en7_wd = reg_wdata[1]; - assign mp_region_cfg7_prog_en7_we = addr_hit[14] & reg_we & ~wr_err; + assign mp_region_cfg7_prog_en7_we = addr_hit[15] & reg_we & ~wr_err; assign mp_region_cfg7_prog_en7_wd = reg_wdata[2]; - assign mp_region_cfg7_erase_en7_we = addr_hit[14] & reg_we & ~wr_err; + assign mp_region_cfg7_erase_en7_we = addr_hit[15] & reg_we & ~wr_err; assign mp_region_cfg7_erase_en7_wd = reg_wdata[3]; - assign mp_region_cfg7_base7_we = addr_hit[14] & reg_we & ~wr_err; + assign mp_region_cfg7_base7_we = addr_hit[15] & reg_we & ~wr_err; assign mp_region_cfg7_base7_wd = reg_wdata[12:4]; - assign mp_region_cfg7_size7_we = addr_hit[14] & reg_we & ~wr_err; + assign mp_region_cfg7_size7_we = addr_hit[15] & reg_we & ~wr_err; assign mp_region_cfg7_size7_wd = reg_wdata[25:16]; - assign mp_region_cfg7_partition7_we = addr_hit[14] & reg_we & ~wr_err; + assign mp_region_cfg7_partition7_we = addr_hit[15] & reg_we & ~wr_err; assign mp_region_cfg7_partition7_wd = reg_wdata[28]; - assign default_region_rd_en_we = addr_hit[15] & reg_we & ~wr_err; + assign default_region_rd_en_we = addr_hit[16] & reg_we & ~wr_err; assign default_region_rd_en_wd = reg_wdata[0]; - assign default_region_prog_en_we = addr_hit[15] & reg_we & ~wr_err; + assign default_region_prog_en_we = addr_hit[16] & reg_we & ~wr_err; assign default_region_prog_en_wd = reg_wdata[1]; - assign default_region_erase_en_we = addr_hit[15] & reg_we & ~wr_err; + assign default_region_erase_en_we = addr_hit[16] & reg_we & ~wr_err; assign default_region_erase_en_wd = reg_wdata[2]; - assign bank_cfg_regwen_we = addr_hit[16] & reg_we & ~wr_err; + assign bank_cfg_regwen_we = addr_hit[17] & reg_we & ~wr_err; assign bank_cfg_regwen_wd = reg_wdata[0]; - assign mp_bank_cfg_erase_en0_we = addr_hit[17] & reg_we & ~wr_err; + assign mp_bank_cfg_erase_en0_we = addr_hit[18] & reg_we & ~wr_err; assign mp_bank_cfg_erase_en0_wd = reg_wdata[0]; - assign mp_bank_cfg_erase_en1_we = addr_hit[17] & reg_we & ~wr_err; + assign mp_bank_cfg_erase_en1_we = addr_hit[18] & reg_we & ~wr_err; assign mp_bank_cfg_erase_en1_wd = reg_wdata[1]; - assign op_status_done_we = addr_hit[18] & reg_we & ~wr_err; + assign op_status_done_we = addr_hit[19] & reg_we & ~wr_err; assign op_status_done_wd = reg_wdata[0]; - assign op_status_err_we = addr_hit[18] & reg_we & ~wr_err; + assign op_status_err_we = addr_hit[19] & reg_we & ~wr_err; assign op_status_err_wd = reg_wdata[1]; - assign status_rd_full_re = addr_hit[19] && reg_re; + assign status_rd_full_re = addr_hit[20] && reg_re; - assign status_rd_empty_re = addr_hit[19] && reg_re; + assign status_rd_empty_re = addr_hit[20] && reg_re; - assign status_prog_full_re = addr_hit[19] && reg_re; + assign status_prog_full_re = addr_hit[20] && reg_re; - assign status_prog_empty_re = addr_hit[19] && reg_re; + assign status_prog_empty_re = addr_hit[20] && reg_re; - assign status_init_wip_re = addr_hit[19] && reg_re; + assign status_init_wip_re = addr_hit[20] && reg_re; - assign status_error_page_re = addr_hit[19] && reg_re; + assign status_error_page_re = addr_hit[20] && reg_re; - assign status_error_bank_re = addr_hit[19] && reg_re; + assign status_error_bank_re = addr_hit[20] && reg_re; - assign scratch_we = addr_hit[20] & reg_we & ~wr_err; + assign scratch_we = addr_hit[21] & reg_we & ~wr_err; assign scratch_wd = reg_wdata[31:0]; - assign fifo_lvl_prog_we = addr_hit[21] & reg_we & ~wr_err; + assign fifo_lvl_prog_we = addr_hit[22] & reg_we & ~wr_err; assign fifo_lvl_prog_wd = reg_wdata[4:0]; - assign fifo_lvl_rd_we = addr_hit[21] & reg_we & ~wr_err; + assign fifo_lvl_rd_we = addr_hit[22] & reg_we & ~wr_err; assign fifo_lvl_rd_wd = reg_wdata[12:8]; - assign fifo_rst_we = addr_hit[22] & reg_we & ~wr_err; + assign fifo_rst_we = addr_hit[23] & reg_we & ~wr_err; assign fifo_rst_wd = reg_wdata[0]; // Read data return @@ -3340,10 +3375,14 @@ end addr_hit[6]: begin - reg_rdata_next[0] = region_cfg_regwen_qs; + reg_rdata_next[0] = scramble_en_qs; end addr_hit[7]: begin + reg_rdata_next[0] = region_cfg_regwen_qs; + end + + addr_hit[8]: begin reg_rdata_next[0] = mp_region_cfg0_en0_qs; reg_rdata_next[1] = mp_region_cfg0_rd_en0_qs; reg_rdata_next[2] = mp_region_cfg0_prog_en0_qs; @@ -3353,7 +3392,7 @@ reg_rdata_next[28] = mp_region_cfg0_partition0_qs; end - addr_hit[8]: begin + addr_hit[9]: begin reg_rdata_next[0] = mp_region_cfg1_en1_qs; reg_rdata_next[1] = mp_region_cfg1_rd_en1_qs; reg_rdata_next[2] = mp_region_cfg1_prog_en1_qs; @@ -3363,7 +3402,7 @@ reg_rdata_next[28] = mp_region_cfg1_partition1_qs; end - addr_hit[9]: begin + addr_hit[10]: begin reg_rdata_next[0] = mp_region_cfg2_en2_qs; reg_rdata_next[1] = mp_region_cfg2_rd_en2_qs; reg_rdata_next[2] = mp_region_cfg2_prog_en2_qs; @@ -3373,7 +3412,7 @@ reg_rdata_next[28] = mp_region_cfg2_partition2_qs; end - addr_hit[10]: begin + addr_hit[11]: begin reg_rdata_next[0] = mp_region_cfg3_en3_qs; reg_rdata_next[1] = mp_region_cfg3_rd_en3_qs; reg_rdata_next[2] = mp_region_cfg3_prog_en3_qs; @@ -3383,7 +3422,7 @@ reg_rdata_next[28] = mp_region_cfg3_partition3_qs; end - addr_hit[11]: begin + addr_hit[12]: begin reg_rdata_next[0] = mp_region_cfg4_en4_qs; reg_rdata_next[1] = mp_region_cfg4_rd_en4_qs; reg_rdata_next[2] = mp_region_cfg4_prog_en4_qs; @@ -3393,7 +3432,7 @@ reg_rdata_next[28] = mp_region_cfg4_partition4_qs; end - addr_hit[12]: begin + addr_hit[13]: begin reg_rdata_next[0] = mp_region_cfg5_en5_qs; reg_rdata_next[1] = mp_region_cfg5_rd_en5_qs; reg_rdata_next[2] = mp_region_cfg5_prog_en5_qs; @@ -3403,7 +3442,7 @@ reg_rdata_next[28] = mp_region_cfg5_partition5_qs; end - addr_hit[13]: begin + addr_hit[14]: begin reg_rdata_next[0] = mp_region_cfg6_en6_qs; reg_rdata_next[1] = mp_region_cfg6_rd_en6_qs; reg_rdata_next[2] = mp_region_cfg6_prog_en6_qs; @@ -3413,7 +3452,7 @@ reg_rdata_next[28] = mp_region_cfg6_partition6_qs; end - addr_hit[14]: begin + addr_hit[15]: begin reg_rdata_next[0] = mp_region_cfg7_en7_qs; reg_rdata_next[1] = mp_region_cfg7_rd_en7_qs; reg_rdata_next[2] = mp_region_cfg7_prog_en7_qs; @@ -3423,27 +3462,27 @@ reg_rdata_next[28] = mp_region_cfg7_partition7_qs; end - addr_hit[15]: begin + addr_hit[16]: begin reg_rdata_next[0] = default_region_rd_en_qs; reg_rdata_next[1] = default_region_prog_en_qs; reg_rdata_next[2] = default_region_erase_en_qs; end - addr_hit[16]: begin + addr_hit[17]: begin reg_rdata_next[0] = bank_cfg_regwen_qs; end - addr_hit[17]: begin + addr_hit[18]: begin reg_rdata_next[0] = mp_bank_cfg_erase_en0_qs; reg_rdata_next[1] = mp_bank_cfg_erase_en1_qs; end - addr_hit[18]: begin + addr_hit[19]: begin reg_rdata_next[0] = op_status_done_qs; reg_rdata_next[1] = op_status_err_qs; end - addr_hit[19]: begin + addr_hit[20]: begin reg_rdata_next[0] = status_rd_full_qs; reg_rdata_next[1] = status_rd_empty_qs; reg_rdata_next[2] = status_prog_full_qs; @@ -3453,16 +3492,16 @@ reg_rdata_next[17] = status_error_bank_qs; end - addr_hit[20]: begin + addr_hit[21]: begin reg_rdata_next[31:0] = scratch_qs; end - addr_hit[21]: begin + addr_hit[22]: begin reg_rdata_next[4:0] = fifo_lvl_prog_qs; reg_rdata_next[12:8] = fifo_lvl_rd_qs; end - addr_hit[22]: begin + addr_hit[23]: begin reg_rdata_next[0] = fifo_rst_qs; end
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 397e00a..a70be09 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -651,6 +651,15 @@ top_signame: flash_ctrl_flash index: -1 } + { + struct: otp_flash + type: uni + name: otp + act: rcv + package: flash_ctrl_pkg + inst_name: flash_ctrl + index: -1 + } ] } { @@ -3564,6 +3573,15 @@ index: -1 } { + struct: otp_flash + type: uni + name: otp + act: rcv + package: flash_ctrl_pkg + inst_name: flash_ctrl + index: -1 + } + { struct: lc_strap type: req_rsp name: lc_pinmux_strap
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index ec83816..52b8a3f 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -310,7 +310,7 @@ type: "req_rsp", name: "flash_ctrl", // flash_ctrl_i (req), flash_ctrl_o (rsp) act: "rsp", - } + }, ], }, ],
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index c23739f..5776264 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -619,6 +619,7 @@ // Inter-module signals .flash_o(flash_ctrl_flash_req), .flash_i(flash_ctrl_flash_rsp), + .otp_i(flash_ctrl_pkg::OTP_FLASH_DEFAULT), .clk_i (clkmgr_clocks.clk_main_infra), .rst_ni (rstmgr_resets.rst_lc_n) );