hw/ip/aes/dv/aes_base_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: aes

  // Top level dut name (sv module).
  dut: aes

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: xcelium

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:aes_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/aes/data/aes_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/aes/data/aes.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Enable C compilation of AES model for DPI-C
                "{proj_root}/hw/ip/aes/model/aes_model_sim_opts.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson"]
                // TODO: enable stress tests later.
                // "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: [ "aes_bind",
              "aes_cov_bind",
              "sec_cm_prim_sparse_fsm_flop_bind",
              "sec_cm_prim_onehot_check_bind",
              "aes_err_injection_bind"]


  xcelium_cov_refine_files: []

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Need to override the default output directory
  overrides: [
    {
      name: scratch_path
      value: "{scratch_base_path}/{name}_{variant}-{flow}-{tool}"
    }
    {
      name: rel_path
      value: "hw/ip/{name}_{variant}/dv"
    }
  ]

  build_modes: [
    {
      name: aes_unmasked
      build_opts: ["+define+EN_MASKING=0",
                   "+define+SBOX_IMPL=aes_pkg::SBoxImplCanright" ]
    }
    {
      name: aes_masked
        build_opts: ["+define+EN_MASKING=1",
                     "+define+SBOX_IMPL=aes_pkg::SBoxImplDom" ]
    }
  ]

  // Default UVM test and seq class name.
  uvm_test: aes_base_test
  uvm_test_seq: aes_wake_up_vseq

  // Update all builds to add options specific to AES C model compilation.
  en_build_modes: ["{tool}_aes_model_build_opts"]

  component_a: "uvm_test_top.env.scoreboard"
  id_a: _ALL_
  verbosity_a: UVM_MEDIUM
  phase_a: run
  run_modes: [
    {
      name: set_verbosity_comp_a_uvm_debug
      run_opts: ["+uvm_set_verbosity={component_a},{id_a},{verbosity_a},{phase_a}"]
    }
  ]

  run_opts: ["+uvm_set_verbosity={component_a},{id_a},{verbosity_a},{phase_a}"]

  // List of test specifications.
  tests: [
    {
      name: aes_wake_up
      uvm_test: aes_wake_up_test
      uvm_test_seq: aes_wake_up_vseq
      reseed: 1
    }
    {
      name: aes_nist_vectors
      uvm_test: aes_wake_up_test
      uvm_test_seq: aes_nist_vectors_vseq
      reseed: 1
    }
    {
      name: aes_smoke
      uvm_test: aes_smoke_test
      uvm_test_seq: aes_stress_vseq
    }
    {
      name: aes_config_error
      uvm_test: aes_config_error_test
      uvm_test_seq: aes_stress_vseq
    }
    {
      name: aes_stress
      uvm_test: aes_stress_test
      uvm_test_seq: aes_stress_vseq
    }
    {
      name: aes_b2b
      uvm_test: aes_b2b_test
      uvm_test_seq: aes_stress_vseq
    }
    {
      name: aes_clear
      uvm_test: aes_clear_test
      uvm_test_seq: aes_stress_vseq
    }
    {
      name: aes_alert_reset
      uvm_test: aes_alert_reset_test
      uvm_test_seq: aes_alert_reset_vseq
    }
    {
      name: aes_sideload
      uvm_test: aes_sideload_test
      uvm_test_seq: aes_stress_vseq
    }
    {
      name: aes_deinit
      uvm_test: aes_deinit_test
      uvm_test_seq: aes_deinit_vseq
    }
    {
      name: aes_man_cfg_err
      uvm_test: aes_manual_config_err_test
      uvm_test_seq: aes_manual_config_err_vseq
    }
    {
      name: aes_reseed
      uvm_test: aes_reseed_test
      uvm_test_seq: aes_reseed_vseq
    }
    {
      name: aes_fi
      uvm_test: aes_alert_reset_test
      uvm_test_seq: aes_fi_vseq
    }
    {
      name: aes_control_fi
      uvm_test: aes_fi_test
      uvm_test_seq: aes_control_fi_vseq
      reseed: 300 // Test must cover 150 bins. Overseed by 2x to get reasonable coverage.
      run_timeout_mins: 1 // Short test; if not done within 1 min, something's wrong.
    }
    {
      name: aes_cipher_fi
      uvm_test: aes_fi_test
      uvm_test_seq: aes_cipher_fi_vseq
      reseed: 350 // Test must cover 175 bins. Overseed by 2x to get reasonable coverage.
      run_timeout_mins: 1 // Short test; if not done within 1 min, something's wrong.
    }
    {
      name: aes_ctr_fi
      uvm_test: aes_fi_test
      uvm_test_seq: aes_ctr_fi_vseq
      run_timeout_mins: 1 // Short test; if not done within 1 min, something's wrong.
    }
    {
      name: aes_core_fi
      uvm_test: aes_fi_test
      uvm_test_seq: aes_core_fi_vseq
      reseed: 70 // Test must cover 35 bins. Overseed by 2x to get reasonable coverage.
    }
    {
      name: aes_readability
      uvm_test: aes_fi_test
      uvm_test_seq: aes_readability_vseq
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["aes_smoke"]
    }
    {
      name: failure
      tests: ["aes_config_error", "aes_alert_reset"]
    }
    {
      name: stress
      tests: ["aes_stress","aes_b2b", "aes_clear", "aes_config_error", "aes_smoke",
              "aes_alert_reset"]
    }
  ]
}