hw/dv/tools/dvsim/testplans/csr_testplan.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  testpoints: [
    {
      name: csr_hw_reset
      desc: '''
            Verify the reset values as indicated in the RAL specification.
            - Write all CSRs with a random value.
            - Apply reset to the DUT as well as the RAL model.
            - Read each CSR and compare it against the reset value.
              it is mandatory to replicate this test for each reset that affects
              all or a subset of the CSRs.
            - It is mandatory to run this test for all available interfaces the
              CSRs are accessible from.
            - Shuffle the list of CSRs first to remove the effect of ordering.
            '''
      stage: V1
      tests: ["{name}{intf}_csr_hw_reset"]
    }
    {
      name: csr_rw
      desc: '''
            Verify accessibility of CSRs as indicated in the RAL specification.
            - Loop through each CSR to write it with a random value.
            - Read the CSR back and check for correctness while adhering to its
              access policies.
            - It is mandatory to run this test for all available interfaces the
              CSRs are accessible from.
            - Shuffle the list of CSRs first to remove the effect of ordering.
            '''
      stage: V1
      tests: ["{name}{intf}_csr_rw"]
    }
    {
      name: csr_bit_bash
      desc: '''
            Verify no aliasing within individual bits of a CSR.
            - Walk a 1 through each CSR by flipping 1 bit at a time.
            - Read the CSR back and check for correctness while adhering to its
              access policies.
            - This verify that writing a specific bit within the CSR did not affect
              any of the other bits.
            - It is mandatory to run this test for all available interfaces the
              CSRs are accessible from.
            - Shuffle the list of CSRs first to remove the effect of ordering.
            '''
      stage: V1
      tests: ["{name}{intf}_csr_bit_bash"]
    }
    {
      name: csr_aliasing
      desc: '''
            Verify no aliasing within the CSR address space.
            - Loop through each CSR to write it with a random value
            - Shuffle and read ALL CSRs back.
            - All CSRs except for the one that was written in this iteration should
              read back the previous value.
            - The CSR that was written in this iteration is checked for correctness
              while adhering to its access policies.
            - It is mandatory to run this test for all available interfaces the
              CSRs are accessible from.
            - Shuffle the list of CSRs first to remove the effect of ordering.
            '''
      stage: V1
      tests: ["{name}{intf}_csr_aliasing"]
    }
    {
      name: csr_mem_rw_with_rand_reset
      desc: '''
            Verify random reset during CSR/memory access.
            - Run csr_rw sequence to randomly access CSRs
            - If memory exists, run mem_partial_access in parallel with csr_rw
            - Randomly issue reset and then use hw_reset sequence to check all CSRs
              are reset to default value
            - It is mandatory to run this test for all available interfaces the
              CSRs are accessible from.
            '''
      stage: V1
      tests: ["{name}{intf}_csr_mem_rw_with_rand_reset"]
    }
    {
      name: regwen_csr_and_corresponding_lockable_csr
      desc: '''
            Verify regwen CSR and its corresponding lockable CSRs.
            - Randomly access all CSRs
            - Test when regwen CSR is set, its corresponding lockable CSRs become
              read-only registers

            Note:
            - If regwen CSR is HW read-only, this feature can be fully tested by common
              CSR tests - csr_rw and csr_aliasing.
            - If regwen CSR is HW updated, a separate test should be created to test it.

            This is only applicable if the block contains regwen and locakable CSRs.
            '''
      stage: V1
      tests: ["{name}{intf}_csr_rw", "{name}{intf}_csr_aliasing"]
    }
  ]
  covergroups: [
    {
      name: regwen_val_when_new_value_written_cg
      desc: '''
            Cover each lockable reg field with these 2 cases:
            - When regwen = 1, a different value is written to the lockable CSR field, and a read
              occurs after that.
            - When regwen = 0, a different value is written to the lockable CSR field, and a read
              occurs after that.

            This is only applicable if the block contains regwen and locakable CSRs.
            '''
    }
  ]
}