| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Generated UNR file from Synopsys UNR tool with D2S rstmgr_cnsty_chk module |
| // excluded. |
| // This needs to be reviewed with designer: |
| // TODO(https://github.com/lowRISC/opentitan/issues/10694) |
| // |
| //================================================== |
| // This file contains the Excluded objects |
| // Generated By User: maturana |
| // Format Version: 2 |
| // Date: Tue Feb 8 12:30:32 2022 |
| // ExclMode: default |
| //================================================== |
| CHECKSUM: "4136145515 674809128" |
| INSTANCE: tb.dut |
| ANNOTATION: "VC_COV_UNR" |
| Condition 2 "856994301" "(reg_intg_err || ((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs)) || ((|fsm_errs)) || ((|shadow_fsm_errs))) 1 -1" (2 "00001") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 2 "856994301" "(reg_intg_err || ((|cnsty_chk_errs)) || ((|shadow_cnsty_chk_errs)) || ((|fsm_errs)) || ((|shadow_fsm_errs))) 1 -1" (3 "00010") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_por |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_por_io |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_por_io_div2 |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_por_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_por_usb |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_d0_lc |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_d0_lc_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_lc_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_d0_lc_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_lc_io_div4_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_d0_lc_io_div4_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_lc_aon |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_d0_sys |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_d0_sys_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_sys_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_d0_sys_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_daon_sys_aon |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1359147661" |
| INSTANCE: tb.dut.u_d0_sys_aon |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (2 "10") |
| ANNOTATION: "VC_COV_UNR" |
| Condition 1 "2362817788" "(sw_rst_req_q && clr_sw_rst_req) 1 -1" (3 "11") |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_por |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_por_io |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_por_io_div2 |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_por_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_por_usb |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_lc_io_div4_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_d0_lc |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_d0_lc_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_lc_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_d0_lc_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_d0_lc_io_div4_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_lc_aon |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_d0_sys |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_d0_sys_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_sys_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_d0_sys_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_daon_sys_aon |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "3435455202 1666455474" |
| INSTANCE: tb.dut.u_d0_sys_aon |
| ANNOTATION: "VC_COV_UNR" |
| Block 4 "762045522" "sw_rst_req_q <= '0;" |
| CHECKSUM: "4136145515 4124731032" |
| INSTANCE: tb.dut |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_i2c1_n [0] "logic resets_o.rst_i2c1_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_i2c1_n [0] "logic resets_o.rst_i2c1_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_i2c0_n [0] "logic resets_o.rst_i2c0_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_i2c0_n [0] "logic resets_o.rst_i2c0_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_usb_n [0] "logic resets_o.rst_usb_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_usb_n [0] "logic resets_o.rst_usb_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_spi_host1_n [0] "logic resets_o.rst_spi_host1_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_spi_host1_n [0] "logic resets_o.rst_spi_host1_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_spi_host0_n [0] "logic resets_o.rst_spi_host0_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_spi_host0_n [0] "logic resets_o.rst_spi_host0_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_spi_device_n [0] "logic resets_o.rst_spi_device_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_spi_device_n [0] "logic resets_o.rst_spi_device_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_sys_n [0] "logic resets_o.rst_sys_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_sys_n [0] "logic resets_o.rst_sys_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_sys_shadowed_n [0] "logic resets_o.rst_sys_shadowed_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_sys_shadowed_n [0] "logic resets_o.rst_sys_shadowed_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_lc_aon_n [1] "logic resets_o.rst_lc_aon_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_lc_aon_n [1] "logic resets_o.rst_lc_aon_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_lc_n [0] "logic resets_o.rst_lc_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_lc_n [0] "logic resets_o.rst_lc_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_lc_shadowed_n [0] "logic resets_o.rst_lc_shadowed_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_lc_shadowed_n [0] "logic resets_o.rst_lc_shadowed_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_por_usb_n [1] "logic resets_o.rst_por_usb_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_por_usb_n [1] "logic resets_o.rst_por_usb_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_por_io_div4_n [1] "logic resets_o.rst_por_io_div4_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_por_io_div4_n [1] "logic resets_o.rst_por_io_div4_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_por_io_div2_n [1] "logic resets_o.rst_por_io_div2_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_por_io_div2_n [1] "logic resets_o.rst_por_io_div2_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_por_io_n [1] "logic resets_o.rst_por_io_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_por_io_n [1] "logic resets_o.rst_por_io_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 0to1 resets_o.rst_por_n [1] "logic resets_o.rst_por_n[1:0]" |
| ANNOTATION: "VC_COV_UNR" |
| Toggle 1to0 resets_o.rst_por_n [1] "logic resets_o.rst_por_n[1:0]" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_por |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_por_io |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_por_io_div2 |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_por_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_por_usb |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_d0_lc |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_d0_lc_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_lc_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_d0_lc_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_lc_io_div4_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_d0_lc_io_div4_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_lc_aon |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_d0_sys |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_d0_sys_shadowed |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_sys_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_d0_sys_io_div4 |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_daon_sys_aon |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |
| CHECKSUM: "3435455202 1292564160" |
| INSTANCE: tb.dut.u_d0_sys_aon |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (1) "(!rst_ni) 0,1,-" |
| ANNOTATION: "VC_COV_UNR" |
| Branch 0 "3488500852" "(!rst_ni)" (2) "(!rst_ni) 0,0,1" |