hw/ip/pwrmgr/dv/pwrmgr_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: pwrmgr

  // Top level dut name (sv module).
  dut: pwrmgr

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:pwrmgr_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/pwrmgr/data/pwrmgr_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson"

  // Import additional common sim cfg files.
  // TODO: remove imported cfgs that do not apply.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]

  // Overrides
  overrides: [
    {
      name: design_level
      value: "top"
    }
  ]

  // Add additional tops for simulation.
  sim_tops: ["pwrmgr_bind",
             "pwrmgr_rstmgr_bind",
             "pwrmgr_cov_bind",
             "sec_cm_prim_count_bind",
             "sec_cm_prim_sparse_fsm_flop_bind",
             "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: pwrmgr_base_test
  uvm_test_seq: pwrmgr_base_vseq

  // List of test specifications.
  tests: [
    {
      name: pwrmgr_smoke
      uvm_test_seq: pwrmgr_smoke_vseq
      run_opts: ["+test_timeout_ns=1000000"]
    }
    {
      name: pwrmgr_reset
      uvm_test_seq: pwrmgr_reset_vseq
      run_opts: ["+test_timeout_ns=1000000"]
    }
    {
      name: pwrmgr_lowpower_wakeup_race
      uvm_test_seq: pwrmgr_lowpower_wakeup_race_vseq
      run_opts: ["+test_timeout_ns=1000000"]
    }
    {
      name: pwrmgr_wakeup
      uvm_test_seq: pwrmgr_wakeup_vseq
      run_opts: ["+test_timeout_ns=1000000"]
    }
    {
      name: pwrmgr_wakeup_reset
      uvm_test_seq: pwrmgr_wakeup_reset_vseq
      run_opts: ["+test_timeout_ns=1000000"]
    }
    {
      name: pwrmgr_aborted_low_power
      uvm_test_seq: pwrmgr_aborted_low_power_vseq
    }
    {
      name: pwrmgr_sec_cm_lc_ctrl_intersig_mubi
      uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq
      run_opts: ["+test_timeout_ns=2000000", "+pwrmgr_mubi_mode=PwrmgrMubiLcCtrl"]
    }
    {
      name: pwrmgr_sec_cm_rom_ctrl_intersig_mubi
      uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq
      run_opts: ["+test_timeout_ns=2000000", "+pwrmgr_mubi_mode=PwrmgrMubiRomCtrl"]
    }
    {
      name: pwrmgr_sec_cm_rstmgr_intersig_mubi
      uvm_test_seq: pwrmgr_sw_reset_vseq
      run_opts: ["+test_timeout_ns=1000000"]
    }
    {
      name: pwrmgr_esc_clk_rst_malfunc
      uvm_test_seq: pwrmgr_esc_clk_rst_malfunc_vseq
      run_opts: ["+test_timeout_ns=1000000"]
    }
    {
      name: pwrmgr_sec_cm_ctrl_config_regwen
      uvm_test_seq: pwrmgr_sec_cm_ctrl_config_regwen_vseq
      run_opts: ["+test_timeout_ns=50000000"]
    }
    {
      name: pwrmgr_global_esc
      uvm_test_seq: pwrmgr_global_esc_vseq
      run_opts: ["+test_timeout_ns=1000000000"]
    }
    {
      name: pwrmgr_glitch
      uvm_test_seq: pwrmgr_glitch_vseq
      run_opts: ["+test_timeout_ns=1000000"]
    }
    // TODO: add more tests here
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["pwrmgr_smoke"]
    }
  ]
}