| commit | a39042ab5e01eccc7fc21bf86a347e29ff1496bc | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Fri Jul 31 14:35:13 2020 -0700 |
| committer | Eunchan Kim <eunchan@opentitan.org> | Thu Aug 06 18:44:01 2020 -0700 |
| tree | 3ef78a1b9e304c94b6d7e3c0be037db27c78196a | |
| parent | ea90aace618ee9607cb2f89b19e38fa3a684d70a [diff] |
[reggen] Add bus port to `inter_signal_list` Make bus_device, bus_host to be inter-module signal. reggen, when it reads the comportable IP hjson, adds entries to inter_signal_list if bus port exists in the IP hjson. This commit itself breaks the top level stuff. `topgen` and `tlgen` should be modified to support this. This commit is related to Issue #3031 Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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