)]}'
{
  "commit": "a39042ab5e01eccc7fc21bf86a347e29ff1496bc",
  "tree": "3ef78a1b9e304c94b6d7e3c0be037db27c78196a",
  "parents": [
    "ea90aace618ee9607cb2f89b19e38fa3a684d70a"
  ],
  "author": {
    "name": "Eunchan Kim",
    "email": "eunchan@opentitan.org",
    "time": "Fri Jul 31 14:35:13 2020 -0700"
  },
  "committer": {
    "name": "Eunchan Kim",
    "email": "eunchan@opentitan.org",
    "time": "Thu Aug 06 18:44:01 2020 -0700"
  },
  "message": "[reggen] Add bus port to `inter_signal_list`\n\nMake bus_device, bus_host to be inter-module signal. reggen, when it\nreads the comportable IP hjson, adds entries to inter_signal_list if bus\nport exists in the IP hjson.\n\nThis commit itself breaks the top level stuff. `topgen` and `tlgen`\nshould be modified to support this.\n\nThis commit is related to Issue #3031\n\nSigned-off-by: Eunchan Kim \u003ceunchan@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cc9fbc774aa5aa86874ec22ab4300228b64725cc",
      "old_mode": 33188,
      "old_path": "util/reggen/validate.py",
      "new_id": "a3978d0c5d3016cfb674cd6a1d46c874ded5c9c3",
      "new_mode": 33188,
      "new_path": "util/reggen/validate.py"
    }
  ]
}