[cw310] Break out all HW/SW straps and connect to SAM3X
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 1583800..1910b70 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -12311,16 +12311,18 @@
OTP_EXT_VOLT
FLASH_TEST_MODE0
FLASH_TEST_MODE1
+ IOB3
+ IOB6
+ IOB7
+ IOB8
+ IOB9
IOB10
IOB11
IOB12
- IOC0
- IOC1
IOC12
IOR1
IOR2
IOR3
- IOR4
IOR5
IOR6
IOR7
@@ -12434,27 +12436,27 @@
[
{
name: tap0
- pad: IOC0
- desc: TAP strap signal, maps to a stubbed-off MIO.
- idx: 22
+ pad: IOC8
+ desc: TAP strap signal.
+ idx: 30
}
{
name: tap1
- pad: IOB7
- desc: TAP strap signal, maps to MIO pad 16.
- idx: 16
+ pad: IOC5
+ desc: TAP strap signal.
+ idx: 27
}
{
name: dft0
- pad: IOC1
- desc: DFT strap signal, maps to a stubbed-off MIO.
- idx: 23
+ pad: IOC3
+ desc: DFT strap signal.
+ idx: 25
}
{
name: dft1
- pad: IOC12
- desc: DFT strap signal, maps to a stubbed-off MIO.
- idx: 34
+ pad: IOC4
+ desc: DFT strap signal.
+ idx: 26
}
{
name: tck
@@ -12470,9 +12472,9 @@
}
{
name: trst_n
- pad: IOB9
- desc: JTAG trst_n signal, maps to MIO pad 18.
- idx: 18
+ pad: IOR4
+ desc: JTAG trst_n signal.
+ idx: 39
}
{
name: tdi
diff --git a/hw/top_earlgrey/data/pins_cw310.xdc b/hw/top_earlgrey/data/pins_cw310.xdc
index 915a701..b4c963e 100644
--- a/hw/top_earlgrey/data/pins_cw310.xdc
+++ b/hw/top_earlgrey/data/pins_cw310.xdc
@@ -21,37 +21,44 @@
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IO_SDCK_IBUF]; # SDCK clock to be ignored
## LEDs
-set_property -dict { PACKAGE_PIN M26 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA8 }]; #LED 0
-set_property -dict { PACKAGE_PIN M25 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB0 }]; #LED 1
-set_property -dict { PACKAGE_PIN M24 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB1 }]; #LED 2
-set_property -dict { PACKAGE_PIN M19 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB2 }]; #LED 3
-set_property -dict { PACKAGE_PIN L25 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB3 }]; #LED 4
-set_property -dict { PACKAGE_PIN K26 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB4 }]; #LED 5
-set_property -dict { PACKAGE_PIN L24 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB5 }]; #LED 6
-set_property -dict { PACKAGE_PIN K25 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB6 }]; #LED 7
+set_property -dict { PACKAGE_PIN M26 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA0 }]; #LED 0
+set_property -dict { PACKAGE_PIN M25 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA1 }]; #LED 1
+set_property -dict { PACKAGE_PIN M24 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA2 }]; #LED 2
+set_property -dict { PACKAGE_PIN M19 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA3 }]; #LED 3
+set_property -dict { PACKAGE_PIN L25 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA4 }]; #LED 4
+set_property -dict { PACKAGE_PIN K26 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA5 }]; #LED 5
+set_property -dict { PACKAGE_PIN L24 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA6 }]; #LED 6
+set_property -dict { PACKAGE_PIN K25 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOA7 }]; #LED 7
## Buttons
set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS18 } [get_ports { POR_N }]; #pushbutton SW2
## Switches
-set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVCMOS18 } [get_ports { IOA0 }]; #USRDIP0
-set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS18 } [get_ports { IOA1 }]; #USRDIP1
-set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS18 } [get_ports { IOA2 }]; #USRDIP2
-set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS18 } [get_ports { IOA3 }]; #USRDIP3
-set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVCMOS18 } [get_ports { IOA4 }]; #USRDIP4
-set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS18 } [get_ports { IOA5 }]; #USRDIP5
-set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS18 } [get_ports { IOA6 }]; #USRDIP6
-set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS18 } [get_ports { IOA7 }]; #USRDIP7
+set_property -dict { PACKAGE_PIN U9 IOSTANDARD LVCMOS18 } [get_ports { IOA8 }]; #USRDIP0
+set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS18 } [get_ports { IOB0 }]; #USRDIP1
+set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS18 } [get_ports { IOB1 }]; #USRDIP2
+set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS18 } [get_ports { IOB2 }]; #USRDIP3
+#set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVCMOS18 } [get_ports { }]; #USRDIP4
+#set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS18 } [get_ports { }]; #USRDIP5
+#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS18 } [get_ports { }]; #USRDIP6
+#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS18 } [get_ports { }]; #USRDIP7
-## SPI/JTAG
+## SPI / JTAG (part of it, other JTAG signals further below)
set_property -dict { PACKAGE_PIN D26 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CLK }]; #SCK (SPI1_SCK)
set_property -dict { PACKAGE_PIN A24 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D0 }]; #SDI (SPI1_COPI)
set_property -dict { PACKAGE_PIN A22 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D1 }]; #SDO (SPI1_CIPO)
set_property -dict { PACKAGE_PIN C26 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CS_L }]; #CSB (SPI1_CS)
-set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 } [get_ports { IOB9 }]; #JTAG TRST (USB_A17) #SAM3X
-set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_JSRST_N }]; #JTAG SRST (USB_A18)
-set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB7 }]; #JTAG/SPI (USB_A19)
-set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB8 }]; #Bootstrap (USB_A16)
+
+# JTAG (second part)
+set_property -dict { PACKAGE_PIN U24 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IOR4 }]; #USB_A13 (SAM3X)
+set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_JSRST_N }]; #USB_A14 (SAM3X)
+# SW Straps
+set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOC0 }]; #USB_A15 (SAM3X)
+set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOC1 }]; #USB_A16 (SAM3X)
+set_property -dict { PACKAGE_PIN V21 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOC2 }]; #USB_A17 (SAM3X)
+# TAP Straps
+set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOC8 }]; #USB_A18 (SAM3X)
+set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOC5 }]; #USB_A19 (SAM3X)
## SPI HOST
set_property -dict { PACKAGE_PIN AF8 IOSTANDARD LVCMOS18 } [get_ports { SPI_HOST_CLK }]; #SCK (USR_SPI0CLK)
@@ -62,18 +69,18 @@
set_property -dict { PACKAGE_PIN AE11 IOSTANDARD LVCMOS18 } [get_ports { SPI_HOST_CS_L }]; #CSB (USR_SPI0CS)
## OTHER IO
-set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { IOC2 }]; #USERIOB-9
-set_property -dict { PACKAGE_PIN E10 IOSTANDARD LVCMOS33 } [get_ports { IOC5 }]; #USERIOB-14
+#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { }]; #USERIOB-9
+#set_property -dict { PACKAGE_PIN E10 IOSTANDARD LVCMOS33 } [get_ports { }]; #USERIOB-14
set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { IOC6 }]; #USERIOB-16
set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { IOC7 }]; #USERIOB-18
-#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { IOC8 }]; #USERIOB-24
-#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { IOC9 }]; #USERIOB-26
+#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { }]; #USERIOB-24
+set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { IOC9 }]; #USERIOB-26
set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { IOC10 }]; #USERIOB-11
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { IOC11 }]; #USERIOB-15
## ChipWhisperer 20-Pin Connector (J14)
-set_property -dict { PACKAGE_PIN AF25 IOSTANDARD LVCMOS33 } [get_ports { IOC9 }]; #J14 PIN 12 CWIO_IO2 - OpenTitan UART1 TX
-set_property -dict { PACKAGE_PIN AE25 IOSTANDARD LVCMOS33 } [get_ports { IOC8 }]; #J14 PIN 10 CWIO_IO1 - OpenTitan UART1 RX
+set_property -dict { PACKAGE_PIN AF25 IOSTANDARD LVCMOS33 } [get_ports { IOB5 }]; #J14 PIN 12 CWIO_IO2 - OpenTitan UART1 TX
+set_property -dict { PACKAGE_PIN AE25 IOSTANDARD LVCMOS33 } [get_ports { IOB4 }]; #J14 PIN 10 CWIO_IO1 - OpenTitan UART1 RX
set_property -dict { PACKAGE_PIN AF24 IOSTANDARD LVCMOS33 } [get_ports { IO_TRIGGER }]; #J14 PIN 16 CWIO_IO4 - Capture Trigger
set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { IO_CLKOUT }]; #J14 PIN 4 CWIO_HS1 - Target clock
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 995a6d7..4a5cee2 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -1378,9 +1378,9 @@
'SPI_DEV_D2', 'SPI_DEV_D3'
'FLASH_TEST_VOLT', 'OTP_EXT_VOLT'
'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1',
- 'IOB10', 'IOB11', 'IOB12',
- 'IOC0', 'IOC1', 'IOC12',
- 'IOR1', 'IOR2', 'IOR3', 'IOR4', 'IOR5', 'IOR6', 'IOR7', 'IOR8', 'IOR9', 'IOR10', 'IOR11', 'IOR12', 'IOR13',
+ 'IOB3', 'IOB6', 'IOB7', 'IOB8', 'IOB9', 'IOB10', 'IOB11', 'IOB12',
+ 'IOC12',
+ 'IOR1', 'IOR2', 'IOR3', 'IOR5', 'IOR6', 'IOR7', 'IOR8', 'IOR9', 'IOR10', 'IOR11', 'IOR12', 'IOR13',
'USB_P', 'USB_N'
],
@@ -1407,14 +1407,14 @@
pinmux: {
special_signals: [
// Straps
- { name: 'tap0', pad: 'IOC0' , desc: 'TAP strap signal, maps to a stubbed-off MIO.' },
- { name: 'tap1', pad: 'IOB7', desc: 'TAP strap signal, maps to MIO pad 16.' },
- { name: 'dft0', pad: 'IOC1' , desc: 'DFT strap signal, maps to a stubbed-off MIO.' },
- { name: 'dft1', pad: 'IOC12', desc: 'DFT strap signal, maps to a stubbed-off MIO.' },
+ { name: 'tap0', pad: 'IOC8', desc: 'TAP strap signal.' },
+ { name: 'tap1', pad: 'IOC5', desc: 'TAP strap signal.' },
+ { name: 'dft0', pad: 'IOC3', desc: 'DFT strap signal.' },
+ { name: 'dft1', pad: 'IOC4', desc: 'DFT strap signal.' },
// JTAG
{ name: 'tck', pad: 'SPI_DEV_CLK' , desc: 'JTAG tck signal, overlaid on SPI_DEV.' },
{ name: 'tms', pad: 'SPI_DEV_CS_L', desc: 'JTAG tms signal, overlaid on SPI_DEV.' },
- { name: 'trst_n', pad: 'IOB9' , desc: 'JTAG trst_n signal, maps to MIO pad 18.' },
+ { name: 'trst_n', pad: 'IOR4', desc: 'JTAG trst_n signal.' },
{ name: 'tdi', pad: 'SPI_DEV_D0' , desc: 'JTAG tdi signal, overlaid on SPI_DEV.' },
{ name: 'tdo', pad: 'SPI_DEV_D1' , desc: 'JTAG tdo signal, overlaid on SPI_DEV.' },
],
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index d5451f9..9f607d6 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -83,7 +83,7 @@
// TODO: Replace with correct interfaces once
// pinmux/padring and pinout have been updated.
- wire [25:0] tie_off;
+ wire [16:0] tie_off;
wire [5:0] spi_host_tie_off;
wire [1:0] spi_dev_tie_off;
assign (weak0, weak1) tie_off = '0;
@@ -150,29 +150,27 @@
.IOB0(gpio_pins[9]), // MIO 9
.IOB1(gpio_pins[10]), // MIO 10
.IOB2(gpio_pins[11]), // MIO 11
- .IOB3(gpio_pins[12]), // MIO 12
- .IOB4(gpio_pins[13]), // MIO 13
- .IOB5(gpio_pins[14]), // MIO 14
- .IOB6(gpio_pins[15]), // MIO 15
+ .IOB3(tie_off[0]), // MIO 12
+ .IOB4(uart_rx[1]), // MIO 13
+ .IOB5(uart_tx[1]), // MIO 14
+ .IOB6(tie_off[1]), // MIO 15
.IOB7(iob7), // MIO 16
- // TODO, we probably need to change this when we have the final pinout configuration
- // Connect this to IOB8 to align with SW bootstrap.c
- .IOB8(sw_straps[0]), // MIO 17
- .IOB9(tie_off[1]), // MIO 18
+ .IOB8(tie_off[2]), // MIO 17
+ .IOB9(tie_off[3]), // MIO 18
.IOB10(iob10), // MIO 19
.IOB11(iob11), // MIO 20
.IOB12(iob12), // MIO 21
// Bank C (VCC domain)
- .IOC0(tie_off[5]), // MIO 22
+ .IOC0(sw_straps[0]), // MIO 22
.IOC1(sw_straps[1]), // MIO 23
.IOC2(sw_straps[2]), // MIO 24
.IOC3(ioc3), // MIO 25
.IOC4(ioc4), // MIO 26
.IOC5(tap_straps[1]), // MIO 27
.IOC6(clk), // MIO 28 - external clock fed in at a fixed position
- .IOC7(tie_off[7]), // MIO 29
+ .IOC7(tie_off[4]), // MIO 29
.IOC8(tap_straps[0]), // MIO 30
- .IOC9(tie_off[8]), // MIO 31
+ .IOC9(tie_off[5]), // MIO 31
.IOC10(ioc10), // MIO 32
.IOC11(ioc11), // MIO 33
.IOC12(ioc12), // MIO 34
@@ -182,29 +180,29 @@
.IOR2(jtag_tdi), // MIO 37
.IOR3(jtag_tck), // MIO 38
.IOR4(jtag_trst_n), // MIO 39
- .IOR5(uart_rx[1]), // MIO 40
- .IOR6(uart_tx[1]), // MIO 41
+ .IOR5(tie_off[6]), // MIO 40
+ .IOR6(tie_off[7]), // MIO 41
.IOR7(uart_rx[2]), // MIO 42
- .IOR8(tie_off[13]), // MIO 43, Dedicated sysrst_ctrl output (ec_rst_l)
- .IOR9(tie_off[14]), // MIO 44, Dedicated sysrst_ctrl output (pwrb_out)
+ .IOR8(tie_off[8]), // MIO 43, Dedicated sysrst_ctrl output (ec_rst_l)
+ .IOR9(tie_off[9]), // MIO 44, Dedicated sysrst_ctrl output (pwrb_out)
.IOR10(uart_tx[2]), // MIO 45
.IOR11(uart_rx[3]), // MIO 46
.IOR12(uart_tx[3]), // MIO 47
.IOR13(ior13), // MIO 48
// DCD (VCC domain)
- .CC1(tie_off[19]),
- .CC2(tie_off[20]),
+ .CC1(tie_off[10]),
+ .CC2(tie_off[11]),
// USB (VCC domain)
.USB_P(usb_dp0),
.USB_N(usb_dn0),
// FLASH
- .FLASH_TEST_MODE0(tie_off[21]),
- .FLASH_TEST_MODE1(tie_off[22]),
- .FLASH_TEST_VOLT(tie_off[23]),
+ .FLASH_TEST_MODE0(tie_off[12]),
+ .FLASH_TEST_MODE1(tie_off[13]),
+ .FLASH_TEST_VOLT(tie_off[14]),
// OTP
- .OTP_EXT_VOLT(tie_off[24]),
+ .OTP_EXT_VOLT(tie_off[15]),
// MISC pad
- .AST_MISC(tie_off[25])
+ .AST_MISC(tie_off[16])
);
// connect signals
diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md
index a28a368..7179441 100644
--- a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md
+++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md
@@ -192,4 +192,4 @@
| <p style="font-size:smaller">sysrst_ctrl_aon_key1_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonKey1Out / -</p> | <p style="font-size:smaller"></p> |
| <p style="font-size:smaller">sysrst_ctrl_aon_key2_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonKey2Out / -</p> | <p style="font-size:smaller"></p> |
| <p style="font-size:smaller">sysrst_ctrl_aon_pwrb_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonPwrbOut / -</p> | <p style="font-size:smaller"></p> |
-| <p style="font-size:smaller">sysrst_ctrl_aon_z3_wakeup</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonZ3Wakeup / -</p> | <p style="font-size:smaller"></p> |
\ No newline at end of file
+| <p style="font-size:smaller">sysrst_ctrl_aon_z3_wakeup</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonZ3Wakeup / -</p> | <p style="font-size:smaller"></p> |
diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md
index 67fd6b4..3ed1b7b 100644
--- a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md
+++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md
@@ -35,24 +35,22 @@
| <p style="font-size:smaller">IOB0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob0 / kTopEarlgreyPinmuxMioOutIob0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
| <p style="font-size:smaller">IOB1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob1 / kTopEarlgreyPinmuxMioOutIob1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
| <p style="font-size:smaller">IOB2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob2 / kTopEarlgreyPinmuxMioOutIob2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
-| <p style="font-size:smaller">IOB3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob3 / kTopEarlgreyPinmuxMioOutIob3</p> | <p style="font-size:smaller">Muxed IO pad</p> |
| <p style="font-size:smaller">IOB4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob4 / kTopEarlgreyPinmuxMioOutIob4</p> | <p style="font-size:smaller">Muxed IO pad</p> |
| <p style="font-size:smaller">IOB5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob5 / kTopEarlgreyPinmuxMioOutIob5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
-| <p style="font-size:smaller">IOB6</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob6 / kTopEarlgreyPinmuxMioOutIob6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
-| <p style="font-size:smaller">IOB7</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tap1</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob7 / kTopEarlgreyPinmuxMioOutIob7</p> | <p style="font-size:smaller">Muxed IO pad / TAP strap signal, maps to MIO pad 16.</p> |
-| <p style="font-size:smaller">IOB8</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob8 / kTopEarlgreyPinmuxMioOutIob8</p> | <p style="font-size:smaller">Muxed IO pad</p> |
-| <p style="font-size:smaller">IOB9</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VIOB</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">trst_n</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIob9 / kTopEarlgreyPinmuxMioOutIob9</p> | <p style="font-size:smaller">Muxed IO pad / JTAG trst_n signal, maps to MIO pad 18.</p> |
+| <p style="font-size:smaller">IOC0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc0 / kTopEarlgreyPinmuxMioOutIoc0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC1</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc1 / kTopEarlgreyPinmuxMioOutIoc1</p> | <p style="font-size:smaller">Muxed IO pad</p> |
| <p style="font-size:smaller">IOC2</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc2 / kTopEarlgreyPinmuxMioOutIoc2</p> | <p style="font-size:smaller">Muxed IO pad</p> |
-| <p style="font-size:smaller">IOC3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc3 / kTopEarlgreyPinmuxMioOutIoc3</p> | <p style="font-size:smaller">Muxed IO pad</p> |
-| <p style="font-size:smaller">IOC4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc4 / kTopEarlgreyPinmuxMioOutIoc4</p> | <p style="font-size:smaller">Muxed IO pad</p> |
-| <p style="font-size:smaller">IOC5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc5 / kTopEarlgreyPinmuxMioOutIoc5</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC3</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">dft0</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc3 / kTopEarlgreyPinmuxMioOutIoc3</p> | <p style="font-size:smaller">Muxed IO pad / DFT strap signal.</p> |
+| <p style="font-size:smaller">IOC4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">dft1</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc4 / kTopEarlgreyPinmuxMioOutIoc4</p> | <p style="font-size:smaller">Muxed IO pad / DFT strap signal.</p> |
+| <p style="font-size:smaller">IOC5</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tap1</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc5 / kTopEarlgreyPinmuxMioOutIoc5</p> | <p style="font-size:smaller">Muxed IO pad / TAP strap signal.</p> |
| <p style="font-size:smaller">IOC6</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc6 / kTopEarlgreyPinmuxMioOutIoc6</p> | <p style="font-size:smaller">Muxed IO pad</p> |
| <p style="font-size:smaller">IOC7</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc7 / kTopEarlgreyPinmuxMioOutIoc7</p> | <p style="font-size:smaller">Muxed IO pad</p> |
-| <p style="font-size:smaller">IOC8</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc8 / kTopEarlgreyPinmuxMioOutIoc8</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOC8</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">tap0</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc8 / kTopEarlgreyPinmuxMioOutIoc8</p> | <p style="font-size:smaller">Muxed IO pad / TAP strap signal.</p> |
| <p style="font-size:smaller">IOC9</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc9 / kTopEarlgreyPinmuxMioOutIoc9</p> | <p style="font-size:smaller">Muxed IO pad</p> |
| <p style="font-size:smaller">IOC10</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc10 / kTopEarlgreyPinmuxMioOutIoc10</p> | <p style="font-size:smaller">Muxed IO pad</p> |
| <p style="font-size:smaller">IOC11</p> | <p style="font-size:smaller">BidirOd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIoc11 / kTopEarlgreyPinmuxMioOutIoc11</p> | <p style="font-size:smaller">Muxed IO pad</p> |
| <p style="font-size:smaller">IOR0</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIor0 / kTopEarlgreyPinmuxMioOutIor0</p> | <p style="font-size:smaller">Muxed IO pad</p> |
+| <p style="font-size:smaller">IOR4</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">trst_n</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxInselIor4 / kTopEarlgreyPinmuxMioOutIor4</p> | <p style="font-size:smaller">Muxed IO pad / JTAG trst_n signal.</p> |
| <p style="font-size:smaller">IO_CLK</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Extra clock input for FPGA target</p> |
| <p style="font-size:smaller">IO_JSRST_N</p> | <p style="font-size:smaller">InputStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Dedicated JTAG system reset input</p> |
| <p style="font-size:smaller">IO_USB_CONNECT</p> | <p style="font-size:smaller">BidirStd</p> | <p style="font-size:smaller">VCC</p> | <p style="font-size:smaller">manual</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">- / -</p> | <p style="font-size:smaller">Manual USB UPHY signal for FPGA target</p> |
@@ -175,4 +173,4 @@
| <p style="font-size:smaller">sysrst_ctrl_aon_key1_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonKey1Out / -</p> | <p style="font-size:smaller"></p> |
| <p style="font-size:smaller">sysrst_ctrl_aon_key2_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonKey2Out / -</p> | <p style="font-size:smaller"></p> |
| <p style="font-size:smaller">sysrst_ctrl_aon_pwrb_out</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonPwrbOut / -</p> | <p style="font-size:smaller"></p> |
-| <p style="font-size:smaller">sysrst_ctrl_aon_z3_wakeup</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonZ3Wakeup / -</p> | <p style="font-size:smaller"></p> |
\ No newline at end of file
+| <p style="font-size:smaller">sysrst_ctrl_aon_z3_wakeup</p> | <p style="font-size:smaller">muxed</p> | <p style="font-size:smaller">-</p> | <p style="font-size:smaller">kTopEarlgreyPinmuxOutselSysrstCtrlAonZ3Wakeup / -</p> | <p style="font-size:smaller"></p> |
diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md
index d6a7ff0..fde140d 100644
--- a/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md
+++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md
@@ -8,4 +8,4 @@
| Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables |
|:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:-----------------------------------------------------------------------------------:|
| ASIC | 4 | 47 | 14 | 10 | 71 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_asic/index.html) |
-| CW310 | 4 | 30 | 10 | 14 | 54 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310/index.html) |
+| CW310 | 4 | 28 | 10 | 14 | 52 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310/index.html) |
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
index 777c7a2..7182811 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
@@ -56,13 +56,10 @@
inout IOB0, // MIO Pad 9
inout IOB1, // MIO Pad 10
inout IOB2, // MIO Pad 11
- inout IOB3, // MIO Pad 12
inout IOB4, // MIO Pad 13
inout IOB5, // MIO Pad 14
- inout IOB6, // MIO Pad 15
- inout IOB7, // MIO Pad 16
- inout IOB8, // MIO Pad 17
- inout IOB9, // MIO Pad 18
+ inout IOC0, // MIO Pad 22
+ inout IOC1, // MIO Pad 23
inout IOC2, // MIO Pad 24
inout IOC3, // MIO Pad 25
inout IOC4, // MIO Pad 26
@@ -73,7 +70,8 @@
inout IOC9, // MIO Pad 31
inout IOC10, // MIO Pad 32
inout IOC11, // MIO Pad 33
- inout IOR0 // MIO Pad 35
+ inout IOR0, // MIO Pad 35
+ inout IOR4 // MIO Pad 39
);
import top_earlgrey_pkg::*;
@@ -83,13 +81,13 @@
// Special Signal Indices //
////////////////////////////
- localparam int Tap0PadIdx = 22;
- localparam int Tap1PadIdx = 16;
- localparam int Dft0PadIdx = 23;
- localparam int Dft1PadIdx = 34;
+ localparam int Tap0PadIdx = 30;
+ localparam int Tap1PadIdx = 27;
+ localparam int Dft0PadIdx = 25;
+ localparam int Dft1PadIdx = 26;
localparam int TckPadIdx = 59;
localparam int TmsPadIdx = 60;
- localparam int TrstNPadIdx = 18;
+ localparam int TrstNPadIdx = 39;
localparam int TdiPadIdx = 53;
localparam int TdoPadIdx = 54;
@@ -237,6 +235,21 @@
assign unused_sig[17] = dio_out[DioSpiDeviceSd2] ^ dio_oe[DioSpiDeviceSd2];
assign dio_in[DioSpiDeviceSd3] = 1'b0;
assign unused_sig[18] = dio_out[DioSpiDeviceSd3] ^ dio_oe[DioSpiDeviceSd3];
+ assign mio_in[12] = 1'b0;
+ assign mio_in_raw[12] = 1'b0;
+ assign unused_sig[33] = mio_out[12] ^ mio_oe[12];
+ assign mio_in[15] = 1'b0;
+ assign mio_in_raw[15] = 1'b0;
+ assign unused_sig[36] = mio_out[15] ^ mio_oe[15];
+ assign mio_in[16] = 1'b0;
+ assign mio_in_raw[16] = 1'b0;
+ assign unused_sig[37] = mio_out[16] ^ mio_oe[16];
+ assign mio_in[17] = 1'b0;
+ assign mio_in_raw[17] = 1'b0;
+ assign unused_sig[38] = mio_out[17] ^ mio_oe[17];
+ assign mio_in[18] = 1'b0;
+ assign mio_in_raw[18] = 1'b0;
+ assign unused_sig[39] = mio_out[18] ^ mio_oe[18];
assign mio_in[19] = 1'b0;
assign mio_in_raw[19] = 1'b0;
assign unused_sig[40] = mio_out[19] ^ mio_oe[19];
@@ -246,12 +259,6 @@
assign mio_in[21] = 1'b0;
assign mio_in_raw[21] = 1'b0;
assign unused_sig[42] = mio_out[21] ^ mio_oe[21];
- assign mio_in[22] = 1'b0;
- assign mio_in_raw[22] = 1'b0;
- assign unused_sig[43] = mio_out[22] ^ mio_oe[22];
- assign mio_in[23] = 1'b0;
- assign mio_in_raw[23] = 1'b0;
- assign unused_sig[44] = mio_out[23] ^ mio_oe[23];
assign mio_in[34] = 1'b0;
assign mio_in_raw[34] = 1'b0;
assign unused_sig[55] = mio_out[34] ^ mio_oe[34];
@@ -264,9 +271,6 @@
assign mio_in[38] = 1'b0;
assign mio_in_raw[38] = 1'b0;
assign unused_sig[59] = mio_out[38] ^ mio_oe[38];
- assign mio_in[39] = 1'b0;
- assign mio_in_raw[39] = 1'b0;
- assign unused_sig[60] = mio_out[39] ^ mio_oe[39];
assign mio_in[40] = 1'b0;
assign mio_in_raw[40] = 1'b0;
assign unused_sig[61] = mio_out[40] ^ mio_oe[40];
@@ -304,7 +308,7 @@
// Padring specific counts may differ from pinmux config due
// to custom, stubbed or added pads.
.NDioPads(24),
- .NMioPads(30),
+ .NMioPads(28),
.DioPadType ({
BidirStd, // IO_TRIGGER
BidirStd, // IO_CLKOUT
@@ -332,6 +336,7 @@
InputStd // POR_N
}),
.MioPadType ({
+ BidirStd, // IOR4
BidirStd, // IOR0
BidirOd, // IOC11
BidirOd, // IOC10
@@ -343,13 +348,10 @@
BidirStd, // IOC4
BidirStd, // IOC3
BidirStd, // IOC2
- BidirOd, // IOB9
- BidirStd, // IOB8
- BidirStd, // IOB7
- BidirStd, // IOB6
+ BidirStd, // IOC1
+ BidirStd, // IOC0
BidirStd, // IOB5
BidirStd, // IOB4
- BidirStd, // IOB3
BidirStd, // IOB2
BidirStd, // IOB1
BidirStd, // IOB0
@@ -397,6 +399,7 @@
}),
.mio_pad_io ({
+ IOR4,
IOR0,
IOC11,
IOC10,
@@ -408,13 +411,10 @@
IOC4,
IOC3,
IOC2,
- IOB9,
- IOB8,
- IOB7,
- IOB6,
+ IOC1,
+ IOC0,
IOB5,
IOB4,
- IOB3,
IOB2,
IOB1,
IOB0,
@@ -536,29 +536,39 @@
}),
.mio_in_o ({
+ mio_in[39],
mio_in[35],
- mio_in[33:24],
- mio_in[18:0]
+ mio_in[33:22],
+ mio_in[14:13],
+ mio_in[11:0]
}),
.mio_out_i ({
+ mio_out[39],
mio_out[35],
- mio_out[33:24],
- mio_out[18:0]
+ mio_out[33:22],
+ mio_out[14:13],
+ mio_out[11:0]
}),
.mio_oe_i ({
+ mio_oe[39],
mio_oe[35],
- mio_oe[33:24],
- mio_oe[18:0]
+ mio_oe[33:22],
+ mio_oe[14:13],
+ mio_oe[11:0]
}),
.mio_attr_i ({
+ mio_attr[39],
mio_attr[35],
- mio_attr[33:24],
- mio_attr[18:0]
+ mio_attr[33:22],
+ mio_attr[14:13],
+ mio_attr[11:0]
}),
.mio_in_raw_o ({
+ mio_in_raw[39],
mio_in_raw[35],
- mio_in_raw[33:24],
- mio_in_raw[18:0]
+ mio_in_raw[33:22],
+ mio_in_raw[14:13],
+ mio_in_raw[11:0]
})
);
diff --git a/sw/host/opentitanlib/src/transport/cw310/mod.rs b/sw/host/opentitanlib/src/transport/cw310/mod.rs
index b478050..c275118 100644
--- a/sw/host/opentitanlib/src/transport/cw310/mod.rs
+++ b/sw/host/opentitanlib/src/transport/cw310/mod.rs
@@ -39,15 +39,20 @@
}
impl CW310 {
- // Pins needed for reset & bootstrap on the CW310 board.
- const PIN_SRST: &'static str = "USB_A18";
- const PIN_BOOTSTRAP: &'static str = "USB_A16";
// Pins needed for SPI on the CW310 board.
const PIN_CLK: &'static str = "USB_SPI_SCK";
const PIN_SDI: &'static str = "USB_SPI_COPI";
const PIN_SDO: &'static str = "USB_SPI_CIPO";
const PIN_CS: &'static str = "USB_SPI_CS";
- const PIN_JTAG: &'static str = "USB_A19";
+ // Pins needed for reset & bootstrap on the CW310 board.
+ const PIN_TRST: &'static str = "USB_A13";
+ const PIN_SRST: &'static str = "USB_A14";
+ const PIN_SW_STRAP0: &'static str = "USB_A15";
+ const PIN_SW_STRAP1: &'static str = "USB_A16";
+ const PIN_SW_STRAP2: &'static str = "USB_A17";
+ const PIN_TAP_STRAP0: &'static str = "USB_A18";
+ const PIN_TAP_STRAP1: &'static str = "USB_A19";
+
pub fn new(
usb_vid: Option<u16>,
@@ -67,9 +72,13 @@
// Initialize the IO direction of some basic pins on the board.
fn init_direction(&self) -> anyhow::Result<()> {
let device = self.device.borrow();
+ device.pin_set_output(Self::PIN_TRST, true)?;
device.pin_set_output(Self::PIN_SRST, true)?;
- device.pin_set_output(Self::PIN_JTAG, true)?;
- device.pin_set_output(Self::PIN_BOOTSTRAP, true)?;
+ device.pin_set_output(Self::PIN_TAP_STRAP0, true)?;
+ device.pin_set_output(Self::PIN_TAP_STRAP1, true)?;
+ device.pin_set_output(Self::PIN_SW_STRAP0, true)?;
+ device.pin_set_output(Self::PIN_SW_STRAP1, true)?;
+ device.pin_set_output(Self::PIN_SW_STRAP2, true)?;
Ok(())
}
@@ -180,7 +189,9 @@
// Program the FPGA bitstream.
let usb = self.device.borrow();
usb.spi1_enable(false)?;
- usb.pin_set_state(CW310::PIN_JTAG, true)?;
+ usb.pin_set_state(CW310::PIN_TAP_STRAP0, true)?;
+ usb.pin_set_state(CW310::PIN_TAP_STRAP1, true)?;
+ usb.pin_set_state(CW310::PIN_TAP_STRAP2, true)?;
usb.fpga_program(&fpga_program.bitstream)?;
Ok(None)
} else {
diff --git a/sw/host/opentitantool/config/opentitan_cw310.json b/sw/host/opentitantool/config/opentitan_cw310.json
index 903240b..13a691a 100644
--- a/sw/host/opentitantool/config/opentitan_cw310.json
+++ b/sw/host/opentitantool/config/opentitan_cw310.json
@@ -7,14 +7,14 @@
"mode": "OpenDrain",
"level": true,
"pullup": true,
- "alias_of": "USB_A18"
+ "alias_of": "USB_A14"
},
{
"name": "BOOTSTRAP",
"mode": "PushPull",
"level": false,
"pullup": false,
- "alias_of": "USB_A16"
+ "alias_of": "USB_A15"
}
],
"uarts": [
diff --git a/util/topgen/gen_top_docs.py b/util/topgen/gen_top_docs.py
index 3749ea9..53c6580 100644
--- a/util/topgen/gen_top_docs.py
+++ b/util/topgen/gen_top_docs.py
@@ -174,6 +174,7 @@
pinout_table += table_str + '\n'
pinout_table += '## Pinmux Connectivity\n\n'
pinout_table += create_pinmux_table(top, c_helper)
+ pinout_table += "\n"
pinout_table_path = doc_path / ("pinout_" + target['name'] + ".md")
with open(pinout_table_path, 'w') as outfile:
