| commit | a1ba95ee32a5e77992da21b0d8230af8e5f7112f | [log] [tgz] |
|---|---|---|
| author | Alexander Williams <awill@google.com> | Thu Jan 20 19:24:36 2022 -0800 |
| committer | tjaychen <timothytim@google.com> | Thu Jan 27 10:39:27 2022 -0800 |
| tree | 5990b77c50377d13de01e8a6f157623b55dc3e55 | |
| parent | ad83a4669be1681f314f54eee728d69543f9caa4 [diff] |
[usbdev] Move sense to an MIO The ASIC was missing a connection for the VBUS detection, so the MIO adds that. In addition, the FPGAs connect the two VBUS detection sources to IOR0 and IOR1--Software will have to select the correct I/O based on the `use_uphy` value. Moving to an MIO brings straightforward options for a simple constant via periph_insel if OT is completely bus-powered, in addition to making it available to both power domains for usbdev. Signed-off-by: Alexander Williams <awill@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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