)]}'
{
  "commit": "a1ba95ee32a5e77992da21b0d8230af8e5f7112f",
  "tree": "5990b77c50377d13de01e8a6f157623b55dc3e55",
  "parents": [
    "ad83a4669be1681f314f54eee728d69543f9caa4"
  ],
  "author": {
    "name": "Alexander Williams",
    "email": "awill@google.com",
    "time": "Thu Jan 20 19:24:36 2022 -0800"
  },
  "committer": {
    "name": "tjaychen",
    "email": "timothytim@google.com",
    "time": "Thu Jan 27 10:39:27 2022 -0800"
  },
  "message": "[usbdev] Move sense to an MIO\n\nThe ASIC was missing a connection for the VBUS detection, so the MIO\nadds that. In addition, the FPGAs connect the two VBUS detection sources\nto IOR0 and IOR1--Software will have to select the correct I/O based on\nthe `use_uphy` value.\n\nMoving to an MIO brings straightforward options for a simple constant\nvia periph_insel if OT is completely bus-powered, in addition to\nmaking it available to both power domains for usbdev.\n\nSigned-off-by: Alexander Williams \u003cawill@google.com\u003e\n",
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