tree: 6a3acd2985dd3ecc5446cc0458efab71357bf3a4 [path history] [tgz]
  1. top_earlgrey/
  2. README.md
  3. srcs.mk
sw/benchmarks/coremark/README.md

Options

There are two main options available for coremark SIM, ITERATIONS

ITERATIONS

Controls how many iteartions are run. By default this value is 0 and will cause coremark to run >10s. For simulation and verilator, set to 1 for a reduced run

For verilator

make distclean; make SIM=1 ITERATIONS=1 SIM=1 matces the verilator UART baudrates

For DV / FPGA

make distclean; make ITERATIONS=1/N