| <?xml version="1.0" encoding="UTF-8" standalone="no"?> |
| <!-- |
| Copyright lowRISC contributors. |
| Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| SPDX-License-Identifier: Apache-2.0 |
| --> |
| <refinement-file-root> |
| <information comment-version="1" creation-time="Thu 12 May 2022 14:35:59 PDT" creator="None" csCheck="false" save-ref-method="seq" tool-version="Cadence vManager21.03" rules-signature-c="3db4248040ca789e42d3d2d250c09760"> |
| <ucm-files> |
| <ucm-file domain="icc" modelCheckSum="575177409" path="/workspace/mnt/pattgen-sim-xcelium/cov_merge/merged/icc_224882c1_42ffa02c.ucm"></ucm-file> |
| </ucm-files> |
| <ccf-files> |
| <ccf-file content="// Copyright lowRISC contributors.;// Licensed under the Apache License, Version 2.0, see LICENSE for details.;// SPDX-License-Identifier: Apache-2.0;;// Include our common coverage CCF.;include_ccf ${dv_root}/tools/xcelium/common.ccf; /workspace/mnt/repo_top/hw/dv/tools/xcelium/common.ccf; // Copyright lowRISC contributors.; // Licensed under the Apache License, Version 2.0, see LICENSE for details.; // SPDX-License-Identifier: Apache-2.0; ; // Common coverage commands that apply to all DUTs.; //; // This coverge config file is provided by Xcelium and is located at:; // ${XCELIUM_HOME}/tools/icc/include/all_coverage.ccf; // Xcelium recommends including it, since it bundles together the common set of commands that enable; // coverage collection on various design elements, that are otherwise turned off by default. We; // maintain it locally with minor amends.; ; // Enables expression coverage of various Verilog operators.; set_expr_coverable_operators -all -event_or; ; // Enables expression coverage of operators in various conditions and assignments.; set_expr_coverable_statements -all; ; // Enables scoring of Verilog modules compiled with -v/-y or -libcell option but continues to; // disable the scoring of Verilog modules defined with the 'celldefine compiler directive.; set_libcell_scoring; ; // Enables scoring of SystemVerilog continuous assignments, which is by disabled by default.; set_assign_scoring; ; // Scores branches together with block coverage.; set_branch_scoring; ; // Scores statements within a block.; set_statement_scoring; ; ; // Enables Toggle scoring and reporting of SystemVerilog enumerations and multidimensional static; // arrays , vectors, packed union, modport and generate blocks.; set_toggle_scoring -sv_enum enable_mda -sv_struct_with_enum -sv_modport -sv_mda 16 -sv_mda_of_struct -sv_generate -sv_packed_union; ; // Enables scoring of reset states and transitions for identified FSMs.; set_fsm_reset_scoring; ; // Enable toggle coverage only on ports.; set_toggle_portsonly; ; // Enable scoring of FSM arcs (state transitions).; set_fsm_arc_scoring; ; // Include X->1|0 for toggle coverage collection. #10332; set_toggle_includex;;// enable coverage on dut and below;;select_coverage -befts -module ${DUT_TOP}...;;// Black-box pre-verified IPs from coverage collection.;deselect_coverage -betfs -module pins_if;deselect_coverage -betfs -module clk_rst_if;deselect_coverage -betfs -module prim_alert_sender...;deselect_coverage -betfs -module prim_alert_receiver...;deselect_coverage -betfs -module prim_esc_sender...;deselect_coverage -betfs -module prim_esc_receiver...;deselect_coverage -betfs -module prim_prince...;deselect_coverage -betfs -module prim_lfsr...;;;// Black-box DV CDC module.;deselect_coverage -betfs -module prim_cdc_rand_delay;// csr_assert_fpv is an auto-generated csr read assertion module. So only assertion coverage is;// meaningful to collect.;deselect_coverage -betf -module *csr_assert_fpv...;;// Only collect toggle coverage on the DUT and the black-boxed IP (above) ports.;;;select_coverage -toggle -module prim_alert_sender;select_coverage -toggle -module prim_alert_receiver;select_coverage -toggle -module prim_esc_sender;select_coverage -toggle -module prim_esc_receiver;select_coverage -toggle -module prim_prince;select_coverage -toggle -module prim_lfsr;;// These three assertions in prim_lc_sync and prim_mubi* check when `lc_ctrl_pkg::lc_tx_t` or;// `mubi*_t` input are neither `On` or `Off`, it is interrupted to the correct `On` or `Off`;// after one clock cycle. This behavior is implemented outside of IP level design thus these;// assertions are not covered in IP level testbenchs.;// TODO: check these assertions in top-level or FPV.;deselect_coverage -assertion *.PrimLcSyncCheckTransients_A;deselect_coverage -assertion *.PrimLcSyncCheckTransients0_A;deselect_coverage -assertion *.PrimLcSyncCheckTransients1_A;;deselect_coverage -assertion *.PrimMubi4SyncCheckTransients_A;deselect_coverage -assertion *.PrimMubi4SyncCheckTransients0_A;deselect_coverage -assertion *.PrimMubi4SyncCheckTransients1_A;;deselect_coverage -assertion PrimMubi8SyncCheckTransients_A;deselect_coverage -assertion PrimMubi8SyncCheckTransients0_A;deselect_coverage -assertion PrimMubi8SyncCheckTransients1_A;;deselect_coverage -assertion PrimMubi12SyncCheckTransients_A;deselect_coverage -assertion PrimMubi12SyncCheckTransients0_A;deselect_coverage -assertion PrimMubi12SyncCheckTransients1_A;;deselect_coverage -assertion PrimMubi16SyncCheckTransients_A;deselect_coverage -assertion PrimMubi16SyncCheckTransients0_A;deselect_coverage -assertion PrimMubi16SyncCheckTransients1_A;" path="/workspace/mnt/repo_top/hw/dv/tools/xcelium/cover.ccf"></ccf-file> |
| </ccf-files> |
| </information> |
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| <rule ccType="inst" domain="icc" entityName="pattgen/cio_pda0_tx_o" entityType="toggle" excTime="1652391264" name="exclude" reviewer="unknown" user="0" vscope="default"></rule> |
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| </rules> |
| <cache-map> |
| <cache-entry key="0" value="None"></cache-entry> |
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