[uart] Wire up integrity alert Signed-off-by: Michael Schaffner <msf@opentitan.org>

commit: 9d1fd4aa64f91e8663b73c045d68a7bafedb7325 [log] [tgz]
author: Michael Schaffner <msf@opentitan.org> Mon Jun 07 16:03:22 2021 -0700
committer: Michael Schaffner <msf@google.com> Tue Jun 15 07:50:12 2021 -0700
tree: 6debe6bbee3dcf2a643d8f56ff3f096a18ffa524
parent: 05dabb3f86afd6c7790e8e5f6218783b1305819c [diff]
diff --git a/hw/ip/uart/data/uart.hjson b/hw/ip/uart/data/uart.hjson
index 3f72908..4fff1e9 100644
--- a/hw/ip/uart/data/uart.hjson
+++ b/hw/ip/uart/data/uart.hjson

@@ -33,7 +33,14 @@
     }
     { name: "rx_parity_err"
       desc: "raised if the receiver has detected a parity error."}
-  ]
+  ],
+  alert_list: [
+    { name: "fatal_fault",
+      desc: '''
+      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the UART unit.
+      '''
+    }
+  ],
   regwidth: "32",
   registers: [
     { name: "CTRL",

diff --git a/hw/ip/uart/dv/env/uart_env_cfg.sv b/hw/ip/uart/dv/env/uart_env_cfg.sv
index 575f5b5..4860384 100644
--- a/hw/ip/uart/dv/env/uart_env_cfg.sv
+++ b/hw/ip/uart/dv/env/uart_env_cfg.sv

@@ -18,6 +18,7 @@
   `uvm_object_new
 
   virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+    list_of_alerts = uart_env_pkg::LIST_OF_ALERTS;
     super.initialize(csr_base_addr);
     // create uart agent config obj
     m_uart_agent_cfg = uart_agent_cfg::type_id::create("m_uart_agent_cfg");

diff --git a/hw/ip/uart/dv/env/uart_env_pkg.sv b/hw/ip/uart/dv/env/uart_env_pkg.sv
index 508e09b..d2df65f 100644
--- a/hw/ip/uart/dv/env/uart_env_pkg.sv
+++ b/hw/ip/uart/dv/env/uart_env_pkg.sv

@@ -20,6 +20,9 @@
 
   // local types
   parameter uint UART_FIFO_DEPTH = 32;
+  // alerts
+  parameter uint NUM_ALERTS = 1;
+  parameter string LIST_OF_ALERTS[] = {"fatal_fault"};
 
   typedef enum int {
     TxWatermark = 0,

diff --git a/hw/ip/uart/dv/tb/tb.sv b/hw/ip/uart/dv/tb/tb.sv
index c84677f..d942f8b 100644
--- a/hw/ip/uart/dv/tb/tb.sv
+++ b/hw/ip/uart/dv/tb/tb.sv

@@ -34,6 +34,8 @@
   tl_if tl_if(.clk, .rst_n);
   uart_if uart_if();
 
+ `DV_ALERT_IF_CONNECT
+
   // dut
   uart dut (
     .clk_i                (clk        ),
@@ -42,6 +44,9 @@
     .tl_i                 (tl_if.h2d  ),
     .tl_o                 (tl_if.d2h  ),
 
+    .alert_rx_i           (alert_rx   ),
+    .alert_tx_o           (alert_tx   ),
+
     .cio_rx_i             (uart_rx    ),
     .cio_tx_o             (uart_tx    ),
     .cio_tx_en_o          (uart_tx_en ),

diff --git a/hw/ip/uart/rtl/uart.sv b/hw/ip/uart/rtl/uart.sv
index 6a43618..d83f4e2 100644
--- a/hw/ip/uart/rtl/uart.sv
+++ b/hw/ip/uart/rtl/uart.sv

@@ -6,7 +6,11 @@
 
 `include "prim_assert.sv"
 
-module uart (
+module uart
+    import uart_reg_pkg::*;
+#(
+  parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
   input           clk_i,
   input           rst_ni,
 
@@ -14,6 +18,10 @@
   input  tlul_pkg::tl_h2d_t tl_i,
   output tlul_pkg::tl_d2h_t tl_o,
 
+  // Alerts
+  input  prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+  output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
   // Generic IO
   input           cio_rx_i,
   output logic    cio_tx_o,
@@ -32,6 +40,7 @@
 
   import uart_reg_pkg::*;
 
+  logic [NumAlerts-1:0] alert_test, alerts;
   uart_reg2hw_t reg2hw;
   uart_hw2reg_t hw2reg;
 
@@ -42,7 +51,7 @@
     .tl_o,
     .reg2hw,
     .hw2reg,
-    .intg_err_o (),
+    .intg_err_o (alerts[0]),
     .devmode_i  (1'b1)
   );
 
@@ -65,6 +74,28 @@
     .intr_rx_parity_err_o
   );
 
+  // Alerts
+  assign alert_test = {
+    reg2hw.alert_test.q &
+    reg2hw.alert_test.qe
+  };
+
+  for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+    prim_alert_sender #(
+      .AsyncOn(AlertAsyncOn[i]),
+      .IsFatal(i)
+    ) u_prim_alert_sender (
+      .clk_i,
+      .rst_ni,
+      .alert_test_i  ( alert_test[i] ),
+      .alert_req_i   ( alerts[0]     ),
+      .alert_ack_o   (               ),
+      .alert_state_o (               ),
+      .alert_rx_i    ( alert_rx_i[i] ),
+      .alert_tx_o    ( alert_tx_o[i] )
+    );
+  end
+
   // always enable the driving out of TX
   assign cio_tx_en_o = 1'b1;
 
@@ -72,6 +103,9 @@
   `ASSERT_KNOWN(txenKnown, cio_tx_en_o)
   `ASSERT_KNOWN(txKnown, cio_tx_o, clk_i, !rst_ni || !cio_tx_en_o)
 
+  // Assert Known for alerts
+  `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o)
+
   // Assert Known for interrupts
   `ASSERT_KNOWN(txWatermarkKnown, intr_tx_watermark_o)
   `ASSERT_KNOWN(rxWatermarkKnown, intr_rx_watermark_o)

diff --git a/hw/ip/uart/rtl/uart_reg_pkg.sv b/hw/ip/uart/rtl/uart_reg_pkg.sv
index f874558..24e1662 100644
--- a/hw/ip/uart/rtl/uart_reg_pkg.sv
+++ b/hw/ip/uart/rtl/uart_reg_pkg.sv

@@ -6,6 +6,9 @@
 
 package uart_reg_pkg;
 
+  // Param list
+  parameter int NumAlerts = 1;
+
   // Address widths within the block
   parameter int BlockAw = 6;
 
@@ -103,6 +106,11 @@
   } uart_reg2hw_intr_test_reg_t;
 
   typedef struct packed {
+    logic        q;
+    logic        qe;
+  } uart_reg2hw_alert_test_reg_t;
+
+  typedef struct packed {
     struct packed {
       logic        q;
     } tx;
@@ -292,9 +300,10 @@
 
   // Register -> HW type
   typedef struct packed {
-    uart_reg2hw_intr_state_reg_t intr_state; // [124:117]
-    uart_reg2hw_intr_enable_reg_t intr_enable; // [116:109]
-    uart_reg2hw_intr_test_reg_t intr_test; // [108:93]
+    uart_reg2hw_intr_state_reg_t intr_state; // [126:119]
+    uart_reg2hw_intr_enable_reg_t intr_enable; // [118:111]
+    uart_reg2hw_intr_test_reg_t intr_test; // [110:95]
+    uart_reg2hw_alert_test_reg_t alert_test; // [94:93]
     uart_reg2hw_ctrl_reg_t ctrl; // [92:68]
     uart_reg2hw_status_reg_t status; // [67:56]
     uart_reg2hw_rdata_reg_t rdata; // [55:47]
@@ -318,15 +327,16 @@
   parameter logic [BlockAw-1:0] UART_INTR_STATE_OFFSET = 6'h 0;
   parameter logic [BlockAw-1:0] UART_INTR_ENABLE_OFFSET = 6'h 4;
   parameter logic [BlockAw-1:0] UART_INTR_TEST_OFFSET = 6'h 8;
-  parameter logic [BlockAw-1:0] UART_CTRL_OFFSET = 6'h c;
-  parameter logic [BlockAw-1:0] UART_STATUS_OFFSET = 6'h 10;
-  parameter logic [BlockAw-1:0] UART_RDATA_OFFSET = 6'h 14;
-  parameter logic [BlockAw-1:0] UART_WDATA_OFFSET = 6'h 18;
-  parameter logic [BlockAw-1:0] UART_FIFO_CTRL_OFFSET = 6'h 1c;
-  parameter logic [BlockAw-1:0] UART_FIFO_STATUS_OFFSET = 6'h 20;
-  parameter logic [BlockAw-1:0] UART_OVRD_OFFSET = 6'h 24;
-  parameter logic [BlockAw-1:0] UART_VAL_OFFSET = 6'h 28;
-  parameter logic [BlockAw-1:0] UART_TIMEOUT_CTRL_OFFSET = 6'h 2c;
+  parameter logic [BlockAw-1:0] UART_ALERT_TEST_OFFSET = 6'h c;
+  parameter logic [BlockAw-1:0] UART_CTRL_OFFSET = 6'h 10;
+  parameter logic [BlockAw-1:0] UART_STATUS_OFFSET = 6'h 14;
+  parameter logic [BlockAw-1:0] UART_RDATA_OFFSET = 6'h 18;
+  parameter logic [BlockAw-1:0] UART_WDATA_OFFSET = 6'h 1c;
+  parameter logic [BlockAw-1:0] UART_FIFO_CTRL_OFFSET = 6'h 20;
+  parameter logic [BlockAw-1:0] UART_FIFO_STATUS_OFFSET = 6'h 24;
+  parameter logic [BlockAw-1:0] UART_OVRD_OFFSET = 6'h 28;
+  parameter logic [BlockAw-1:0] UART_VAL_OFFSET = 6'h 2c;
+  parameter logic [BlockAw-1:0] UART_TIMEOUT_CTRL_OFFSET = 6'h 30;
 
   // Reset values for hwext registers and their fields
   parameter logic [7:0] UART_INTR_TEST_RESVAL = 8'h 0;
@@ -338,6 +348,8 @@
   parameter logic [0:0] UART_INTR_TEST_RX_BREAK_ERR_RESVAL = 1'h 0;
   parameter logic [0:0] UART_INTR_TEST_RX_TIMEOUT_RESVAL = 1'h 0;
   parameter logic [0:0] UART_INTR_TEST_RX_PARITY_ERR_RESVAL = 1'h 0;
+  parameter logic [0:0] UART_ALERT_TEST_RESVAL = 1'h 0;
+  parameter logic [0:0] UART_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
   parameter logic [5:0] UART_STATUS_RESVAL = 6'h 3c;
   parameter logic [0:0] UART_STATUS_TXEMPTY_RESVAL = 1'h 1;
   parameter logic [0:0] UART_STATUS_TXIDLE_RESVAL = 1'h 1;
@@ -352,6 +364,7 @@
     UART_INTR_STATE,
     UART_INTR_ENABLE,
     UART_INTR_TEST,
+    UART_ALERT_TEST,
     UART_CTRL,
     UART_STATUS,
     UART_RDATA,
@@ -364,19 +377,20 @@
   } uart_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] UART_PERMIT [12] = '{
+  parameter logic [3:0] UART_PERMIT [13] = '{
     4'b 0001, // index[ 0] UART_INTR_STATE
     4'b 0001, // index[ 1] UART_INTR_ENABLE
     4'b 0001, // index[ 2] UART_INTR_TEST
-    4'b 1111, // index[ 3] UART_CTRL
-    4'b 0001, // index[ 4] UART_STATUS
-    4'b 0001, // index[ 5] UART_RDATA
-    4'b 0001, // index[ 6] UART_WDATA
-    4'b 0001, // index[ 7] UART_FIFO_CTRL
-    4'b 0111, // index[ 8] UART_FIFO_STATUS
-    4'b 0001, // index[ 9] UART_OVRD
-    4'b 0011, // index[10] UART_VAL
-    4'b 1111  // index[11] UART_TIMEOUT_CTRL
+    4'b 0001, // index[ 3] UART_ALERT_TEST
+    4'b 1111, // index[ 4] UART_CTRL
+    4'b 0001, // index[ 5] UART_STATUS
+    4'b 0001, // index[ 6] UART_RDATA
+    4'b 0001, // index[ 7] UART_WDATA
+    4'b 0001, // index[ 8] UART_FIFO_CTRL
+    4'b 0111, // index[ 9] UART_FIFO_STATUS
+    4'b 0001, // index[10] UART_OVRD
+    4'b 0011, // index[11] UART_VAL
+    4'b 1111  // index[12] UART_TIMEOUT_CTRL
   };
 
 endpackage

diff --git a/hw/ip/uart/rtl/uart_reg_top.sv b/hw/ip/uart/rtl/uart_reg_top.sv
index 30b706d..33b5aca 100644
--- a/hw/ip/uart/rtl/uart_reg_top.sv
+++ b/hw/ip/uart/rtl/uart_reg_top.sv

@@ -168,6 +168,8 @@
   logic intr_test_rx_timeout_we;
   logic intr_test_rx_parity_err_wd;
   logic intr_test_rx_parity_err_we;
+  logic alert_test_wd;
+  logic alert_test_we;
   logic ctrl_tx_qs;
   logic ctrl_tx_wd;
   logic ctrl_tx_we;
@@ -783,6 +785,22 @@
   );
 
 
+  // R[alert_test]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_alert_test (
+    .re     (1'b0),
+    .we     (alert_test_we),
+    .wd     (alert_test_wd),
+    .d      ('0),
+    .qre    (),
+    .qe     (reg2hw.alert_test.qe),
+    .q      (reg2hw.alert_test.q),
+    .qs     ()
+  );
+
+
   // R[ctrl]: V(False)
 
   //   F[tx]: 0:0
@@ -1418,21 +1436,22 @@
 
 
 
-  logic [11:0] addr_hit;
+  logic [12:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[ 0] = (reg_addr == UART_INTR_STATE_OFFSET);
     addr_hit[ 1] = (reg_addr == UART_INTR_ENABLE_OFFSET);
     addr_hit[ 2] = (reg_addr == UART_INTR_TEST_OFFSET);
-    addr_hit[ 3] = (reg_addr == UART_CTRL_OFFSET);
-    addr_hit[ 4] = (reg_addr == UART_STATUS_OFFSET);
-    addr_hit[ 5] = (reg_addr == UART_RDATA_OFFSET);
-    addr_hit[ 6] = (reg_addr == UART_WDATA_OFFSET);
-    addr_hit[ 7] = (reg_addr == UART_FIFO_CTRL_OFFSET);
-    addr_hit[ 8] = (reg_addr == UART_FIFO_STATUS_OFFSET);
-    addr_hit[ 9] = (reg_addr == UART_OVRD_OFFSET);
-    addr_hit[10] = (reg_addr == UART_VAL_OFFSET);
-    addr_hit[11] = (reg_addr == UART_TIMEOUT_CTRL_OFFSET);
+    addr_hit[ 3] = (reg_addr == UART_ALERT_TEST_OFFSET);
+    addr_hit[ 4] = (reg_addr == UART_CTRL_OFFSET);
+    addr_hit[ 5] = (reg_addr == UART_STATUS_OFFSET);
+    addr_hit[ 6] = (reg_addr == UART_RDATA_OFFSET);
+    addr_hit[ 7] = (reg_addr == UART_WDATA_OFFSET);
+    addr_hit[ 8] = (reg_addr == UART_FIFO_CTRL_OFFSET);
+    addr_hit[ 9] = (reg_addr == UART_FIFO_STATUS_OFFSET);
+    addr_hit[10] = (reg_addr == UART_OVRD_OFFSET);
+    addr_hit[11] = (reg_addr == UART_VAL_OFFSET);
+    addr_hit[12] = (reg_addr == UART_TIMEOUT_CTRL_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -1451,7 +1470,8 @@
                (addr_hit[ 8] & (|(UART_PERMIT[ 8] & ~reg_be))) |
                (addr_hit[ 9] & (|(UART_PERMIT[ 9] & ~reg_be))) |
                (addr_hit[10] & (|(UART_PERMIT[10] & ~reg_be))) |
-               (addr_hit[11] & (|(UART_PERMIT[11] & ~reg_be)))));
+               (addr_hit[11] & (|(UART_PERMIT[11] & ~reg_be))) |
+               (addr_hit[12] & (|(UART_PERMIT[12] & ~reg_be)))));
   end
 
   assign intr_state_tx_watermark_we = addr_hit[0] & reg_we & !reg_error;
@@ -1526,78 +1546,81 @@
   assign intr_test_rx_parity_err_we = addr_hit[2] & reg_we & !reg_error;
   assign intr_test_rx_parity_err_wd = reg_wdata[7];
 
-  assign ctrl_tx_we = addr_hit[3] & reg_we & !reg_error;
+  assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+  assign alert_test_wd = reg_wdata[0];
+
+  assign ctrl_tx_we = addr_hit[4] & reg_we & !reg_error;
   assign ctrl_tx_wd = reg_wdata[0];
 
-  assign ctrl_rx_we = addr_hit[3] & reg_we & !reg_error;
+  assign ctrl_rx_we = addr_hit[4] & reg_we & !reg_error;
   assign ctrl_rx_wd = reg_wdata[1];
 
-  assign ctrl_nf_we = addr_hit[3] & reg_we & !reg_error;
+  assign ctrl_nf_we = addr_hit[4] & reg_we & !reg_error;
   assign ctrl_nf_wd = reg_wdata[2];
 
-  assign ctrl_slpbk_we = addr_hit[3] & reg_we & !reg_error;
+  assign ctrl_slpbk_we = addr_hit[4] & reg_we & !reg_error;
   assign ctrl_slpbk_wd = reg_wdata[4];
 
-  assign ctrl_llpbk_we = addr_hit[3] & reg_we & !reg_error;
+  assign ctrl_llpbk_we = addr_hit[4] & reg_we & !reg_error;
   assign ctrl_llpbk_wd = reg_wdata[5];
 
-  assign ctrl_parity_en_we = addr_hit[3] & reg_we & !reg_error;
+  assign ctrl_parity_en_we = addr_hit[4] & reg_we & !reg_error;
   assign ctrl_parity_en_wd = reg_wdata[6];
 
-  assign ctrl_parity_odd_we = addr_hit[3] & reg_we & !reg_error;
+  assign ctrl_parity_odd_we = addr_hit[4] & reg_we & !reg_error;
   assign ctrl_parity_odd_wd = reg_wdata[7];
 
-  assign ctrl_rxblvl_we = addr_hit[3] & reg_we & !reg_error;
+  assign ctrl_rxblvl_we = addr_hit[4] & reg_we & !reg_error;
   assign ctrl_rxblvl_wd = reg_wdata[9:8];
 
-  assign ctrl_nco_we = addr_hit[3] & reg_we & !reg_error;
+  assign ctrl_nco_we = addr_hit[4] & reg_we & !reg_error;
   assign ctrl_nco_wd = reg_wdata[31:16];
 
-  assign status_txfull_re = addr_hit[4] & reg_re & !reg_error;
+  assign status_txfull_re = addr_hit[5] & reg_re & !reg_error;
 
-  assign status_rxfull_re = addr_hit[4] & reg_re & !reg_error;
+  assign status_rxfull_re = addr_hit[5] & reg_re & !reg_error;
 
-  assign status_txempty_re = addr_hit[4] & reg_re & !reg_error;
+  assign status_txempty_re = addr_hit[5] & reg_re & !reg_error;
 
-  assign status_txidle_re = addr_hit[4] & reg_re & !reg_error;
+  assign status_txidle_re = addr_hit[5] & reg_re & !reg_error;
 
-  assign status_rxidle_re = addr_hit[4] & reg_re & !reg_error;
+  assign status_rxidle_re = addr_hit[5] & reg_re & !reg_error;
 
-  assign status_rxempty_re = addr_hit[4] & reg_re & !reg_error;
+  assign status_rxempty_re = addr_hit[5] & reg_re & !reg_error;
 
-  assign rdata_re = addr_hit[5] & reg_re & !reg_error;
+  assign rdata_re = addr_hit[6] & reg_re & !reg_error;
 
-  assign wdata_we = addr_hit[6] & reg_we & !reg_error;
+  assign wdata_we = addr_hit[7] & reg_we & !reg_error;
   assign wdata_wd = reg_wdata[7:0];
 
-  assign fifo_ctrl_rxrst_we = addr_hit[7] & reg_we & !reg_error;
+  assign fifo_ctrl_rxrst_we = addr_hit[8] & reg_we & !reg_error;
   assign fifo_ctrl_rxrst_wd = reg_wdata[0];
 
-  assign fifo_ctrl_txrst_we = addr_hit[7] & reg_we & !reg_error;
+  assign fifo_ctrl_txrst_we = addr_hit[8] & reg_we & !reg_error;
   assign fifo_ctrl_txrst_wd = reg_wdata[1];
 
-  assign fifo_ctrl_rxilvl_we = addr_hit[7] & reg_we & !reg_error;
+  assign fifo_ctrl_rxilvl_we = addr_hit[8] & reg_we & !reg_error;
   assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
 
-  assign fifo_ctrl_txilvl_we = addr_hit[7] & reg_we & !reg_error;
+  assign fifo_ctrl_txilvl_we = addr_hit[8] & reg_we & !reg_error;
   assign fifo_ctrl_txilvl_wd = reg_wdata[6:5];
 
-  assign fifo_status_txlvl_re = addr_hit[8] & reg_re & !reg_error;
+  assign fifo_status_txlvl_re = addr_hit[9] & reg_re & !reg_error;
 
-  assign fifo_status_rxlvl_re = addr_hit[8] & reg_re & !reg_error;
+  assign fifo_status_rxlvl_re = addr_hit[9] & reg_re & !reg_error;
 
-  assign ovrd_txen_we = addr_hit[9] & reg_we & !reg_error;
+  assign ovrd_txen_we = addr_hit[10] & reg_we & !reg_error;
   assign ovrd_txen_wd = reg_wdata[0];
 
-  assign ovrd_txval_we = addr_hit[9] & reg_we & !reg_error;
+  assign ovrd_txval_we = addr_hit[10] & reg_we & !reg_error;
   assign ovrd_txval_wd = reg_wdata[1];
 
-  assign val_re = addr_hit[10] & reg_re & !reg_error;
+  assign val_re = addr_hit[11] & reg_re & !reg_error;
 
-  assign timeout_ctrl_val_we = addr_hit[11] & reg_we & !reg_error;
+  assign timeout_ctrl_val_we = addr_hit[12] & reg_we & !reg_error;
   assign timeout_ctrl_val_wd = reg_wdata[23:0];
 
-  assign timeout_ctrl_en_we = addr_hit[11] & reg_we & !reg_error;
+  assign timeout_ctrl_en_we = addr_hit[12] & reg_we & !reg_error;
   assign timeout_ctrl_en_wd = reg_wdata[31];
 
   // Read data return
@@ -1638,6 +1661,10 @@
       end
 
       addr_hit[3]: begin
+        reg_rdata_next[0] = '0;
+      end
+
+      addr_hit[4]: begin
         reg_rdata_next[0] = ctrl_tx_qs;
         reg_rdata_next[1] = ctrl_rx_qs;
         reg_rdata_next[2] = ctrl_nf_qs;
@@ -1649,7 +1676,7 @@
         reg_rdata_next[31:16] = ctrl_nco_qs;
       end
 
-      addr_hit[4]: begin
+      addr_hit[5]: begin
         reg_rdata_next[0] = status_txfull_qs;
         reg_rdata_next[1] = status_rxfull_qs;
         reg_rdata_next[2] = status_txempty_qs;
@@ -1658,36 +1685,36 @@
         reg_rdata_next[5] = status_rxempty_qs;
       end
 
-      addr_hit[5]: begin
+      addr_hit[6]: begin
         reg_rdata_next[7:0] = rdata_qs;
       end
 
-      addr_hit[6]: begin
+      addr_hit[7]: begin
         reg_rdata_next[7:0] = '0;
       end
 
-      addr_hit[7]: begin
+      addr_hit[8]: begin
         reg_rdata_next[0] = '0;
         reg_rdata_next[1] = '0;
         reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs;
         reg_rdata_next[6:5] = fifo_ctrl_txilvl_qs;
       end
 
-      addr_hit[8]: begin
+      addr_hit[9]: begin
         reg_rdata_next[5:0] = fifo_status_txlvl_qs;
         reg_rdata_next[21:16] = fifo_status_rxlvl_qs;
       end
 
-      addr_hit[9]: begin
+      addr_hit[10]: begin
         reg_rdata_next[0] = ovrd_txen_qs;
         reg_rdata_next[1] = ovrd_txval_qs;
       end
 
-      addr_hit[10]: begin
+      addr_hit[11]: begin
         reg_rdata_next[15:0] = val_qs;
       end
 
-      addr_hit[11]: begin
+      addr_hit[12]: begin
         reg_rdata_next[23:0] = timeout_ctrl_val_qs;
         reg_rdata_next[31] = timeout_ctrl_en_qs;
       end

diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index eae0098..33d3f0e 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson

@@ -11522,6 +11522,10 @@
   ]
   alert_module:
   [
+    uart0
+    uart1
+    uart2
+    uart3
     gpio
     spi_device
     spi_host0
@@ -11548,6 +11552,34 @@
   alert:
   [
     {
+      name: uart0_fatal_fault
+      width: 1
+      type: alert
+      async: "0"
+      module_name: uart0
+    }
+    {
+      name: uart1_fatal_fault
+      width: 1
+      type: alert
+      async: "0"
+      module_name: uart1
+    }
+    {
+      name: uart2_fatal_fault
+      width: 1
+      type: alert
+      async: "0"
+      module_name: uart2
+    }
+    {
+      name: uart3_fatal_fault
+      width: 1
+      type: alert
+      async: "0"
+      module_name: uart3
+    }
+    {
       name: gpio_fatal_fault
       width: 1
       type: alert

diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 703c122..965dfa4 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv

@@ -4,47 +4,51 @@
 //
 // tb__alert_handler_connect.sv is auto-generated by `topgen.py` tool
 
-assign alert_if[0].alert_tx = `CHIP_HIER.u_gpio.alert_tx_o[0];
-assign alert_if[1].alert_tx = `CHIP_HIER.u_spi_device.alert_tx_o[0];
-assign alert_if[2].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0];
-assign alert_if[3].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0];
-assign alert_if[4].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0];
-assign alert_if[5].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
-assign alert_if[6].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
-assign alert_if[7].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
-assign alert_if[8].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
-assign alert_if[9].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
-assign alert_if[10].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0];
-assign alert_if[11].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
-assign alert_if[12].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
-assign alert_if[13].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
-assign alert_if[14].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
-assign alert_if[15].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
-assign alert_if[16].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
-assign alert_if[17].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
-assign alert_if[18].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
-assign alert_if[20].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
-assign alert_if[21].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
-assign alert_if[22].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
-assign alert_if[23].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
-assign alert_if[24].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
-assign alert_if[25].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
-assign alert_if[26].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
-assign alert_if[27].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
-assign alert_if[28].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[29].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[30].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
-assign alert_if[31].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
-assign alert_if[32].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[33].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[34].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[35].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[36].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[37].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[38].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[39].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[40].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
-assign alert_if[41].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[42].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[43].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[0].alert_tx = `CHIP_HIER.u_uart0.alert_tx_o[0];
+assign alert_if[1].alert_tx = `CHIP_HIER.u_uart1.alert_tx_o[0];
+assign alert_if[2].alert_tx = `CHIP_HIER.u_uart2.alert_tx_o[0];
+assign alert_if[3].alert_tx = `CHIP_HIER.u_uart3.alert_tx_o[0];
+assign alert_if[4].alert_tx = `CHIP_HIER.u_gpio.alert_tx_o[0];
+assign alert_if[5].alert_tx = `CHIP_HIER.u_spi_device.alert_tx_o[0];
+assign alert_if[6].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0];
+assign alert_if[7].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0];
+assign alert_if[8].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0];
+assign alert_if[9].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
+assign alert_if[10].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
+assign alert_if[11].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
+assign alert_if[12].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
+assign alert_if[13].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
+assign alert_if[14].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0];
+assign alert_if[15].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
+assign alert_if[16].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
+assign alert_if[17].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
+assign alert_if[20].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
+assign alert_if[21].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
+assign alert_if[22].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
+assign alert_if[23].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
+assign alert_if[24].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
+assign alert_if[25].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
+assign alert_if[26].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
+assign alert_if[27].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
+assign alert_if[28].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
+assign alert_if[29].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
+assign alert_if[30].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[31].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
+assign alert_if[32].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[33].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[34].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
+assign alert_if[35].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
+assign alert_if[36].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[37].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[38].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[39].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[40].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[41].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[42].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[43].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[44].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
+assign alert_if[45].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[46].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[47].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];

diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index 672e067..003512c 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv

@@ -5,6 +5,10 @@
 // Generated by topgen.py
 
 parameter string LIST_OF_ALERTS[] = {
+  "uart0_fatal_fault",
+  "uart1_fatal_fault",
+  "uart2_fatal_fault",
+  "uart3_fatal_fault",
   "gpio_fatal_fault",
   "spi_device_fatal_fault",
   "spi_host0_fatal_fault",
@@ -51,4 +55,4 @@
   "rom_ctrl_fatal"
 };
 
-parameter uint NUM_ALERTS = 44;
+parameter uint NUM_ALERTS = 48;

diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index 3376679..433586c 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson

@@ -48,7 +48,7 @@
     { name: "NAlerts",
       desc: "Number of peripheral inputs",
       type: "int",
-      default: "44",
+      default: "48",
       local: "true"
     },
     { name: "EscCntDw",
@@ -66,7 +66,7 @@
     { name: "AsyncOn",
       desc: "Number of peripheral outputs",
       type: "logic [NAlerts-1:0]",
-      default: "44'b11111111111111111111000000000000000000000000",
+      default: "48'b111111111111111111110000000000000000000000000000",
       local: "true"
     },
     { name: "N_CLASSES",

diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index 6151e52..7c5cbf6 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv

@@ -7,10 +7,10 @@
 package alert_handler_reg_pkg;
 
   // Param list
-  parameter int NAlerts = 44;
+  parameter int NAlerts = 48;
   parameter int EscCntDw = 32;
   parameter int AccuCntDw = 16;
-  parameter logic [NAlerts-1:0] AsyncOn = 44'b11111111111111111111000000000000000000000000;
+  parameter logic [NAlerts-1:0] AsyncOn = 48'b111111111111111111110000000000000000000000000000;
   parameter int N_CLASSES = 4;
   parameter int N_ESC_SEV = 4;
   parameter int N_PHASES = 4;
@@ -20,7 +20,7 @@
   parameter int CLASS_DW = 2;
 
   // Address widths within the block
-  parameter int BlockAw = 10;
+  parameter int BlockAw = 11;
 
   ////////////////////////////
   // Typedefs for registers //
@@ -458,15 +458,15 @@
 
   // Register -> HW type
   typedef struct packed {
-    alert_handler_reg2hw_intr_state_reg_t intr_state; // [1048:1045]
-    alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1044:1041]
-    alert_handler_reg2hw_intr_test_reg_t intr_test; // [1040:1033]
-    alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1032:1009]
-    alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1008:1008]
-    alert_handler_reg2hw_alert_regwen_mreg_t [43:0] alert_regwen; // [1007:964]
-    alert_handler_reg2hw_alert_en_mreg_t [43:0] alert_en; // [963:920]
-    alert_handler_reg2hw_alert_class_mreg_t [43:0] alert_class; // [919:832]
-    alert_handler_reg2hw_alert_cause_mreg_t [43:0] alert_cause; // [831:788]
+    alert_handler_reg2hw_intr_state_reg_t intr_state; // [1068:1065]
+    alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1064:1061]
+    alert_handler_reg2hw_intr_test_reg_t intr_test; // [1060:1053]
+    alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1052:1029]
+    alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1028:1028]
+    alert_handler_reg2hw_alert_regwen_mreg_t [47:0] alert_regwen; // [1027:980]
+    alert_handler_reg2hw_alert_en_mreg_t [47:0] alert_en; // [979:932]
+    alert_handler_reg2hw_alert_class_mreg_t [47:0] alert_class; // [931:836]
+    alert_handler_reg2hw_alert_cause_mreg_t [47:0] alert_cause; // [835:788]
     alert_handler_reg2hw_loc_alert_en_mreg_t [4:0] loc_alert_en; // [787:783]
     alert_handler_reg2hw_loc_alert_class_mreg_t [4:0] loc_alert_class; // [782:773]
     alert_handler_reg2hw_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [772:768]
@@ -506,8 +506,8 @@
 
   // HW -> register type
   typedef struct packed {
-    alert_handler_hw2reg_intr_state_reg_t intr_state; // [317:310]
-    alert_handler_hw2reg_alert_cause_mreg_t [43:0] alert_cause; // [309:222]
+    alert_handler_hw2reg_intr_state_reg_t intr_state; // [325:318]
+    alert_handler_hw2reg_alert_cause_mreg_t [47:0] alert_cause; // [317:222]
     alert_handler_hw2reg_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [221:212]
     alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
     alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -528,260 +528,276 @@
   } alert_handler_hw2reg_t;
 
   // Register offsets
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_STATE_OFFSET = 10'h 0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_ENABLE_OFFSET = 10'h 4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_TEST_OFFSET = 10'h 8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET = 10'h c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET = 10'h 10;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_EN_OFFSET = 10'h 14;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_0_OFFSET = 10'h 18;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_1_OFFSET = 10'h 1c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_2_OFFSET = 10'h 20;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_3_OFFSET = 10'h 24;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_4_OFFSET = 10'h 28;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_5_OFFSET = 10'h 2c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_6_OFFSET = 10'h 30;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_7_OFFSET = 10'h 34;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_8_OFFSET = 10'h 38;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_9_OFFSET = 10'h 3c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_10_OFFSET = 10'h 40;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_11_OFFSET = 10'h 44;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_12_OFFSET = 10'h 48;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_13_OFFSET = 10'h 4c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_14_OFFSET = 10'h 50;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_15_OFFSET = 10'h 54;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_16_OFFSET = 10'h 58;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_17_OFFSET = 10'h 5c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_18_OFFSET = 10'h 60;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_19_OFFSET = 10'h 64;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_20_OFFSET = 10'h 68;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_21_OFFSET = 10'h 6c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_22_OFFSET = 10'h 70;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_23_OFFSET = 10'h 74;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_24_OFFSET = 10'h 78;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_25_OFFSET = 10'h 7c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_26_OFFSET = 10'h 80;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_27_OFFSET = 10'h 84;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_28_OFFSET = 10'h 88;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_29_OFFSET = 10'h 8c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_30_OFFSET = 10'h 90;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_31_OFFSET = 10'h 94;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_32_OFFSET = 10'h 98;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_33_OFFSET = 10'h 9c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_34_OFFSET = 10'h a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_35_OFFSET = 10'h a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_36_OFFSET = 10'h a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_37_OFFSET = 10'h ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_38_OFFSET = 10'h b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_39_OFFSET = 10'h b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_40_OFFSET = 10'h b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_41_OFFSET = 10'h bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_42_OFFSET = 10'h c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_43_OFFSET = 10'h c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 10'h c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 10'h cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 10'h d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 10'h d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 10'h d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 10'h dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 10'h e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 10'h e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 10'h e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 10'h ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 10'h f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 10'h f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 10'h f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 10'h fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 10'h 100;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 10'h 104;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 10'h 108;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 10'h 10c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 10'h 110;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 10'h 114;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 10'h 118;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 10'h 11c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 10'h 120;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 10'h 124;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 10'h 128;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 10'h 12c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 10'h 130;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 10'h 134;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 10'h 138;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 10'h 13c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 10'h 140;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 10'h 144;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 10'h 148;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 10'h 14c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 10'h 150;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 10'h 154;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 10'h 158;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 10'h 15c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 10'h 160;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 10'h 164;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 10'h 168;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 10'h 16c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 10'h 170;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_43_OFFSET = 10'h 174;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 10'h 178;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 10'h 17c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 10'h 180;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 10'h 184;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 10'h 188;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 10'h 18c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 10'h 190;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 10'h 194;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 10'h 198;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 10'h 19c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 10'h 1a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 10'h 1a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 10'h 1a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 10'h 1ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 10'h 1b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 10'h 1b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 10'h 1b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 10'h 1bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 10'h 1c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 10'h 1c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 10'h 1c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 10'h 1cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 10'h 1d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 10'h 1d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 10'h 1d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 10'h 1dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 10'h 1e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 10'h 1e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 10'h 1e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 10'h 1ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 10'h 1f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 10'h 1f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 10'h 1f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 10'h 1fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 10'h 200;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 10'h 204;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 10'h 208;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 10'h 20c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 10'h 210;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 10'h 214;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 10'h 218;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 10'h 21c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 10'h 220;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_43_OFFSET = 10'h 224;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 10'h 228;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 10'h 22c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 10'h 230;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 10'h 234;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 10'h 238;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 10'h 23c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 10'h 240;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 10'h 244;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 10'h 248;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 10'h 24c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 10'h 250;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 10'h 254;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 10'h 258;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 10'h 25c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 10'h 260;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 10'h 264;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 10'h 268;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 10'h 26c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 10'h 270;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 10'h 274;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 10'h 278;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 10'h 27c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 10'h 280;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 10'h 284;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 10'h 288;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 10'h 28c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 10'h 290;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 10'h 294;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 10'h 298;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 10'h 29c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 10'h 2a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 10'h 2a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 10'h 2a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 10'h 2ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 10'h 2b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 10'h 2b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 10'h 2b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 10'h 2bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 10'h 2c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 10'h 2c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 10'h 2c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 10'h 2cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 10'h 2d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 10'h 2d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 10'h 2d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 10'h 2dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 10'h 2e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 10'h 2e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 10'h 2e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 10'h 2ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 10'h 2f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 10'h 2f4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 10'h 2f8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 10'h 2fc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 10'h 300;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 10'h 304;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 10'h 308;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 10'h 30c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 10'h 310;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 10'h 314;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 10'h 318;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 10'h 31c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 10'h 320;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 10'h 324;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 10'h 328;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 10'h 32c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 10'h 330;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 10'h 334;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 10'h 338;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 10'h 33c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 10'h 340;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 10'h 344;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 10'h 348;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 10'h 34c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 10'h 350;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 10'h 354;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 10'h 358;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 10'h 35c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 10'h 360;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 10'h 364;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 10'h 368;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 10'h 36c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 10'h 370;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 10'h 374;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 10'h 378;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 10'h 37c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 10'h 380;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 10'h 384;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 10'h 388;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 10'h 38c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 10'h 390;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 10'h 394;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 10'h 398;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 10'h 39c;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 10'h 3a0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 10'h 3a4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 10'h 3a8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 10'h 3ac;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 10'h 3b0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 10'h 3b4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 10'h 3b8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 10'h 3bc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 10'h 3c0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 10'h 3c4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 10'h 3c8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 10'h 3cc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 10'h 3d0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 10'h 3d4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 10'h 3d8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 10'h 3dc;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 10'h 3e0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 10'h 3e4;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 10'h 3e8;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 10'h 3ec;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 10'h 3f0;
-  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 10'h 3f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_STATE_OFFSET = 11'h 0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_ENABLE_OFFSET = 11'h 4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_TEST_OFFSET = 11'h 8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET = 11'h c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET = 11'h 10;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_EN_OFFSET = 11'h 14;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_0_OFFSET = 11'h 18;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_1_OFFSET = 11'h 1c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_2_OFFSET = 11'h 20;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_3_OFFSET = 11'h 24;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_4_OFFSET = 11'h 28;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_5_OFFSET = 11'h 2c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_6_OFFSET = 11'h 30;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_7_OFFSET = 11'h 34;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_8_OFFSET = 11'h 38;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_9_OFFSET = 11'h 3c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_10_OFFSET = 11'h 40;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_11_OFFSET = 11'h 44;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_12_OFFSET = 11'h 48;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_13_OFFSET = 11'h 4c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_14_OFFSET = 11'h 50;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_15_OFFSET = 11'h 54;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_16_OFFSET = 11'h 58;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_17_OFFSET = 11'h 5c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_18_OFFSET = 11'h 60;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_19_OFFSET = 11'h 64;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_20_OFFSET = 11'h 68;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_21_OFFSET = 11'h 6c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_22_OFFSET = 11'h 70;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_23_OFFSET = 11'h 74;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_24_OFFSET = 11'h 78;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_25_OFFSET = 11'h 7c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_26_OFFSET = 11'h 80;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_27_OFFSET = 11'h 84;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_28_OFFSET = 11'h 88;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_29_OFFSET = 11'h 8c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_30_OFFSET = 11'h 90;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_31_OFFSET = 11'h 94;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_32_OFFSET = 11'h 98;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_33_OFFSET = 11'h 9c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_34_OFFSET = 11'h a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_35_OFFSET = 11'h a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_36_OFFSET = 11'h a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_37_OFFSET = 11'h ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_38_OFFSET = 11'h b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_39_OFFSET = 11'h b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_40_OFFSET = 11'h b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_41_OFFSET = 11'h bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_42_OFFSET = 11'h c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_43_OFFSET = 11'h c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_44_OFFSET = 11'h c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_45_OFFSET = 11'h cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_46_OFFSET = 11'h d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_47_OFFSET = 11'h d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 11'h d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 11'h dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 11'h e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 11'h e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 11'h e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 11'h ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 11'h f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 11'h f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 11'h f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 11'h fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 11'h 100;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 11'h 104;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 11'h 108;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 11'h 10c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 11'h 110;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 11'h 114;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 11'h 118;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 11'h 11c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 11'h 120;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 11'h 124;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 11'h 128;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 11'h 12c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 11'h 130;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 11'h 134;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 11'h 138;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 11'h 13c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 11'h 140;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 11'h 144;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 11'h 148;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 11'h 14c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 11'h 150;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 11'h 154;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 11'h 158;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 11'h 15c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 11'h 160;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 11'h 164;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 11'h 168;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 11'h 16c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 11'h 170;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 11'h 174;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 11'h 178;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 11'h 17c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 11'h 180;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_43_OFFSET = 11'h 184;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_44_OFFSET = 11'h 188;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_45_OFFSET = 11'h 18c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_46_OFFSET = 11'h 190;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_47_OFFSET = 11'h 194;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 11'h 198;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 11'h 19c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 11'h 1a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 11'h 1a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 11'h 1a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 11'h 1ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 11'h 1b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 11'h 1b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 11'h 1b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 11'h 1bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 11'h 1c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 11'h 1c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 11'h 1c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 11'h 1cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 11'h 1d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 11'h 1d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 11'h 1d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 11'h 1dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 11'h 1e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 11'h 1e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 11'h 1e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 11'h 1ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 11'h 1f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 11'h 1f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 11'h 1f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 11'h 1fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 11'h 200;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 11'h 204;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 11'h 208;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 11'h 20c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 11'h 210;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 11'h 214;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 11'h 218;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 11'h 21c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 11'h 220;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 11'h 224;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 11'h 228;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 11'h 22c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 11'h 230;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 11'h 234;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 11'h 238;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 11'h 23c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 11'h 240;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_43_OFFSET = 11'h 244;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_44_OFFSET = 11'h 248;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_45_OFFSET = 11'h 24c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_46_OFFSET = 11'h 250;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_47_OFFSET = 11'h 254;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 258;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 25c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 260;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 264;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 268;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 26c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 270;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 274;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 278;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 27c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 280;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 284;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 288;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 28c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 290;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 294;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 298;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 29c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 2a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 2a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 2a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 2ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 2b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 2b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 2b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 2bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 2c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 2c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 2c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 2cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 2d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 2d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 2d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 2dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 2e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 2e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 2e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 2ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 2f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 2f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 2f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 2fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 300;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 304;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 308;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 30c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 310;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 314;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 318;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 31c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 320;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 324;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 328;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 11'h 32c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 11'h 330;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 11'h 334;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 11'h 338;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 11'h 33c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 11'h 340;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 11'h 344;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 11'h 348;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 11'h 34c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 11'h 350;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 354;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 358;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 35c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 360;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 364;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 368;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 11'h 36c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 370;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 11'h 374;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 378;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 11'h 37c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 11'h 380;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 11'h 384;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 11'h 388;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 11'h 38c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 11'h 390;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 394;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 398;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 39c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 11'h 3a0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 3a4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 11'h 3a8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 3ac;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 11'h 3b0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 11'h 3b4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 11'h 3b8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 11'h 3bc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 11'h 3c0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 11'h 3c4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 3c8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 3cc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 3d0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 11'h 3d4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 3d8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 11'h 3dc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 3e0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 11'h 3e4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 11'h 3e8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 11'h 3ec;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 11'h 3f0;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 11'h 3f4;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 11'h 3f8;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 3fc;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 400;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 404;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 11'h 408;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 40c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 11'h 410;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 414;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 11'h 418;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 11'h 41c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 11'h 420;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 11'h 424;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 11'h 428;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 11'h 42c;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 430;
+  parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 434;
 
   // Reset values for hwext registers and their fields
   parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
@@ -854,6 +870,10 @@
     ALERT_HANDLER_ALERT_REGWEN_41,
     ALERT_HANDLER_ALERT_REGWEN_42,
     ALERT_HANDLER_ALERT_REGWEN_43,
+    ALERT_HANDLER_ALERT_REGWEN_44,
+    ALERT_HANDLER_ALERT_REGWEN_45,
+    ALERT_HANDLER_ALERT_REGWEN_46,
+    ALERT_HANDLER_ALERT_REGWEN_47,
     ALERT_HANDLER_ALERT_EN_0,
     ALERT_HANDLER_ALERT_EN_1,
     ALERT_HANDLER_ALERT_EN_2,
@@ -898,6 +918,10 @@
     ALERT_HANDLER_ALERT_EN_41,
     ALERT_HANDLER_ALERT_EN_42,
     ALERT_HANDLER_ALERT_EN_43,
+    ALERT_HANDLER_ALERT_EN_44,
+    ALERT_HANDLER_ALERT_EN_45,
+    ALERT_HANDLER_ALERT_EN_46,
+    ALERT_HANDLER_ALERT_EN_47,
     ALERT_HANDLER_ALERT_CLASS_0,
     ALERT_HANDLER_ALERT_CLASS_1,
     ALERT_HANDLER_ALERT_CLASS_2,
@@ -942,6 +966,10 @@
     ALERT_HANDLER_ALERT_CLASS_41,
     ALERT_HANDLER_ALERT_CLASS_42,
     ALERT_HANDLER_ALERT_CLASS_43,
+    ALERT_HANDLER_ALERT_CLASS_44,
+    ALERT_HANDLER_ALERT_CLASS_45,
+    ALERT_HANDLER_ALERT_CLASS_46,
+    ALERT_HANDLER_ALERT_CLASS_47,
     ALERT_HANDLER_ALERT_CAUSE_0,
     ALERT_HANDLER_ALERT_CAUSE_1,
     ALERT_HANDLER_ALERT_CAUSE_2,
@@ -986,6 +1014,10 @@
     ALERT_HANDLER_ALERT_CAUSE_41,
     ALERT_HANDLER_ALERT_CAUSE_42,
     ALERT_HANDLER_ALERT_CAUSE_43,
+    ALERT_HANDLER_ALERT_CAUSE_44,
+    ALERT_HANDLER_ALERT_CAUSE_45,
+    ALERT_HANDLER_ALERT_CAUSE_46,
+    ALERT_HANDLER_ALERT_CAUSE_47,
     ALERT_HANDLER_LOC_ALERT_REGWEN_0,
     ALERT_HANDLER_LOC_ALERT_REGWEN_1,
     ALERT_HANDLER_LOC_ALERT_REGWEN_2,
@@ -1061,7 +1093,7 @@
   } alert_handler_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] ALERT_HANDLER_PERMIT [254] = '{
+  parameter logic [3:0] ALERT_HANDLER_PERMIT [270] = '{
     4'b 0001, // index[  0] ALERT_HANDLER_INTR_STATE
     4'b 0001, // index[  1] ALERT_HANDLER_INTR_ENABLE
     4'b 0001, // index[  2] ALERT_HANDLER_INTR_TEST
@@ -1112,210 +1144,226 @@
     4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_REGWEN_41
     4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_REGWEN_42
     4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_REGWEN_43
-    4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_EN_0
-    4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_EN_1
-    4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_EN_2
-    4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_EN_3
-    4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_4
-    4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_5
-    4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_6
-    4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_7
-    4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_8
-    4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_9
-    4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_10
-    4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_11
-    4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_12
-    4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_13
-    4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_14
-    4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_15
-    4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_16
-    4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_17
-    4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_18
-    4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_19
-    4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_20
-    4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_21
-    4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_22
-    4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_23
-    4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_24
-    4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_25
-    4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_26
-    4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_27
-    4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_28
-    4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_29
-    4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_30
-    4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_31
-    4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_32
-    4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_33
-    4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_34
-    4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_35
-    4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_36
-    4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_37
-    4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_38
-    4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_39
-    4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_40
-    4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_41
-    4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_42
-    4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_43
-    4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_CLASS_0
-    4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_CLASS_1
-    4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_CLASS_2
-    4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_CLASS_3
-    4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_CLASS_4
-    4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_CLASS_5
-    4'b 0001, // index[100] ALERT_HANDLER_ALERT_CLASS_6
-    4'b 0001, // index[101] ALERT_HANDLER_ALERT_CLASS_7
-    4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_8
-    4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_9
-    4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_10
-    4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_11
-    4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_12
-    4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_13
-    4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_14
-    4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_15
-    4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_16
-    4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_17
-    4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_18
-    4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_19
-    4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_20
-    4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_21
-    4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_22
-    4'b 0001, // index[117] ALERT_HANDLER_ALERT_CLASS_23
-    4'b 0001, // index[118] ALERT_HANDLER_ALERT_CLASS_24
-    4'b 0001, // index[119] ALERT_HANDLER_ALERT_CLASS_25
-    4'b 0001, // index[120] ALERT_HANDLER_ALERT_CLASS_26
-    4'b 0001, // index[121] ALERT_HANDLER_ALERT_CLASS_27
-    4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_28
-    4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_29
-    4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_30
-    4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_31
-    4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_32
-    4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_33
-    4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_34
-    4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_35
-    4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_36
-    4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_37
-    4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_38
-    4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_39
-    4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_40
-    4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_41
-    4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_42
-    4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_43
-    4'b 0001, // index[138] ALERT_HANDLER_ALERT_CAUSE_0
-    4'b 0001, // index[139] ALERT_HANDLER_ALERT_CAUSE_1
-    4'b 0001, // index[140] ALERT_HANDLER_ALERT_CAUSE_2
-    4'b 0001, // index[141] ALERT_HANDLER_ALERT_CAUSE_3
-    4'b 0001, // index[142] ALERT_HANDLER_ALERT_CAUSE_4
-    4'b 0001, // index[143] ALERT_HANDLER_ALERT_CAUSE_5
-    4'b 0001, // index[144] ALERT_HANDLER_ALERT_CAUSE_6
-    4'b 0001, // index[145] ALERT_HANDLER_ALERT_CAUSE_7
-    4'b 0001, // index[146] ALERT_HANDLER_ALERT_CAUSE_8
-    4'b 0001, // index[147] ALERT_HANDLER_ALERT_CAUSE_9
-    4'b 0001, // index[148] ALERT_HANDLER_ALERT_CAUSE_10
-    4'b 0001, // index[149] ALERT_HANDLER_ALERT_CAUSE_11
-    4'b 0001, // index[150] ALERT_HANDLER_ALERT_CAUSE_12
-    4'b 0001, // index[151] ALERT_HANDLER_ALERT_CAUSE_13
-    4'b 0001, // index[152] ALERT_HANDLER_ALERT_CAUSE_14
-    4'b 0001, // index[153] ALERT_HANDLER_ALERT_CAUSE_15
-    4'b 0001, // index[154] ALERT_HANDLER_ALERT_CAUSE_16
-    4'b 0001, // index[155] ALERT_HANDLER_ALERT_CAUSE_17
-    4'b 0001, // index[156] ALERT_HANDLER_ALERT_CAUSE_18
-    4'b 0001, // index[157] ALERT_HANDLER_ALERT_CAUSE_19
-    4'b 0001, // index[158] ALERT_HANDLER_ALERT_CAUSE_20
-    4'b 0001, // index[159] ALERT_HANDLER_ALERT_CAUSE_21
-    4'b 0001, // index[160] ALERT_HANDLER_ALERT_CAUSE_22
-    4'b 0001, // index[161] ALERT_HANDLER_ALERT_CAUSE_23
-    4'b 0001, // index[162] ALERT_HANDLER_ALERT_CAUSE_24
-    4'b 0001, // index[163] ALERT_HANDLER_ALERT_CAUSE_25
-    4'b 0001, // index[164] ALERT_HANDLER_ALERT_CAUSE_26
-    4'b 0001, // index[165] ALERT_HANDLER_ALERT_CAUSE_27
-    4'b 0001, // index[166] ALERT_HANDLER_ALERT_CAUSE_28
-    4'b 0001, // index[167] ALERT_HANDLER_ALERT_CAUSE_29
-    4'b 0001, // index[168] ALERT_HANDLER_ALERT_CAUSE_30
-    4'b 0001, // index[169] ALERT_HANDLER_ALERT_CAUSE_31
-    4'b 0001, // index[170] ALERT_HANDLER_ALERT_CAUSE_32
-    4'b 0001, // index[171] ALERT_HANDLER_ALERT_CAUSE_33
-    4'b 0001, // index[172] ALERT_HANDLER_ALERT_CAUSE_34
-    4'b 0001, // index[173] ALERT_HANDLER_ALERT_CAUSE_35
-    4'b 0001, // index[174] ALERT_HANDLER_ALERT_CAUSE_36
-    4'b 0001, // index[175] ALERT_HANDLER_ALERT_CAUSE_37
-    4'b 0001, // index[176] ALERT_HANDLER_ALERT_CAUSE_38
-    4'b 0001, // index[177] ALERT_HANDLER_ALERT_CAUSE_39
-    4'b 0001, // index[178] ALERT_HANDLER_ALERT_CAUSE_40
-    4'b 0001, // index[179] ALERT_HANDLER_ALERT_CAUSE_41
-    4'b 0001, // index[180] ALERT_HANDLER_ALERT_CAUSE_42
-    4'b 0001, // index[181] ALERT_HANDLER_ALERT_CAUSE_43
-    4'b 0001, // index[182] ALERT_HANDLER_LOC_ALERT_REGWEN_0
-    4'b 0001, // index[183] ALERT_HANDLER_LOC_ALERT_REGWEN_1
-    4'b 0001, // index[184] ALERT_HANDLER_LOC_ALERT_REGWEN_2
-    4'b 0001, // index[185] ALERT_HANDLER_LOC_ALERT_REGWEN_3
-    4'b 0001, // index[186] ALERT_HANDLER_LOC_ALERT_REGWEN_4
-    4'b 0001, // index[187] ALERT_HANDLER_LOC_ALERT_EN_0
-    4'b 0001, // index[188] ALERT_HANDLER_LOC_ALERT_EN_1
-    4'b 0001, // index[189] ALERT_HANDLER_LOC_ALERT_EN_2
-    4'b 0001, // index[190] ALERT_HANDLER_LOC_ALERT_EN_3
-    4'b 0001, // index[191] ALERT_HANDLER_LOC_ALERT_EN_4
-    4'b 0001, // index[192] ALERT_HANDLER_LOC_ALERT_CLASS_0
-    4'b 0001, // index[193] ALERT_HANDLER_LOC_ALERT_CLASS_1
-    4'b 0001, // index[194] ALERT_HANDLER_LOC_ALERT_CLASS_2
-    4'b 0001, // index[195] ALERT_HANDLER_LOC_ALERT_CLASS_3
-    4'b 0001, // index[196] ALERT_HANDLER_LOC_ALERT_CLASS_4
-    4'b 0001, // index[197] ALERT_HANDLER_LOC_ALERT_CAUSE_0
-    4'b 0001, // index[198] ALERT_HANDLER_LOC_ALERT_CAUSE_1
-    4'b 0001, // index[199] ALERT_HANDLER_LOC_ALERT_CAUSE_2
-    4'b 0001, // index[200] ALERT_HANDLER_LOC_ALERT_CAUSE_3
-    4'b 0001, // index[201] ALERT_HANDLER_LOC_ALERT_CAUSE_4
-    4'b 0001, // index[202] ALERT_HANDLER_CLASSA_REGWEN
-    4'b 0011, // index[203] ALERT_HANDLER_CLASSA_CTRL
-    4'b 0001, // index[204] ALERT_HANDLER_CLASSA_CLR_REGWEN
-    4'b 0001, // index[205] ALERT_HANDLER_CLASSA_CLR
-    4'b 0011, // index[206] ALERT_HANDLER_CLASSA_ACCUM_CNT
-    4'b 0011, // index[207] ALERT_HANDLER_CLASSA_ACCUM_THRESH
-    4'b 1111, // index[208] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
-    4'b 1111, // index[209] ALERT_HANDLER_CLASSA_PHASE0_CYC
-    4'b 1111, // index[210] ALERT_HANDLER_CLASSA_PHASE1_CYC
-    4'b 1111, // index[211] ALERT_HANDLER_CLASSA_PHASE2_CYC
-    4'b 1111, // index[212] ALERT_HANDLER_CLASSA_PHASE3_CYC
-    4'b 1111, // index[213] ALERT_HANDLER_CLASSA_ESC_CNT
-    4'b 0001, // index[214] ALERT_HANDLER_CLASSA_STATE
-    4'b 0001, // index[215] ALERT_HANDLER_CLASSB_REGWEN
-    4'b 0011, // index[216] ALERT_HANDLER_CLASSB_CTRL
-    4'b 0001, // index[217] ALERT_HANDLER_CLASSB_CLR_REGWEN
-    4'b 0001, // index[218] ALERT_HANDLER_CLASSB_CLR
-    4'b 0011, // index[219] ALERT_HANDLER_CLASSB_ACCUM_CNT
-    4'b 0011, // index[220] ALERT_HANDLER_CLASSB_ACCUM_THRESH
-    4'b 1111, // index[221] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
-    4'b 1111, // index[222] ALERT_HANDLER_CLASSB_PHASE0_CYC
-    4'b 1111, // index[223] ALERT_HANDLER_CLASSB_PHASE1_CYC
-    4'b 1111, // index[224] ALERT_HANDLER_CLASSB_PHASE2_CYC
-    4'b 1111, // index[225] ALERT_HANDLER_CLASSB_PHASE3_CYC
-    4'b 1111, // index[226] ALERT_HANDLER_CLASSB_ESC_CNT
-    4'b 0001, // index[227] ALERT_HANDLER_CLASSB_STATE
-    4'b 0001, // index[228] ALERT_HANDLER_CLASSC_REGWEN
-    4'b 0011, // index[229] ALERT_HANDLER_CLASSC_CTRL
-    4'b 0001, // index[230] ALERT_HANDLER_CLASSC_CLR_REGWEN
-    4'b 0001, // index[231] ALERT_HANDLER_CLASSC_CLR
-    4'b 0011, // index[232] ALERT_HANDLER_CLASSC_ACCUM_CNT
-    4'b 0011, // index[233] ALERT_HANDLER_CLASSC_ACCUM_THRESH
-    4'b 1111, // index[234] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
-    4'b 1111, // index[235] ALERT_HANDLER_CLASSC_PHASE0_CYC
-    4'b 1111, // index[236] ALERT_HANDLER_CLASSC_PHASE1_CYC
-    4'b 1111, // index[237] ALERT_HANDLER_CLASSC_PHASE2_CYC
-    4'b 1111, // index[238] ALERT_HANDLER_CLASSC_PHASE3_CYC
-    4'b 1111, // index[239] ALERT_HANDLER_CLASSC_ESC_CNT
-    4'b 0001, // index[240] ALERT_HANDLER_CLASSC_STATE
-    4'b 0001, // index[241] ALERT_HANDLER_CLASSD_REGWEN
-    4'b 0011, // index[242] ALERT_HANDLER_CLASSD_CTRL
-    4'b 0001, // index[243] ALERT_HANDLER_CLASSD_CLR_REGWEN
-    4'b 0001, // index[244] ALERT_HANDLER_CLASSD_CLR
-    4'b 0011, // index[245] ALERT_HANDLER_CLASSD_ACCUM_CNT
-    4'b 0011, // index[246] ALERT_HANDLER_CLASSD_ACCUM_THRESH
-    4'b 1111, // index[247] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
-    4'b 1111, // index[248] ALERT_HANDLER_CLASSD_PHASE0_CYC
-    4'b 1111, // index[249] ALERT_HANDLER_CLASSD_PHASE1_CYC
-    4'b 1111, // index[250] ALERT_HANDLER_CLASSD_PHASE2_CYC
-    4'b 1111, // index[251] ALERT_HANDLER_CLASSD_PHASE3_CYC
-    4'b 1111, // index[252] ALERT_HANDLER_CLASSD_ESC_CNT
-    4'b 0001  // index[253] ALERT_HANDLER_CLASSD_STATE
+    4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_REGWEN_44
+    4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_REGWEN_45
+    4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_REGWEN_46
+    4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_REGWEN_47
+    4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_0
+    4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_1
+    4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_2
+    4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_3
+    4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_4
+    4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_5
+    4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_6
+    4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_7
+    4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_8
+    4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_9
+    4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_10
+    4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_11
+    4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_12
+    4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_13
+    4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_14
+    4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_15
+    4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_16
+    4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_17
+    4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_18
+    4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_19
+    4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_20
+    4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_21
+    4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_22
+    4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_23
+    4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_24
+    4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_25
+    4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_26
+    4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_27
+    4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_28
+    4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_29
+    4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_30
+    4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_31
+    4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_32
+    4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_33
+    4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_34
+    4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_35
+    4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_36
+    4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_37
+    4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_38
+    4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_39
+    4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_40
+    4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_41
+    4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_42
+    4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_43
+    4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_44
+    4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_45
+    4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_46
+    4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_47
+    4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_0
+    4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_1
+    4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_2
+    4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_3
+    4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_4
+    4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_5
+    4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_6
+    4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_7
+    4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_8
+    4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_9
+    4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_10
+    4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_11
+    4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_12
+    4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_13
+    4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_14
+    4'b 0001, // index[117] ALERT_HANDLER_ALERT_CLASS_15
+    4'b 0001, // index[118] ALERT_HANDLER_ALERT_CLASS_16
+    4'b 0001, // index[119] ALERT_HANDLER_ALERT_CLASS_17
+    4'b 0001, // index[120] ALERT_HANDLER_ALERT_CLASS_18
+    4'b 0001, // index[121] ALERT_HANDLER_ALERT_CLASS_19
+    4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_20
+    4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_21
+    4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_22
+    4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_23
+    4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_24
+    4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_25
+    4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_26
+    4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_27
+    4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_28
+    4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_29
+    4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_30
+    4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_31
+    4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_32
+    4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_33
+    4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_34
+    4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_35
+    4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_36
+    4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_37
+    4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_38
+    4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_39
+    4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_40
+    4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_41
+    4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_42
+    4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_43
+    4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_44
+    4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_45
+    4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_46
+    4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_47
+    4'b 0001, // index[150] ALERT_HANDLER_ALERT_CAUSE_0
+    4'b 0001, // index[151] ALERT_HANDLER_ALERT_CAUSE_1
+    4'b 0001, // index[152] ALERT_HANDLER_ALERT_CAUSE_2
+    4'b 0001, // index[153] ALERT_HANDLER_ALERT_CAUSE_3
+    4'b 0001, // index[154] ALERT_HANDLER_ALERT_CAUSE_4
+    4'b 0001, // index[155] ALERT_HANDLER_ALERT_CAUSE_5
+    4'b 0001, // index[156] ALERT_HANDLER_ALERT_CAUSE_6
+    4'b 0001, // index[157] ALERT_HANDLER_ALERT_CAUSE_7
+    4'b 0001, // index[158] ALERT_HANDLER_ALERT_CAUSE_8
+    4'b 0001, // index[159] ALERT_HANDLER_ALERT_CAUSE_9
+    4'b 0001, // index[160] ALERT_HANDLER_ALERT_CAUSE_10
+    4'b 0001, // index[161] ALERT_HANDLER_ALERT_CAUSE_11
+    4'b 0001, // index[162] ALERT_HANDLER_ALERT_CAUSE_12
+    4'b 0001, // index[163] ALERT_HANDLER_ALERT_CAUSE_13
+    4'b 0001, // index[164] ALERT_HANDLER_ALERT_CAUSE_14
+    4'b 0001, // index[165] ALERT_HANDLER_ALERT_CAUSE_15
+    4'b 0001, // index[166] ALERT_HANDLER_ALERT_CAUSE_16
+    4'b 0001, // index[167] ALERT_HANDLER_ALERT_CAUSE_17
+    4'b 0001, // index[168] ALERT_HANDLER_ALERT_CAUSE_18
+    4'b 0001, // index[169] ALERT_HANDLER_ALERT_CAUSE_19
+    4'b 0001, // index[170] ALERT_HANDLER_ALERT_CAUSE_20
+    4'b 0001, // index[171] ALERT_HANDLER_ALERT_CAUSE_21
+    4'b 0001, // index[172] ALERT_HANDLER_ALERT_CAUSE_22
+    4'b 0001, // index[173] ALERT_HANDLER_ALERT_CAUSE_23
+    4'b 0001, // index[174] ALERT_HANDLER_ALERT_CAUSE_24
+    4'b 0001, // index[175] ALERT_HANDLER_ALERT_CAUSE_25
+    4'b 0001, // index[176] ALERT_HANDLER_ALERT_CAUSE_26
+    4'b 0001, // index[177] ALERT_HANDLER_ALERT_CAUSE_27
+    4'b 0001, // index[178] ALERT_HANDLER_ALERT_CAUSE_28
+    4'b 0001, // index[179] ALERT_HANDLER_ALERT_CAUSE_29
+    4'b 0001, // index[180] ALERT_HANDLER_ALERT_CAUSE_30
+    4'b 0001, // index[181] ALERT_HANDLER_ALERT_CAUSE_31
+    4'b 0001, // index[182] ALERT_HANDLER_ALERT_CAUSE_32
+    4'b 0001, // index[183] ALERT_HANDLER_ALERT_CAUSE_33
+    4'b 0001, // index[184] ALERT_HANDLER_ALERT_CAUSE_34
+    4'b 0001, // index[185] ALERT_HANDLER_ALERT_CAUSE_35
+    4'b 0001, // index[186] ALERT_HANDLER_ALERT_CAUSE_36
+    4'b 0001, // index[187] ALERT_HANDLER_ALERT_CAUSE_37
+    4'b 0001, // index[188] ALERT_HANDLER_ALERT_CAUSE_38
+    4'b 0001, // index[189] ALERT_HANDLER_ALERT_CAUSE_39
+    4'b 0001, // index[190] ALERT_HANDLER_ALERT_CAUSE_40
+    4'b 0001, // index[191] ALERT_HANDLER_ALERT_CAUSE_41
+    4'b 0001, // index[192] ALERT_HANDLER_ALERT_CAUSE_42
+    4'b 0001, // index[193] ALERT_HANDLER_ALERT_CAUSE_43
+    4'b 0001, // index[194] ALERT_HANDLER_ALERT_CAUSE_44
+    4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_45
+    4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_46
+    4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_47
+    4'b 0001, // index[198] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+    4'b 0001, // index[199] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+    4'b 0001, // index[200] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+    4'b 0001, // index[201] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+    4'b 0001, // index[202] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+    4'b 0001, // index[203] ALERT_HANDLER_LOC_ALERT_EN_0
+    4'b 0001, // index[204] ALERT_HANDLER_LOC_ALERT_EN_1
+    4'b 0001, // index[205] ALERT_HANDLER_LOC_ALERT_EN_2
+    4'b 0001, // index[206] ALERT_HANDLER_LOC_ALERT_EN_3
+    4'b 0001, // index[207] ALERT_HANDLER_LOC_ALERT_EN_4
+    4'b 0001, // index[208] ALERT_HANDLER_LOC_ALERT_CLASS_0
+    4'b 0001, // index[209] ALERT_HANDLER_LOC_ALERT_CLASS_1
+    4'b 0001, // index[210] ALERT_HANDLER_LOC_ALERT_CLASS_2
+    4'b 0001, // index[211] ALERT_HANDLER_LOC_ALERT_CLASS_3
+    4'b 0001, // index[212] ALERT_HANDLER_LOC_ALERT_CLASS_4
+    4'b 0001, // index[213] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+    4'b 0001, // index[214] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+    4'b 0001, // index[215] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+    4'b 0001, // index[216] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+    4'b 0001, // index[217] ALERT_HANDLER_LOC_ALERT_CAUSE_4
+    4'b 0001, // index[218] ALERT_HANDLER_CLASSA_REGWEN
+    4'b 0011, // index[219] ALERT_HANDLER_CLASSA_CTRL
+    4'b 0001, // index[220] ALERT_HANDLER_CLASSA_CLR_REGWEN
+    4'b 0001, // index[221] ALERT_HANDLER_CLASSA_CLR
+    4'b 0011, // index[222] ALERT_HANDLER_CLASSA_ACCUM_CNT
+    4'b 0011, // index[223] ALERT_HANDLER_CLASSA_ACCUM_THRESH
+    4'b 1111, // index[224] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
+    4'b 1111, // index[225] ALERT_HANDLER_CLASSA_PHASE0_CYC
+    4'b 1111, // index[226] ALERT_HANDLER_CLASSA_PHASE1_CYC
+    4'b 1111, // index[227] ALERT_HANDLER_CLASSA_PHASE2_CYC
+    4'b 1111, // index[228] ALERT_HANDLER_CLASSA_PHASE3_CYC
+    4'b 1111, // index[229] ALERT_HANDLER_CLASSA_ESC_CNT
+    4'b 0001, // index[230] ALERT_HANDLER_CLASSA_STATE
+    4'b 0001, // index[231] ALERT_HANDLER_CLASSB_REGWEN
+    4'b 0011, // index[232] ALERT_HANDLER_CLASSB_CTRL
+    4'b 0001, // index[233] ALERT_HANDLER_CLASSB_CLR_REGWEN
+    4'b 0001, // index[234] ALERT_HANDLER_CLASSB_CLR
+    4'b 0011, // index[235] ALERT_HANDLER_CLASSB_ACCUM_CNT
+    4'b 0011, // index[236] ALERT_HANDLER_CLASSB_ACCUM_THRESH
+    4'b 1111, // index[237] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
+    4'b 1111, // index[238] ALERT_HANDLER_CLASSB_PHASE0_CYC
+    4'b 1111, // index[239] ALERT_HANDLER_CLASSB_PHASE1_CYC
+    4'b 1111, // index[240] ALERT_HANDLER_CLASSB_PHASE2_CYC
+    4'b 1111, // index[241] ALERT_HANDLER_CLASSB_PHASE3_CYC
+    4'b 1111, // index[242] ALERT_HANDLER_CLASSB_ESC_CNT
+    4'b 0001, // index[243] ALERT_HANDLER_CLASSB_STATE
+    4'b 0001, // index[244] ALERT_HANDLER_CLASSC_REGWEN
+    4'b 0011, // index[245] ALERT_HANDLER_CLASSC_CTRL
+    4'b 0001, // index[246] ALERT_HANDLER_CLASSC_CLR_REGWEN
+    4'b 0001, // index[247] ALERT_HANDLER_CLASSC_CLR
+    4'b 0011, // index[248] ALERT_HANDLER_CLASSC_ACCUM_CNT
+    4'b 0011, // index[249] ALERT_HANDLER_CLASSC_ACCUM_THRESH
+    4'b 1111, // index[250] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
+    4'b 1111, // index[251] ALERT_HANDLER_CLASSC_PHASE0_CYC
+    4'b 1111, // index[252] ALERT_HANDLER_CLASSC_PHASE1_CYC
+    4'b 1111, // index[253] ALERT_HANDLER_CLASSC_PHASE2_CYC
+    4'b 1111, // index[254] ALERT_HANDLER_CLASSC_PHASE3_CYC
+    4'b 1111, // index[255] ALERT_HANDLER_CLASSC_ESC_CNT
+    4'b 0001, // index[256] ALERT_HANDLER_CLASSC_STATE
+    4'b 0001, // index[257] ALERT_HANDLER_CLASSD_REGWEN
+    4'b 0011, // index[258] ALERT_HANDLER_CLASSD_CTRL
+    4'b 0001, // index[259] ALERT_HANDLER_CLASSD_CLR_REGWEN
+    4'b 0001, // index[260] ALERT_HANDLER_CLASSD_CLR
+    4'b 0011, // index[261] ALERT_HANDLER_CLASSD_ACCUM_CNT
+    4'b 0011, // index[262] ALERT_HANDLER_CLASSD_ACCUM_THRESH
+    4'b 1111, // index[263] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
+    4'b 1111, // index[264] ALERT_HANDLER_CLASSD_PHASE0_CYC
+    4'b 1111, // index[265] ALERT_HANDLER_CLASSD_PHASE1_CYC
+    4'b 1111, // index[266] ALERT_HANDLER_CLASSD_PHASE2_CYC
+    4'b 1111, // index[267] ALERT_HANDLER_CLASSD_PHASE3_CYC
+    4'b 1111, // index[268] ALERT_HANDLER_CLASSD_ESC_CNT
+    4'b 0001  // index[269] ALERT_HANDLER_CLASSD_STATE
   };
 
 endpackage

diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index 91a0332..fe26b75 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv

@@ -25,7 +25,7 @@
 
   import alert_handler_reg_pkg::* ;
 
-  localparam int AW = 10;
+  localparam int AW = 11;
   localparam int DW = 32;
   localparam int DBW = DW/8;                    // Byte Width
 
@@ -277,6 +277,18 @@
   logic alert_regwen_43_qs;
   logic alert_regwen_43_wd;
   logic alert_regwen_43_we;
+  logic alert_regwen_44_qs;
+  logic alert_regwen_44_wd;
+  logic alert_regwen_44_we;
+  logic alert_regwen_45_qs;
+  logic alert_regwen_45_wd;
+  logic alert_regwen_45_we;
+  logic alert_regwen_46_qs;
+  logic alert_regwen_46_wd;
+  logic alert_regwen_46_we;
+  logic alert_regwen_47_qs;
+  logic alert_regwen_47_wd;
+  logic alert_regwen_47_we;
   logic alert_en_0_qs;
   logic alert_en_0_wd;
   logic alert_en_0_we;
@@ -409,6 +421,18 @@
   logic alert_en_43_qs;
   logic alert_en_43_wd;
   logic alert_en_43_we;
+  logic alert_en_44_qs;
+  logic alert_en_44_wd;
+  logic alert_en_44_we;
+  logic alert_en_45_qs;
+  logic alert_en_45_wd;
+  logic alert_en_45_we;
+  logic alert_en_46_qs;
+  logic alert_en_46_wd;
+  logic alert_en_46_we;
+  logic alert_en_47_qs;
+  logic alert_en_47_wd;
+  logic alert_en_47_we;
   logic [1:0] alert_class_0_qs;
   logic [1:0] alert_class_0_wd;
   logic alert_class_0_we;
@@ -541,6 +565,18 @@
   logic [1:0] alert_class_43_qs;
   logic [1:0] alert_class_43_wd;
   logic alert_class_43_we;
+  logic [1:0] alert_class_44_qs;
+  logic [1:0] alert_class_44_wd;
+  logic alert_class_44_we;
+  logic [1:0] alert_class_45_qs;
+  logic [1:0] alert_class_45_wd;
+  logic alert_class_45_we;
+  logic [1:0] alert_class_46_qs;
+  logic [1:0] alert_class_46_wd;
+  logic alert_class_46_we;
+  logic [1:0] alert_class_47_qs;
+  logic [1:0] alert_class_47_wd;
+  logic alert_class_47_we;
   logic alert_cause_0_qs;
   logic alert_cause_0_wd;
   logic alert_cause_0_we;
@@ -673,6 +709,18 @@
   logic alert_cause_43_qs;
   logic alert_cause_43_wd;
   logic alert_cause_43_we;
+  logic alert_cause_44_qs;
+  logic alert_cause_44_wd;
+  logic alert_cause_44_we;
+  logic alert_cause_45_qs;
+  logic alert_cause_45_wd;
+  logic alert_cause_45_we;
+  logic alert_cause_46_qs;
+  logic alert_cause_46_wd;
+  logic alert_cause_46_we;
+  logic alert_cause_47_qs;
+  logic alert_cause_47_wd;
+  logic alert_cause_47_we;
   logic loc_alert_regwen_0_qs;
   logic loc_alert_regwen_0_wd;
   logic loc_alert_regwen_0_we;
@@ -2527,6 +2575,114 @@
     .qs     (alert_regwen_43_qs)
   );
 
+  // Subregister 44 of Multireg alert_regwen
+  // R[alert_regwen_44]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_alert_regwen_44 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_regwen_44_we),
+    .wd     (alert_regwen_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_regwen[44].q),
+
+    // to register interface (read)
+    .qs     (alert_regwen_44_qs)
+  );
+
+  // Subregister 45 of Multireg alert_regwen
+  // R[alert_regwen_45]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_alert_regwen_45 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_regwen_45_we),
+    .wd     (alert_regwen_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_regwen[45].q),
+
+    // to register interface (read)
+    .qs     (alert_regwen_45_qs)
+  );
+
+  // Subregister 46 of Multireg alert_regwen
+  // R[alert_regwen_46]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_alert_regwen_46 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_regwen_46_we),
+    .wd     (alert_regwen_46_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_regwen[46].q),
+
+    // to register interface (read)
+    .qs     (alert_regwen_46_qs)
+  );
+
+  // Subregister 47 of Multireg alert_regwen
+  // R[alert_regwen_47]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_alert_regwen_47 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_regwen_47_we),
+    .wd     (alert_regwen_47_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_regwen[47].q),
+
+    // to register interface (read)
+    .qs     (alert_regwen_47_qs)
+  );
+
 
 
   // Subregister 0 of Multireg alert_en
@@ -3717,6 +3873,114 @@
     .qs     (alert_en_43_qs)
   );
 
+  // Subregister 44 of Multireg alert_en
+  // R[alert_en_44]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_alert_en_44 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_en_44_we & alert_regwen_44_qs),
+    .wd     (alert_en_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_en[44].q),
+
+    // to register interface (read)
+    .qs     (alert_en_44_qs)
+  );
+
+  // Subregister 45 of Multireg alert_en
+  // R[alert_en_45]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_alert_en_45 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_en_45_we & alert_regwen_45_qs),
+    .wd     (alert_en_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_en[45].q),
+
+    // to register interface (read)
+    .qs     (alert_en_45_qs)
+  );
+
+  // Subregister 46 of Multireg alert_en
+  // R[alert_en_46]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_alert_en_46 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_en_46_we & alert_regwen_46_qs),
+    .wd     (alert_en_46_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_en[46].q),
+
+    // to register interface (read)
+    .qs     (alert_en_46_qs)
+  );
+
+  // Subregister 47 of Multireg alert_en
+  // R[alert_en_47]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_alert_en_47 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_en_47_we & alert_regwen_47_qs),
+    .wd     (alert_en_47_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_en[47].q),
+
+    // to register interface (read)
+    .qs     (alert_en_47_qs)
+  );
+
 
 
   // Subregister 0 of Multireg alert_class
@@ -4907,6 +5171,114 @@
     .qs     (alert_class_43_qs)
   );
 
+  // Subregister 44 of Multireg alert_class
+  // R[alert_class_44]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_alert_class_44 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_class_44_we & alert_regwen_44_qs),
+    .wd     (alert_class_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_class[44].q),
+
+    // to register interface (read)
+    .qs     (alert_class_44_qs)
+  );
+
+  // Subregister 45 of Multireg alert_class
+  // R[alert_class_45]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_alert_class_45 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_class_45_we & alert_regwen_45_qs),
+    .wd     (alert_class_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_class[45].q),
+
+    // to register interface (read)
+    .qs     (alert_class_45_qs)
+  );
+
+  // Subregister 46 of Multireg alert_class
+  // R[alert_class_46]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_alert_class_46 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_class_46_we & alert_regwen_46_qs),
+    .wd     (alert_class_46_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_class[46].q),
+
+    // to register interface (read)
+    .qs     (alert_class_46_qs)
+  );
+
+  // Subregister 47 of Multireg alert_class
+  // R[alert_class_47]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h0)
+  ) u_alert_class_47 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_class_47_we & alert_regwen_47_qs),
+    .wd     (alert_class_47_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_class[47].q),
+
+    // to register interface (read)
+    .qs     (alert_class_47_qs)
+  );
+
 
 
   // Subregister 0 of Multireg alert_cause
@@ -6097,6 +6469,114 @@
     .qs     (alert_cause_43_qs)
   );
 
+  // Subregister 44 of Multireg alert_cause
+  // R[alert_cause_44]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_alert_cause_44 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_cause_44_we),
+    .wd     (alert_cause_44_wd),
+
+    // from internal hardware
+    .de     (hw2reg.alert_cause[44].de),
+    .d      (hw2reg.alert_cause[44].d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_cause[44].q),
+
+    // to register interface (read)
+    .qs     (alert_cause_44_qs)
+  );
+
+  // Subregister 45 of Multireg alert_cause
+  // R[alert_cause_45]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_alert_cause_45 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_cause_45_we),
+    .wd     (alert_cause_45_wd),
+
+    // from internal hardware
+    .de     (hw2reg.alert_cause[45].de),
+    .d      (hw2reg.alert_cause[45].d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_cause[45].q),
+
+    // to register interface (read)
+    .qs     (alert_cause_45_qs)
+  );
+
+  // Subregister 46 of Multireg alert_cause
+  // R[alert_cause_46]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_alert_cause_46 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_cause_46_we),
+    .wd     (alert_cause_46_wd),
+
+    // from internal hardware
+    .de     (hw2reg.alert_cause[46].de),
+    .d      (hw2reg.alert_cause[46].d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_cause[46].q),
+
+    // to register interface (read)
+    .qs     (alert_cause_46_qs)
+  );
+
+  // Subregister 47 of Multireg alert_cause
+  // R[alert_cause_47]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W1C"),
+    .RESVAL  (1'h0)
+  ) u_alert_cause_47 (
+    .clk_i   (clk_i),
+    .rst_ni  (rst_ni),
+
+    // from register interface
+    .we     (alert_cause_47_we),
+    .wd     (alert_cause_47_wd),
+
+    // from internal hardware
+    .de     (hw2reg.alert_cause[47].de),
+    .d      (hw2reg.alert_cause[47].d),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.alert_cause[47].q),
+
+    // to register interface (read)
+    .qs     (alert_cause_47_qs)
+  );
+
 
 
   // Subregister 0 of Multireg loc_alert_regwen
@@ -8860,7 +9340,7 @@
 
 
 
-  logic [253:0] addr_hit;
+  logic [269:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[  0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
@@ -8913,210 +9393,226 @@
     addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_41_OFFSET);
     addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_42_OFFSET);
     addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_43_OFFSET);
-    addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
-    addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
-    addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
-    addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
-    addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
-    addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
-    addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
-    addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
-    addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
-    addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
-    addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
-    addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
-    addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
-    addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
-    addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
-    addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
-    addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
-    addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
-    addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
-    addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
-    addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
-    addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
-    addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
-    addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
-    addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
-    addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
-    addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
-    addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
-    addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
-    addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
-    addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
-    addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
-    addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
-    addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
-    addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
-    addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
-    addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
-    addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET);
-    addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET);
-    addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET);
-    addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET);
-    addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET);
-    addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET);
-    addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_43_OFFSET);
-    addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
-    addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
-    addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
-    addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
-    addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
-    addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
-    addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
-    addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
-    addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
-    addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
-    addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
-    addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
-    addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
-    addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
-    addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
-    addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
-    addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
-    addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
-    addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
-    addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
-    addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
-    addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
-    addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
-    addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
-    addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
-    addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
-    addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
-    addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
-    addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
-    addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
-    addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
-    addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
-    addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
-    addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
-    addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
-    addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
-    addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
-    addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET);
-    addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET);
-    addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET);
-    addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET);
-    addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET);
-    addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET);
-    addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_43_OFFSET);
-    addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
-    addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
-    addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
-    addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
-    addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
-    addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
-    addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
-    addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
-    addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
-    addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
-    addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
-    addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
-    addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
-    addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
-    addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
-    addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
-    addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
-    addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
-    addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
-    addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
-    addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
-    addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
-    addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
-    addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
-    addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
-    addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
-    addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
-    addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
-    addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
-    addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
-    addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
-    addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
-    addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
-    addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
-    addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
-    addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
-    addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
-    addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
-    addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
-    addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
-    addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
-    addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
-    addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
-    addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
-    addr_hit[182] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
-    addr_hit[183] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
-    addr_hit[184] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
-    addr_hit[185] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
-    addr_hit[186] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
-    addr_hit[187] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
-    addr_hit[188] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
-    addr_hit[189] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
-    addr_hit[190] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
-    addr_hit[191] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET);
-    addr_hit[192] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
-    addr_hit[193] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
-    addr_hit[194] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
-    addr_hit[195] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
-    addr_hit[196] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET);
-    addr_hit[197] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
-    addr_hit[198] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
-    addr_hit[199] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
-    addr_hit[200] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
-    addr_hit[201] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
-    addr_hit[202] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
-    addr_hit[203] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
-    addr_hit[204] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
-    addr_hit[205] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
-    addr_hit[206] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
-    addr_hit[207] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
-    addr_hit[208] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
-    addr_hit[209] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
-    addr_hit[210] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
-    addr_hit[211] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
-    addr_hit[212] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
-    addr_hit[213] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
-    addr_hit[214] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
-    addr_hit[215] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
-    addr_hit[216] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
-    addr_hit[217] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
-    addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
-    addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
-    addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
-    addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
-    addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
-    addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
-    addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
-    addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
-    addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
-    addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
-    addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
-    addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
-    addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
-    addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
-    addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
-    addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
-    addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
-    addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
-    addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
-    addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
-    addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
-    addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
-    addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
-    addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
-    addr_hit[242] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
-    addr_hit[243] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
-    addr_hit[244] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
-    addr_hit[245] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
-    addr_hit[246] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
-    addr_hit[247] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
-    addr_hit[248] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
-    addr_hit[249] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
-    addr_hit[250] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
-    addr_hit[251] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
-    addr_hit[252] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
-    addr_hit[253] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+    addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_44_OFFSET);
+    addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_45_OFFSET);
+    addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_46_OFFSET);
+    addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_47_OFFSET);
+    addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
+    addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
+    addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
+    addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
+    addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
+    addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
+    addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
+    addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
+    addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
+    addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
+    addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
+    addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
+    addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
+    addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
+    addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
+    addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
+    addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
+    addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
+    addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
+    addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
+    addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
+    addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
+    addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
+    addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
+    addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
+    addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
+    addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
+    addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
+    addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
+    addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
+    addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
+    addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
+    addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
+    addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
+    addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
+    addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
+    addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
+    addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET);
+    addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET);
+    addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET);
+    addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET);
+    addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET);
+    addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET);
+    addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_43_OFFSET);
+    addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_44_OFFSET);
+    addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_45_OFFSET);
+    addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_46_OFFSET);
+    addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_47_OFFSET);
+    addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
+    addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
+    addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
+    addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
+    addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
+    addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
+    addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
+    addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
+    addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
+    addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
+    addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
+    addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
+    addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
+    addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
+    addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
+    addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
+    addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
+    addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
+    addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
+    addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
+    addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
+    addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
+    addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
+    addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
+    addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
+    addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
+    addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
+    addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
+    addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
+    addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
+    addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
+    addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
+    addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
+    addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
+    addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
+    addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
+    addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
+    addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET);
+    addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET);
+    addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET);
+    addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET);
+    addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET);
+    addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET);
+    addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_43_OFFSET);
+    addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_44_OFFSET);
+    addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_45_OFFSET);
+    addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_46_OFFSET);
+    addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_47_OFFSET);
+    addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+    addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+    addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+    addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+    addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+    addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+    addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+    addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+    addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+    addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+    addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+    addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+    addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+    addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+    addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+    addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+    addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+    addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+    addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+    addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+    addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+    addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+    addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+    addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+    addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+    addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+    addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+    addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+    addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+    addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+    addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+    addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+    addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+    addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+    addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+    addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+    addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+    addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+    addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+    addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
+    addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
+    addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
+    addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
+    addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
+    addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
+    addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
+    addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
+    addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
+    addr_hit[198] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+    addr_hit[199] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+    addr_hit[200] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+    addr_hit[201] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+    addr_hit[202] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+    addr_hit[203] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
+    addr_hit[204] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
+    addr_hit[205] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
+    addr_hit[206] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
+    addr_hit[207] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET);
+    addr_hit[208] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
+    addr_hit[209] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
+    addr_hit[210] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
+    addr_hit[211] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
+    addr_hit[212] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET);
+    addr_hit[213] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+    addr_hit[214] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+    addr_hit[215] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+    addr_hit[216] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+    addr_hit[217] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
+    addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+    addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
+    addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+    addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
+    addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+    addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
+    addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
+    addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
+    addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
+    addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
+    addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
+    addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+    addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+    addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+    addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
+    addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+    addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
+    addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+    addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
+    addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
+    addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
+    addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
+    addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
+    addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
+    addr_hit[242] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+    addr_hit[243] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+    addr_hit[244] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+    addr_hit[245] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
+    addr_hit[246] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+    addr_hit[247] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
+    addr_hit[248] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+    addr_hit[249] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
+    addr_hit[250] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
+    addr_hit[251] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
+    addr_hit[252] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
+    addr_hit[253] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
+    addr_hit[254] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
+    addr_hit[255] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+    addr_hit[256] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+    addr_hit[257] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+    addr_hit[258] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
+    addr_hit[259] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+    addr_hit[260] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
+    addr_hit[261] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+    addr_hit[262] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
+    addr_hit[263] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
+    addr_hit[264] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
+    addr_hit[265] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
+    addr_hit[266] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
+    addr_hit[267] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
+    addr_hit[268] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+    addr_hit[269] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -9377,7 +9873,23 @@
                (addr_hit[250] & (|(ALERT_HANDLER_PERMIT[250] & ~reg_be))) |
                (addr_hit[251] & (|(ALERT_HANDLER_PERMIT[251] & ~reg_be))) |
                (addr_hit[252] & (|(ALERT_HANDLER_PERMIT[252] & ~reg_be))) |
-               (addr_hit[253] & (|(ALERT_HANDLER_PERMIT[253] & ~reg_be)))));
+               (addr_hit[253] & (|(ALERT_HANDLER_PERMIT[253] & ~reg_be))) |
+               (addr_hit[254] & (|(ALERT_HANDLER_PERMIT[254] & ~reg_be))) |
+               (addr_hit[255] & (|(ALERT_HANDLER_PERMIT[255] & ~reg_be))) |
+               (addr_hit[256] & (|(ALERT_HANDLER_PERMIT[256] & ~reg_be))) |
+               (addr_hit[257] & (|(ALERT_HANDLER_PERMIT[257] & ~reg_be))) |
+               (addr_hit[258] & (|(ALERT_HANDLER_PERMIT[258] & ~reg_be))) |
+               (addr_hit[259] & (|(ALERT_HANDLER_PERMIT[259] & ~reg_be))) |
+               (addr_hit[260] & (|(ALERT_HANDLER_PERMIT[260] & ~reg_be))) |
+               (addr_hit[261] & (|(ALERT_HANDLER_PERMIT[261] & ~reg_be))) |
+               (addr_hit[262] & (|(ALERT_HANDLER_PERMIT[262] & ~reg_be))) |
+               (addr_hit[263] & (|(ALERT_HANDLER_PERMIT[263] & ~reg_be))) |
+               (addr_hit[264] & (|(ALERT_HANDLER_PERMIT[264] & ~reg_be))) |
+               (addr_hit[265] & (|(ALERT_HANDLER_PERMIT[265] & ~reg_be))) |
+               (addr_hit[266] & (|(ALERT_HANDLER_PERMIT[266] & ~reg_be))) |
+               (addr_hit[267] & (|(ALERT_HANDLER_PERMIT[267] & ~reg_be))) |
+               (addr_hit[268] & (|(ALERT_HANDLER_PERMIT[268] & ~reg_be))) |
+               (addr_hit[269] & (|(ALERT_HANDLER_PERMIT[269] & ~reg_be)))));
   end
 
   assign intr_state_classa_we = addr_hit[0] & reg_we & !reg_error;
@@ -9557,713 +10069,761 @@
   assign alert_regwen_43_we = addr_hit[49] & reg_we & !reg_error;
   assign alert_regwen_43_wd = reg_wdata[0];
 
-  assign alert_en_0_we = addr_hit[50] & reg_we & !reg_error;
+  assign alert_regwen_44_we = addr_hit[50] & reg_we & !reg_error;
+  assign alert_regwen_44_wd = reg_wdata[0];
+
+  assign alert_regwen_45_we = addr_hit[51] & reg_we & !reg_error;
+  assign alert_regwen_45_wd = reg_wdata[0];
+
+  assign alert_regwen_46_we = addr_hit[52] & reg_we & !reg_error;
+  assign alert_regwen_46_wd = reg_wdata[0];
+
+  assign alert_regwen_47_we = addr_hit[53] & reg_we & !reg_error;
+  assign alert_regwen_47_wd = reg_wdata[0];
+
+  assign alert_en_0_we = addr_hit[54] & reg_we & !reg_error;
   assign alert_en_0_wd = reg_wdata[0];
 
-  assign alert_en_1_we = addr_hit[51] & reg_we & !reg_error;
+  assign alert_en_1_we = addr_hit[55] & reg_we & !reg_error;
   assign alert_en_1_wd = reg_wdata[0];
 
-  assign alert_en_2_we = addr_hit[52] & reg_we & !reg_error;
+  assign alert_en_2_we = addr_hit[56] & reg_we & !reg_error;
   assign alert_en_2_wd = reg_wdata[0];
 
-  assign alert_en_3_we = addr_hit[53] & reg_we & !reg_error;
+  assign alert_en_3_we = addr_hit[57] & reg_we & !reg_error;
   assign alert_en_3_wd = reg_wdata[0];
 
-  assign alert_en_4_we = addr_hit[54] & reg_we & !reg_error;
+  assign alert_en_4_we = addr_hit[58] & reg_we & !reg_error;
   assign alert_en_4_wd = reg_wdata[0];
 
-  assign alert_en_5_we = addr_hit[55] & reg_we & !reg_error;
+  assign alert_en_5_we = addr_hit[59] & reg_we & !reg_error;
   assign alert_en_5_wd = reg_wdata[0];
 
-  assign alert_en_6_we = addr_hit[56] & reg_we & !reg_error;
+  assign alert_en_6_we = addr_hit[60] & reg_we & !reg_error;
   assign alert_en_6_wd = reg_wdata[0];
 
-  assign alert_en_7_we = addr_hit[57] & reg_we & !reg_error;
+  assign alert_en_7_we = addr_hit[61] & reg_we & !reg_error;
   assign alert_en_7_wd = reg_wdata[0];
 
-  assign alert_en_8_we = addr_hit[58] & reg_we & !reg_error;
+  assign alert_en_8_we = addr_hit[62] & reg_we & !reg_error;
   assign alert_en_8_wd = reg_wdata[0];
 
-  assign alert_en_9_we = addr_hit[59] & reg_we & !reg_error;
+  assign alert_en_9_we = addr_hit[63] & reg_we & !reg_error;
   assign alert_en_9_wd = reg_wdata[0];
 
-  assign alert_en_10_we = addr_hit[60] & reg_we & !reg_error;
+  assign alert_en_10_we = addr_hit[64] & reg_we & !reg_error;
   assign alert_en_10_wd = reg_wdata[0];
 
-  assign alert_en_11_we = addr_hit[61] & reg_we & !reg_error;
+  assign alert_en_11_we = addr_hit[65] & reg_we & !reg_error;
   assign alert_en_11_wd = reg_wdata[0];
 
-  assign alert_en_12_we = addr_hit[62] & reg_we & !reg_error;
+  assign alert_en_12_we = addr_hit[66] & reg_we & !reg_error;
   assign alert_en_12_wd = reg_wdata[0];
 
-  assign alert_en_13_we = addr_hit[63] & reg_we & !reg_error;
+  assign alert_en_13_we = addr_hit[67] & reg_we & !reg_error;
   assign alert_en_13_wd = reg_wdata[0];
 
-  assign alert_en_14_we = addr_hit[64] & reg_we & !reg_error;
+  assign alert_en_14_we = addr_hit[68] & reg_we & !reg_error;
   assign alert_en_14_wd = reg_wdata[0];
 
-  assign alert_en_15_we = addr_hit[65] & reg_we & !reg_error;
+  assign alert_en_15_we = addr_hit[69] & reg_we & !reg_error;
   assign alert_en_15_wd = reg_wdata[0];
 
-  assign alert_en_16_we = addr_hit[66] & reg_we & !reg_error;
+  assign alert_en_16_we = addr_hit[70] & reg_we & !reg_error;
   assign alert_en_16_wd = reg_wdata[0];
 
-  assign alert_en_17_we = addr_hit[67] & reg_we & !reg_error;
+  assign alert_en_17_we = addr_hit[71] & reg_we & !reg_error;
   assign alert_en_17_wd = reg_wdata[0];
 
-  assign alert_en_18_we = addr_hit[68] & reg_we & !reg_error;
+  assign alert_en_18_we = addr_hit[72] & reg_we & !reg_error;
   assign alert_en_18_wd = reg_wdata[0];
 
-  assign alert_en_19_we = addr_hit[69] & reg_we & !reg_error;
+  assign alert_en_19_we = addr_hit[73] & reg_we & !reg_error;
   assign alert_en_19_wd = reg_wdata[0];
 
-  assign alert_en_20_we = addr_hit[70] & reg_we & !reg_error;
+  assign alert_en_20_we = addr_hit[74] & reg_we & !reg_error;
   assign alert_en_20_wd = reg_wdata[0];
 
-  assign alert_en_21_we = addr_hit[71] & reg_we & !reg_error;
+  assign alert_en_21_we = addr_hit[75] & reg_we & !reg_error;
   assign alert_en_21_wd = reg_wdata[0];
 
-  assign alert_en_22_we = addr_hit[72] & reg_we & !reg_error;
+  assign alert_en_22_we = addr_hit[76] & reg_we & !reg_error;
   assign alert_en_22_wd = reg_wdata[0];
 
-  assign alert_en_23_we = addr_hit[73] & reg_we & !reg_error;
+  assign alert_en_23_we = addr_hit[77] & reg_we & !reg_error;
   assign alert_en_23_wd = reg_wdata[0];
 
-  assign alert_en_24_we = addr_hit[74] & reg_we & !reg_error;
+  assign alert_en_24_we = addr_hit[78] & reg_we & !reg_error;
   assign alert_en_24_wd = reg_wdata[0];
 
-  assign alert_en_25_we = addr_hit[75] & reg_we & !reg_error;
+  assign alert_en_25_we = addr_hit[79] & reg_we & !reg_error;
   assign alert_en_25_wd = reg_wdata[0];
 
-  assign alert_en_26_we = addr_hit[76] & reg_we & !reg_error;
+  assign alert_en_26_we = addr_hit[80] & reg_we & !reg_error;
   assign alert_en_26_wd = reg_wdata[0];
 
-  assign alert_en_27_we = addr_hit[77] & reg_we & !reg_error;
+  assign alert_en_27_we = addr_hit[81] & reg_we & !reg_error;
   assign alert_en_27_wd = reg_wdata[0];
 
-  assign alert_en_28_we = addr_hit[78] & reg_we & !reg_error;
+  assign alert_en_28_we = addr_hit[82] & reg_we & !reg_error;
   assign alert_en_28_wd = reg_wdata[0];
 
-  assign alert_en_29_we = addr_hit[79] & reg_we & !reg_error;
+  assign alert_en_29_we = addr_hit[83] & reg_we & !reg_error;
   assign alert_en_29_wd = reg_wdata[0];
 
-  assign alert_en_30_we = addr_hit[80] & reg_we & !reg_error;
+  assign alert_en_30_we = addr_hit[84] & reg_we & !reg_error;
   assign alert_en_30_wd = reg_wdata[0];
 
-  assign alert_en_31_we = addr_hit[81] & reg_we & !reg_error;
+  assign alert_en_31_we = addr_hit[85] & reg_we & !reg_error;
   assign alert_en_31_wd = reg_wdata[0];
 
-  assign alert_en_32_we = addr_hit[82] & reg_we & !reg_error;
+  assign alert_en_32_we = addr_hit[86] & reg_we & !reg_error;
   assign alert_en_32_wd = reg_wdata[0];
 
-  assign alert_en_33_we = addr_hit[83] & reg_we & !reg_error;
+  assign alert_en_33_we = addr_hit[87] & reg_we & !reg_error;
   assign alert_en_33_wd = reg_wdata[0];
 
-  assign alert_en_34_we = addr_hit[84] & reg_we & !reg_error;
+  assign alert_en_34_we = addr_hit[88] & reg_we & !reg_error;
   assign alert_en_34_wd = reg_wdata[0];
 
-  assign alert_en_35_we = addr_hit[85] & reg_we & !reg_error;
+  assign alert_en_35_we = addr_hit[89] & reg_we & !reg_error;
   assign alert_en_35_wd = reg_wdata[0];
 
-  assign alert_en_36_we = addr_hit[86] & reg_we & !reg_error;
+  assign alert_en_36_we = addr_hit[90] & reg_we & !reg_error;
   assign alert_en_36_wd = reg_wdata[0];
 
-  assign alert_en_37_we = addr_hit[87] & reg_we & !reg_error;
+  assign alert_en_37_we = addr_hit[91] & reg_we & !reg_error;
   assign alert_en_37_wd = reg_wdata[0];
 
-  assign alert_en_38_we = addr_hit[88] & reg_we & !reg_error;
+  assign alert_en_38_we = addr_hit[92] & reg_we & !reg_error;
   assign alert_en_38_wd = reg_wdata[0];
 
-  assign alert_en_39_we = addr_hit[89] & reg_we & !reg_error;
+  assign alert_en_39_we = addr_hit[93] & reg_we & !reg_error;
   assign alert_en_39_wd = reg_wdata[0];
 
-  assign alert_en_40_we = addr_hit[90] & reg_we & !reg_error;
+  assign alert_en_40_we = addr_hit[94] & reg_we & !reg_error;
   assign alert_en_40_wd = reg_wdata[0];
 
-  assign alert_en_41_we = addr_hit[91] & reg_we & !reg_error;
+  assign alert_en_41_we = addr_hit[95] & reg_we & !reg_error;
   assign alert_en_41_wd = reg_wdata[0];
 
-  assign alert_en_42_we = addr_hit[92] & reg_we & !reg_error;
+  assign alert_en_42_we = addr_hit[96] & reg_we & !reg_error;
   assign alert_en_42_wd = reg_wdata[0];
 
-  assign alert_en_43_we = addr_hit[93] & reg_we & !reg_error;
+  assign alert_en_43_we = addr_hit[97] & reg_we & !reg_error;
   assign alert_en_43_wd = reg_wdata[0];
 
-  assign alert_class_0_we = addr_hit[94] & reg_we & !reg_error;
+  assign alert_en_44_we = addr_hit[98] & reg_we & !reg_error;
+  assign alert_en_44_wd = reg_wdata[0];
+
+  assign alert_en_45_we = addr_hit[99] & reg_we & !reg_error;
+  assign alert_en_45_wd = reg_wdata[0];
+
+  assign alert_en_46_we = addr_hit[100] & reg_we & !reg_error;
+  assign alert_en_46_wd = reg_wdata[0];
+
+  assign alert_en_47_we = addr_hit[101] & reg_we & !reg_error;
+  assign alert_en_47_wd = reg_wdata[0];
+
+  assign alert_class_0_we = addr_hit[102] & reg_we & !reg_error;
   assign alert_class_0_wd = reg_wdata[1:0];
 
-  assign alert_class_1_we = addr_hit[95] & reg_we & !reg_error;
+  assign alert_class_1_we = addr_hit[103] & reg_we & !reg_error;
   assign alert_class_1_wd = reg_wdata[1:0];
 
-  assign alert_class_2_we = addr_hit[96] & reg_we & !reg_error;
+  assign alert_class_2_we = addr_hit[104] & reg_we & !reg_error;
   assign alert_class_2_wd = reg_wdata[1:0];
 
-  assign alert_class_3_we = addr_hit[97] & reg_we & !reg_error;
+  assign alert_class_3_we = addr_hit[105] & reg_we & !reg_error;
   assign alert_class_3_wd = reg_wdata[1:0];
 
-  assign alert_class_4_we = addr_hit[98] & reg_we & !reg_error;
+  assign alert_class_4_we = addr_hit[106] & reg_we & !reg_error;
   assign alert_class_4_wd = reg_wdata[1:0];
 
-  assign alert_class_5_we = addr_hit[99] & reg_we & !reg_error;
+  assign alert_class_5_we = addr_hit[107] & reg_we & !reg_error;
   assign alert_class_5_wd = reg_wdata[1:0];
 
-  assign alert_class_6_we = addr_hit[100] & reg_we & !reg_error;
+  assign alert_class_6_we = addr_hit[108] & reg_we & !reg_error;
   assign alert_class_6_wd = reg_wdata[1:0];
 
-  assign alert_class_7_we = addr_hit[101] & reg_we & !reg_error;
+  assign alert_class_7_we = addr_hit[109] & reg_we & !reg_error;
   assign alert_class_7_wd = reg_wdata[1:0];
 
-  assign alert_class_8_we = addr_hit[102] & reg_we & !reg_error;
+  assign alert_class_8_we = addr_hit[110] & reg_we & !reg_error;
   assign alert_class_8_wd = reg_wdata[1:0];
 
-  assign alert_class_9_we = addr_hit[103] & reg_we & !reg_error;
+  assign alert_class_9_we = addr_hit[111] & reg_we & !reg_error;
   assign alert_class_9_wd = reg_wdata[1:0];
 
-  assign alert_class_10_we = addr_hit[104] & reg_we & !reg_error;
+  assign alert_class_10_we = addr_hit[112] & reg_we & !reg_error;
   assign alert_class_10_wd = reg_wdata[1:0];
 
-  assign alert_class_11_we = addr_hit[105] & reg_we & !reg_error;
+  assign alert_class_11_we = addr_hit[113] & reg_we & !reg_error;
   assign alert_class_11_wd = reg_wdata[1:0];
 
-  assign alert_class_12_we = addr_hit[106] & reg_we & !reg_error;
+  assign alert_class_12_we = addr_hit[114] & reg_we & !reg_error;
   assign alert_class_12_wd = reg_wdata[1:0];
 
-  assign alert_class_13_we = addr_hit[107] & reg_we & !reg_error;
+  assign alert_class_13_we = addr_hit[115] & reg_we & !reg_error;
   assign alert_class_13_wd = reg_wdata[1:0];
 
-  assign alert_class_14_we = addr_hit[108] & reg_we & !reg_error;
+  assign alert_class_14_we = addr_hit[116] & reg_we & !reg_error;
   assign alert_class_14_wd = reg_wdata[1:0];
 
-  assign alert_class_15_we = addr_hit[109] & reg_we & !reg_error;
+  assign alert_class_15_we = addr_hit[117] & reg_we & !reg_error;
   assign alert_class_15_wd = reg_wdata[1:0];
 
-  assign alert_class_16_we = addr_hit[110] & reg_we & !reg_error;
+  assign alert_class_16_we = addr_hit[118] & reg_we & !reg_error;
   assign alert_class_16_wd = reg_wdata[1:0];
 
-  assign alert_class_17_we = addr_hit[111] & reg_we & !reg_error;
+  assign alert_class_17_we = addr_hit[119] & reg_we & !reg_error;
   assign alert_class_17_wd = reg_wdata[1:0];
 
-  assign alert_class_18_we = addr_hit[112] & reg_we & !reg_error;
+  assign alert_class_18_we = addr_hit[120] & reg_we & !reg_error;
   assign alert_class_18_wd = reg_wdata[1:0];
 
-  assign alert_class_19_we = addr_hit[113] & reg_we & !reg_error;
+  assign alert_class_19_we = addr_hit[121] & reg_we & !reg_error;
   assign alert_class_19_wd = reg_wdata[1:0];
 
-  assign alert_class_20_we = addr_hit[114] & reg_we & !reg_error;
+  assign alert_class_20_we = addr_hit[122] & reg_we & !reg_error;
   assign alert_class_20_wd = reg_wdata[1:0];
 
-  assign alert_class_21_we = addr_hit[115] & reg_we & !reg_error;
+  assign alert_class_21_we = addr_hit[123] & reg_we & !reg_error;
   assign alert_class_21_wd = reg_wdata[1:0];
 
-  assign alert_class_22_we = addr_hit[116] & reg_we & !reg_error;
+  assign alert_class_22_we = addr_hit[124] & reg_we & !reg_error;
   assign alert_class_22_wd = reg_wdata[1:0];
 
-  assign alert_class_23_we = addr_hit[117] & reg_we & !reg_error;
+  assign alert_class_23_we = addr_hit[125] & reg_we & !reg_error;
   assign alert_class_23_wd = reg_wdata[1:0];
 
-  assign alert_class_24_we = addr_hit[118] & reg_we & !reg_error;
+  assign alert_class_24_we = addr_hit[126] & reg_we & !reg_error;
   assign alert_class_24_wd = reg_wdata[1:0];
 
-  assign alert_class_25_we = addr_hit[119] & reg_we & !reg_error;
+  assign alert_class_25_we = addr_hit[127] & reg_we & !reg_error;
   assign alert_class_25_wd = reg_wdata[1:0];
 
-  assign alert_class_26_we = addr_hit[120] & reg_we & !reg_error;
+  assign alert_class_26_we = addr_hit[128] & reg_we & !reg_error;
   assign alert_class_26_wd = reg_wdata[1:0];
 
-  assign alert_class_27_we = addr_hit[121] & reg_we & !reg_error;
+  assign alert_class_27_we = addr_hit[129] & reg_we & !reg_error;
   assign alert_class_27_wd = reg_wdata[1:0];
 
-  assign alert_class_28_we = addr_hit[122] & reg_we & !reg_error;
+  assign alert_class_28_we = addr_hit[130] & reg_we & !reg_error;
   assign alert_class_28_wd = reg_wdata[1:0];
 
-  assign alert_class_29_we = addr_hit[123] & reg_we & !reg_error;
+  assign alert_class_29_we = addr_hit[131] & reg_we & !reg_error;
   assign alert_class_29_wd = reg_wdata[1:0];
 
-  assign alert_class_30_we = addr_hit[124] & reg_we & !reg_error;
+  assign alert_class_30_we = addr_hit[132] & reg_we & !reg_error;
   assign alert_class_30_wd = reg_wdata[1:0];
 
-  assign alert_class_31_we = addr_hit[125] & reg_we & !reg_error;
+  assign alert_class_31_we = addr_hit[133] & reg_we & !reg_error;
   assign alert_class_31_wd = reg_wdata[1:0];
 
-  assign alert_class_32_we = addr_hit[126] & reg_we & !reg_error;
+  assign alert_class_32_we = addr_hit[134] & reg_we & !reg_error;
   assign alert_class_32_wd = reg_wdata[1:0];
 
-  assign alert_class_33_we = addr_hit[127] & reg_we & !reg_error;
+  assign alert_class_33_we = addr_hit[135] & reg_we & !reg_error;
   assign alert_class_33_wd = reg_wdata[1:0];
 
-  assign alert_class_34_we = addr_hit[128] & reg_we & !reg_error;
+  assign alert_class_34_we = addr_hit[136] & reg_we & !reg_error;
   assign alert_class_34_wd = reg_wdata[1:0];
 
-  assign alert_class_35_we = addr_hit[129] & reg_we & !reg_error;
+  assign alert_class_35_we = addr_hit[137] & reg_we & !reg_error;
   assign alert_class_35_wd = reg_wdata[1:0];
 
-  assign alert_class_36_we = addr_hit[130] & reg_we & !reg_error;
+  assign alert_class_36_we = addr_hit[138] & reg_we & !reg_error;
   assign alert_class_36_wd = reg_wdata[1:0];
 
-  assign alert_class_37_we = addr_hit[131] & reg_we & !reg_error;
+  assign alert_class_37_we = addr_hit[139] & reg_we & !reg_error;
   assign alert_class_37_wd = reg_wdata[1:0];
 
-  assign alert_class_38_we = addr_hit[132] & reg_we & !reg_error;
+  assign alert_class_38_we = addr_hit[140] & reg_we & !reg_error;
   assign alert_class_38_wd = reg_wdata[1:0];
 
-  assign alert_class_39_we = addr_hit[133] & reg_we & !reg_error;
+  assign alert_class_39_we = addr_hit[141] & reg_we & !reg_error;
   assign alert_class_39_wd = reg_wdata[1:0];
 
-  assign alert_class_40_we = addr_hit[134] & reg_we & !reg_error;
+  assign alert_class_40_we = addr_hit[142] & reg_we & !reg_error;
   assign alert_class_40_wd = reg_wdata[1:0];
 
-  assign alert_class_41_we = addr_hit[135] & reg_we & !reg_error;
+  assign alert_class_41_we = addr_hit[143] & reg_we & !reg_error;
   assign alert_class_41_wd = reg_wdata[1:0];
 
-  assign alert_class_42_we = addr_hit[136] & reg_we & !reg_error;
+  assign alert_class_42_we = addr_hit[144] & reg_we & !reg_error;
   assign alert_class_42_wd = reg_wdata[1:0];
 
-  assign alert_class_43_we = addr_hit[137] & reg_we & !reg_error;
+  assign alert_class_43_we = addr_hit[145] & reg_we & !reg_error;
   assign alert_class_43_wd = reg_wdata[1:0];
 
-  assign alert_cause_0_we = addr_hit[138] & reg_we & !reg_error;
+  assign alert_class_44_we = addr_hit[146] & reg_we & !reg_error;
+  assign alert_class_44_wd = reg_wdata[1:0];
+
+  assign alert_class_45_we = addr_hit[147] & reg_we & !reg_error;
+  assign alert_class_45_wd = reg_wdata[1:0];
+
+  assign alert_class_46_we = addr_hit[148] & reg_we & !reg_error;
+  assign alert_class_46_wd = reg_wdata[1:0];
+
+  assign alert_class_47_we = addr_hit[149] & reg_we & !reg_error;
+  assign alert_class_47_wd = reg_wdata[1:0];
+
+  assign alert_cause_0_we = addr_hit[150] & reg_we & !reg_error;
   assign alert_cause_0_wd = reg_wdata[0];
 
-  assign alert_cause_1_we = addr_hit[139] & reg_we & !reg_error;
+  assign alert_cause_1_we = addr_hit[151] & reg_we & !reg_error;
   assign alert_cause_1_wd = reg_wdata[0];
 
-  assign alert_cause_2_we = addr_hit[140] & reg_we & !reg_error;
+  assign alert_cause_2_we = addr_hit[152] & reg_we & !reg_error;
   assign alert_cause_2_wd = reg_wdata[0];
 
-  assign alert_cause_3_we = addr_hit[141] & reg_we & !reg_error;
+  assign alert_cause_3_we = addr_hit[153] & reg_we & !reg_error;
   assign alert_cause_3_wd = reg_wdata[0];
 
-  assign alert_cause_4_we = addr_hit[142] & reg_we & !reg_error;
+  assign alert_cause_4_we = addr_hit[154] & reg_we & !reg_error;
   assign alert_cause_4_wd = reg_wdata[0];
 
-  assign alert_cause_5_we = addr_hit[143] & reg_we & !reg_error;
+  assign alert_cause_5_we = addr_hit[155] & reg_we & !reg_error;
   assign alert_cause_5_wd = reg_wdata[0];
 
-  assign alert_cause_6_we = addr_hit[144] & reg_we & !reg_error;
+  assign alert_cause_6_we = addr_hit[156] & reg_we & !reg_error;
   assign alert_cause_6_wd = reg_wdata[0];
 
-  assign alert_cause_7_we = addr_hit[145] & reg_we & !reg_error;
+  assign alert_cause_7_we = addr_hit[157] & reg_we & !reg_error;
   assign alert_cause_7_wd = reg_wdata[0];
 
-  assign alert_cause_8_we = addr_hit[146] & reg_we & !reg_error;
+  assign alert_cause_8_we = addr_hit[158] & reg_we & !reg_error;
   assign alert_cause_8_wd = reg_wdata[0];
 
-  assign alert_cause_9_we = addr_hit[147] & reg_we & !reg_error;
+  assign alert_cause_9_we = addr_hit[159] & reg_we & !reg_error;
   assign alert_cause_9_wd = reg_wdata[0];
 
-  assign alert_cause_10_we = addr_hit[148] & reg_we & !reg_error;
+  assign alert_cause_10_we = addr_hit[160] & reg_we & !reg_error;
   assign alert_cause_10_wd = reg_wdata[0];
 
-  assign alert_cause_11_we = addr_hit[149] & reg_we & !reg_error;
+  assign alert_cause_11_we = addr_hit[161] & reg_we & !reg_error;
   assign alert_cause_11_wd = reg_wdata[0];
 
-  assign alert_cause_12_we = addr_hit[150] & reg_we & !reg_error;
+  assign alert_cause_12_we = addr_hit[162] & reg_we & !reg_error;
   assign alert_cause_12_wd = reg_wdata[0];
 
-  assign alert_cause_13_we = addr_hit[151] & reg_we & !reg_error;
+  assign alert_cause_13_we = addr_hit[163] & reg_we & !reg_error;
   assign alert_cause_13_wd = reg_wdata[0];
 
-  assign alert_cause_14_we = addr_hit[152] & reg_we & !reg_error;
+  assign alert_cause_14_we = addr_hit[164] & reg_we & !reg_error;
   assign alert_cause_14_wd = reg_wdata[0];
 
-  assign alert_cause_15_we = addr_hit[153] & reg_we & !reg_error;
+  assign alert_cause_15_we = addr_hit[165] & reg_we & !reg_error;
   assign alert_cause_15_wd = reg_wdata[0];
 
-  assign alert_cause_16_we = addr_hit[154] & reg_we & !reg_error;
+  assign alert_cause_16_we = addr_hit[166] & reg_we & !reg_error;
   assign alert_cause_16_wd = reg_wdata[0];
 
-  assign alert_cause_17_we = addr_hit[155] & reg_we & !reg_error;
+  assign alert_cause_17_we = addr_hit[167] & reg_we & !reg_error;
   assign alert_cause_17_wd = reg_wdata[0];
 
-  assign alert_cause_18_we = addr_hit[156] & reg_we & !reg_error;
+  assign alert_cause_18_we = addr_hit[168] & reg_we & !reg_error;
   assign alert_cause_18_wd = reg_wdata[0];
 
-  assign alert_cause_19_we = addr_hit[157] & reg_we & !reg_error;
+  assign alert_cause_19_we = addr_hit[169] & reg_we & !reg_error;
   assign alert_cause_19_wd = reg_wdata[0];
 
-  assign alert_cause_20_we = addr_hit[158] & reg_we & !reg_error;
+  assign alert_cause_20_we = addr_hit[170] & reg_we & !reg_error;
   assign alert_cause_20_wd = reg_wdata[0];
 
-  assign alert_cause_21_we = addr_hit[159] & reg_we & !reg_error;
+  assign alert_cause_21_we = addr_hit[171] & reg_we & !reg_error;
   assign alert_cause_21_wd = reg_wdata[0];
 
-  assign alert_cause_22_we = addr_hit[160] & reg_we & !reg_error;
+  assign alert_cause_22_we = addr_hit[172] & reg_we & !reg_error;
   assign alert_cause_22_wd = reg_wdata[0];
 
-  assign alert_cause_23_we = addr_hit[161] & reg_we & !reg_error;
+  assign alert_cause_23_we = addr_hit[173] & reg_we & !reg_error;
   assign alert_cause_23_wd = reg_wdata[0];
 
-  assign alert_cause_24_we = addr_hit[162] & reg_we & !reg_error;
+  assign alert_cause_24_we = addr_hit[174] & reg_we & !reg_error;
   assign alert_cause_24_wd = reg_wdata[0];
 
-  assign alert_cause_25_we = addr_hit[163] & reg_we & !reg_error;
+  assign alert_cause_25_we = addr_hit[175] & reg_we & !reg_error;
   assign alert_cause_25_wd = reg_wdata[0];
 
-  assign alert_cause_26_we = addr_hit[164] & reg_we & !reg_error;
+  assign alert_cause_26_we = addr_hit[176] & reg_we & !reg_error;
   assign alert_cause_26_wd = reg_wdata[0];
 
-  assign alert_cause_27_we = addr_hit[165] & reg_we & !reg_error;
+  assign alert_cause_27_we = addr_hit[177] & reg_we & !reg_error;
   assign alert_cause_27_wd = reg_wdata[0];
 
-  assign alert_cause_28_we = addr_hit[166] & reg_we & !reg_error;
+  assign alert_cause_28_we = addr_hit[178] & reg_we & !reg_error;
   assign alert_cause_28_wd = reg_wdata[0];
 
-  assign alert_cause_29_we = addr_hit[167] & reg_we & !reg_error;
+  assign alert_cause_29_we = addr_hit[179] & reg_we & !reg_error;
   assign alert_cause_29_wd = reg_wdata[0];
 
-  assign alert_cause_30_we = addr_hit[168] & reg_we & !reg_error;
+  assign alert_cause_30_we = addr_hit[180] & reg_we & !reg_error;
   assign alert_cause_30_wd = reg_wdata[0];
 
-  assign alert_cause_31_we = addr_hit[169] & reg_we & !reg_error;
+  assign alert_cause_31_we = addr_hit[181] & reg_we & !reg_error;
   assign alert_cause_31_wd = reg_wdata[0];
 
-  assign alert_cause_32_we = addr_hit[170] & reg_we & !reg_error;
+  assign alert_cause_32_we = addr_hit[182] & reg_we & !reg_error;
   assign alert_cause_32_wd = reg_wdata[0];
 
-  assign alert_cause_33_we = addr_hit[171] & reg_we & !reg_error;
+  assign alert_cause_33_we = addr_hit[183] & reg_we & !reg_error;
   assign alert_cause_33_wd = reg_wdata[0];
 
-  assign alert_cause_34_we = addr_hit[172] & reg_we & !reg_error;
+  assign alert_cause_34_we = addr_hit[184] & reg_we & !reg_error;
   assign alert_cause_34_wd = reg_wdata[0];
 
-  assign alert_cause_35_we = addr_hit[173] & reg_we & !reg_error;
+  assign alert_cause_35_we = addr_hit[185] & reg_we & !reg_error;
   assign alert_cause_35_wd = reg_wdata[0];
 
-  assign alert_cause_36_we = addr_hit[174] & reg_we & !reg_error;
+  assign alert_cause_36_we = addr_hit[186] & reg_we & !reg_error;
   assign alert_cause_36_wd = reg_wdata[0];
 
-  assign alert_cause_37_we = addr_hit[175] & reg_we & !reg_error;
+  assign alert_cause_37_we = addr_hit[187] & reg_we & !reg_error;
   assign alert_cause_37_wd = reg_wdata[0];
 
-  assign alert_cause_38_we = addr_hit[176] & reg_we & !reg_error;
+  assign alert_cause_38_we = addr_hit[188] & reg_we & !reg_error;
   assign alert_cause_38_wd = reg_wdata[0];
 
-  assign alert_cause_39_we = addr_hit[177] & reg_we & !reg_error;
+  assign alert_cause_39_we = addr_hit[189] & reg_we & !reg_error;
   assign alert_cause_39_wd = reg_wdata[0];
 
-  assign alert_cause_40_we = addr_hit[178] & reg_we & !reg_error;
+  assign alert_cause_40_we = addr_hit[190] & reg_we & !reg_error;
   assign alert_cause_40_wd = reg_wdata[0];
 
-  assign alert_cause_41_we = addr_hit[179] & reg_we & !reg_error;
+  assign alert_cause_41_we = addr_hit[191] & reg_we & !reg_error;
   assign alert_cause_41_wd = reg_wdata[0];
 
-  assign alert_cause_42_we = addr_hit[180] & reg_we & !reg_error;
+  assign alert_cause_42_we = addr_hit[192] & reg_we & !reg_error;
   assign alert_cause_42_wd = reg_wdata[0];
 
-  assign alert_cause_43_we = addr_hit[181] & reg_we & !reg_error;
+  assign alert_cause_43_we = addr_hit[193] & reg_we & !reg_error;
   assign alert_cause_43_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_0_we = addr_hit[182] & reg_we & !reg_error;
+  assign alert_cause_44_we = addr_hit[194] & reg_we & !reg_error;
+  assign alert_cause_44_wd = reg_wdata[0];
+
+  assign alert_cause_45_we = addr_hit[195] & reg_we & !reg_error;
+  assign alert_cause_45_wd = reg_wdata[0];
+
+  assign alert_cause_46_we = addr_hit[196] & reg_we & !reg_error;
+  assign alert_cause_46_wd = reg_wdata[0];
+
+  assign alert_cause_47_we = addr_hit[197] & reg_we & !reg_error;
+  assign alert_cause_47_wd = reg_wdata[0];
+
+  assign loc_alert_regwen_0_we = addr_hit[198] & reg_we & !reg_error;
   assign loc_alert_regwen_0_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_1_we = addr_hit[183] & reg_we & !reg_error;
+  assign loc_alert_regwen_1_we = addr_hit[199] & reg_we & !reg_error;
   assign loc_alert_regwen_1_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_2_we = addr_hit[184] & reg_we & !reg_error;
+  assign loc_alert_regwen_2_we = addr_hit[200] & reg_we & !reg_error;
   assign loc_alert_regwen_2_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_3_we = addr_hit[185] & reg_we & !reg_error;
+  assign loc_alert_regwen_3_we = addr_hit[201] & reg_we & !reg_error;
   assign loc_alert_regwen_3_wd = reg_wdata[0];
 
-  assign loc_alert_regwen_4_we = addr_hit[186] & reg_we & !reg_error;
+  assign loc_alert_regwen_4_we = addr_hit[202] & reg_we & !reg_error;
   assign loc_alert_regwen_4_wd = reg_wdata[0];
 
-  assign loc_alert_en_0_we = addr_hit[187] & reg_we & !reg_error;
+  assign loc_alert_en_0_we = addr_hit[203] & reg_we & !reg_error;
   assign loc_alert_en_0_wd = reg_wdata[0];
 
-  assign loc_alert_en_1_we = addr_hit[188] & reg_we & !reg_error;
+  assign loc_alert_en_1_we = addr_hit[204] & reg_we & !reg_error;
   assign loc_alert_en_1_wd = reg_wdata[0];
 
-  assign loc_alert_en_2_we = addr_hit[189] & reg_we & !reg_error;
+  assign loc_alert_en_2_we = addr_hit[205] & reg_we & !reg_error;
   assign loc_alert_en_2_wd = reg_wdata[0];
 
-  assign loc_alert_en_3_we = addr_hit[190] & reg_we & !reg_error;
+  assign loc_alert_en_3_we = addr_hit[206] & reg_we & !reg_error;
   assign loc_alert_en_3_wd = reg_wdata[0];
 
-  assign loc_alert_en_4_we = addr_hit[191] & reg_we & !reg_error;
+  assign loc_alert_en_4_we = addr_hit[207] & reg_we & !reg_error;
   assign loc_alert_en_4_wd = reg_wdata[0];
 
-  assign loc_alert_class_0_we = addr_hit[192] & reg_we & !reg_error;
+  assign loc_alert_class_0_we = addr_hit[208] & reg_we & !reg_error;
   assign loc_alert_class_0_wd = reg_wdata[1:0];
 
-  assign loc_alert_class_1_we = addr_hit[193] & reg_we & !reg_error;
+  assign loc_alert_class_1_we = addr_hit[209] & reg_we & !reg_error;
   assign loc_alert_class_1_wd = reg_wdata[1:0];
 
-  assign loc_alert_class_2_we = addr_hit[194] & reg_we & !reg_error;
+  assign loc_alert_class_2_we = addr_hit[210] & reg_we & !reg_error;
   assign loc_alert_class_2_wd = reg_wdata[1:0];
 
-  assign loc_alert_class_3_we = addr_hit[195] & reg_we & !reg_error;
+  assign loc_alert_class_3_we = addr_hit[211] & reg_we & !reg_error;
   assign loc_alert_class_3_wd = reg_wdata[1:0];
 
-  assign loc_alert_class_4_we = addr_hit[196] & reg_we & !reg_error;
+  assign loc_alert_class_4_we = addr_hit[212] & reg_we & !reg_error;
   assign loc_alert_class_4_wd = reg_wdata[1:0];
 
-  assign loc_alert_cause_0_we = addr_hit[197] & reg_we & !reg_error;
+  assign loc_alert_cause_0_we = addr_hit[213] & reg_we & !reg_error;
   assign loc_alert_cause_0_wd = reg_wdata[0];
 
-  assign loc_alert_cause_1_we = addr_hit[198] & reg_we & !reg_error;
+  assign loc_alert_cause_1_we = addr_hit[214] & reg_we & !reg_error;
   assign loc_alert_cause_1_wd = reg_wdata[0];
 
-  assign loc_alert_cause_2_we = addr_hit[199] & reg_we & !reg_error;
+  assign loc_alert_cause_2_we = addr_hit[215] & reg_we & !reg_error;
   assign loc_alert_cause_2_wd = reg_wdata[0];
 
-  assign loc_alert_cause_3_we = addr_hit[200] & reg_we & !reg_error;
+  assign loc_alert_cause_3_we = addr_hit[216] & reg_we & !reg_error;
   assign loc_alert_cause_3_wd = reg_wdata[0];
 
-  assign loc_alert_cause_4_we = addr_hit[201] & reg_we & !reg_error;
+  assign loc_alert_cause_4_we = addr_hit[217] & reg_we & !reg_error;
   assign loc_alert_cause_4_wd = reg_wdata[0];
 
-  assign classa_regwen_we = addr_hit[202] & reg_we & !reg_error;
+  assign classa_regwen_we = addr_hit[218] & reg_we & !reg_error;
   assign classa_regwen_wd = reg_wdata[0];
 
-  assign classa_ctrl_en_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_en_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_en_wd = reg_wdata[0];
 
-  assign classa_ctrl_lock_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_lock_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_lock_wd = reg_wdata[1];
 
-  assign classa_ctrl_en_e0_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_en_e0_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_en_e0_wd = reg_wdata[2];
 
-  assign classa_ctrl_en_e1_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_en_e1_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_en_e1_wd = reg_wdata[3];
 
-  assign classa_ctrl_en_e2_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_en_e2_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_en_e2_wd = reg_wdata[4];
 
-  assign classa_ctrl_en_e3_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_en_e3_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_en_e3_wd = reg_wdata[5];
 
-  assign classa_ctrl_map_e0_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_map_e0_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_map_e0_wd = reg_wdata[7:6];
 
-  assign classa_ctrl_map_e1_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_map_e1_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_map_e1_wd = reg_wdata[9:8];
 
-  assign classa_ctrl_map_e2_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_map_e2_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_map_e2_wd = reg_wdata[11:10];
 
-  assign classa_ctrl_map_e3_we = addr_hit[203] & reg_we & !reg_error;
+  assign classa_ctrl_map_e3_we = addr_hit[219] & reg_we & !reg_error;
   assign classa_ctrl_map_e3_wd = reg_wdata[13:12];
 
-  assign classa_clr_regwen_we = addr_hit[204] & reg_we & !reg_error;
+  assign classa_clr_regwen_we = addr_hit[220] & reg_we & !reg_error;
   assign classa_clr_regwen_wd = reg_wdata[0];
 
-  assign classa_clr_we = addr_hit[205] & reg_we & !reg_error;
+  assign classa_clr_we = addr_hit[221] & reg_we & !reg_error;
   assign classa_clr_wd = reg_wdata[0];
 
-  assign classa_accum_cnt_re = addr_hit[206] & reg_re & !reg_error;
+  assign classa_accum_cnt_re = addr_hit[222] & reg_re & !reg_error;
 
-  assign classa_accum_thresh_we = addr_hit[207] & reg_we & !reg_error;
+  assign classa_accum_thresh_we = addr_hit[223] & reg_we & !reg_error;
   assign classa_accum_thresh_wd = reg_wdata[15:0];
 
-  assign classa_timeout_cyc_we = addr_hit[208] & reg_we & !reg_error;
+  assign classa_timeout_cyc_we = addr_hit[224] & reg_we & !reg_error;
   assign classa_timeout_cyc_wd = reg_wdata[31:0];
 
-  assign classa_phase0_cyc_we = addr_hit[209] & reg_we & !reg_error;
+  assign classa_phase0_cyc_we = addr_hit[225] & reg_we & !reg_error;
   assign classa_phase0_cyc_wd = reg_wdata[31:0];
 
-  assign classa_phase1_cyc_we = addr_hit[210] & reg_we & !reg_error;
+  assign classa_phase1_cyc_we = addr_hit[226] & reg_we & !reg_error;
   assign classa_phase1_cyc_wd = reg_wdata[31:0];
 
-  assign classa_phase2_cyc_we = addr_hit[211] & reg_we & !reg_error;
+  assign classa_phase2_cyc_we = addr_hit[227] & reg_we & !reg_error;
   assign classa_phase2_cyc_wd = reg_wdata[31:0];
 
-  assign classa_phase3_cyc_we = addr_hit[212] & reg_we & !reg_error;
+  assign classa_phase3_cyc_we = addr_hit[228] & reg_we & !reg_error;
   assign classa_phase3_cyc_wd = reg_wdata[31:0];
 
-  assign classa_esc_cnt_re = addr_hit[213] & reg_re & !reg_error;
+  assign classa_esc_cnt_re = addr_hit[229] & reg_re & !reg_error;
 
-  assign classa_state_re = addr_hit[214] & reg_re & !reg_error;
+  assign classa_state_re = addr_hit[230] & reg_re & !reg_error;
 
-  assign classb_regwen_we = addr_hit[215] & reg_we & !reg_error;
+  assign classb_regwen_we = addr_hit[231] & reg_we & !reg_error;
   assign classb_regwen_wd = reg_wdata[0];
 
-  assign classb_ctrl_en_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_en_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_en_wd = reg_wdata[0];
 
-  assign classb_ctrl_lock_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_lock_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_lock_wd = reg_wdata[1];
 
-  assign classb_ctrl_en_e0_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_en_e0_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_en_e0_wd = reg_wdata[2];
 
-  assign classb_ctrl_en_e1_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_en_e1_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_en_e1_wd = reg_wdata[3];
 
-  assign classb_ctrl_en_e2_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_en_e2_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_en_e2_wd = reg_wdata[4];
 
-  assign classb_ctrl_en_e3_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_en_e3_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_en_e3_wd = reg_wdata[5];
 
-  assign classb_ctrl_map_e0_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_map_e0_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_map_e0_wd = reg_wdata[7:6];
 
-  assign classb_ctrl_map_e1_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_map_e1_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_map_e1_wd = reg_wdata[9:8];
 
-  assign classb_ctrl_map_e2_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_map_e2_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_map_e2_wd = reg_wdata[11:10];
 
-  assign classb_ctrl_map_e3_we = addr_hit[216] & reg_we & !reg_error;
+  assign classb_ctrl_map_e3_we = addr_hit[232] & reg_we & !reg_error;
   assign classb_ctrl_map_e3_wd = reg_wdata[13:12];
 
-  assign classb_clr_regwen_we = addr_hit[217] & reg_we & !reg_error;
+  assign classb_clr_regwen_we = addr_hit[233] & reg_we & !reg_error;
   assign classb_clr_regwen_wd = reg_wdata[0];
 
-  assign classb_clr_we = addr_hit[218] & reg_we & !reg_error;
+  assign classb_clr_we = addr_hit[234] & reg_we & !reg_error;
   assign classb_clr_wd = reg_wdata[0];
 
-  assign classb_accum_cnt_re = addr_hit[219] & reg_re & !reg_error;
+  assign classb_accum_cnt_re = addr_hit[235] & reg_re & !reg_error;
 
-  assign classb_accum_thresh_we = addr_hit[220] & reg_we & !reg_error;
+  assign classb_accum_thresh_we = addr_hit[236] & reg_we & !reg_error;
   assign classb_accum_thresh_wd = reg_wdata[15:0];
 
-  assign classb_timeout_cyc_we = addr_hit[221] & reg_we & !reg_error;
+  assign classb_timeout_cyc_we = addr_hit[237] & reg_we & !reg_error;
   assign classb_timeout_cyc_wd = reg_wdata[31:0];
 
-  assign classb_phase0_cyc_we = addr_hit[222] & reg_we & !reg_error;
+  assign classb_phase0_cyc_we = addr_hit[238] & reg_we & !reg_error;
   assign classb_phase0_cyc_wd = reg_wdata[31:0];
 
-  assign classb_phase1_cyc_we = addr_hit[223] & reg_we & !reg_error;
+  assign classb_phase1_cyc_we = addr_hit[239] & reg_we & !reg_error;
   assign classb_phase1_cyc_wd = reg_wdata[31:0];
 
-  assign classb_phase2_cyc_we = addr_hit[224] & reg_we & !reg_error;
+  assign classb_phase2_cyc_we = addr_hit[240] & reg_we & !reg_error;
   assign classb_phase2_cyc_wd = reg_wdata[31:0];
 
-  assign classb_phase3_cyc_we = addr_hit[225] & reg_we & !reg_error;
+  assign classb_phase3_cyc_we = addr_hit[241] & reg_we & !reg_error;
   assign classb_phase3_cyc_wd = reg_wdata[31:0];
 
-  assign classb_esc_cnt_re = addr_hit[226] & reg_re & !reg_error;
+  assign classb_esc_cnt_re = addr_hit[242] & reg_re & !reg_error;
 
-  assign classb_state_re = addr_hit[227] & reg_re & !reg_error;
+  assign classb_state_re = addr_hit[243] & reg_re & !reg_error;
 
-  assign classc_regwen_we = addr_hit[228] & reg_we & !reg_error;
+  assign classc_regwen_we = addr_hit[244] & reg_we & !reg_error;
   assign classc_regwen_wd = reg_wdata[0];
 
-  assign classc_ctrl_en_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_en_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_en_wd = reg_wdata[0];
 
-  assign classc_ctrl_lock_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_lock_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_lock_wd = reg_wdata[1];
 
-  assign classc_ctrl_en_e0_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_en_e0_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_en_e0_wd = reg_wdata[2];
 
-  assign classc_ctrl_en_e1_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_en_e1_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_en_e1_wd = reg_wdata[3];
 
-  assign classc_ctrl_en_e2_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_en_e2_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_en_e2_wd = reg_wdata[4];
 
-  assign classc_ctrl_en_e3_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_en_e3_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_en_e3_wd = reg_wdata[5];
 
-  assign classc_ctrl_map_e0_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_map_e0_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_map_e0_wd = reg_wdata[7:6];
 
-  assign classc_ctrl_map_e1_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_map_e1_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_map_e1_wd = reg_wdata[9:8];
 
-  assign classc_ctrl_map_e2_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_map_e2_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_map_e2_wd = reg_wdata[11:10];
 
-  assign classc_ctrl_map_e3_we = addr_hit[229] & reg_we & !reg_error;
+  assign classc_ctrl_map_e3_we = addr_hit[245] & reg_we & !reg_error;
   assign classc_ctrl_map_e3_wd = reg_wdata[13:12];
 
-  assign classc_clr_regwen_we = addr_hit[230] & reg_we & !reg_error;
+  assign classc_clr_regwen_we = addr_hit[246] & reg_we & !reg_error;
   assign classc_clr_regwen_wd = reg_wdata[0];
 
-  assign classc_clr_we = addr_hit[231] & reg_we & !reg_error;
+  assign classc_clr_we = addr_hit[247] & reg_we & !reg_error;
   assign classc_clr_wd = reg_wdata[0];
 
-  assign classc_accum_cnt_re = addr_hit[232] & reg_re & !reg_error;
+  assign classc_accum_cnt_re = addr_hit[248] & reg_re & !reg_error;
 
-  assign classc_accum_thresh_we = addr_hit[233] & reg_we & !reg_error;
+  assign classc_accum_thresh_we = addr_hit[249] & reg_we & !reg_error;
   assign classc_accum_thresh_wd = reg_wdata[15:0];
 
-  assign classc_timeout_cyc_we = addr_hit[234] & reg_we & !reg_error;
+  assign classc_timeout_cyc_we = addr_hit[250] & reg_we & !reg_error;
   assign classc_timeout_cyc_wd = reg_wdata[31:0];
 
-  assign classc_phase0_cyc_we = addr_hit[235] & reg_we & !reg_error;
+  assign classc_phase0_cyc_we = addr_hit[251] & reg_we & !reg_error;
   assign classc_phase0_cyc_wd = reg_wdata[31:0];
 
-  assign classc_phase1_cyc_we = addr_hit[236] & reg_we & !reg_error;
+  assign classc_phase1_cyc_we = addr_hit[252] & reg_we & !reg_error;
   assign classc_phase1_cyc_wd = reg_wdata[31:0];
 
-  assign classc_phase2_cyc_we = addr_hit[237] & reg_we & !reg_error;
+  assign classc_phase2_cyc_we = addr_hit[253] & reg_we & !reg_error;
   assign classc_phase2_cyc_wd = reg_wdata[31:0];
 
-  assign classc_phase3_cyc_we = addr_hit[238] & reg_we & !reg_error;
+  assign classc_phase3_cyc_we = addr_hit[254] & reg_we & !reg_error;
   assign classc_phase3_cyc_wd = reg_wdata[31:0];
 
-  assign classc_esc_cnt_re = addr_hit[239] & reg_re & !reg_error;
+  assign classc_esc_cnt_re = addr_hit[255] & reg_re & !reg_error;
 
-  assign classc_state_re = addr_hit[240] & reg_re & !reg_error;
+  assign classc_state_re = addr_hit[256] & reg_re & !reg_error;
 
-  assign classd_regwen_we = addr_hit[241] & reg_we & !reg_error;
+  assign classd_regwen_we = addr_hit[257] & reg_we & !reg_error;
   assign classd_regwen_wd = reg_wdata[0];
 
-  assign classd_ctrl_en_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_en_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_en_wd = reg_wdata[0];
 
-  assign classd_ctrl_lock_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_lock_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_lock_wd = reg_wdata[1];
 
-  assign classd_ctrl_en_e0_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_en_e0_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_en_e0_wd = reg_wdata[2];
 
-  assign classd_ctrl_en_e1_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_en_e1_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_en_e1_wd = reg_wdata[3];
 
-  assign classd_ctrl_en_e2_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_en_e2_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_en_e2_wd = reg_wdata[4];
 
-  assign classd_ctrl_en_e3_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_en_e3_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_en_e3_wd = reg_wdata[5];
 
-  assign classd_ctrl_map_e0_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_map_e0_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_map_e0_wd = reg_wdata[7:6];
 
-  assign classd_ctrl_map_e1_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_map_e1_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_map_e1_wd = reg_wdata[9:8];
 
-  assign classd_ctrl_map_e2_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_map_e2_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_map_e2_wd = reg_wdata[11:10];
 
-  assign classd_ctrl_map_e3_we = addr_hit[242] & reg_we & !reg_error;
+  assign classd_ctrl_map_e3_we = addr_hit[258] & reg_we & !reg_error;
   assign classd_ctrl_map_e3_wd = reg_wdata[13:12];
 
-  assign classd_clr_regwen_we = addr_hit[243] & reg_we & !reg_error;
+  assign classd_clr_regwen_we = addr_hit[259] & reg_we & !reg_error;
   assign classd_clr_regwen_wd = reg_wdata[0];
 
-  assign classd_clr_we = addr_hit[244] & reg_we & !reg_error;
+  assign classd_clr_we = addr_hit[260] & reg_we & !reg_error;
   assign classd_clr_wd = reg_wdata[0];
 
-  assign classd_accum_cnt_re = addr_hit[245] & reg_re & !reg_error;
+  assign classd_accum_cnt_re = addr_hit[261] & reg_re & !reg_error;
 
-  assign classd_accum_thresh_we = addr_hit[246] & reg_we & !reg_error;
+  assign classd_accum_thresh_we = addr_hit[262] & reg_we & !reg_error;
   assign classd_accum_thresh_wd = reg_wdata[15:0];
 
-  assign classd_timeout_cyc_we = addr_hit[247] & reg_we & !reg_error;
+  assign classd_timeout_cyc_we = addr_hit[263] & reg_we & !reg_error;
   assign classd_timeout_cyc_wd = reg_wdata[31:0];
 
-  assign classd_phase0_cyc_we = addr_hit[248] & reg_we & !reg_error;
+  assign classd_phase0_cyc_we = addr_hit[264] & reg_we & !reg_error;
   assign classd_phase0_cyc_wd = reg_wdata[31:0];
 
-  assign classd_phase1_cyc_we = addr_hit[249] & reg_we & !reg_error;
+  assign classd_phase1_cyc_we = addr_hit[265] & reg_we & !reg_error;
   assign classd_phase1_cyc_wd = reg_wdata[31:0];
 
-  assign classd_phase2_cyc_we = addr_hit[250] & reg_we & !reg_error;
+  assign classd_phase2_cyc_we = addr_hit[266] & reg_we & !reg_error;
   assign classd_phase2_cyc_wd = reg_wdata[31:0];
 
-  assign classd_phase3_cyc_we = addr_hit[251] & reg_we & !reg_error;
+  assign classd_phase3_cyc_we = addr_hit[267] & reg_we & !reg_error;
   assign classd_phase3_cyc_wd = reg_wdata[31:0];
 
-  assign classd_esc_cnt_re = addr_hit[252] & reg_re & !reg_error;
+  assign classd_esc_cnt_re = addr_hit[268] & reg_re & !reg_error;
 
-  assign classd_state_re = addr_hit[253] & reg_re & !reg_error;
+  assign classd_state_re = addr_hit[269] & reg_re & !reg_error;
 
   // Read data return
   always_comb begin
@@ -10479,618 +11039,682 @@
       end
 
       addr_hit[50]: begin
-        reg_rdata_next[0] = alert_en_0_qs;
+        reg_rdata_next[0] = alert_regwen_44_qs;
       end
 
       addr_hit[51]: begin
-        reg_rdata_next[0] = alert_en_1_qs;
+        reg_rdata_next[0] = alert_regwen_45_qs;
       end
 
       addr_hit[52]: begin
-        reg_rdata_next[0] = alert_en_2_qs;
+        reg_rdata_next[0] = alert_regwen_46_qs;
       end
 
       addr_hit[53]: begin
-        reg_rdata_next[0] = alert_en_3_qs;
+        reg_rdata_next[0] = alert_regwen_47_qs;
       end
 
       addr_hit[54]: begin
-        reg_rdata_next[0] = alert_en_4_qs;
+        reg_rdata_next[0] = alert_en_0_qs;
       end
 
       addr_hit[55]: begin
-        reg_rdata_next[0] = alert_en_5_qs;
+        reg_rdata_next[0] = alert_en_1_qs;
       end
 
       addr_hit[56]: begin
-        reg_rdata_next[0] = alert_en_6_qs;
+        reg_rdata_next[0] = alert_en_2_qs;
       end
 
       addr_hit[57]: begin
-        reg_rdata_next[0] = alert_en_7_qs;
+        reg_rdata_next[0] = alert_en_3_qs;
       end
 
       addr_hit[58]: begin
-        reg_rdata_next[0] = alert_en_8_qs;
+        reg_rdata_next[0] = alert_en_4_qs;
       end
 
       addr_hit[59]: begin
-        reg_rdata_next[0] = alert_en_9_qs;
+        reg_rdata_next[0] = alert_en_5_qs;
       end
 
       addr_hit[60]: begin
-        reg_rdata_next[0] = alert_en_10_qs;
+        reg_rdata_next[0] = alert_en_6_qs;
       end
 
       addr_hit[61]: begin
-        reg_rdata_next[0] = alert_en_11_qs;
+        reg_rdata_next[0] = alert_en_7_qs;
       end
 
       addr_hit[62]: begin
-        reg_rdata_next[0] = alert_en_12_qs;
+        reg_rdata_next[0] = alert_en_8_qs;
       end
 
       addr_hit[63]: begin
-        reg_rdata_next[0] = alert_en_13_qs;
+        reg_rdata_next[0] = alert_en_9_qs;
       end
 
       addr_hit[64]: begin
-        reg_rdata_next[0] = alert_en_14_qs;
+        reg_rdata_next[0] = alert_en_10_qs;
       end
 
       addr_hit[65]: begin
-        reg_rdata_next[0] = alert_en_15_qs;
+        reg_rdata_next[0] = alert_en_11_qs;
       end
 
       addr_hit[66]: begin
-        reg_rdata_next[0] = alert_en_16_qs;
+        reg_rdata_next[0] = alert_en_12_qs;
       end
 
       addr_hit[67]: begin
-        reg_rdata_next[0] = alert_en_17_qs;
+        reg_rdata_next[0] = alert_en_13_qs;
       end
 
       addr_hit[68]: begin
-        reg_rdata_next[0] = alert_en_18_qs;
+        reg_rdata_next[0] = alert_en_14_qs;
       end
 
       addr_hit[69]: begin
-        reg_rdata_next[0] = alert_en_19_qs;
+        reg_rdata_next[0] = alert_en_15_qs;
       end
 
       addr_hit[70]: begin
-        reg_rdata_next[0] = alert_en_20_qs;
+        reg_rdata_next[0] = alert_en_16_qs;
       end
 
       addr_hit[71]: begin
-        reg_rdata_next[0] = alert_en_21_qs;
+        reg_rdata_next[0] = alert_en_17_qs;
       end
 
       addr_hit[72]: begin
-        reg_rdata_next[0] = alert_en_22_qs;
+        reg_rdata_next[0] = alert_en_18_qs;
       end
 
       addr_hit[73]: begin
-        reg_rdata_next[0] = alert_en_23_qs;
+        reg_rdata_next[0] = alert_en_19_qs;
       end
 
       addr_hit[74]: begin
-        reg_rdata_next[0] = alert_en_24_qs;
+        reg_rdata_next[0] = alert_en_20_qs;
       end
 
       addr_hit[75]: begin
-        reg_rdata_next[0] = alert_en_25_qs;
+        reg_rdata_next[0] = alert_en_21_qs;
       end
 
       addr_hit[76]: begin
-        reg_rdata_next[0] = alert_en_26_qs;
+        reg_rdata_next[0] = alert_en_22_qs;
       end
 
       addr_hit[77]: begin
-        reg_rdata_next[0] = alert_en_27_qs;
+        reg_rdata_next[0] = alert_en_23_qs;
       end
 
       addr_hit[78]: begin
-        reg_rdata_next[0] = alert_en_28_qs;
+        reg_rdata_next[0] = alert_en_24_qs;
       end
 
       addr_hit[79]: begin
-        reg_rdata_next[0] = alert_en_29_qs;
+        reg_rdata_next[0] = alert_en_25_qs;
       end
 
       addr_hit[80]: begin
-        reg_rdata_next[0] = alert_en_30_qs;
+        reg_rdata_next[0] = alert_en_26_qs;
       end
 
       addr_hit[81]: begin
-        reg_rdata_next[0] = alert_en_31_qs;
+        reg_rdata_next[0] = alert_en_27_qs;
       end
 
       addr_hit[82]: begin
-        reg_rdata_next[0] = alert_en_32_qs;
+        reg_rdata_next[0] = alert_en_28_qs;
       end
 
       addr_hit[83]: begin
-        reg_rdata_next[0] = alert_en_33_qs;
+        reg_rdata_next[0] = alert_en_29_qs;
       end
 
       addr_hit[84]: begin
-        reg_rdata_next[0] = alert_en_34_qs;
+        reg_rdata_next[0] = alert_en_30_qs;
       end
 
       addr_hit[85]: begin
-        reg_rdata_next[0] = alert_en_35_qs;
+        reg_rdata_next[0] = alert_en_31_qs;
       end
 
       addr_hit[86]: begin
-        reg_rdata_next[0] = alert_en_36_qs;
+        reg_rdata_next[0] = alert_en_32_qs;
       end
 
       addr_hit[87]: begin
-        reg_rdata_next[0] = alert_en_37_qs;
+        reg_rdata_next[0] = alert_en_33_qs;
       end
 
       addr_hit[88]: begin
-        reg_rdata_next[0] = alert_en_38_qs;
+        reg_rdata_next[0] = alert_en_34_qs;
       end
 
       addr_hit[89]: begin
-        reg_rdata_next[0] = alert_en_39_qs;
+        reg_rdata_next[0] = alert_en_35_qs;
       end
 
       addr_hit[90]: begin
-        reg_rdata_next[0] = alert_en_40_qs;
+        reg_rdata_next[0] = alert_en_36_qs;
       end
 
       addr_hit[91]: begin
-        reg_rdata_next[0] = alert_en_41_qs;
+        reg_rdata_next[0] = alert_en_37_qs;
       end
 
       addr_hit[92]: begin
-        reg_rdata_next[0] = alert_en_42_qs;
+        reg_rdata_next[0] = alert_en_38_qs;
       end
 
       addr_hit[93]: begin
-        reg_rdata_next[0] = alert_en_43_qs;
+        reg_rdata_next[0] = alert_en_39_qs;
       end
 
       addr_hit[94]: begin
-        reg_rdata_next[1:0] = alert_class_0_qs;
+        reg_rdata_next[0] = alert_en_40_qs;
       end
 
       addr_hit[95]: begin
-        reg_rdata_next[1:0] = alert_class_1_qs;
+        reg_rdata_next[0] = alert_en_41_qs;
       end
 
       addr_hit[96]: begin
-        reg_rdata_next[1:0] = alert_class_2_qs;
+        reg_rdata_next[0] = alert_en_42_qs;
       end
 
       addr_hit[97]: begin
-        reg_rdata_next[1:0] = alert_class_3_qs;
+        reg_rdata_next[0] = alert_en_43_qs;
       end
 
       addr_hit[98]: begin
-        reg_rdata_next[1:0] = alert_class_4_qs;
+        reg_rdata_next[0] = alert_en_44_qs;
       end
 
       addr_hit[99]: begin
-        reg_rdata_next[1:0] = alert_class_5_qs;
+        reg_rdata_next[0] = alert_en_45_qs;
       end
 
       addr_hit[100]: begin
-        reg_rdata_next[1:0] = alert_class_6_qs;
+        reg_rdata_next[0] = alert_en_46_qs;
       end
 
       addr_hit[101]: begin
-        reg_rdata_next[1:0] = alert_class_7_qs;
+        reg_rdata_next[0] = alert_en_47_qs;
       end
 
       addr_hit[102]: begin
-        reg_rdata_next[1:0] = alert_class_8_qs;
+        reg_rdata_next[1:0] = alert_class_0_qs;
       end
 
       addr_hit[103]: begin
-        reg_rdata_next[1:0] = alert_class_9_qs;
+        reg_rdata_next[1:0] = alert_class_1_qs;
       end
 
       addr_hit[104]: begin
-        reg_rdata_next[1:0] = alert_class_10_qs;
+        reg_rdata_next[1:0] = alert_class_2_qs;
       end
 
       addr_hit[105]: begin
-        reg_rdata_next[1:0] = alert_class_11_qs;
+        reg_rdata_next[1:0] = alert_class_3_qs;
       end
 
       addr_hit[106]: begin
-        reg_rdata_next[1:0] = alert_class_12_qs;
+        reg_rdata_next[1:0] = alert_class_4_qs;
       end
 
       addr_hit[107]: begin
-        reg_rdata_next[1:0] = alert_class_13_qs;
+        reg_rdata_next[1:0] = alert_class_5_qs;
       end
 
       addr_hit[108]: begin
-        reg_rdata_next[1:0] = alert_class_14_qs;
+        reg_rdata_next[1:0] = alert_class_6_qs;
       end
 
       addr_hit[109]: begin
-        reg_rdata_next[1:0] = alert_class_15_qs;
+        reg_rdata_next[1:0] = alert_class_7_qs;
       end
 
       addr_hit[110]: begin
-        reg_rdata_next[1:0] = alert_class_16_qs;
+        reg_rdata_next[1:0] = alert_class_8_qs;
       end
 
       addr_hit[111]: begin
-        reg_rdata_next[1:0] = alert_class_17_qs;
+        reg_rdata_next[1:0] = alert_class_9_qs;
       end
 
       addr_hit[112]: begin
-        reg_rdata_next[1:0] = alert_class_18_qs;
+        reg_rdata_next[1:0] = alert_class_10_qs;
       end
 
       addr_hit[113]: begin
-        reg_rdata_next[1:0] = alert_class_19_qs;
+        reg_rdata_next[1:0] = alert_class_11_qs;
       end
 
       addr_hit[114]: begin
-        reg_rdata_next[1:0] = alert_class_20_qs;
+        reg_rdata_next[1:0] = alert_class_12_qs;
       end
 
       addr_hit[115]: begin
-        reg_rdata_next[1:0] = alert_class_21_qs;
+        reg_rdata_next[1:0] = alert_class_13_qs;
       end
 
       addr_hit[116]: begin
-        reg_rdata_next[1:0] = alert_class_22_qs;
+        reg_rdata_next[1:0] = alert_class_14_qs;
       end
 
       addr_hit[117]: begin
-        reg_rdata_next[1:0] = alert_class_23_qs;
+        reg_rdata_next[1:0] = alert_class_15_qs;
       end
 
       addr_hit[118]: begin
-        reg_rdata_next[1:0] = alert_class_24_qs;
+        reg_rdata_next[1:0] = alert_class_16_qs;
       end
 
       addr_hit[119]: begin
-        reg_rdata_next[1:0] = alert_class_25_qs;
+        reg_rdata_next[1:0] = alert_class_17_qs;
       end
 
       addr_hit[120]: begin
-        reg_rdata_next[1:0] = alert_class_26_qs;
+        reg_rdata_next[1:0] = alert_class_18_qs;
       end
 
       addr_hit[121]: begin
-        reg_rdata_next[1:0] = alert_class_27_qs;
+        reg_rdata_next[1:0] = alert_class_19_qs;
       end
 
       addr_hit[122]: begin
-        reg_rdata_next[1:0] = alert_class_28_qs;
+        reg_rdata_next[1:0] = alert_class_20_qs;
       end
 
       addr_hit[123]: begin
-        reg_rdata_next[1:0] = alert_class_29_qs;
+        reg_rdata_next[1:0] = alert_class_21_qs;
       end
 
       addr_hit[124]: begin
-        reg_rdata_next[1:0] = alert_class_30_qs;
+        reg_rdata_next[1:0] = alert_class_22_qs;
       end
 
       addr_hit[125]: begin
-        reg_rdata_next[1:0] = alert_class_31_qs;
+        reg_rdata_next[1:0] = alert_class_23_qs;
       end
 
       addr_hit[126]: begin
-        reg_rdata_next[1:0] = alert_class_32_qs;
+        reg_rdata_next[1:0] = alert_class_24_qs;
       end
 
       addr_hit[127]: begin
-        reg_rdata_next[1:0] = alert_class_33_qs;
+        reg_rdata_next[1:0] = alert_class_25_qs;
       end
 
       addr_hit[128]: begin
-        reg_rdata_next[1:0] = alert_class_34_qs;
+        reg_rdata_next[1:0] = alert_class_26_qs;
       end
 
       addr_hit[129]: begin
-        reg_rdata_next[1:0] = alert_class_35_qs;
+        reg_rdata_next[1:0] = alert_class_27_qs;
       end
 
       addr_hit[130]: begin
-        reg_rdata_next[1:0] = alert_class_36_qs;
+        reg_rdata_next[1:0] = alert_class_28_qs;
       end
 
       addr_hit[131]: begin
-        reg_rdata_next[1:0] = alert_class_37_qs;
+        reg_rdata_next[1:0] = alert_class_29_qs;
       end
 
       addr_hit[132]: begin
-        reg_rdata_next[1:0] = alert_class_38_qs;
+        reg_rdata_next[1:0] = alert_class_30_qs;
       end
 
       addr_hit[133]: begin
-        reg_rdata_next[1:0] = alert_class_39_qs;
+        reg_rdata_next[1:0] = alert_class_31_qs;
       end
 
       addr_hit[134]: begin
-        reg_rdata_next[1:0] = alert_class_40_qs;
+        reg_rdata_next[1:0] = alert_class_32_qs;
       end
 
       addr_hit[135]: begin
-        reg_rdata_next[1:0] = alert_class_41_qs;
+        reg_rdata_next[1:0] = alert_class_33_qs;
       end
 
       addr_hit[136]: begin
-        reg_rdata_next[1:0] = alert_class_42_qs;
+        reg_rdata_next[1:0] = alert_class_34_qs;
       end
 
       addr_hit[137]: begin
-        reg_rdata_next[1:0] = alert_class_43_qs;
+        reg_rdata_next[1:0] = alert_class_35_qs;
       end
 
       addr_hit[138]: begin
-        reg_rdata_next[0] = alert_cause_0_qs;
+        reg_rdata_next[1:0] = alert_class_36_qs;
       end
 
       addr_hit[139]: begin
-        reg_rdata_next[0] = alert_cause_1_qs;
+        reg_rdata_next[1:0] = alert_class_37_qs;
       end
 
       addr_hit[140]: begin
-        reg_rdata_next[0] = alert_cause_2_qs;
+        reg_rdata_next[1:0] = alert_class_38_qs;
       end
 
       addr_hit[141]: begin
-        reg_rdata_next[0] = alert_cause_3_qs;
+        reg_rdata_next[1:0] = alert_class_39_qs;
       end
 
       addr_hit[142]: begin
-        reg_rdata_next[0] = alert_cause_4_qs;
+        reg_rdata_next[1:0] = alert_class_40_qs;
       end
 
       addr_hit[143]: begin
-        reg_rdata_next[0] = alert_cause_5_qs;
+        reg_rdata_next[1:0] = alert_class_41_qs;
       end
 
       addr_hit[144]: begin
-        reg_rdata_next[0] = alert_cause_6_qs;
+        reg_rdata_next[1:0] = alert_class_42_qs;
       end
 
       addr_hit[145]: begin
-        reg_rdata_next[0] = alert_cause_7_qs;
+        reg_rdata_next[1:0] = alert_class_43_qs;
       end
 
       addr_hit[146]: begin
-        reg_rdata_next[0] = alert_cause_8_qs;
+        reg_rdata_next[1:0] = alert_class_44_qs;
       end
 
       addr_hit[147]: begin
-        reg_rdata_next[0] = alert_cause_9_qs;
+        reg_rdata_next[1:0] = alert_class_45_qs;
       end
 
       addr_hit[148]: begin
-        reg_rdata_next[0] = alert_cause_10_qs;
+        reg_rdata_next[1:0] = alert_class_46_qs;
       end
 
       addr_hit[149]: begin
-        reg_rdata_next[0] = alert_cause_11_qs;
+        reg_rdata_next[1:0] = alert_class_47_qs;
       end
 
       addr_hit[150]: begin
-        reg_rdata_next[0] = alert_cause_12_qs;
+        reg_rdata_next[0] = alert_cause_0_qs;
       end
 
       addr_hit[151]: begin
-        reg_rdata_next[0] = alert_cause_13_qs;
+        reg_rdata_next[0] = alert_cause_1_qs;
       end
 
       addr_hit[152]: begin
-        reg_rdata_next[0] = alert_cause_14_qs;
+        reg_rdata_next[0] = alert_cause_2_qs;
       end
 
       addr_hit[153]: begin
-        reg_rdata_next[0] = alert_cause_15_qs;
+        reg_rdata_next[0] = alert_cause_3_qs;
       end
 
       addr_hit[154]: begin
-        reg_rdata_next[0] = alert_cause_16_qs;
+        reg_rdata_next[0] = alert_cause_4_qs;
       end
 
       addr_hit[155]: begin
-        reg_rdata_next[0] = alert_cause_17_qs;
+        reg_rdata_next[0] = alert_cause_5_qs;
       end
 
       addr_hit[156]: begin
-        reg_rdata_next[0] = alert_cause_18_qs;
+        reg_rdata_next[0] = alert_cause_6_qs;
       end
 
       addr_hit[157]: begin
-        reg_rdata_next[0] = alert_cause_19_qs;
+        reg_rdata_next[0] = alert_cause_7_qs;
       end
 
       addr_hit[158]: begin
-        reg_rdata_next[0] = alert_cause_20_qs;
+        reg_rdata_next[0] = alert_cause_8_qs;
       end
 
       addr_hit[159]: begin
-        reg_rdata_next[0] = alert_cause_21_qs;
+        reg_rdata_next[0] = alert_cause_9_qs;
       end
 
       addr_hit[160]: begin
-        reg_rdata_next[0] = alert_cause_22_qs;
+        reg_rdata_next[0] = alert_cause_10_qs;
       end
 
       addr_hit[161]: begin
-        reg_rdata_next[0] = alert_cause_23_qs;
+        reg_rdata_next[0] = alert_cause_11_qs;
       end
 
       addr_hit[162]: begin
-        reg_rdata_next[0] = alert_cause_24_qs;
+        reg_rdata_next[0] = alert_cause_12_qs;
       end
 
       addr_hit[163]: begin
-        reg_rdata_next[0] = alert_cause_25_qs;
+        reg_rdata_next[0] = alert_cause_13_qs;
       end
 
       addr_hit[164]: begin
-        reg_rdata_next[0] = alert_cause_26_qs;
+        reg_rdata_next[0] = alert_cause_14_qs;
       end
 
       addr_hit[165]: begin
-        reg_rdata_next[0] = alert_cause_27_qs;
+        reg_rdata_next[0] = alert_cause_15_qs;
       end
 
       addr_hit[166]: begin
-        reg_rdata_next[0] = alert_cause_28_qs;
+        reg_rdata_next[0] = alert_cause_16_qs;
       end
 
       addr_hit[167]: begin
-        reg_rdata_next[0] = alert_cause_29_qs;
+        reg_rdata_next[0] = alert_cause_17_qs;
       end
 
       addr_hit[168]: begin
-        reg_rdata_next[0] = alert_cause_30_qs;
+        reg_rdata_next[0] = alert_cause_18_qs;
       end
 
       addr_hit[169]: begin
-        reg_rdata_next[0] = alert_cause_31_qs;
+        reg_rdata_next[0] = alert_cause_19_qs;
       end
 
       addr_hit[170]: begin
-        reg_rdata_next[0] = alert_cause_32_qs;
+        reg_rdata_next[0] = alert_cause_20_qs;
       end
 
       addr_hit[171]: begin
-        reg_rdata_next[0] = alert_cause_33_qs;
+        reg_rdata_next[0] = alert_cause_21_qs;
       end
 
       addr_hit[172]: begin
-        reg_rdata_next[0] = alert_cause_34_qs;
+        reg_rdata_next[0] = alert_cause_22_qs;
       end
 
       addr_hit[173]: begin
-        reg_rdata_next[0] = alert_cause_35_qs;
+        reg_rdata_next[0] = alert_cause_23_qs;
       end
 
       addr_hit[174]: begin
-        reg_rdata_next[0] = alert_cause_36_qs;
+        reg_rdata_next[0] = alert_cause_24_qs;
       end
 
       addr_hit[175]: begin
-        reg_rdata_next[0] = alert_cause_37_qs;
+        reg_rdata_next[0] = alert_cause_25_qs;
       end
 
       addr_hit[176]: begin
-        reg_rdata_next[0] = alert_cause_38_qs;
+        reg_rdata_next[0] = alert_cause_26_qs;
       end
 
       addr_hit[177]: begin
-        reg_rdata_next[0] = alert_cause_39_qs;
+        reg_rdata_next[0] = alert_cause_27_qs;
       end
 
       addr_hit[178]: begin
-        reg_rdata_next[0] = alert_cause_40_qs;
+        reg_rdata_next[0] = alert_cause_28_qs;
       end
 
       addr_hit[179]: begin
-        reg_rdata_next[0] = alert_cause_41_qs;
+        reg_rdata_next[0] = alert_cause_29_qs;
       end
 
       addr_hit[180]: begin
-        reg_rdata_next[0] = alert_cause_42_qs;
+        reg_rdata_next[0] = alert_cause_30_qs;
       end
 
       addr_hit[181]: begin
-        reg_rdata_next[0] = alert_cause_43_qs;
+        reg_rdata_next[0] = alert_cause_31_qs;
       end
 
       addr_hit[182]: begin
-        reg_rdata_next[0] = loc_alert_regwen_0_qs;
+        reg_rdata_next[0] = alert_cause_32_qs;
       end
 
       addr_hit[183]: begin
-        reg_rdata_next[0] = loc_alert_regwen_1_qs;
+        reg_rdata_next[0] = alert_cause_33_qs;
       end
 
       addr_hit[184]: begin
-        reg_rdata_next[0] = loc_alert_regwen_2_qs;
+        reg_rdata_next[0] = alert_cause_34_qs;
       end
 
       addr_hit[185]: begin
-        reg_rdata_next[0] = loc_alert_regwen_3_qs;
+        reg_rdata_next[0] = alert_cause_35_qs;
       end
 
       addr_hit[186]: begin
-        reg_rdata_next[0] = loc_alert_regwen_4_qs;
+        reg_rdata_next[0] = alert_cause_36_qs;
       end
 
       addr_hit[187]: begin
-        reg_rdata_next[0] = loc_alert_en_0_qs;
+        reg_rdata_next[0] = alert_cause_37_qs;
       end
 
       addr_hit[188]: begin
-        reg_rdata_next[0] = loc_alert_en_1_qs;
+        reg_rdata_next[0] = alert_cause_38_qs;
       end
 
       addr_hit[189]: begin
-        reg_rdata_next[0] = loc_alert_en_2_qs;
+        reg_rdata_next[0] = alert_cause_39_qs;
       end
 
       addr_hit[190]: begin
-        reg_rdata_next[0] = loc_alert_en_3_qs;
+        reg_rdata_next[0] = alert_cause_40_qs;
       end
 
       addr_hit[191]: begin
-        reg_rdata_next[0] = loc_alert_en_4_qs;
+        reg_rdata_next[0] = alert_cause_41_qs;
       end
 
       addr_hit[192]: begin
-        reg_rdata_next[1:0] = loc_alert_class_0_qs;
+        reg_rdata_next[0] = alert_cause_42_qs;
       end
 
       addr_hit[193]: begin
-        reg_rdata_next[1:0] = loc_alert_class_1_qs;
+        reg_rdata_next[0] = alert_cause_43_qs;
       end
 
       addr_hit[194]: begin
-        reg_rdata_next[1:0] = loc_alert_class_2_qs;
+        reg_rdata_next[0] = alert_cause_44_qs;
       end
 
       addr_hit[195]: begin
-        reg_rdata_next[1:0] = loc_alert_class_3_qs;
+        reg_rdata_next[0] = alert_cause_45_qs;
       end
 
       addr_hit[196]: begin
-        reg_rdata_next[1:0] = loc_alert_class_4_qs;
+        reg_rdata_next[0] = alert_cause_46_qs;
       end
 
       addr_hit[197]: begin
-        reg_rdata_next[0] = loc_alert_cause_0_qs;
+        reg_rdata_next[0] = alert_cause_47_qs;
       end
 
       addr_hit[198]: begin
-        reg_rdata_next[0] = loc_alert_cause_1_qs;
+        reg_rdata_next[0] = loc_alert_regwen_0_qs;
       end
 
       addr_hit[199]: begin
-        reg_rdata_next[0] = loc_alert_cause_2_qs;
+        reg_rdata_next[0] = loc_alert_regwen_1_qs;
       end
 
       addr_hit[200]: begin
-        reg_rdata_next[0] = loc_alert_cause_3_qs;
+        reg_rdata_next[0] = loc_alert_regwen_2_qs;
       end
 
       addr_hit[201]: begin
-        reg_rdata_next[0] = loc_alert_cause_4_qs;
+        reg_rdata_next[0] = loc_alert_regwen_3_qs;
       end
 
       addr_hit[202]: begin
-        reg_rdata_next[0] = classa_regwen_qs;
+        reg_rdata_next[0] = loc_alert_regwen_4_qs;
       end
 
       addr_hit[203]: begin
+        reg_rdata_next[0] = loc_alert_en_0_qs;
+      end
+
+      addr_hit[204]: begin
+        reg_rdata_next[0] = loc_alert_en_1_qs;
+      end
+
+      addr_hit[205]: begin
+        reg_rdata_next[0] = loc_alert_en_2_qs;
+      end
+
+      addr_hit[206]: begin
+        reg_rdata_next[0] = loc_alert_en_3_qs;
+      end
+
+      addr_hit[207]: begin
+        reg_rdata_next[0] = loc_alert_en_4_qs;
+      end
+
+      addr_hit[208]: begin
+        reg_rdata_next[1:0] = loc_alert_class_0_qs;
+      end
+
+      addr_hit[209]: begin
+        reg_rdata_next[1:0] = loc_alert_class_1_qs;
+      end
+
+      addr_hit[210]: begin
+        reg_rdata_next[1:0] = loc_alert_class_2_qs;
+      end
+
+      addr_hit[211]: begin
+        reg_rdata_next[1:0] = loc_alert_class_3_qs;
+      end
+
+      addr_hit[212]: begin
+        reg_rdata_next[1:0] = loc_alert_class_4_qs;
+      end
+
+      addr_hit[213]: begin
+        reg_rdata_next[0] = loc_alert_cause_0_qs;
+      end
+
+      addr_hit[214]: begin
+        reg_rdata_next[0] = loc_alert_cause_1_qs;
+      end
+
+      addr_hit[215]: begin
+        reg_rdata_next[0] = loc_alert_cause_2_qs;
+      end
+
+      addr_hit[216]: begin
+        reg_rdata_next[0] = loc_alert_cause_3_qs;
+      end
+
+      addr_hit[217]: begin
+        reg_rdata_next[0] = loc_alert_cause_4_qs;
+      end
+
+      addr_hit[218]: begin
+        reg_rdata_next[0] = classa_regwen_qs;
+      end
+
+      addr_hit[219]: begin
         reg_rdata_next[0] = classa_ctrl_en_qs;
         reg_rdata_next[1] = classa_ctrl_lock_qs;
         reg_rdata_next[2] = classa_ctrl_en_e0_qs;
@@ -11103,55 +11727,55 @@
         reg_rdata_next[13:12] = classa_ctrl_map_e3_qs;
       end
 
-      addr_hit[204]: begin
+      addr_hit[220]: begin
         reg_rdata_next[0] = classa_clr_regwen_qs;
       end
 
-      addr_hit[205]: begin
+      addr_hit[221]: begin
         reg_rdata_next[0] = '0;
       end
 
-      addr_hit[206]: begin
+      addr_hit[222]: begin
         reg_rdata_next[15:0] = classa_accum_cnt_qs;
       end
 
-      addr_hit[207]: begin
+      addr_hit[223]: begin
         reg_rdata_next[15:0] = classa_accum_thresh_qs;
       end
 
-      addr_hit[208]: begin
+      addr_hit[224]: begin
         reg_rdata_next[31:0] = classa_timeout_cyc_qs;
       end
 
-      addr_hit[209]: begin
+      addr_hit[225]: begin
         reg_rdata_next[31:0] = classa_phase0_cyc_qs;
       end
 
-      addr_hit[210]: begin
+      addr_hit[226]: begin
         reg_rdata_next[31:0] = classa_phase1_cyc_qs;
       end
 
-      addr_hit[211]: begin
+      addr_hit[227]: begin
         reg_rdata_next[31:0] = classa_phase2_cyc_qs;
       end
 
-      addr_hit[212]: begin
+      addr_hit[228]: begin
         reg_rdata_next[31:0] = classa_phase3_cyc_qs;
       end
 
-      addr_hit[213]: begin
+      addr_hit[229]: begin
         reg_rdata_next[31:0] = classa_esc_cnt_qs;
       end
 
-      addr_hit[214]: begin
+      addr_hit[230]: begin
         reg_rdata_next[2:0] = classa_state_qs;
       end
 
-      addr_hit[215]: begin
+      addr_hit[231]: begin
         reg_rdata_next[0] = classb_regwen_qs;
       end
 
-      addr_hit[216]: begin
+      addr_hit[232]: begin
         reg_rdata_next[0] = classb_ctrl_en_qs;
         reg_rdata_next[1] = classb_ctrl_lock_qs;
         reg_rdata_next[2] = classb_ctrl_en_e0_qs;
@@ -11164,55 +11788,55 @@
         reg_rdata_next[13:12] = classb_ctrl_map_e3_qs;
       end
 
-      addr_hit[217]: begin
+      addr_hit[233]: begin
         reg_rdata_next[0] = classb_clr_regwen_qs;
       end
 
-      addr_hit[218]: begin
+      addr_hit[234]: begin
         reg_rdata_next[0] = '0;
       end
 
-      addr_hit[219]: begin
+      addr_hit[235]: begin
         reg_rdata_next[15:0] = classb_accum_cnt_qs;
       end
 
-      addr_hit[220]: begin
+      addr_hit[236]: begin
         reg_rdata_next[15:0] = classb_accum_thresh_qs;
       end
 
-      addr_hit[221]: begin
+      addr_hit[237]: begin
         reg_rdata_next[31:0] = classb_timeout_cyc_qs;
       end
 
-      addr_hit[222]: begin
+      addr_hit[238]: begin
         reg_rdata_next[31:0] = classb_phase0_cyc_qs;
       end
 
-      addr_hit[223]: begin
+      addr_hit[239]: begin
         reg_rdata_next[31:0] = classb_phase1_cyc_qs;
       end
 
-      addr_hit[224]: begin
+      addr_hit[240]: begin
         reg_rdata_next[31:0] = classb_phase2_cyc_qs;
       end
 
-      addr_hit[225]: begin
+      addr_hit[241]: begin
         reg_rdata_next[31:0] = classb_phase3_cyc_qs;
       end
 
-      addr_hit[226]: begin
+      addr_hit[242]: begin
         reg_rdata_next[31:0] = classb_esc_cnt_qs;
       end
 
-      addr_hit[227]: begin
+      addr_hit[243]: begin
         reg_rdata_next[2:0] = classb_state_qs;
       end
 
-      addr_hit[228]: begin
+      addr_hit[244]: begin
         reg_rdata_next[0] = classc_regwen_qs;
       end
 
-      addr_hit[229]: begin
+      addr_hit[245]: begin
         reg_rdata_next[0] = classc_ctrl_en_qs;
         reg_rdata_next[1] = classc_ctrl_lock_qs;
         reg_rdata_next[2] = classc_ctrl_en_e0_qs;
@@ -11225,55 +11849,55 @@
         reg_rdata_next[13:12] = classc_ctrl_map_e3_qs;
       end
 
-      addr_hit[230]: begin
+      addr_hit[246]: begin
         reg_rdata_next[0] = classc_clr_regwen_qs;
       end
 
-      addr_hit[231]: begin
+      addr_hit[247]: begin
         reg_rdata_next[0] = '0;
       end
 
-      addr_hit[232]: begin
+      addr_hit[248]: begin
         reg_rdata_next[15:0] = classc_accum_cnt_qs;
       end
 
-      addr_hit[233]: begin
+      addr_hit[249]: begin
         reg_rdata_next[15:0] = classc_accum_thresh_qs;
       end
 
-      addr_hit[234]: begin
+      addr_hit[250]: begin
         reg_rdata_next[31:0] = classc_timeout_cyc_qs;
       end
 
-      addr_hit[235]: begin
+      addr_hit[251]: begin
         reg_rdata_next[31:0] = classc_phase0_cyc_qs;
       end
 
-      addr_hit[236]: begin
+      addr_hit[252]: begin
         reg_rdata_next[31:0] = classc_phase1_cyc_qs;
       end
 
-      addr_hit[237]: begin
+      addr_hit[253]: begin
         reg_rdata_next[31:0] = classc_phase2_cyc_qs;
       end
 
-      addr_hit[238]: begin
+      addr_hit[254]: begin
         reg_rdata_next[31:0] = classc_phase3_cyc_qs;
       end
 
-      addr_hit[239]: begin
+      addr_hit[255]: begin
         reg_rdata_next[31:0] = classc_esc_cnt_qs;
       end
 
-      addr_hit[240]: begin
+      addr_hit[256]: begin
         reg_rdata_next[2:0] = classc_state_qs;
       end
 
-      addr_hit[241]: begin
+      addr_hit[257]: begin
         reg_rdata_next[0] = classd_regwen_qs;
       end
 
-      addr_hit[242]: begin
+      addr_hit[258]: begin
         reg_rdata_next[0] = classd_ctrl_en_qs;
         reg_rdata_next[1] = classd_ctrl_lock_qs;
         reg_rdata_next[2] = classd_ctrl_en_e0_qs;
@@ -11286,47 +11910,47 @@
         reg_rdata_next[13:12] = classd_ctrl_map_e3_qs;
       end
 
-      addr_hit[243]: begin
+      addr_hit[259]: begin
         reg_rdata_next[0] = classd_clr_regwen_qs;
       end
 
-      addr_hit[244]: begin
+      addr_hit[260]: begin
         reg_rdata_next[0] = '0;
       end
 
-      addr_hit[245]: begin
+      addr_hit[261]: begin
         reg_rdata_next[15:0] = classd_accum_cnt_qs;
       end
 
-      addr_hit[246]: begin
+      addr_hit[262]: begin
         reg_rdata_next[15:0] = classd_accum_thresh_qs;
       end
 
-      addr_hit[247]: begin
+      addr_hit[263]: begin
         reg_rdata_next[31:0] = classd_timeout_cyc_qs;
       end
 
-      addr_hit[248]: begin
+      addr_hit[264]: begin
         reg_rdata_next[31:0] = classd_phase0_cyc_qs;
       end
 
-      addr_hit[249]: begin
+      addr_hit[265]: begin
         reg_rdata_next[31:0] = classd_phase1_cyc_qs;
       end
 
-      addr_hit[250]: begin
+      addr_hit[266]: begin
         reg_rdata_next[31:0] = classd_phase2_cyc_qs;
       end
 
-      addr_hit[251]: begin
+      addr_hit[267]: begin
         reg_rdata_next[31:0] = classd_phase3_cyc_qs;
       end
 
-      addr_hit[252]: begin
+      addr_hit[268]: begin
         reg_rdata_next[31:0] = classd_esc_cnt_qs;
       end
 
-      addr_hit[253]: begin
+      addr_hit[269]: begin
         reg_rdata_next[2:0] = classd_state_qs;
       end
 

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 5a5558f..c46dc83 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

@@ -1061,7 +1061,9 @@
 
 
 
-  uart u_uart0 (
+  uart #(
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[0:0])
+  ) u_uart0 (
 
       // Input
       .cio_rx_i    (cio_uart0_rx_p2d),
@@ -1079,6 +1081,9 @@
       .intr_rx_break_err_o  (intr_uart0_rx_break_err),
       .intr_rx_timeout_o    (intr_uart0_rx_timeout),
       .intr_rx_parity_err_o (intr_uart0_rx_parity_err),
+      // [0]: fatal_fault
+      .alert_tx_o  ( alert_tx[0:0] ),
+      .alert_rx_i  ( alert_rx[0:0] ),
 
       // Inter-module signals
       .tl_i(uart0_tl_req),
@@ -1089,7 +1094,9 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
   );
 
-  uart u_uart1 (
+  uart #(
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:1])
+  ) u_uart1 (
 
       // Input
       .cio_rx_i    (cio_uart1_rx_p2d),
@@ -1107,6 +1114,9 @@
       .intr_rx_break_err_o  (intr_uart1_rx_break_err),
       .intr_rx_timeout_o    (intr_uart1_rx_timeout),
       .intr_rx_parity_err_o (intr_uart1_rx_parity_err),
+      // [1]: fatal_fault
+      .alert_tx_o  ( alert_tx[1:1] ),
+      .alert_rx_i  ( alert_rx[1:1] ),
 
       // Inter-module signals
       .tl_i(uart1_tl_req),
@@ -1117,7 +1127,9 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
   );
 
-  uart u_uart2 (
+  uart #(
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[2:2])
+  ) u_uart2 (
 
       // Input
       .cio_rx_i    (cio_uart2_rx_p2d),
@@ -1135,6 +1147,9 @@
       .intr_rx_break_err_o  (intr_uart2_rx_break_err),
       .intr_rx_timeout_o    (intr_uart2_rx_timeout),
       .intr_rx_parity_err_o (intr_uart2_rx_parity_err),
+      // [2]: fatal_fault
+      .alert_tx_o  ( alert_tx[2:2] ),
+      .alert_rx_i  ( alert_rx[2:2] ),
 
       // Inter-module signals
       .tl_i(uart2_tl_req),
@@ -1145,7 +1160,9 @@
       .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
   );
 
-  uart u_uart3 (
+  uart #(
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:3])
+  ) u_uart3 (
 
       // Input
       .cio_rx_i    (cio_uart3_rx_p2d),
@@ -1163,6 +1180,9 @@
       .intr_rx_break_err_o  (intr_uart3_rx_break_err),
       .intr_rx_timeout_o    (intr_uart3_rx_timeout),
       .intr_rx_parity_err_o (intr_uart3_rx_parity_err),
+      // [3]: fatal_fault
+      .alert_tx_o  ( alert_tx[3:3] ),
+      .alert_rx_i  ( alert_rx[3:3] ),
 
       // Inter-module signals
       .tl_i(uart3_tl_req),
@@ -1174,7 +1194,7 @@
   );
 
   gpio #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[0:0])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[4:4])
   ) u_gpio (
 
       // Input
@@ -1186,9 +1206,9 @@
 
       // Interrupt
       .intr_gpio_o (intr_gpio_gpio),
-      // [0]: fatal_fault
-      .alert_tx_o  ( alert_tx[0:0] ),
-      .alert_rx_i  ( alert_rx[0:0] ),
+      // [4]: fatal_fault
+      .alert_tx_o  ( alert_tx[4:4] ),
+      .alert_rx_i  ( alert_rx[4:4] ),
 
       // Inter-module signals
       .tl_i(gpio_tl_req),
@@ -1200,7 +1220,7 @@
   );
 
   spi_device #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:1])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[5:5])
   ) u_spi_device (
 
       // Input
@@ -1219,9 +1239,9 @@
       .intr_rxerr_o       (intr_spi_device_rxerr),
       .intr_rxoverflow_o  (intr_spi_device_rxoverflow),
       .intr_txunderflow_o (intr_spi_device_txunderflow),
-      // [1]: fatal_fault
-      .alert_tx_o  ( alert_tx[1:1] ),
-      .alert_rx_i  ( alert_rx[1:1] ),
+      // [5]: fatal_fault
+      .alert_tx_o  ( alert_tx[5:5] ),
+      .alert_rx_i  ( alert_rx[5:5] ),
 
       // Inter-module signals
       .ram_cfg_i(ast_ram_2p_cfg),
@@ -1240,7 +1260,7 @@
   );
 
   spi_host #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[2:2])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[6:6])
   ) u_spi_host0 (
 
       // Input
@@ -1257,9 +1277,9 @@
       // Interrupt
       .intr_error_o     (intr_spi_host0_error),
       .intr_spi_event_o (intr_spi_host0_spi_event),
-      // [2]: fatal_fault
-      .alert_tx_o  ( alert_tx[2:2] ),
-      .alert_rx_i  ( alert_rx[2:2] ),
+      // [6]: fatal_fault
+      .alert_tx_o  ( alert_tx[6:6] ),
+      .alert_rx_i  ( alert_rx[6:6] ),
 
       // Inter-module signals
       .passthrough_i(spi_device_passthrough_req),
@@ -1276,7 +1296,7 @@
   );
 
   spi_host #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:3])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[7:7])
   ) u_spi_host1 (
 
       // Input
@@ -1293,9 +1313,9 @@
       // Interrupt
       .intr_error_o     (intr_spi_host1_error),
       .intr_spi_event_o (intr_spi_host1_spi_event),
-      // [3]: fatal_fault
-      .alert_tx_o  ( alert_tx[3:3] ),
-      .alert_rx_i  ( alert_rx[3:3] ),
+      // [7]: fatal_fault
+      .alert_tx_o  ( alert_tx[7:7] ),
+      .alert_rx_i  ( alert_rx[7:7] ),
 
       // Inter-module signals
       .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
@@ -1429,7 +1449,7 @@
   );
 
   pattgen #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[4:4])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:8])
   ) u_pattgen (
 
       // Output
@@ -1445,9 +1465,9 @@
       // Interrupt
       .intr_done_ch0_o (intr_pattgen_done_ch0),
       .intr_done_ch1_o (intr_pattgen_done_ch1),
-      // [4]: fatal_fault
-      .alert_tx_o  ( alert_tx[4:4] ),
-      .alert_rx_i  ( alert_rx[4:4] ),
+      // [8]: fatal_fault
+      .alert_tx_o  ( alert_tx[8:8] ),
+      .alert_rx_i  ( alert_rx[8:8] ),
 
       // Inter-module signals
       .tl_i(pattgen_tl_req),
@@ -1541,7 +1561,7 @@
   );
 
   otp_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[6:5]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:9]),
     .MemInitFile(OtpCtrlMemInitFile),
     .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
     .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm)
@@ -1550,10 +1570,10 @@
       // Interrupt
       .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
       .intr_otp_error_o          (intr_otp_ctrl_otp_error),
-      // [5]: fatal_macro_error
-      // [6]: fatal_check_error
-      .alert_tx_o  ( alert_tx[6:5] ),
-      .alert_rx_i  ( alert_rx[6:5] ),
+      // [9]: fatal_macro_error
+      // [10]: fatal_check_error
+      .alert_tx_o  ( alert_tx[10:9] ),
+      .alert_rx_i  ( alert_rx[10:9] ),
 
       // Inter-module signals
       .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
@@ -1594,16 +1614,16 @@
   );
 
   lc_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:7]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[13:11]),
     .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
     .RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma),
     .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction)
   ) u_lc_ctrl (
-      // [7]: fatal_prog_error
-      // [8]: fatal_state_error
-      // [9]: fatal_bus_integ_error
-      .alert_tx_o  ( alert_tx[9:7] ),
-      .alert_rx_i  ( alert_rx[9:7] ),
+      // [11]: fatal_prog_error
+      // [12]: fatal_state_error
+      // [13]: fatal_bus_integ_error
+      .alert_tx_o  ( alert_tx[13:11] ),
+      .alert_rx_i  ( alert_rx[13:11] ),
 
       // Inter-module signals
       .jtag_i(pinmux_aon_lc_jtag_req),
@@ -1851,12 +1871,12 @@
   );
 
   pinmux #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[14:14]),
     .TargetCfg(PinmuxAonTargetCfg)
   ) u_pinmux_aon (
-      // [10]: fatal_fault
-      .alert_tx_o  ( alert_tx[10:10] ),
-      .alert_rx_i  ( alert_rx[10:10] ),
+      // [14]: fatal_fault
+      .alert_tx_o  ( alert_tx[14:14] ),
+      .alert_rx_i  ( alert_rx[14:14] ),
 
       // Inter-module signals
       .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
@@ -1930,25 +1950,25 @@
   );
 
   sensor_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:11])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:15])
   ) u_sensor_ctrl_aon (
 
       // Output
       .cio_ast_debug_out_o    (cio_sensor_ctrl_aon_ast_debug_out_d2p),
       .cio_ast_debug_out_en_o (cio_sensor_ctrl_aon_ast_debug_out_en_d2p),
-      // [11]: recov_as
-      // [12]: recov_cg
-      // [13]: recov_gd
-      // [14]: recov_ts_hi
-      // [15]: recov_ts_lo
-      // [16]: recov_fla
-      // [17]: recov_otp
-      // [18]: recov_ot0
-      // [19]: recov_ot1
-      // [20]: recov_ot2
-      // [21]: recov_ot3
-      .alert_tx_o  ( alert_tx[21:11] ),
-      .alert_rx_i  ( alert_rx[21:11] ),
+      // [15]: recov_as
+      // [16]: recov_cg
+      // [17]: recov_gd
+      // [18]: recov_ts_hi
+      // [19]: recov_ts_lo
+      // [20]: recov_fla
+      // [21]: recov_otp
+      // [22]: recov_ot0
+      // [23]: recov_ot1
+      // [24]: recov_ot2
+      // [25]: recov_ot3
+      .alert_tx_o  ( alert_tx[25:15] ),
+      .alert_rx_i  ( alert_rx[25:15] ),
 
       // Inter-module signals
       .ast_alert_i(sensor_ctrl_ast_alert_req_i),
@@ -1965,16 +1985,16 @@
   );
 
   sram_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:22]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:26]),
     .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey),
     .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce),
     .RndCnstSramLfsrPerm(RndCnstSramCtrlRetAonSramLfsrPerm),
     .InstrExec(SramCtrlRetAonInstrExec)
   ) u_sram_ctrl_ret_aon (
-      // [22]: fatal_intg_error
-      // [23]: fatal_parity_error
-      .alert_tx_o  ( alert_tx[23:22] ),
-      .alert_rx_i  ( alert_rx[23:22] ),
+      // [26]: fatal_intg_error
+      // [27]: fatal_parity_error
+      .alert_tx_o  ( alert_tx[27:26] ),
+      .alert_rx_i  ( alert_rx[27:26] ),
 
       // Inter-module signals
       .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]),
@@ -1999,7 +2019,7 @@
   );
 
   flash_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:24]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:28]),
     .RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
     .RndCnstDataKey(RndCnstFlashCtrlDataKey),
     .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
@@ -2022,12 +2042,12 @@
       .intr_rd_lvl_o     (intr_flash_ctrl_rd_lvl),
       .intr_op_done_o    (intr_flash_ctrl_op_done),
       .intr_err_o        (intr_flash_ctrl_err),
-      // [24]: recov_err
-      // [25]: recov_mp_err
-      // [26]: recov_ecc_err
-      // [27]: fatal_intg_err
-      .alert_tx_o  ( alert_tx[27:24] ),
-      .alert_rx_i  ( alert_rx[27:24] ),
+      // [28]: recov_err
+      // [29]: recov_mp_err
+      // [30]: recov_ecc_err
+      // [31]: fatal_intg_err
+      .alert_tx_o  ( alert_tx[31:28] ),
+      .alert_rx_i  ( alert_rx[31:28] ),
 
       // Inter-module signals
       .flash_o(flash_ctrl_flash_req),
@@ -2073,7 +2093,7 @@
   );
 
   aes #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:28]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]),
     .AES192Enable(1'b1),
     .Masking(AesMasking),
     .SBoxImpl(AesSBoxImpl),
@@ -2086,10 +2106,10 @@
     .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
     .RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm)
   ) u_aes (
-      // [28]: recov_ctrl_update_err
-      // [29]: fatal_fault
-      .alert_tx_o  ( alert_tx[29:28] ),
-      .alert_rx_i  ( alert_rx[29:28] ),
+      // [32]: recov_ctrl_update_err
+      // [33]: fatal_fault
+      .alert_tx_o  ( alert_tx[33:32] ),
+      .alert_rx_i  ( alert_rx[33:32] ),
 
       // Inter-module signals
       .idle_o(clkmgr_aon_idle[0]),
@@ -2107,16 +2127,16 @@
   );
 
   hmac #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34])
   ) u_hmac (
 
       // Interrupt
       .intr_hmac_done_o  (intr_hmac_hmac_done),
       .intr_fifo_empty_o (intr_hmac_fifo_empty),
       .intr_hmac_err_o   (intr_hmac_hmac_err),
-      // [30]: fatal_fault
-      .alert_tx_o  ( alert_tx[30:30] ),
-      .alert_rx_i  ( alert_rx[30:30] ),
+      // [34]: fatal_fault
+      .alert_tx_o  ( alert_tx[34:34] ),
+      .alert_rx_i  ( alert_rx[34:34] ),
 
       // Inter-module signals
       .idle_o(clkmgr_aon_idle[1]),
@@ -2129,7 +2149,7 @@
   );
 
   kmac #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:35]),
     .EnMasking(KmacEnMasking),
     .ReuseShare(KmacReuseShare)
   ) u_kmac (
@@ -2138,9 +2158,9 @@
       .intr_kmac_done_o  (intr_kmac_kmac_done),
       .intr_fifo_empty_o (intr_kmac_fifo_empty),
       .intr_kmac_err_o   (intr_kmac_kmac_err),
-      // [31]: fatal_fault
-      .alert_tx_o  ( alert_tx[31:31] ),
-      .alert_rx_i  ( alert_rx[31:31] ),
+      // [35]: fatal_fault
+      .alert_tx_o  ( alert_tx[35:35] ),
+      .alert_rx_i  ( alert_rx[35:35] ),
 
       // Inter-module signals
       .keymgr_key_i(keymgr_kmac_key),
@@ -2160,7 +2180,7 @@
   );
 
   keymgr #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:36]),
     .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
     .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
     .RndCnstRandPerm(RndCnstKeymgrRandPerm),
@@ -2178,10 +2198,10 @@
 
       // Interrupt
       .intr_op_done_o (intr_keymgr_op_done),
-      // [32]: fatal_fault_err
-      // [33]: recov_operation_err
-      .alert_tx_o  ( alert_tx[33:32] ),
-      .alert_rx_i  ( alert_rx[33:32] ),
+      // [36]: fatal_fault_err
+      // [37]: recov_operation_err
+      .alert_tx_o  ( alert_tx[37:36] ),
+      .alert_rx_i  ( alert_rx[37:36] ),
 
       // Inter-module signals
       .edn_o(edn0_edn_req[0]),
@@ -2208,7 +2228,7 @@
   );
 
   csrng #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:38]),
     .SBoxImpl(CsrngSBoxImpl)
   ) u_csrng (
 
@@ -2217,9 +2237,9 @@
       .intr_cs_entropy_req_o  (intr_csrng_cs_entropy_req),
       .intr_cs_hw_inst_exc_o  (intr_csrng_cs_hw_inst_exc),
       .intr_cs_fatal_err_o    (intr_csrng_cs_fatal_err),
-      // [34]: fatal_alert
-      .alert_tx_o  ( alert_tx[34:34] ),
-      .alert_rx_i  ( alert_rx[34:34] ),
+      // [38]: fatal_alert
+      .alert_tx_o  ( alert_tx[38:38] ),
+      .alert_rx_i  ( alert_rx[38:38] ),
 
       // Inter-module signals
       .csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2239,7 +2259,7 @@
   );
 
   entropy_src #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[36:35]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:39]),
     .Stub(EntropySrcStub)
   ) u_entropy_src (
 
@@ -2248,10 +2268,10 @@
       .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
       .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
       .intr_es_fatal_err_o          (intr_entropy_src_es_fatal_err),
-      // [35]: recov_alert
-      // [36]: fatal_alert
-      .alert_tx_o  ( alert_tx[36:35] ),
-      .alert_rx_i  ( alert_rx[36:35] ),
+      // [39]: recov_alert
+      // [40]: fatal_alert
+      .alert_tx_o  ( alert_tx[40:39] ),
+      .alert_rx_i  ( alert_rx[40:39] ),
 
       // Inter-module signals
       .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2274,15 +2294,15 @@
   );
 
   edn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:37])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41])
   ) u_edn0 (
 
       // Interrupt
       .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
       .intr_edn_fatal_err_o    (intr_edn0_edn_fatal_err),
-      // [37]: fatal_alert
-      .alert_tx_o  ( alert_tx[37:37] ),
-      .alert_rx_i  ( alert_rx[37:37] ),
+      // [41]: fatal_alert
+      .alert_tx_o  ( alert_tx[41:41] ),
+      .alert_rx_i  ( alert_rx[41:41] ),
 
       // Inter-module signals
       .csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2298,15 +2318,15 @@
   );
 
   edn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:38])
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:42])
   ) u_edn1 (
 
       // Interrupt
       .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
       .intr_edn_fatal_err_o    (intr_edn1_edn_fatal_err),
-      // [38]: fatal_alert
-      .alert_tx_o  ( alert_tx[38:38] ),
-      .alert_rx_i  ( alert_rx[38:38] ),
+      // [42]: fatal_alert
+      .alert_tx_o  ( alert_tx[42:42] ),
+      .alert_rx_i  ( alert_rx[42:42] ),
 
       // Inter-module signals
       .csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2322,16 +2342,16 @@
   );
 
   sram_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:39]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:43]),
     .RndCnstSramKey(RndCnstSramCtrlMainSramKey),
     .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
     .RndCnstSramLfsrPerm(RndCnstSramCtrlMainSramLfsrPerm),
     .InstrExec(SramCtrlMainInstrExec)
   ) u_sram_ctrl_main (
-      // [39]: fatal_intg_error
-      // [40]: fatal_parity_error
-      .alert_tx_o  ( alert_tx[40:39] ),
-      .alert_rx_i  ( alert_rx[40:39] ),
+      // [43]: fatal_intg_error
+      // [44]: fatal_parity_error
+      .alert_tx_o  ( alert_tx[44:43] ),
+      .alert_rx_i  ( alert_rx[44:43] ),
 
       // Inter-module signals
       .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2356,7 +2376,7 @@
   );
 
   otbn #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:41]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]),
     .Stub(OtbnStub),
     .RegFile(OtbnRegFile),
     .RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed),
@@ -2365,10 +2385,10 @@
 
       // Interrupt
       .intr_done_o (intr_otbn_done),
-      // [41]: fatal
-      // [42]: recov
-      .alert_tx_o  ( alert_tx[42:41] ),
-      .alert_rx_i  ( alert_rx[42:41] ),
+      // [45]: fatal
+      // [46]: recov
+      .alert_tx_o  ( alert_tx[46:45] ),
+      .alert_rx_i  ( alert_rx[46:45] ),
 
       // Inter-module signals
       .edn_rnd_o(edn1_edn_req[0]),
@@ -2388,14 +2408,14 @@
   );
 
   rom_ctrl #(
-    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:43]),
+    .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:47]),
     .BootRomInitFile(RomCtrlBootRomInitFile),
     .RndCnstScrNonce(RndCnstRomCtrlScrNonce),
     .RndCnstScrKey(RndCnstRomCtrlScrKey)
   ) u_rom_ctrl (
-      // [43]: fatal
-      .alert_tx_o  ( alert_tx[43:43] ),
-      .alert_rx_i  ( alert_rx[43:43] ),
+      // [47]: fatal
+      .alert_tx_o  ( alert_tx[47:47] ),
+      .alert_rx_i  ( alert_rx[47:47] ),
 
       // Inter-module signals
       .rom_cfg_i(ast_rom_cfg),

diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index c646b5f..32d3950 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c

@@ -202,7 +202,11 @@
  * `top_earlgrey_alert_peripheral_t`.
  */
 const top_earlgrey_alert_peripheral_t
-    top_earlgrey_alert_for_peripheral[44] = {
+    top_earlgrey_alert_for_peripheral[48] = {
+  [kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0,
+  [kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1,
+  [kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2,
+  [kTopEarlgreyAlertIdUart3FatalFault] = kTopEarlgreyAlertPeripheralUart3,
   [kTopEarlgreyAlertIdGpioFatalFault] = kTopEarlgreyAlertPeripheralGpio,
   [kTopEarlgreyAlertIdSpiDeviceFatalFault] = kTopEarlgreyAlertPeripheralSpiDevice,
   [kTopEarlgreyAlertIdSpiHost0FatalFault] = kTopEarlgreyAlertPeripheralSpiHost0,

diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index c9754e1..eb95b77 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h

@@ -1088,29 +1088,33 @@
  * alert.
  */
 typedef enum top_earlgrey_alert_peripheral {
-  kTopEarlgreyAlertPeripheralGpio = 0, /**< gpio */
-  kTopEarlgreyAlertPeripheralSpiDevice = 1, /**< spi_device */
-  kTopEarlgreyAlertPeripheralSpiHost0 = 2, /**< spi_host0 */
-  kTopEarlgreyAlertPeripheralSpiHost1 = 3, /**< spi_host1 */
-  kTopEarlgreyAlertPeripheralPattgen = 4, /**< pattgen */
-  kTopEarlgreyAlertPeripheralOtpCtrl = 5, /**< otp_ctrl */
-  kTopEarlgreyAlertPeripheralLcCtrl = 6, /**< lc_ctrl */
-  kTopEarlgreyAlertPeripheralPinmuxAon = 7, /**< pinmux_aon */
-  kTopEarlgreyAlertPeripheralSensorCtrlAon = 8, /**< sensor_ctrl_aon */
-  kTopEarlgreyAlertPeripheralSramCtrlRetAon = 9, /**< sram_ctrl_ret_aon */
-  kTopEarlgreyAlertPeripheralFlashCtrl = 10, /**< flash_ctrl */
-  kTopEarlgreyAlertPeripheralAes = 11, /**< aes */
-  kTopEarlgreyAlertPeripheralHmac = 12, /**< hmac */
-  kTopEarlgreyAlertPeripheralKmac = 13, /**< kmac */
-  kTopEarlgreyAlertPeripheralKeymgr = 14, /**< keymgr */
-  kTopEarlgreyAlertPeripheralCsrng = 15, /**< csrng */
-  kTopEarlgreyAlertPeripheralEntropySrc = 16, /**< entropy_src */
-  kTopEarlgreyAlertPeripheralEdn0 = 17, /**< edn0 */
-  kTopEarlgreyAlertPeripheralEdn1 = 18, /**< edn1 */
-  kTopEarlgreyAlertPeripheralSramCtrlMain = 19, /**< sram_ctrl_main */
-  kTopEarlgreyAlertPeripheralOtbn = 20, /**< otbn */
-  kTopEarlgreyAlertPeripheralRomCtrl = 21, /**< rom_ctrl */
-  kTopEarlgreyAlertPeripheralLast = 21, /**< \internal Final Alert peripheral */
+  kTopEarlgreyAlertPeripheralUart0 = 0, /**< uart0 */
+  kTopEarlgreyAlertPeripheralUart1 = 1, /**< uart1 */
+  kTopEarlgreyAlertPeripheralUart2 = 2, /**< uart2 */
+  kTopEarlgreyAlertPeripheralUart3 = 3, /**< uart3 */
+  kTopEarlgreyAlertPeripheralGpio = 4, /**< gpio */
+  kTopEarlgreyAlertPeripheralSpiDevice = 5, /**< spi_device */
+  kTopEarlgreyAlertPeripheralSpiHost0 = 6, /**< spi_host0 */
+  kTopEarlgreyAlertPeripheralSpiHost1 = 7, /**< spi_host1 */
+  kTopEarlgreyAlertPeripheralPattgen = 8, /**< pattgen */
+  kTopEarlgreyAlertPeripheralOtpCtrl = 9, /**< otp_ctrl */
+  kTopEarlgreyAlertPeripheralLcCtrl = 10, /**< lc_ctrl */
+  kTopEarlgreyAlertPeripheralPinmuxAon = 11, /**< pinmux_aon */
+  kTopEarlgreyAlertPeripheralSensorCtrlAon = 12, /**< sensor_ctrl_aon */
+  kTopEarlgreyAlertPeripheralSramCtrlRetAon = 13, /**< sram_ctrl_ret_aon */
+  kTopEarlgreyAlertPeripheralFlashCtrl = 14, /**< flash_ctrl */
+  kTopEarlgreyAlertPeripheralAes = 15, /**< aes */
+  kTopEarlgreyAlertPeripheralHmac = 16, /**< hmac */
+  kTopEarlgreyAlertPeripheralKmac = 17, /**< kmac */
+  kTopEarlgreyAlertPeripheralKeymgr = 18, /**< keymgr */
+  kTopEarlgreyAlertPeripheralCsrng = 19, /**< csrng */
+  kTopEarlgreyAlertPeripheralEntropySrc = 20, /**< entropy_src */
+  kTopEarlgreyAlertPeripheralEdn0 = 21, /**< edn0 */
+  kTopEarlgreyAlertPeripheralEdn1 = 22, /**< edn1 */
+  kTopEarlgreyAlertPeripheralSramCtrlMain = 23, /**< sram_ctrl_main */
+  kTopEarlgreyAlertPeripheralOtbn = 24, /**< otbn */
+  kTopEarlgreyAlertPeripheralRomCtrl = 25, /**< rom_ctrl */
+  kTopEarlgreyAlertPeripheralLast = 25, /**< \internal Final Alert peripheral */
 } top_earlgrey_alert_peripheral_t;
 
 /**
@@ -1120,51 +1124,55 @@
  * the same peripheral are guaranteed to be consecutive.
  */
 typedef enum top_earlgrey_alert_id {
-  kTopEarlgreyAlertIdGpioFatalFault = 0, /**< gpio_fatal_fault */
-  kTopEarlgreyAlertIdSpiDeviceFatalFault = 1, /**< spi_device_fatal_fault */
-  kTopEarlgreyAlertIdSpiHost0FatalFault = 2, /**< spi_host0_fatal_fault */
-  kTopEarlgreyAlertIdSpiHost1FatalFault = 3, /**< spi_host1_fatal_fault */
-  kTopEarlgreyAlertIdPattgenFatalFault = 4, /**< pattgen_fatal_fault */
-  kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 5, /**< otp_ctrl_fatal_macro_error */
-  kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 6, /**< otp_ctrl_fatal_check_error */
-  kTopEarlgreyAlertIdLcCtrlFatalProgError = 7, /**< lc_ctrl_fatal_prog_error */
-  kTopEarlgreyAlertIdLcCtrlFatalStateError = 8, /**< lc_ctrl_fatal_state_error */
-  kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 9, /**< lc_ctrl_fatal_bus_integ_error */
-  kTopEarlgreyAlertIdPinmuxAonFatalFault = 10, /**< pinmux_aon_fatal_fault */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 11, /**< sensor_ctrl_aon_recov_as */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 12, /**< sensor_ctrl_aon_recov_cg */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 13, /**< sensor_ctrl_aon_recov_gd */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 14, /**< sensor_ctrl_aon_recov_ts_hi */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 15, /**< sensor_ctrl_aon_recov_ts_lo */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 16, /**< sensor_ctrl_aon_recov_fla */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 17, /**< sensor_ctrl_aon_recov_otp */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 18, /**< sensor_ctrl_aon_recov_ot0 */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 19, /**< sensor_ctrl_aon_recov_ot1 */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 20, /**< sensor_ctrl_aon_recov_ot2 */
-  kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 21, /**< sensor_ctrl_aon_recov_ot3 */
-  kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 22, /**< sram_ctrl_ret_aon_fatal_intg_error */
-  kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 23, /**< sram_ctrl_ret_aon_fatal_parity_error */
-  kTopEarlgreyAlertIdFlashCtrlRecovErr = 24, /**< flash_ctrl_recov_err */
-  kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 25, /**< flash_ctrl_recov_mp_err */
-  kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 26, /**< flash_ctrl_recov_ecc_err */
-  kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 27, /**< flash_ctrl_fatal_intg_err */
-  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 28, /**< aes_recov_ctrl_update_err */
-  kTopEarlgreyAlertIdAesFatalFault = 29, /**< aes_fatal_fault */
-  kTopEarlgreyAlertIdHmacFatalFault = 30, /**< hmac_fatal_fault */
-  kTopEarlgreyAlertIdKmacFatalFault = 31, /**< kmac_fatal_fault */
-  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 32, /**< keymgr_fatal_fault_err */
-  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 33, /**< keymgr_recov_operation_err */
-  kTopEarlgreyAlertIdCsrngFatalAlert = 34, /**< csrng_fatal_alert */
-  kTopEarlgreyAlertIdEntropySrcRecovAlert = 35, /**< entropy_src_recov_alert */
-  kTopEarlgreyAlertIdEntropySrcFatalAlert = 36, /**< entropy_src_fatal_alert */
-  kTopEarlgreyAlertIdEdn0FatalAlert = 37, /**< edn0_fatal_alert */
-  kTopEarlgreyAlertIdEdn1FatalAlert = 38, /**< edn1_fatal_alert */
-  kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 39, /**< sram_ctrl_main_fatal_intg_error */
-  kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 40, /**< sram_ctrl_main_fatal_parity_error */
-  kTopEarlgreyAlertIdOtbnFatal = 41, /**< otbn_fatal */
-  kTopEarlgreyAlertIdOtbnRecov = 42, /**< otbn_recov */
-  kTopEarlgreyAlertIdRomCtrlFatal = 43, /**< rom_ctrl_fatal */
-  kTopEarlgreyAlertIdLast = 43, /**< \internal The Last Valid Alert ID. */
+  kTopEarlgreyAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */
+  kTopEarlgreyAlertIdUart1FatalFault = 1, /**< uart1_fatal_fault */
+  kTopEarlgreyAlertIdUart2FatalFault = 2, /**< uart2_fatal_fault */
+  kTopEarlgreyAlertIdUart3FatalFault = 3, /**< uart3_fatal_fault */
+  kTopEarlgreyAlertIdGpioFatalFault = 4, /**< gpio_fatal_fault */
+  kTopEarlgreyAlertIdSpiDeviceFatalFault = 5, /**< spi_device_fatal_fault */
+  kTopEarlgreyAlertIdSpiHost0FatalFault = 6, /**< spi_host0_fatal_fault */
+  kTopEarlgreyAlertIdSpiHost1FatalFault = 7, /**< spi_host1_fatal_fault */
+  kTopEarlgreyAlertIdPattgenFatalFault = 8, /**< pattgen_fatal_fault */
+  kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 9, /**< otp_ctrl_fatal_macro_error */
+  kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 10, /**< otp_ctrl_fatal_check_error */
+  kTopEarlgreyAlertIdLcCtrlFatalProgError = 11, /**< lc_ctrl_fatal_prog_error */
+  kTopEarlgreyAlertIdLcCtrlFatalStateError = 12, /**< lc_ctrl_fatal_state_error */
+  kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 13, /**< lc_ctrl_fatal_bus_integ_error */
+  kTopEarlgreyAlertIdPinmuxAonFatalFault = 14, /**< pinmux_aon_fatal_fault */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 15, /**< sensor_ctrl_aon_recov_as */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 16, /**< sensor_ctrl_aon_recov_cg */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 17, /**< sensor_ctrl_aon_recov_gd */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 18, /**< sensor_ctrl_aon_recov_ts_hi */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 19, /**< sensor_ctrl_aon_recov_ts_lo */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 20, /**< sensor_ctrl_aon_recov_fla */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 21, /**< sensor_ctrl_aon_recov_otp */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 22, /**< sensor_ctrl_aon_recov_ot0 */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 23, /**< sensor_ctrl_aon_recov_ot1 */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 24, /**< sensor_ctrl_aon_recov_ot2 */
+  kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 25, /**< sensor_ctrl_aon_recov_ot3 */
+  kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 26, /**< sram_ctrl_ret_aon_fatal_intg_error */
+  kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 27, /**< sram_ctrl_ret_aon_fatal_parity_error */
+  kTopEarlgreyAlertIdFlashCtrlRecovErr = 28, /**< flash_ctrl_recov_err */
+  kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 29, /**< flash_ctrl_recov_mp_err */
+  kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 30, /**< flash_ctrl_recov_ecc_err */
+  kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 31, /**< flash_ctrl_fatal_intg_err */
+  kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 32, /**< aes_recov_ctrl_update_err */
+  kTopEarlgreyAlertIdAesFatalFault = 33, /**< aes_fatal_fault */
+  kTopEarlgreyAlertIdHmacFatalFault = 34, /**< hmac_fatal_fault */
+  kTopEarlgreyAlertIdKmacFatalFault = 35, /**< kmac_fatal_fault */
+  kTopEarlgreyAlertIdKeymgrFatalFaultErr = 36, /**< keymgr_fatal_fault_err */
+  kTopEarlgreyAlertIdKeymgrRecovOperationErr = 37, /**< keymgr_recov_operation_err */
+  kTopEarlgreyAlertIdCsrngFatalAlert = 38, /**< csrng_fatal_alert */
+  kTopEarlgreyAlertIdEntropySrcRecovAlert = 39, /**< entropy_src_recov_alert */
+  kTopEarlgreyAlertIdEntropySrcFatalAlert = 40, /**< entropy_src_fatal_alert */
+  kTopEarlgreyAlertIdEdn0FatalAlert = 41, /**< edn0_fatal_alert */
+  kTopEarlgreyAlertIdEdn1FatalAlert = 42, /**< edn1_fatal_alert */
+  kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 43, /**< sram_ctrl_main_fatal_intg_error */
+  kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 44, /**< sram_ctrl_main_fatal_parity_error */
+  kTopEarlgreyAlertIdOtbnFatal = 45, /**< otbn_fatal */
+  kTopEarlgreyAlertIdOtbnRecov = 46, /**< otbn_recov */
+  kTopEarlgreyAlertIdRomCtrlFatal = 47, /**< rom_ctrl_fatal */
+  kTopEarlgreyAlertIdLast = 47, /**< \internal The Last Valid Alert ID. */
 } top_earlgrey_alert_id_t;
 
 /**
@@ -1174,7 +1182,7 @@
  * `top_earlgrey_alert_peripheral_t`.
  */
 extern const top_earlgrey_alert_peripheral_t
-    top_earlgrey_alert_for_peripheral[44];
+    top_earlgrey_alert_for_peripheral[48];
 
 #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
commit	9d1fd4aa64f91e8663b73c045d68a7bafedb7325	[log] [tgz]
author	Michael Schaffner <msf@opentitan.org>	Mon Jun 07 16:03:22 2021 -0700
committer	Michael Schaffner <msf@google.com>	Tue Jun 15 07:50:12 2021 -0700
tree	6debe6bbee3dcf2a643d8f56ff3f096a18ffa524
parent	05dabb3f86afd6c7790e8e5f6218783b1305819c [diff]