[hmac] Meet the Verilog Style Guide
Changed registers' name to have `_q` and `_d` postfix to conform the
verilog style guide, especially the state machines' variables.
diff --git a/hw/ip/hmac/rtl/hmac_core.sv b/hw/ip/hmac/rtl/hmac_core.sv
index a71e9d9..3183cfe 100644
--- a/hw/ip/hmac/rtl/hmac_core.sv
+++ b/hw/ip/hmac/rtl/hmac_core.sv
@@ -79,7 +79,7 @@
} round_t ;
logic update_round ;
- round_t round, round_next;
+ round_t round_q, round_d;
typedef enum logic [2:0] {
StIdle,
@@ -91,7 +91,7 @@
StDone // hmac_done
} st_e ;
- st_e st, st_next;
+ st_e st_q, st_d;
logic clr_fifo_wdata_sel;
logic txcnt_eq_blksz ;
@@ -108,7 +108,7 @@
assign o_pad = {secret_key, {(BlockSize-256){1'b0}}} ^ {(BlockSize/8){8'h5c}};
- assign fifo_rready = (hmac_en) ? (st == StMsg) & sha_rready : sha_rready ;
+ assign fifo_rready = (hmac_en) ? (st_q == StMsg) & sha_rready : sha_rready ;
// sha_rvalid is controlled by State Machine below.
assign sha_rvalid = (!hmac_en) ? fifo_rvalid : hmac_sha_rvalid ;
assign sha_rdata =
@@ -157,9 +157,9 @@
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- round <= Inner;
+ round_q <= Inner;
end else if (update_round) begin
- round <= round_next;
+ round_q <= round_d;
end
end
@@ -173,11 +173,11 @@
end
end
- assign sel_msglen = (round == Inner) ? SelIPadMsg : SelOPadMsg ;
+ assign sel_msglen = (round_q == Inner) ? SelIPadMsg : SelOPadMsg ;
always_ff @(posedge clk_i or negedge rst_ni) begin : state_ff
- if (!rst_ni) st <= StIdle;
- else st <= st_next;
+ if (!rst_ni) st_q <= StIdle;
+ else st_q <= st_d;
end
always_comb begin : next_state
@@ -187,7 +187,7 @@
clr_txcount = 1'b0;
update_round = 1'b0;
- round_next = Inner;
+ round_d = Inner;
fifo_wsel = 1'b0; // from register
fifo_wvalid = 1'b0;
@@ -196,20 +196,20 @@
sel_rdata = SelFifo;
- hash_start = 1'b0;
+ hash_start = 1'b0;
hash_process = 1'b0;
- unique case (st)
+ unique case (st_q)
StIdle: begin
if (hmac_en && reg_hash_start) begin
- st_next = StIPad;
+ st_d = StIPad;
- clr_txcount = 1'b1;
+ clr_txcount = 1'b1;
update_round = 1'b1;
- round_next = Inner;
- hash_start = 1'b1;
+ round_d = Inner;
+ hash_start = 1'b1;
end else begin
- st_next = StIdle;
+ st_d = StIdle;
end
end
@@ -217,11 +217,11 @@
sel_rdata = SelIPad;
if (txcnt_eq_blksz) begin
- st_next = StMsg;
+ st_d = StMsg;
hmac_sha_rvalid = 1'b0; // block new read request
end else begin
- st_next = StIPad;
+ st_d = StIPad;
hmac_sha_rvalid = 1'b1;
end
@@ -230,14 +230,14 @@
StMsg: begin
sel_rdata = SelFifo;
- if ( (((round == Inner) && reg_hash_process_flag) || (round == Outer))
+ if ( (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
&& (txcount >= sha_message_length)) begin
- st_next = StWaitResp;
+ st_d = StWaitResp;
hmac_sha_rvalid = 1'b0; // block
- hash_process = (round == Outer);
+ hash_process = (round_q == Outer);
end else begin
- st_next = StMsg;
+ st_d = StMsg;
hmac_sha_rvalid = fifo_rvalid;
end
@@ -247,32 +247,32 @@
hmac_sha_rvalid = 1'b0;
if (sha_hash_done) begin
- if (round == Outer) begin
- st_next = StDone;
- end else begin // round == Inner
- st_next = StPushToMsgFifo;
+ if (round_q == Outer) begin
+ st_d = StDone;
+ end else begin // round_q == Inner
+ st_d = StPushToMsgFifo;
end
end else begin
- st_next = StWaitResp;
+ st_d = StWaitResp;
end
end
StPushToMsgFifo: begin
// TODO: Accelerate by parallel process of PushToMsgFifo and OPad hash
- hmac_sha_rvalid = 1'b0;
- fifo_wsel = 1'b1;
- fifo_wvalid = 1'b1;
+ hmac_sha_rvalid = 1'b0;
+ fifo_wsel = 1'b1;
+ fifo_wvalid = 1'b1;
clr_fifo_wdata_sel = 1'b0;
if (fifo_wready && fifo_wdata_sel == 3'h7) begin
- st_next = StOPad;
+ st_d = StOPad;
- clr_txcount = 1'b1;
+ clr_txcount = 1'b1;
update_round = 1'b1;
- round_next = Outer;
- hash_start = 1'b1;
+ round_d = Outer;
+ hash_start = 1'b1;
end else begin
- st_next = StPushToMsgFifo;
+ st_d = StPushToMsgFifo;
end
end
@@ -281,11 +281,11 @@
sel_rdata = SelOPad;
if (txcnt_eq_blksz) begin
- st_next = StMsg;
+ st_d = StMsg;
hmac_sha_rvalid = 1'b0; // block new read request
end else begin
- st_next = StOPad;
+ st_d = StOPad;
hmac_sha_rvalid = 1'b1;
end
@@ -293,13 +293,13 @@
StDone: begin
// raise interrupt (hash_done)
- st_next = StIdle;
+ st_d = StIdle;
hmac_hash_done = 1'b1;
end
default: begin
- st_next = StIdle;
+ st_d = StIdle;
end
endcase
diff --git a/hw/ip/hmac/rtl/sha2.sv b/hw/ip/hmac/rtl/sha2.sv
index 892406f..ed491d7 100644
--- a/hw/ip/hmac/rtl/sha2.sv
+++ b/hw/ip/hmac/rtl/sha2.sv
@@ -163,43 +163,43 @@
FifoWait
} fifoctl_state_e;
- fifoctl_state_e fifo_st, fifo_st_next;
+ fifoctl_state_e fifo_st_q, fifo_st_d;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- fifo_st <= FifoIdle;
+ fifo_st_q <= FifoIdle;
end else begin
- fifo_st <= fifo_st_next;
+ fifo_st_q <= fifo_st_d;
end
end
always_comb begin
- fifo_st_next = FifoIdle;
+ fifo_st_d = FifoIdle;
update_w_from_fifo = 1'b0;
hash_done_next = 1'b0;
- unique case (fifo_st)
+ unique case (fifo_st_q)
FifoIdle: begin
if (hash_start) begin
- fifo_st_next = FifoLoadFromFifo;
+ fifo_st_d = FifoLoadFromFifo;
end else begin
- fifo_st_next = FifoIdle;
+ fifo_st_d = FifoIdle;
end
end
FifoLoadFromFifo: begin
if (!sha_en) begin
- fifo_st_next = FifoIdle;
+ fifo_st_d = FifoIdle;
update_w_from_fifo = 1'b0;
end else if (!shaf_rvalid) begin
// Wait until it is filled
- fifo_st_next = FifoLoadFromFifo;
+ fifo_st_d = FifoLoadFromFifo;
update_w_from_fifo = 1'b0;
end else if (w_index == 4'd 15) begin
- fifo_st_next = FifoWait;
+ fifo_st_d = FifoWait;
update_w_from_fifo = 1'b1;
end else begin
- fifo_st_next = FifoLoadFromFifo;
+ fifo_st_d = FifoLoadFromFifo;
update_w_from_fifo = 1'b1;
end
end
@@ -209,21 +209,21 @@
// TODO: Detect at the end of the message
if (msg_feed_complete && complete_one_chunk) begin
// TODO: Should we wait until round hits 63?
- fifo_st_next = FifoIdle;
+ fifo_st_d = FifoIdle;
hash_done_next = 1'b1;
// TODO: make below FIFO feeding logic concrete.
// currently, with below commented logic, it doesn't fill FIFO correctly.
//end else if (!in_end_chunk && round == 6'd47) begin
end else if (complete_one_chunk) begin
- fifo_st_next = FifoLoadFromFifo;
+ fifo_st_d = FifoLoadFromFifo;
end else begin
- fifo_st_next = FifoWait;
+ fifo_st_d = FifoWait;
end
end
default: begin
- fifo_st_next = FifoIdle;
+ fifo_st_d = FifoIdle;
end
endcase
end
@@ -235,13 +235,13 @@
ShaUpdateDigest
} sha_st_t;
- sha_st_t sha_st, sha_st_next;
+ sha_st_t sha_st_q, sha_st_d;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- sha_st <= ShaIdle;
+ sha_st_q <= ShaIdle;
end else begin
- sha_st <= sha_st_next;
+ sha_st_q <= sha_st_d;
end
end
@@ -254,13 +254,13 @@
init_hash = 1'b0;
run_hash = 1'b0;
- unique case (sha_st)
+ unique case (sha_st_q)
ShaIdle: begin
- if (fifo_st == FifoWait) begin
+ if (fifo_st_q == FifoWait) begin
init_hash = 1'b1;
- sha_st_next = ShaCompress;
+ sha_st_d = ShaCompress;
end else begin
- sha_st_next = ShaIdle;
+ sha_st_d = ShaIdle;
end
end
@@ -272,24 +272,24 @@
end
if (complete_one_chunk) begin
- sha_st_next = ShaUpdateDigest;
+ sha_st_d = ShaUpdateDigest;
end else begin
- sha_st_next = ShaCompress;
+ sha_st_d = ShaCompress;
end
end
ShaUpdateDigest: begin
update_digest = 1'b1;
- if (fifo_st == FifoWait) begin
+ if (fifo_st_q == FifoWait) begin
init_hash = 1'b1;
- sha_st_next = ShaCompress;
+ sha_st_d = ShaCompress;
end else begin
- sha_st_next = ShaIdle;
+ sha_st_d = ShaIdle;
end
end
default: begin
- sha_st_next = ShaIdle;
+ sha_st_d = ShaIdle;
end
endcase
end
diff --git a/hw/ip/hmac/rtl/sha2_pad.sv b/hw/ip/hmac/rtl/sha2_pad.sv
index 368d658..a7f70f9 100644
--- a/hw/ip/hmac/rtl/sha2_pad.sv
+++ b/hw/ip/hmac/rtl/sha2_pad.sv
@@ -131,13 +131,13 @@
StLenLo
} pad_st_e;
- pad_st_e st, st_next;
+ pad_st_e st_q, st_d;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- st <= StIdle;
+ st_q <= StIdle;
end else begin
- st <= st_next;
+ st_q <= st_d;
end
end
@@ -149,9 +149,9 @@
sel_data = FifoIn;
fifo_rready = 1'b0;
- st_next = StIdle;
+ st_d = StIdle;
- unique case (st)
+ unique case (st_q)
StIdle: begin
sel_data = FifoIn;
shaf_rvalid = 1'b0;
@@ -159,9 +159,9 @@
if (sha_en && hash_start) begin
inc_txcount = 1'b0;
- st_next = StFifoReceive;
+ st_d = StFifoReceive;
end else begin
- st_next = StIdle;
+ st_d = StIdle;
end
end
@@ -174,26 +174,26 @@
inc_txcount = 1'b0;
fifo_rready = 1'b0;
- st_next = StPad80;
+ st_d = StPad80;
end else if (!hash_process_flag) begin
fifo_rready = shaf_rready;
shaf_rvalid = fifo_rvalid;
inc_txcount = shaf_rready;
- st_next = StFifoReceive;
+ st_d = StFifoReceive;
end else if (tx_count == message_length) begin
// already received all msg and was waiting process flag
shaf_rvalid = 1'b0;
inc_txcount = 1'b0;
fifo_rready = 1'b0;
- st_next = StPad80;
+ st_d = StPad80;
end else begin
shaf_rvalid = fifo_rvalid;
fifo_rready = shaf_rready; // 0 always
inc_txcount = shaf_rready; // 0 always
- st_next = StFifoReceive;
+ st_d = StFifoReceive;
end
end
@@ -205,16 +205,16 @@
// exactly 96 bits left, do not need to pad00's
if (shaf_rready && txcnt_eq_1a0) begin
- st_next = StLenHi;
+ st_d = StLenHi;
inc_txcount = 1'b1;
// it does not matter if value is < or > than 416 bits. If it's the former, 00 pad until
// length field. If >, then the next chunk will contain the length field with appropriate
// 0 padding.
end else if (shaf_rready && !txcnt_eq_1a0) begin
- st_next = StPad00;
+ st_d = StPad00;
inc_txcount = 1'b1;
end else begin
- st_next = StPad80;
+ st_d = StPad80;
inc_txcount = 1'b0;
end
@@ -222,23 +222,23 @@
// # (80 clk --> 64 clk)
// # leaving this as a reference but needs to verify it.
//if (shaf_rready && !txcnt_eq_1a0) begin
- // st_next = StPad00;
+ // st_d = StPad00;
//
// inc_txcount = 1'b1;
// shaf_rvalid = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
// fifo_rready = (msg_word_aligned) ? 1'b0 : 1'b1;
//end else if (!shaf_rready && !txcnt_eq_1a0) begin
- // st_next = StPad80;
+ // st_d = StPad80;
//
// inc_txcount = 1'b0;
// shaf_rvalid = (msg_word_aligned) ? 1'b1 : fifo_rvalid;
//
//end else if (shaf_rready && txcnt_eq_1a0) begin
- // st_next = StLenHi;
+ // st_d = StLenHi;
// inc_txcount = 1'b1;
//end else begin
// // !shaf_rready && txcnt_eq_1a0 , just wait until fifo_rready asserted
- // st_next = StPad80;
+ // st_d = StPad80;
// inc_txcount = 1'b0;
//end
end
@@ -251,12 +251,12 @@
inc_txcount = 1'b1;
if (txcnt_eq_1a0) begin
- st_next = StLenHi;
+ st_d = StLenHi;
end else begin
- st_next = StPad00;
+ st_d = StPad00;
end
end else begin
- st_next = StPad00;
+ st_d = StPad00;
end
end
@@ -265,11 +265,11 @@
shaf_rvalid = 1'b1;
if (shaf_rready) begin
- st_next = StLenLo;
+ st_d = StLenLo;
inc_txcount = 1'b1;
end else begin
- st_next = StLenHi;
+ st_d = StLenHi;
inc_txcount = 1'b0;
end
@@ -280,18 +280,18 @@
shaf_rvalid = 1'b1;
if (shaf_rready) begin
- st_next = StIdle;
+ st_d = StIdle;
inc_txcount = 1'b1;
end else begin
- st_next = StLenLo;
+ st_d = StLenLo;
inc_txcount = 1'b0;
end
end
default: begin
- st_next = StIdle;
+ st_d = StIdle;
end
endcase
end
@@ -308,7 +308,7 @@
end
// State machine is in Idle only when it meets tx_count == message length
- assign msg_feed_complete = hash_process_flag && (st == StIdle);
+ assign msg_feed_complete = hash_process_flag && (st_q == StIdle);
// When fifo_partial, fifo shouldn't be empty and hash_process was set
`ASSERT(ValidPartialConditionAssert,
