hw/ip/csrng/data/csrng_testplan.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  name: "csrng"
  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson"]
  entries: [
    {
      name: smoke
      desc: '''
            Enable csrng, send instantiate/generate cmds, verify 0-seed genbits/interrupt.
            '''
      milestone: V1
      tests: ["csrng_smoke"]
    }
    {
      name: firmware
      desc: '''
            Verify ability to access genbits register based on value of efuse input.
            Verify regen bit disables write access of control registers.
            Verify registers at End-Of-Test.
            '''
      milestone: V2
      tests: []
    }
    {
      name: interrupts
      desc: '''
            Verify cs_cmd_req_done interrupt asserts/clears as predicted.
            Verify cs_entropy_req interrupt asserts/clears as predicted.
            Verify cs_hw_inst_exc interrupt asserts/clears as predicted.
            Verify cs_fifo_err interrupt asserts/clears as predicted.
            Verify fifo error status bits are set as predicted.
            '''
      milestone: V2
      tests: []
    }
    {
      name: cmds
      desc: '''
            Verify all SW app csrng commands req/status behave as predicted.
            Verify all HW app csrng commands req/status behave as predicted.
            Verify above for all valid values of acmd, clen, flags, glen.
            Verify for multiple hw app interfaces running in parallel.
            Verify sw/hw app interfaces running in parallel.
            '''
      milestone: V2
      tests: []
    }
    {
      name: life cycle
      desc: '''
            Verify lifecycle hardware debug mode enables AES bypass, reading CSRNG internal state.
	    Verify CSRNG internal state for all csrng/genbits operations.
            '''
      milestone: V2
      tests: []
    }
    {
      name: genbits
      desc: '''
            Verify genbits generated as predicted.
            Verify fips bits is passed through properly.
            Verify for multiple hw app interfaces running in parallel.
            '''
      milestone: V2
      tests: []
    }
    {
      name: stress_all
      desc: '''
            Combine the other individual testpoints while injecting TL errors and running CSR tests in parallel.'''
      milestone: V2
      tests: ["csrng_stress_all"]
    }
  ]
}