[cw_spiflash] Update SAM3X pinmap, OTT and SW tests accordingly Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/sw/device/examples/demos.c b/sw/device/examples/demos.c index 379698f..379941f 100644 --- a/sw/device/examples/demos.c +++ b/sw/device/examples/demos.c
@@ -18,7 +18,7 @@ LOG_INFO("Watch the LEDs!"); // Give a LED pattern as startup indicator for 5 seconds. - CHECK_DIF_OK(dif_gpio_write_all(gpio, 0xff00)); + CHECK_DIF_OK(dif_gpio_write_all(gpio, 0x00ff)); for (int i = 0; i < 32; ++i) { busy_spin_micros(5 * 1000); // 5 ms CHECK_DIF_OK(dif_gpio_write(gpio, 8 + (i % 8), (i / 8) % 2)); @@ -27,15 +27,15 @@ } /** - * Mask for "valid" GPIO bits. The first byte represents switch inputs, - * while byte 16 represents the FTDI bit. + * Mask for "valid" GPIO bits. The nibble at [11:8] represents switch inputs, + * while the bit at [22] represents the FTDI bit (SW strap 0). */ -static const uint32_t kGpioMask = 0x100ff; +static const uint32_t kGpioMask = 0x400f00; /** - * Mask for the FTDI bit among the GPIO bits. + * Mask for the FTDI bit (SW strap 0) among the GPIO bits. */ -static const uint32_t kFtdiMask = 0x10000; +static const uint32_t kFtdiMask = 0x400000; uint32_t demo_gpio_to_log_echo(dif_gpio_t *gpio, uint32_t prev_gpio_state) { uint32_t gpio_state;
diff --git a/sw/device/examples/hello_world/hello_world.c b/sw/device/examples/hello_world/hello_world.c index f0153f6..5efd0f0 100644 --- a/sw/device/examples/hello_world/hello_world.c +++ b/sw/device/examples/hello_world/hello_world.c
@@ -59,8 +59,8 @@ CHECK_DIF_OK( dif_gpio_init(mmio_region_from_addr(TOP_EARLGREY_GPIO_BASE_ADDR), &gpio)); - // Enable GPIO: 0-7 and 16 is input; 8-15 is output. - CHECK_DIF_OK(dif_gpio_output_set_enabled_all(&gpio, 0x0ff00)); + // Enable GPIO: 0-7 is output; 8-11 is input. + CHECK_DIF_OK(dif_gpio_output_set_enabled_all(&gpio, 0x000FF)); // Add DATE and TIME because I keep fooling myself with old versions LOG_INFO("Hello World!");
diff --git a/sw/device/lib/testing/pinmux_testutils.c b/sw/device/lib/testing/pinmux_testutils.c index 0427222..1029359 100644 --- a/sw/device/lib/testing/pinmux_testutils.c +++ b/sw/device/lib/testing/pinmux_testutils.c
@@ -19,7 +19,7 @@ for (uint32_t index = 0; index < NUM_GPIO; index++) { dif_pinmux_index_t mio = kTopEarlgreyPinmuxInselIoa0 + index; if (mio == kTopEarlgreyPinmuxInselIoc3 || - mio == kTopEarlgreyPinmuxInselIoc8) { + mio == kTopEarlgreyPinmuxInselIob4) { // Avoid causing glitches: Don't assign the UART pins to a GPIO. continue; } else { @@ -33,8 +33,8 @@ dif_pinmux_index_t mio = kTopEarlgreyPinmuxMioOutIoa0 + index; if (mio == kTopEarlgreyPinmuxMioOutIoc3 || mio == kTopEarlgreyPinmuxMioOutIoc4 || - mio == kTopEarlgreyPinmuxMioOutIoc8 || - mio == kTopEarlgreyPinmuxMioOutIoc9) { + mio == kTopEarlgreyPinmuxMioOutIob4 || + mio == kTopEarlgreyPinmuxMioOutIob5) { // Avoid causing glitches: Don't assign the UART pins to a GPIO. continue; } else { @@ -54,14 +54,14 @@ kTopEarlgreyPinmuxOutselUart0Tx)); #if !OT_IS_ENGLISH_BREAKFAST - // Configure UART1 RX input to connect to MIO pad IOC8 + // Configure UART1 RX input to connect to MIO pad IOB4 CHECK_DIF_OK(dif_pinmux_input_select(pinmux, kTopEarlgreyPinmuxPeripheralInUart1Rx, - kTopEarlgreyPinmuxInselIoc8)); - CHECK_DIF_OK(dif_pinmux_output_select(pinmux, kTopEarlgreyPinmuxMioOutIoc8, + kTopEarlgreyPinmuxInselIob4)); + CHECK_DIF_OK(dif_pinmux_output_select(pinmux, kTopEarlgreyPinmuxMioOutIob4, kTopEarlgreyPinmuxOutselConstantHighZ)); - // Configure UART1 TX output to connect to MIO pad IOC9 - CHECK_DIF_OK(dif_pinmux_output_select(pinmux, kTopEarlgreyPinmuxMioOutIoc9, + // Configure UART1 TX output to connect to MIO pad IOB5 + CHECK_DIF_OK(dif_pinmux_output_select(pinmux, kTopEarlgreyPinmuxMioOutIob5, kTopEarlgreyPinmuxOutselUart1Tx)); #endif
diff --git a/sw/device/lib/testing/test_rom/bootstrap.c b/sw/device/lib/testing/test_rom/bootstrap.c index 4a70712..4533881 100644 --- a/sw/device/lib/testing/test_rom/bootstrap.c +++ b/sw/device/lib/testing/test_rom/bootstrap.c
@@ -22,7 +22,7 @@ #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" -#define GPIO_BOOTSTRAP_BIT_MASK 0x00020000u +#define GPIO_BOOTSTRAP_BIT_MASK 0x00400000u /** * Check if flash is blank to determine if bootstrap is needed.
diff --git a/sw/device/silicon_creator/lib/drivers/pinmux.c b/sw/device/silicon_creator/lib/drivers/pinmux.c index 020add4..863a9e0 100644 --- a/sw/device/silicon_creator/lib/drivers/pinmux.c +++ b/sw/device/silicon_creator/lib/drivers/pinmux.c
@@ -32,28 +32,34 @@ /** * UART RX pin. */ -static const pinmux_input_t kInputUart = { +static const pinmux_input_t kInputUart0 = { .periph = kTopEarlgreyPinmuxPeripheralInUart0Rx, .pad = kTopEarlgreyPinmuxInselIoc3, }; /** - * Bootstrap pin. - * - * TODO(#11934): The actual chip will have 3 strapping pins that should be - * configured as inputs. + * UART TX pin. */ -static const pinmux_input_t kInputBootstrap = { - .periph = kTopEarlgreyPinmuxPeripheralInGpioGpio17, - .pad = kTopEarlgreyPinmuxInselIob8, +static const pinmux_output_t kOutputUart0 = { + .pad = kTopEarlgreyPinmuxMioOutIoc4, + .periph = kTopEarlgreyPinmuxOutselUart0Tx, }; /** - * UART TX pin. + * SW strap pins. + * */ -static const pinmux_output_t kOutputUart = { - .pad = kTopEarlgreyPinmuxMioOutIoc4, - .periph = kTopEarlgreyPinmuxOutselUart0Tx, +static const pinmux_input_t kInputSwStrap0 = { + .periph = kTopEarlgreyPinmuxPeripheralInGpioGpio22, + .pad = kTopEarlgreyPinmuxInselIoc0, +}; +static const pinmux_input_t kInputSwStrap1 = { + .periph = kTopEarlgreyPinmuxPeripheralInGpioGpio23, + .pad = kTopEarlgreyPinmuxInselIoc1, +}; +static const pinmux_input_t kInputSwStrap2 = { + .periph = kTopEarlgreyPinmuxPeripheralInGpioGpio24, + .pad = kTopEarlgreyPinmuxInselIoc2, }; /** @@ -84,9 +90,11 @@ uint32_t bootstrap_en = otp_read32(OTP_CTRL_PARAM_ROM_BOOTSTRAP_EN_OFFSET); if (launder32(bootstrap_en) == kHardenedBoolTrue) { HARDENED_CHECK_EQ(bootstrap_en, kHardenedBoolTrue); - configure_input(kInputBootstrap); + configure_input(kInputSwStrap0); + configure_input(kInputSwStrap1); + configure_input(kInputSwStrap2); } - configure_input(kInputUart); - configure_output(kOutputUart); + configure_input(kInputUart0); + configure_output(kOutputUart0); }
diff --git a/sw/device/silicon_creator/lib/drivers/pinmux_unittest.cc b/sw/device/silicon_creator/lib/drivers/pinmux_unittest.cc index 52f6b9e..16937ea 100644 --- a/sw/device/silicon_creator/lib/drivers/pinmux_unittest.cc +++ b/sw/device/silicon_creator/lib/drivers/pinmux_unittest.cc
@@ -68,8 +68,12 @@ // The inputs that will be configured. EXPECT_CALL(otp_, read32(OTP_CTRL_PARAM_ROM_BOOTSTRAP_EN_OFFSET)) .WillOnce(Return(kHardenedBoolTrue)); - EXPECT_ABS_WRITE32(RegIn(kTopEarlgreyPinmuxPeripheralInGpioGpio17), - kTopEarlgreyPinmuxInselIob8) + EXPECT_ABS_WRITE32(RegIn(kTopEarlgreyPinmuxPeripheralInGpioGpio22), + kTopEarlgreyPinmuxInselIoc0) + EXPECT_ABS_WRITE32(RegIn(kTopEarlgreyPinmuxPeripheralInGpioGpio23), + kTopEarlgreyPinmuxInselIoc1) + EXPECT_ABS_WRITE32(RegIn(kTopEarlgreyPinmuxPeripheralInGpioGpio24), + kTopEarlgreyPinmuxInselIoc2) EXPECT_ABS_WRITE32(RegIn(kTopEarlgreyPinmuxPeripheralInUart0Rx), kTopEarlgreyPinmuxInselIoc3);
diff --git a/sw/device/tests/gpio_smoketest.c b/sw/device/tests/gpio_smoketest.c index 5780f9c..da480d2 100644 --- a/sw/device/tests/gpio_smoketest.c +++ b/sw/device/tests/gpio_smoketest.c
@@ -28,13 +28,10 @@ /** * Pins to be tested. * - * This test only uses pins 0-15 to be compatible with both FPGA and DV: - * - On the nexys video board (chip_earlgrey_nexysvideo.sv), pins 20-23 are - * grounded and pins 16-19 are reserved for JTAG, while - * - On the OpenTitan ASIC (chip_earlgrey_asic.sv), pins 20-31 are grounded and - * pins 16-19 are reserved for JTAG. + * This test only uses pins 0-12 to be compatible with both FPGA and DV. + * See chip-level testbenches and top-level hjson file for actual configuration. */ -static const uint32_t kGpioMask = 0x0000FFFF; +static const uint32_t kGpioMask = 0x00000FFF; /** * Writes the given value to GPIO pins and compares it against the value read.
diff --git a/sw/device/tests/sim_dv/gpio_test.c b/sw/device/tests/sim_dv/gpio_test.c index 5779ebc..df1352c 100644 --- a/sw/device/tests/sim_dv/gpio_test.c +++ b/sw/device/tests/sim_dv/gpio_test.c
@@ -25,10 +25,10 @@ static const uint32_t kGpiosMask = 0xffffffff; // These constants reflect the GPIOs exposed by the OpenTitan SoC. -static const uint32_t kNumChipGpios = 16; -// TODO #2484: GPIO pins 16-19 are special inputs - do not touch them. -static const uint32_t kGpiosAllowedMask = 0xfff0ffff; -static const uint32_t kChipGpiosMask = 0xffff & kGpiosAllowedMask; +static const uint32_t kNumChipGpios = 12; +// TODO: update GPIO test once the chip-level testbench uses the correct pinout. +static const uint32_t kGpiosAllowedMask = 0xffffffff; +static const uint32_t kChipGpiosMask = 0xfff & kGpiosAllowedMask; // These indicate the GPIO pin irq expected to fire, declared volatile since // they are used by the ISR.
diff --git a/sw/device/tests/sim_dv/uart_tx_rx_test.c b/sw/device/tests/sim_dv/uart_tx_rx_test.c index 87a810f..255b215 100644 --- a/sw/device/tests/sim_dv/uart_tx_rx_test.c +++ b/sw/device/tests/sim_dv/uart_tx_rx_test.c
@@ -535,13 +535,13 @@ LOG_INFO("Test UART%d with base_addr: %08x", kUartIdx, uart_base_addr); - // TODO, remove thse once pinout configuration is provided pinmux_connect_uart_to_pads( kTopEarlgreyPinmuxInselIoc3, kTopEarlgreyPinmuxPeripheralInUart0Rx, kTopEarlgreyPinmuxMioOutIoc4, kTopEarlgreyPinmuxOutselUart0Tx); pinmux_connect_uart_to_pads( - kTopEarlgreyPinmuxInselIor5, kTopEarlgreyPinmuxPeripheralInUart1Rx, - kTopEarlgreyPinmuxMioOutIor6, kTopEarlgreyPinmuxOutselUart1Tx); + kTopEarlgreyPinmuxInselIob4, kTopEarlgreyPinmuxPeripheralInUart1Rx, + kTopEarlgreyPinmuxMioOutIob5, kTopEarlgreyPinmuxOutselUart1Tx); + // TODO: the UARTs below still need to be mapped to the correct location. pinmux_connect_uart_to_pads( kTopEarlgreyPinmuxInselIor7, kTopEarlgreyPinmuxPeripheralInUart2Rx, kTopEarlgreyPinmuxMioOutIor10, kTopEarlgreyPinmuxOutselUart2Tx);
diff --git a/sw/host/opentitanlib/src/transport/cw310/mod.rs b/sw/host/opentitanlib/src/transport/cw310/mod.rs index c275118..d5cdbd2 100644 --- a/sw/host/opentitanlib/src/transport/cw310/mod.rs +++ b/sw/host/opentitanlib/src/transport/cw310/mod.rs
@@ -53,7 +53,6 @@ const PIN_TAP_STRAP0: &'static str = "USB_A18"; const PIN_TAP_STRAP1: &'static str = "USB_A19"; - pub fn new( usb_vid: Option<u16>, usb_pid: Option<u16>, @@ -189,9 +188,9 @@ // Program the FPGA bitstream. let usb = self.device.borrow(); usb.spi1_enable(false)?; - usb.pin_set_state(CW310::PIN_TAP_STRAP0, true)?; - usb.pin_set_state(CW310::PIN_TAP_STRAP1, true)?; - usb.pin_set_state(CW310::PIN_TAP_STRAP2, true)?; + usb.pin_set_state(CW310::PIN_SW_STRAP0, true)?; + usb.pin_set_state(CW310::PIN_SW_STRAP1, true)?; + usb.pin_set_state(CW310::PIN_SW_STRAP2, true)?; usb.fpga_program(&fpga_program.bitstream)?; Ok(None) } else {
diff --git a/sw/host/opentitanlib/src/transport/cw310/spi.rs b/sw/host/opentitanlib/src/transport/cw310/spi.rs index 15621d9..3bb49bf 100644 --- a/sw/host/opentitanlib/src/transport/cw310/spi.rs +++ b/sw/host/opentitanlib/src/transport/cw310/spi.rs
@@ -29,7 +29,7 @@ usb.spi1_enable(true)?; // Set the JTAG pin to false to use SPI mode. - usb.pin_set_state(CW310::PIN_JTAG, false)?; + usb.pin_set_state(CW310::PIN_TAP_STRAP1, false)?; } Ok(CW310Spi { device })
diff --git a/util/fpga/cw_spiflash.py b/util/fpga/cw_spiflash.py index b514564..d1dfa1d 100644 --- a/util/fpga/cw_spiflash.py +++ b/util/fpga/cw_spiflash.py
@@ -135,25 +135,35 @@ 'PIN_CS', 'PIN_TRST', 'PIN_SRST', - 'PIN_JTAG_SPI', - 'PIN_BOOTSTRAP']) + 'PIN_SW_STRAP0', + 'PIN_SW_STRAP1', + 'PIN_SW_STRAP2', + 'PIN_TAP_STRAP0', + 'PIN_TAP_STRAP1' + ]) _PIN_MAPPINGS = {} - _PIN_MAPPINGS['CW305'] = PinMapping('USB_A13', + _PIN_MAPPINGS['CW305'] = PinMapping('USB_A9', + 'USB_A10', + 'USB_A11', + 'USB_A12', + 'USB_A13', 'USB_A14', 'USB_A15', 'USB_A16', 'USB_A17', 'USB_A18', - 'USB_A19', - 'USB_A20') + 'USB_A19') _PIN_MAPPINGS['CW310'] = PinMapping('USB_SPI_SCK', 'USB_SPI_COPI', 'USB_SPI_CIPO', 'USB_SPI_CS', + 'USB_A13', + 'USB_A14', + 'USB_A15', + 'USB_A16', 'USB_A17', 'USB_A18', - 'USB_A19', - 'USB_A16') + 'USB_A19') _board = 'CW305' # Delays below are in seconds. @@ -179,12 +189,18 @@ self._fpga_io = fpga.gpio_mode() self._fpga_io.pin_set_output(self._PIN_MAPPINGS[self._board].PIN_TRST) self._fpga_io.pin_set_output(self._PIN_MAPPINGS[self._board].PIN_SRST) - self._fpga_io.pin_set_output(self._PIN_MAPPINGS[self._board].PIN_JTAG_SPI) - self._fpga_io.pin_set_output(self._PIN_MAPPINGS[self._board].PIN_BOOTSTRAP) + self._fpga_io.pin_set_output(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP0) + self._fpga_io.pin_set_output(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP1) + self._fpga_io.pin_set_output(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP2) + self._fpga_io.pin_set_output(self._PIN_MAPPINGS[self._board].PIN_TAP_STRAP0) + self._fpga_io.pin_set_output(self._PIN_MAPPINGS[self._board].PIN_TAP_STRAP1) self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_TRST, 1) self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SRST, 1) - self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_JTAG_SPI, 1) - self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_BOOTSTRAP, 0) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP0, 0) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP1, 0) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP2, 0) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_TAP_STRAP0, 0) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_TAP_STRAP1, 1) # Initialize SPI pins. self._fpga_io.spi1_setpins(sck=self._PIN_MAPPINGS[self._board].PIN_SCK, sdo=self._PIN_MAPPINGS[self._board].PIN_SDI, @@ -193,7 +209,7 @@ self._fpga_io.spi1_enable(True) def _reset_opentitan(self): - self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_JTAG_SPI, 1) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_TAP_STRAP1, 1) self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SRST, 0) time.sleep(self._BOOTSTRAP_DELAY) self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SRST, 1) @@ -201,16 +217,20 @@ def __enter__(self): """Starts bootstrapping.""" - self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_BOOTSTRAP, 1) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP0, 1) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP1, 1) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP2, 1) self._reset_opentitan() - self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_JTAG_SPI, 0) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_TAP_STRAP1, 0) time.sleep(self._BOOTSTRAP_DELAY) return self def __exit__(self, exc_type, exc_value, traceback): """Ends bootstrapping.""" - self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_BOOTSTRAP, 0) - self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_JTAG_SPI, 1) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP0, 0) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP1, 0) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_SW_STRAP2, 0) + self._fpga_io.pin_set_state(self._PIN_MAPPINGS[self._board].PIN_TAP_STRAP1, 1) time.sleep(self._BOOTSTRAP_DELAY) def transfer(self, frame):