hw/ip/flash_ctrl/data/flash_ctrl_testplan.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  name: "flash_ctrl"
  // TODO: remove the common testplans if not applicable
  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
                     // TODO: Top-level specific Hjson imported here. This will likely be resolved
                     // once we move to IPgen flow.
                     "hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl_sec_cm_testplan.hjson"]
  testpoints: [
    {
      name: smoke
      desc: '''
            Randomly read, program or erase (page or a bank) a randomized chunk of flash memory.
            Only the data partition is accessed. No extra features enabled. Flash memory is
            invalidated and the targeted chunk is initialized with random data for reads and all 1s
            for writes. Interrupts are not enabled, Completion is ascertained through polling. The
            success of each operation is verified via backdoor.
            '''
      milestone: V1
      tests: ["flash_ctrl_smoke"]
    }
    {
      name: smoke_hw
      desc: '''
            Perform host direct read on the single page of Data partition. First Flash memory is
            initialized with random values and then it is being read directly by Host interface.
            Finally, backdoor read is used for checking read data.
            '''
      milestone: V1
      tests: ["flash_ctrl_smoke_hw"]
    }
    {
      name: sw_op
      desc: '''
            Perform flash protocol controller read, program and erase on the single page of one
            bank within Data partition. Finally perform read on same location in order to test
            if previous operation was done successfully.
            '''
      milestone: V2
      tests: ["flash_ctrl_sw_op"]
    }
    {
      name: host_read_direct
      desc: '''
            Perform back-to-back direct reads via Host in order to test bandwidth of hardware host
            interface. In addition, perform stalls to test pipeline structure. Enable scramble to
            test pipeline structure.
            '''
      milestone: V2
      tests: ["flash_ctrl_host_dir_rd"]
    }
    {
      name: rma_hw_if
      desc: '''
            Perform RMA entry requests and check afterwards that the  software has no access to
            the Flash.  After RMA entry, verify that the content of the flash is wiped out.
            '''
      milestone: V2
      tests: ["flash_ctrl_hw_rma"]
    }
    {
      name: host_controller_arb
      desc: '''
            Perform operations via the Flash Software Interface, and at the same time invoke a
            Hardware RMA operation. This verifies the arbitration within the Flash Protocol
            Controller. The arbiter should allow any outstanding Software operations to complete
            before the RMA starts. When the RMA completes the RMA FSM remains in its final state
            until Reset and software access is blocked.
            '''
      milestone: V2
      tests: ["flash_ctrl_host_ctrl_arb"]
    }
    {
      name: erase_suspend
      desc: '''
            Perform erase suspend when erase is ongoing and also when erase is not ongoing.
            Check if request is immediately cleared in case when no erase is ongoing.
            Check if request is cleared in case when suspend is handled.
            Read affected bank in order to verify erase suspension feature.
            '''
      milestone: V2
      tests: ["flash_ctrl_erase_suspend"]
    }
    {
      name: full_memory_access
      desc: '''
            Entire memory is accessed by Controller and directly by Host. In addition, Data
            partitions can be directly read by Software(Flash controller) and hardware hosts,
            while Info partitions can be read only by the Flash controller.
            '''
      milestone: V2
      tests: ["flash_ctrl_full_mem_access"]
    }
    {
      name: rd_buff_eviction
      desc: '''
            Perform following sequences of operations: read/program/read and read/erase/read in
            order to test read buffer eviction properly. Read should be executed by both Software
            and Host interface. All combinations should be tested. Covergroup for this hazardous
            behavior is rd_buff_evict_cg.
            '''
      milestone: V2
      tests: ["flash_ctrl_rd_buff_evict"]
    }
    {
      name: host_arb
      desc: '''
            Test arbitration within Flash Physical Controller by reading from both interfaces at
            the same time. Perform continuously direct read data from host interface and at the
            same time, perform all operations READ/PROGRAM/ERASE from the flash controller is in
            progress. Perform parallel operations at addresses of different banks and also on same
            bank. Expect that operations are successfully executed.
            '''
      milestone: V2
      tests: ["flash_ctrl_phy_arb"]
    }
    {
      name: host_interleave
      desc: '''
            At same time, perform two read operations and the same time via host and via
            controller. At same time, perform read operation via host and program
            operation via controller. Perform mentioned parallel operations at different addresses
            and on the same address. Expect that operations are successfully
            executed.
            '''
      milestone: V2
      tests: ["flash_ctrl_phy_arb"]
    }
    {
      name: memory_protection
      desc: '''
            Perform READ/ PROGRAM/ ERASE operations over protected regions and pages of data and
            info partitions. Use set and reset values of corresponding read, program and erase
            enable bits. Test boundary values of regions. Test overlap of regions in which lower
            region wins arbitration. Covergroup is region_range_cg.
            '''
      milestone: V2
      tests: ["flash_ctrl_mp_regions"]
    }
    {
      name: fetch_code
      desc: '''
            Verify the Code Fetch Feature.
            Reads for instructions via the Hardware Interface are allowed if a specific value
            is written to the EXEC csr.
            '''
      milestone: V2
      tests: ["flash_ctrl_fetch_code"]
    }
    {
      name: all_partitions
      desc: '''
            Sanity + both, legal data and info partitions are accessed. In future, support for
            multiple info partitions may be added - those will be covered as well.
            '''
      milestone: V2
      tests: ["flash_ctrl_rand_ops"]
    }
    {
      name: error_mp
      desc: '''
            Perform accesses in order to provoke memory permission errors. Test the Software
            interface (Erase, Program, Read). Related covergroup is error_cg.
            '''
      milestone: V2
      tests: ["flash_ctrl_error_mp"]
    }
    {
      name: error_rd
      desc: '''
            Perform accesses in order to provoke read data error. Test both, Software interface and
            Hardware interface. Related covergroup is error_cg.
            '''
      milestone: V2S
      tests: []
    }
    {
      name: error_prog_win
      desc: '''
            Perform accesses in order to provoke the 'program resolution' error.
            Test via the Software interface. Related covergroup is error_cg.
            '''
      milestone: V2
      tests: ["flash_ctrl_error_prog_win"]
    }
    {
      name: error_prog_type
      desc: '''
            Perform accesses in order to provoke the 'program type' error.
            Test via the Software interface. Related covergroup is error_cg.
            '''
      milestone: V2
      tests: ["flash_ctrl_error_prog_type"]
    }
    {
      name: stress_all
      desc: '''
            - combine above sequences in one test to run sequentially, except csr sequence
            - randomly add reset between each sequence
            '''
      milestone: V2
      tests: ["flash_ctrl_stress_all"]
    }
    {
      name: error_flash_phy
      desc: '''
            Perform accesses in order to provoke native flash error. Test both, Software interface
            and Hardware interface. Related covergroup is error_cg.
            '''
      milestone: V2S
      tests: []
    }
    {
      name: error_lc
      desc: '''
            Perform accesses in order to provoke life cycle management interface error. Related
            covergroup is error_cg.
            '''
      milestone: V2S
      tests: []
    }
    {
      name: secret_partition
      desc: '''
            Verify the secret information partitions. Accessibility is controlled by the Life Cycle Controller
            Seeds are read upon flash controller initialization and sent to the Key Manager, additionally verify
            that scramble Keys are Read from the OTP and sent into the Flash Ctlr.  Also erify that programmed
            Secret Partitions retain their values through a Reset Cycle.
            '''
      milestone: V2
      tests: ["flash_ctrl_hw_sec_otp"]
    }
    {
      name: isolation_partition
      desc: '''
            Verify the isolated information partitions. Accessablity is controlled by Life
            Cycle Controller.  Verify Partition can be erase, written and programmed, with
            HW control, and wipes after an RMA.
            '''
      milestone: V2
      tests: ["flash_ctrl_hw_rma"]
    }
    {
      name: interrupts
      desc: '''
            Perform accesses in order to raise all interrupts given in register map.
            Check behaviour of Interrupt Enable and Status Registers.
            '''
      milestone: V2
      tests: []
    }
    {
      name: invalid_op
      desc: '''
            Send invalid command in order to check that it does not affect memory content.
            Check that recovery alert is triggered.
            '''
      milestone: V2
      tests: ["flash_ctrl_invalid_op"]
    }
    {
      name: ecc
      desc: '''
            Randomly enable ECC for a randomly selected set of pages. Randomly corrupt a single bit
            in the memory that is about to be read and ensure that the ECC works - the corrupted
            bit should be fixed. Corrupt randomly either the data or the ECC bits. Randomly corrupt
            2 bits in the same word and ensure that the read results in error. Ensure that pages
            with ECC not enabled reads back corrupted data without any errors. Verify both types,
            pre-scramble ECC(integrity ESS, 4-bits) and post-scramble ECC(reliability ECC, 8-bits).
	    Test status and control ECC bits.
            '''
      milestone: V2S
      tests: []
    }
    {
      name: scramble
      desc: '''
            Enable scrambling, along with randomized scramble keys. Program a fresh chunk of
            memory and read back (both, via controller and host) to ensure data integrity. On
            program, verify via backdoor scrambling was done on the raw data correctly. When
            reading via host, read the same memory via host multiple times back-to-back and ensure
            the timing is correct (subsequent reads should be faster). When scrambling is not
            enabled, ensure that the raw data is written and read back.
            '''
      milestone: V2S
      tests: []
    }
    {
      name: robustness
      desc: '''
            Enable full randomization in order to fully stress DUT. Perform illegal accesses in
            order to gain robustness.
            '''
      milestone: V3
      tests: []
    }
  ]

  covergroups: [
    {
      name: control_cg
      desc: '''
            Covers that all operations READ/PROGRAM/ERASE/UNKNOWN have been tested.
            Covers that ERASE operation is performed on a page and on entire bank.
            Covers data and info partitions selection.
            All valid combinations of the above will also be crossed.
            '''
    }
    {
      name: erase_susp_cg
      desc: '''
            Covers if request of erase suspension occured.
            '''
    }
    {
      name: msgfifo_level_cg
      desc: '''
            Covers that all possible fifo statuses generate interrupts for operations READ/PROGRAM.
            Covers both boundary values 0 and 31. Also covers acceptable distributions within
            ranges.
            '''
    }
    {
      name: rd_buff_evict_cg
      desc: '''
            Covers that all possible combinations for following sequences of operations
            READ/PROGRAM/READ and READ/ERASE/READ are executed. Software Interface can perform all
            three operations READ/PROGRAM/ERASE while Host Interface can perform direct READ.
            '''
    }
    {
      name: error_cg
      desc: '''
            Covers following error scenarios given in Flash error code register:
            - mp_err: Flash access has encountered an access permission error.
            - rd_err: Flash read has an uncorrectable data error.
            - prog_win_err: Flash program has a window resolution error.
            - prog_type_err: Flash program selected unavailable type.
            - flash_phy_err: The flash access encountered a native flash error.
            Covers following error scenarios given in Flash fault status register:
            - mp_err: The flash hardware interface encountered a memory permission error.
            - rd_err: The flash hardware interface encountered a read data error.
            - prog_win_err: The flash hardware interface encountered a program resolution error.
            - prog_type_err: The flash hardware interface encountered a program type error.
            - flash_phy_err: The flash hardware interface encountered a native flash error.
            - lcmgr_err: The life cycle management interface has encountered a fatal error.
            '''
    }
  ]
}