[dv common] SW test status interface updates
- Now written in pure SV for Verilator compatibility
- Fixes some simulation issues with previous implementation.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/top_earlgrey/dv/env/sw_test_status_if.sv b/hw/top_earlgrey/dv/env/sw_test_status_if.sv
index 4fa7bca..35f40b6 100644
--- a/hw/top_earlgrey/dv/env/sw_test_status_if.sv
+++ b/hw/top_earlgrey/dv/env/sw_test_status_if.sv
@@ -2,18 +2,24 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-interface sw_test_status_if ();
- import top_pkg::*;
+interface sw_test_status_if (
+ input clk,
+ input valid,
+ input bit [15:0] data
+);
+
+ import bus_params_pkg::*;
import sw_test_status_pkg::*;
+`ifdef UVM
+ import uvm_pkg::*;
+ `include "uvm_macros.svh"
+`endif
// Single cycle qualifier for the sw_test_status_val.
logic valid;
// Address to which the test status is written to.
- logic [TL_AW-1:0] sw_test_status_addr;
-
- // SW test status written by the CPU.
- logic [TL_DW-1:0] sw_test_status_val;
+ logic [bus_params_pkg::BUS_AW-1:0] sw_test_status_addr;
// SW test status indication.
sw_test_status_e sw_test_status;
@@ -21,16 +27,22 @@
// If the sw_test_status reaches the terminal states, assert that we are done.
bit sw_test_done;
- // Logic that updates the sw_test_status from the val.
- // Note that sw_test_status is set by the testbench when the CPU is under reset.
- initial begin
- forever begin
- @(valid);
- if (valid) begin
- sw_test_status = sw_test_status_e'(sw_test_status_val[15:0]);
- if (!sw_test_done) begin
- sw_test_done = (sw_test_status inside {SwTestStatusPassed, SwTestStatusFailed});
- end
+ always @(posedge clk) begin
+ if (valid) begin
+ if ($cast(sw_test_status, data)) begin
+`ifdef UVM
+ `uvm_info($sformatf("%m"), $sformatf("Detected SW test status change: %0s",
+ sw_test_status.name()), UVM_LOW)
+`elsif VERILATOR
+ $display("%t [%m]: Detected SW test status change: 0x%0h", $time, sw_test_status);
+`else
+ $display("%t [%m]: Detected SW test status change: %0s", $time, sw_test_status.name());
+`endif
+ sw_test_done = sw_test_done | (sw_test_status inside {SwTestStatusPassed,
+ SwTestStatusFailed});
+ end else begin
+ $error("%t [%m] Illegal sw_test_status data 0x%0h written to addr 0x%0h",
+ $time, data, sw_test_status_addr);
end
end
end
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index 317fcd6..72e1cae 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -124,11 +124,11 @@
bit [TL_AW-1:0] sw_log_addr;
sw_logger_if sw_logger_if (
- .clk (`RAM_MAIN_SUB_HIER.clk_i),
- .rst_n (`RAM_MAIN_HIER.rst_ni),
- .valid (sw_log_valid),
- .addr_data (`RAM_MAIN_SUB_HIER.wdata_i),
- .sw_log_addr (sw_log_addr)
+ .clk (`RAM_MAIN_SUB_HIER.clk_i),
+ .rst_n (`RAM_MAIN_HIER.rst_ni),
+ .valid (sw_log_valid),
+ .addr_data (`RAM_MAIN_SUB_HIER.wdata_i),
+ .sw_log_addr(sw_log_addr)
);
assign sw_log_valid = !stub_cpu &&
`RAM_MAIN_SUB_HIER.req_i &&
@@ -137,13 +137,17 @@
(`RAM_MAIN_SUB_HIER.addr_i == sw_log_addr[15:2]);
// connect the sw_test_status_if
- sw_test_status_if sw_test_status_if();
- assign sw_test_status_if.valid = !stub_cpu &&
- `RAM_MAIN_SUB_HIER.req_i &&
- `RAM_MAIN_SUB_HIER.write_i &&
- (`RAM_MAIN_SUB_HIER.addr_i ==
- sw_test_status_if.sw_test_status_addr[15:2]);
- assign sw_test_status_if.sw_test_status_val = `RAM_MAIN_SUB_HIER.wdata_i;
+ bit sw_test_status_valid;
+ sw_test_status_if sw_test_status_if(
+ .clk (`RAM_MAIN_SUB_HIER.clk_i),
+ .valid(sw_test_status_valid),
+ .data (`RAM_MAIN_SUB_HIER.wdata_i[15:0])
+ );
+ assign sw_test_status_valid = !stub_cpu &&
+ `RAM_MAIN_SUB_HIER.req_i &&
+ `RAM_MAIN_SUB_HIER.write_i &&
+ (`RAM_MAIN_SUB_HIER.addr_i ==
+ sw_test_status_if.sw_test_status_addr[15:2]);
// Instantiate & connect the simulation SRAM.
sim_sram u_sim_sram (
