| commit | 890cf7cf47ebc49ba839ab9e69ef10df552f27bf | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Sun Oct 04 19:40:12 2020 -0700 |
| committer | sriyerg <46467186+sriyerg@users.noreply.github.com> | Fri Oct 09 14:19:02 2020 -0700 |
| tree | 1f707fb69269c1368cf66015cfbffdb3d824c15f | |
| parent | 4fa34a9cdc438785032e8574bdbbf64710ef2229 [diff] |
[dv, verilator] Simulation memory prototype impl This change set implements a small memory used for chip level simulations. An empty space in the chip address map can be used for this memory. It is primarily used for the embedded CPU in the design (Ibex) to signal information to the testbench, for example indicate when the SW is done and the simulation can exit. Currently, a couple of addresses in our on-device SRAM are being used for this purpose. With this patch, those are completely gone. The simulation SRAM intercepts a TL interface to instantiate a 1:2 socket and the (adapter + ) SRAM. This must NOT exist during synthesis, hence takes the following strategy: - An interception point is created in `rv_core_ibex` - this is done by disconnecting the output of the TL fifo and the module port. This disconnection happens only if `VERILATOR` or `UVM` is defined. - THis allows the user to instantiate the SRAM in the testbench and connect its inputs and outptuts to the interception point in `rv_core_ibex`. - This enables us to preserve the original design hierarchy without pulluting with simulation components (or adding forces which is not supported in Verilator). Please see sim_sram documentation for more details. Once approved, the address locations for signaling the end of test and logging will be switched over to use this address space. Signed-off-by: Srikrishna Iyer <sriyer@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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