| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Top module auto-generated by `reggen` |
| |
| |
| module rv_plic_reg_top ( |
| input clk_i, |
| input rst_ni, |
| |
| // Below Regster interface can be changed |
| input tlul_pkg::tl_h2d_t tl_i, |
| output tlul_pkg::tl_d2h_t tl_o, |
| // To HW |
| output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write |
| input rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg // Read |
| ); |
| |
| import rv_plic_reg_pkg::* ; |
| |
| localparam AW = 9; |
| localparam DW = 32; |
| localparam DBW = DW/8; // Byte Width |
| localparam logic [$clog2($clog2(DBW)+1)-1:0] FSZ = $clog2(DBW); // Full Size 2^(FSZ) = DBW; |
| |
| // register signals |
| logic reg_we; |
| logic reg_re; |
| logic [AW-1:0] reg_addr; |
| logic [DW-1:0] reg_wdata; |
| logic [DBW-1:0] reg_be; |
| logic [DW-1:0] reg_rdata; |
| logic reg_error; |
| |
| logic malformed, addrmiss; |
| |
| logic [DW-1:0] reg_rdata_next; |
| |
| tlul_pkg::tl_h2d_t tl_reg_h2d; |
| tlul_pkg::tl_d2h_t tl_reg_d2h; |
| |
| assign tl_reg_h2d = tl_i; |
| assign tl_o = tl_reg_d2h; |
| |
| tlul_adapter_reg #( |
| .RegAw(AW), |
| .RegDw(DW) |
| ) u_reg_if ( |
| .clk_i, |
| .rst_ni, |
| |
| .tl_i (tl_reg_h2d), |
| .tl_o (tl_reg_d2h), |
| |
| .we_o (reg_we), |
| .re_o (reg_re), |
| .addr_o (reg_addr), |
| .wdata_o (reg_wdata), |
| .be_o (reg_be), |
| .rdata_i (reg_rdata), |
| .error_i (reg_error) |
| ); |
| |
| assign reg_rdata = reg_rdata_next ; |
| assign reg_error = malformed | addrmiss ; |
| |
| // Malformed request check only affects to the write access |
| always_comb begin : malformed_check |
| if (reg_we && (reg_be != '1)) begin |
| malformed = 1'b1; |
| end else begin |
| malformed = 1'b0; |
| end |
| end |
| |
| // TODO(eunchan): Revise Register Interface logic after REG INTF finalized |
| // TODO(eunchan): Make concrete scenario |
| // 1. Write: No response, so that it can guarantee a request completes a clock after we |
| // It means, bus_reg_ready doesn't have to be lowered. |
| // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready |
| // _____ _____ |
| // a_valid _____/ \_______/ \______ |
| // ___________ _____ |
| // a_ready \_______/ \______ <- ERR though no logic malfunction |
| // _____________ |
| // d_valid ___________/ \______ |
| // _____ |
| // d_ready ___________________/ \______ |
| // |
| // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong. |
| |
| // Define SW related signals |
| // Format: <reg>_<field>_{wd|we|qs} |
| // or <reg>_{wd|we|qs} if field == 1 or 0 |
| logic ip0_p0_qs; |
| logic ip0_p1_qs; |
| logic ip0_p2_qs; |
| logic ip0_p3_qs; |
| logic ip0_p4_qs; |
| logic ip0_p5_qs; |
| logic ip0_p6_qs; |
| logic ip0_p7_qs; |
| logic ip0_p8_qs; |
| logic ip0_p9_qs; |
| logic ip0_p10_qs; |
| logic ip0_p11_qs; |
| logic ip0_p12_qs; |
| logic ip0_p13_qs; |
| logic ip0_p14_qs; |
| logic ip0_p15_qs; |
| logic ip0_p16_qs; |
| logic ip0_p17_qs; |
| logic ip0_p18_qs; |
| logic ip0_p19_qs; |
| logic ip0_p20_qs; |
| logic ip0_p21_qs; |
| logic ip0_p22_qs; |
| logic ip0_p23_qs; |
| logic ip0_p24_qs; |
| logic ip0_p25_qs; |
| logic ip0_p26_qs; |
| logic ip0_p27_qs; |
| logic ip0_p28_qs; |
| logic ip0_p29_qs; |
| logic ip0_p30_qs; |
| logic ip0_p31_qs; |
| logic ip1_p32_qs; |
| logic ip1_p33_qs; |
| logic ip1_p34_qs; |
| logic ip1_p35_qs; |
| logic ip1_p36_qs; |
| logic ip1_p37_qs; |
| logic ip1_p38_qs; |
| logic ip1_p39_qs; |
| logic ip1_p40_qs; |
| logic ip1_p41_qs; |
| logic ip1_p42_qs; |
| logic ip1_p43_qs; |
| logic ip1_p44_qs; |
| logic ip1_p45_qs; |
| logic ip1_p46_qs; |
| logic ip1_p47_qs; |
| logic ip1_p48_qs; |
| logic ip1_p49_qs; |
| logic ip1_p50_qs; |
| logic ip1_p51_qs; |
| logic le0_le0_qs; |
| logic le0_le0_wd; |
| logic le0_le0_we; |
| logic le0_le1_qs; |
| logic le0_le1_wd; |
| logic le0_le1_we; |
| logic le0_le2_qs; |
| logic le0_le2_wd; |
| logic le0_le2_we; |
| logic le0_le3_qs; |
| logic le0_le3_wd; |
| logic le0_le3_we; |
| logic le0_le4_qs; |
| logic le0_le4_wd; |
| logic le0_le4_we; |
| logic le0_le5_qs; |
| logic le0_le5_wd; |
| logic le0_le5_we; |
| logic le0_le6_qs; |
| logic le0_le6_wd; |
| logic le0_le6_we; |
| logic le0_le7_qs; |
| logic le0_le7_wd; |
| logic le0_le7_we; |
| logic le0_le8_qs; |
| logic le0_le8_wd; |
| logic le0_le8_we; |
| logic le0_le9_qs; |
| logic le0_le9_wd; |
| logic le0_le9_we; |
| logic le0_le10_qs; |
| logic le0_le10_wd; |
| logic le0_le10_we; |
| logic le0_le11_qs; |
| logic le0_le11_wd; |
| logic le0_le11_we; |
| logic le0_le12_qs; |
| logic le0_le12_wd; |
| logic le0_le12_we; |
| logic le0_le13_qs; |
| logic le0_le13_wd; |
| logic le0_le13_we; |
| logic le0_le14_qs; |
| logic le0_le14_wd; |
| logic le0_le14_we; |
| logic le0_le15_qs; |
| logic le0_le15_wd; |
| logic le0_le15_we; |
| logic le0_le16_qs; |
| logic le0_le16_wd; |
| logic le0_le16_we; |
| logic le0_le17_qs; |
| logic le0_le17_wd; |
| logic le0_le17_we; |
| logic le0_le18_qs; |
| logic le0_le18_wd; |
| logic le0_le18_we; |
| logic le0_le19_qs; |
| logic le0_le19_wd; |
| logic le0_le19_we; |
| logic le0_le20_qs; |
| logic le0_le20_wd; |
| logic le0_le20_we; |
| logic le0_le21_qs; |
| logic le0_le21_wd; |
| logic le0_le21_we; |
| logic le0_le22_qs; |
| logic le0_le22_wd; |
| logic le0_le22_we; |
| logic le0_le23_qs; |
| logic le0_le23_wd; |
| logic le0_le23_we; |
| logic le0_le24_qs; |
| logic le0_le24_wd; |
| logic le0_le24_we; |
| logic le0_le25_qs; |
| logic le0_le25_wd; |
| logic le0_le25_we; |
| logic le0_le26_qs; |
| logic le0_le26_wd; |
| logic le0_le26_we; |
| logic le0_le27_qs; |
| logic le0_le27_wd; |
| logic le0_le27_we; |
| logic le0_le28_qs; |
| logic le0_le28_wd; |
| logic le0_le28_we; |
| logic le0_le29_qs; |
| logic le0_le29_wd; |
| logic le0_le29_we; |
| logic le0_le30_qs; |
| logic le0_le30_wd; |
| logic le0_le30_we; |
| logic le0_le31_qs; |
| logic le0_le31_wd; |
| logic le0_le31_we; |
| logic le1_le32_qs; |
| logic le1_le32_wd; |
| logic le1_le32_we; |
| logic le1_le33_qs; |
| logic le1_le33_wd; |
| logic le1_le33_we; |
| logic le1_le34_qs; |
| logic le1_le34_wd; |
| logic le1_le34_we; |
| logic le1_le35_qs; |
| logic le1_le35_wd; |
| logic le1_le35_we; |
| logic le1_le36_qs; |
| logic le1_le36_wd; |
| logic le1_le36_we; |
| logic le1_le37_qs; |
| logic le1_le37_wd; |
| logic le1_le37_we; |
| logic le1_le38_qs; |
| logic le1_le38_wd; |
| logic le1_le38_we; |
| logic le1_le39_qs; |
| logic le1_le39_wd; |
| logic le1_le39_we; |
| logic le1_le40_qs; |
| logic le1_le40_wd; |
| logic le1_le40_we; |
| logic le1_le41_qs; |
| logic le1_le41_wd; |
| logic le1_le41_we; |
| logic le1_le42_qs; |
| logic le1_le42_wd; |
| logic le1_le42_we; |
| logic le1_le43_qs; |
| logic le1_le43_wd; |
| logic le1_le43_we; |
| logic le1_le44_qs; |
| logic le1_le44_wd; |
| logic le1_le44_we; |
| logic le1_le45_qs; |
| logic le1_le45_wd; |
| logic le1_le45_we; |
| logic le1_le46_qs; |
| logic le1_le46_wd; |
| logic le1_le46_we; |
| logic le1_le47_qs; |
| logic le1_le47_wd; |
| logic le1_le47_we; |
| logic le1_le48_qs; |
| logic le1_le48_wd; |
| logic le1_le48_we; |
| logic le1_le49_qs; |
| logic le1_le49_wd; |
| logic le1_le49_we; |
| logic le1_le50_qs; |
| logic le1_le50_wd; |
| logic le1_le50_we; |
| logic le1_le51_qs; |
| logic le1_le51_wd; |
| logic le1_le51_we; |
| logic [1:0] prio0_qs; |
| logic [1:0] prio0_wd; |
| logic prio0_we; |
| logic [1:0] prio1_qs; |
| logic [1:0] prio1_wd; |
| logic prio1_we; |
| logic [1:0] prio2_qs; |
| logic [1:0] prio2_wd; |
| logic prio2_we; |
| logic [1:0] prio3_qs; |
| logic [1:0] prio3_wd; |
| logic prio3_we; |
| logic [1:0] prio4_qs; |
| logic [1:0] prio4_wd; |
| logic prio4_we; |
| logic [1:0] prio5_qs; |
| logic [1:0] prio5_wd; |
| logic prio5_we; |
| logic [1:0] prio6_qs; |
| logic [1:0] prio6_wd; |
| logic prio6_we; |
| logic [1:0] prio7_qs; |
| logic [1:0] prio7_wd; |
| logic prio7_we; |
| logic [1:0] prio8_qs; |
| logic [1:0] prio8_wd; |
| logic prio8_we; |
| logic [1:0] prio9_qs; |
| logic [1:0] prio9_wd; |
| logic prio9_we; |
| logic [1:0] prio10_qs; |
| logic [1:0] prio10_wd; |
| logic prio10_we; |
| logic [1:0] prio11_qs; |
| logic [1:0] prio11_wd; |
| logic prio11_we; |
| logic [1:0] prio12_qs; |
| logic [1:0] prio12_wd; |
| logic prio12_we; |
| logic [1:0] prio13_qs; |
| logic [1:0] prio13_wd; |
| logic prio13_we; |
| logic [1:0] prio14_qs; |
| logic [1:0] prio14_wd; |
| logic prio14_we; |
| logic [1:0] prio15_qs; |
| logic [1:0] prio15_wd; |
| logic prio15_we; |
| logic [1:0] prio16_qs; |
| logic [1:0] prio16_wd; |
| logic prio16_we; |
| logic [1:0] prio17_qs; |
| logic [1:0] prio17_wd; |
| logic prio17_we; |
| logic [1:0] prio18_qs; |
| logic [1:0] prio18_wd; |
| logic prio18_we; |
| logic [1:0] prio19_qs; |
| logic [1:0] prio19_wd; |
| logic prio19_we; |
| logic [1:0] prio20_qs; |
| logic [1:0] prio20_wd; |
| logic prio20_we; |
| logic [1:0] prio21_qs; |
| logic [1:0] prio21_wd; |
| logic prio21_we; |
| logic [1:0] prio22_qs; |
| logic [1:0] prio22_wd; |
| logic prio22_we; |
| logic [1:0] prio23_qs; |
| logic [1:0] prio23_wd; |
| logic prio23_we; |
| logic [1:0] prio24_qs; |
| logic [1:0] prio24_wd; |
| logic prio24_we; |
| logic [1:0] prio25_qs; |
| logic [1:0] prio25_wd; |
| logic prio25_we; |
| logic [1:0] prio26_qs; |
| logic [1:0] prio26_wd; |
| logic prio26_we; |
| logic [1:0] prio27_qs; |
| logic [1:0] prio27_wd; |
| logic prio27_we; |
| logic [1:0] prio28_qs; |
| logic [1:0] prio28_wd; |
| logic prio28_we; |
| logic [1:0] prio29_qs; |
| logic [1:0] prio29_wd; |
| logic prio29_we; |
| logic [1:0] prio30_qs; |
| logic [1:0] prio30_wd; |
| logic prio30_we; |
| logic [1:0] prio31_qs; |
| logic [1:0] prio31_wd; |
| logic prio31_we; |
| logic [1:0] prio32_qs; |
| logic [1:0] prio32_wd; |
| logic prio32_we; |
| logic [1:0] prio33_qs; |
| logic [1:0] prio33_wd; |
| logic prio33_we; |
| logic [1:0] prio34_qs; |
| logic [1:0] prio34_wd; |
| logic prio34_we; |
| logic [1:0] prio35_qs; |
| logic [1:0] prio35_wd; |
| logic prio35_we; |
| logic [1:0] prio36_qs; |
| logic [1:0] prio36_wd; |
| logic prio36_we; |
| logic [1:0] prio37_qs; |
| logic [1:0] prio37_wd; |
| logic prio37_we; |
| logic [1:0] prio38_qs; |
| logic [1:0] prio38_wd; |
| logic prio38_we; |
| logic [1:0] prio39_qs; |
| logic [1:0] prio39_wd; |
| logic prio39_we; |
| logic [1:0] prio40_qs; |
| logic [1:0] prio40_wd; |
| logic prio40_we; |
| logic [1:0] prio41_qs; |
| logic [1:0] prio41_wd; |
| logic prio41_we; |
| logic [1:0] prio42_qs; |
| logic [1:0] prio42_wd; |
| logic prio42_we; |
| logic [1:0] prio43_qs; |
| logic [1:0] prio43_wd; |
| logic prio43_we; |
| logic [1:0] prio44_qs; |
| logic [1:0] prio44_wd; |
| logic prio44_we; |
| logic [1:0] prio45_qs; |
| logic [1:0] prio45_wd; |
| logic prio45_we; |
| logic [1:0] prio46_qs; |
| logic [1:0] prio46_wd; |
| logic prio46_we; |
| logic [1:0] prio47_qs; |
| logic [1:0] prio47_wd; |
| logic prio47_we; |
| logic [1:0] prio48_qs; |
| logic [1:0] prio48_wd; |
| logic prio48_we; |
| logic [1:0] prio49_qs; |
| logic [1:0] prio49_wd; |
| logic prio49_we; |
| logic [1:0] prio50_qs; |
| logic [1:0] prio50_wd; |
| logic prio50_we; |
| logic [1:0] prio51_qs; |
| logic [1:0] prio51_wd; |
| logic prio51_we; |
| logic ie00_e0_qs; |
| logic ie00_e0_wd; |
| logic ie00_e0_we; |
| logic ie00_e1_qs; |
| logic ie00_e1_wd; |
| logic ie00_e1_we; |
| logic ie00_e2_qs; |
| logic ie00_e2_wd; |
| logic ie00_e2_we; |
| logic ie00_e3_qs; |
| logic ie00_e3_wd; |
| logic ie00_e3_we; |
| logic ie00_e4_qs; |
| logic ie00_e4_wd; |
| logic ie00_e4_we; |
| logic ie00_e5_qs; |
| logic ie00_e5_wd; |
| logic ie00_e5_we; |
| logic ie00_e6_qs; |
| logic ie00_e6_wd; |
| logic ie00_e6_we; |
| logic ie00_e7_qs; |
| logic ie00_e7_wd; |
| logic ie00_e7_we; |
| logic ie00_e8_qs; |
| logic ie00_e8_wd; |
| logic ie00_e8_we; |
| logic ie00_e9_qs; |
| logic ie00_e9_wd; |
| logic ie00_e9_we; |
| logic ie00_e10_qs; |
| logic ie00_e10_wd; |
| logic ie00_e10_we; |
| logic ie00_e11_qs; |
| logic ie00_e11_wd; |
| logic ie00_e11_we; |
| logic ie00_e12_qs; |
| logic ie00_e12_wd; |
| logic ie00_e12_we; |
| logic ie00_e13_qs; |
| logic ie00_e13_wd; |
| logic ie00_e13_we; |
| logic ie00_e14_qs; |
| logic ie00_e14_wd; |
| logic ie00_e14_we; |
| logic ie00_e15_qs; |
| logic ie00_e15_wd; |
| logic ie00_e15_we; |
| logic ie00_e16_qs; |
| logic ie00_e16_wd; |
| logic ie00_e16_we; |
| logic ie00_e17_qs; |
| logic ie00_e17_wd; |
| logic ie00_e17_we; |
| logic ie00_e18_qs; |
| logic ie00_e18_wd; |
| logic ie00_e18_we; |
| logic ie00_e19_qs; |
| logic ie00_e19_wd; |
| logic ie00_e19_we; |
| logic ie00_e20_qs; |
| logic ie00_e20_wd; |
| logic ie00_e20_we; |
| logic ie00_e21_qs; |
| logic ie00_e21_wd; |
| logic ie00_e21_we; |
| logic ie00_e22_qs; |
| logic ie00_e22_wd; |
| logic ie00_e22_we; |
| logic ie00_e23_qs; |
| logic ie00_e23_wd; |
| logic ie00_e23_we; |
| logic ie00_e24_qs; |
| logic ie00_e24_wd; |
| logic ie00_e24_we; |
| logic ie00_e25_qs; |
| logic ie00_e25_wd; |
| logic ie00_e25_we; |
| logic ie00_e26_qs; |
| logic ie00_e26_wd; |
| logic ie00_e26_we; |
| logic ie00_e27_qs; |
| logic ie00_e27_wd; |
| logic ie00_e27_we; |
| logic ie00_e28_qs; |
| logic ie00_e28_wd; |
| logic ie00_e28_we; |
| logic ie00_e29_qs; |
| logic ie00_e29_wd; |
| logic ie00_e29_we; |
| logic ie00_e30_qs; |
| logic ie00_e30_wd; |
| logic ie00_e30_we; |
| logic ie00_e31_qs; |
| logic ie00_e31_wd; |
| logic ie00_e31_we; |
| logic ie01_e32_qs; |
| logic ie01_e32_wd; |
| logic ie01_e32_we; |
| logic ie01_e33_qs; |
| logic ie01_e33_wd; |
| logic ie01_e33_we; |
| logic ie01_e34_qs; |
| logic ie01_e34_wd; |
| logic ie01_e34_we; |
| logic ie01_e35_qs; |
| logic ie01_e35_wd; |
| logic ie01_e35_we; |
| logic ie01_e36_qs; |
| logic ie01_e36_wd; |
| logic ie01_e36_we; |
| logic ie01_e37_qs; |
| logic ie01_e37_wd; |
| logic ie01_e37_we; |
| logic ie01_e38_qs; |
| logic ie01_e38_wd; |
| logic ie01_e38_we; |
| logic ie01_e39_qs; |
| logic ie01_e39_wd; |
| logic ie01_e39_we; |
| logic ie01_e40_qs; |
| logic ie01_e40_wd; |
| logic ie01_e40_we; |
| logic ie01_e41_qs; |
| logic ie01_e41_wd; |
| logic ie01_e41_we; |
| logic ie01_e42_qs; |
| logic ie01_e42_wd; |
| logic ie01_e42_we; |
| logic ie01_e43_qs; |
| logic ie01_e43_wd; |
| logic ie01_e43_we; |
| logic ie01_e44_qs; |
| logic ie01_e44_wd; |
| logic ie01_e44_we; |
| logic ie01_e45_qs; |
| logic ie01_e45_wd; |
| logic ie01_e45_we; |
| logic ie01_e46_qs; |
| logic ie01_e46_wd; |
| logic ie01_e46_we; |
| logic ie01_e47_qs; |
| logic ie01_e47_wd; |
| logic ie01_e47_we; |
| logic ie01_e48_qs; |
| logic ie01_e48_wd; |
| logic ie01_e48_we; |
| logic ie01_e49_qs; |
| logic ie01_e49_wd; |
| logic ie01_e49_we; |
| logic ie01_e50_qs; |
| logic ie01_e50_wd; |
| logic ie01_e50_we; |
| logic ie01_e51_qs; |
| logic ie01_e51_wd; |
| logic ie01_e51_we; |
| logic [1:0] threshold0_qs; |
| logic [1:0] threshold0_wd; |
| logic threshold0_we; |
| logic [5:0] cc0_qs; |
| logic [5:0] cc0_wd; |
| logic cc0_we; |
| logic cc0_re; |
| logic msip0_qs; |
| logic msip0_wd; |
| logic msip0_we; |
| |
| // Register instances |
| // R[ip0]: V(False) |
| |
| // F[p0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p0.de), |
| .d (hw2reg.ip0.p0.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p0_qs) |
| ); |
| |
| |
| // F[p1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p1.de), |
| .d (hw2reg.ip0.p1.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p1_qs) |
| ); |
| |
| |
| // F[p2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p2.de), |
| .d (hw2reg.ip0.p2.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p2_qs) |
| ); |
| |
| |
| // F[p3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p3.de), |
| .d (hw2reg.ip0.p3.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p3_qs) |
| ); |
| |
| |
| // F[p4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p4.de), |
| .d (hw2reg.ip0.p4.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p4_qs) |
| ); |
| |
| |
| // F[p5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p5.de), |
| .d (hw2reg.ip0.p5.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p5_qs) |
| ); |
| |
| |
| // F[p6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p6 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p6.de), |
| .d (hw2reg.ip0.p6.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p6_qs) |
| ); |
| |
| |
| // F[p7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p7 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p7.de), |
| .d (hw2reg.ip0.p7.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p7_qs) |
| ); |
| |
| |
| // F[p8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p8 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p8.de), |
| .d (hw2reg.ip0.p8.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p8_qs) |
| ); |
| |
| |
| // F[p9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p9 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p9.de), |
| .d (hw2reg.ip0.p9.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p9_qs) |
| ); |
| |
| |
| // F[p10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p10 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p10.de), |
| .d (hw2reg.ip0.p10.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p10_qs) |
| ); |
| |
| |
| // F[p11]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p11 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p11.de), |
| .d (hw2reg.ip0.p11.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p11_qs) |
| ); |
| |
| |
| // F[p12]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p12 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p12.de), |
| .d (hw2reg.ip0.p12.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p12_qs) |
| ); |
| |
| |
| // F[p13]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p13 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p13.de), |
| .d (hw2reg.ip0.p13.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p13_qs) |
| ); |
| |
| |
| // F[p14]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p14 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p14.de), |
| .d (hw2reg.ip0.p14.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p14_qs) |
| ); |
| |
| |
| // F[p15]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p15 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p15.de), |
| .d (hw2reg.ip0.p15.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p15_qs) |
| ); |
| |
| |
| // F[p16]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p16 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p16.de), |
| .d (hw2reg.ip0.p16.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p16_qs) |
| ); |
| |
| |
| // F[p17]: 17:17 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p17 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p17.de), |
| .d (hw2reg.ip0.p17.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p17_qs) |
| ); |
| |
| |
| // F[p18]: 18:18 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p18 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p18.de), |
| .d (hw2reg.ip0.p18.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p18_qs) |
| ); |
| |
| |
| // F[p19]: 19:19 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p19 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p19.de), |
| .d (hw2reg.ip0.p19.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p19_qs) |
| ); |
| |
| |
| // F[p20]: 20:20 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p20 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p20.de), |
| .d (hw2reg.ip0.p20.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p20_qs) |
| ); |
| |
| |
| // F[p21]: 21:21 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p21 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p21.de), |
| .d (hw2reg.ip0.p21.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p21_qs) |
| ); |
| |
| |
| // F[p22]: 22:22 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p22 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p22.de), |
| .d (hw2reg.ip0.p22.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p22_qs) |
| ); |
| |
| |
| // F[p23]: 23:23 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p23 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p23.de), |
| .d (hw2reg.ip0.p23.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p23_qs) |
| ); |
| |
| |
| // F[p24]: 24:24 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p24 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p24.de), |
| .d (hw2reg.ip0.p24.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p24_qs) |
| ); |
| |
| |
| // F[p25]: 25:25 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p25 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p25.de), |
| .d (hw2reg.ip0.p25.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p25_qs) |
| ); |
| |
| |
| // F[p26]: 26:26 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p26 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p26.de), |
| .d (hw2reg.ip0.p26.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p26_qs) |
| ); |
| |
| |
| // F[p27]: 27:27 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p27 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p27.de), |
| .d (hw2reg.ip0.p27.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p27_qs) |
| ); |
| |
| |
| // F[p28]: 28:28 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p28 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p28.de), |
| .d (hw2reg.ip0.p28.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p28_qs) |
| ); |
| |
| |
| // F[p29]: 29:29 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p29 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p29.de), |
| .d (hw2reg.ip0.p29.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p29_qs) |
| ); |
| |
| |
| // F[p30]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p30 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p30.de), |
| .d (hw2reg.ip0.p30.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p30_qs) |
| ); |
| |
| |
| // F[p31]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip0_p31 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip0.p31.de), |
| .d (hw2reg.ip0.p31.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip0_p31_qs) |
| ); |
| |
| |
| // R[ip1]: V(False) |
| |
| // F[p32]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p32 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p32.de), |
| .d (hw2reg.ip1.p32.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p32_qs) |
| ); |
| |
| |
| // F[p33]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p33 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p33.de), |
| .d (hw2reg.ip1.p33.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p33_qs) |
| ); |
| |
| |
| // F[p34]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p34 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p34.de), |
| .d (hw2reg.ip1.p34.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p34_qs) |
| ); |
| |
| |
| // F[p35]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p35 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p35.de), |
| .d (hw2reg.ip1.p35.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p35_qs) |
| ); |
| |
| |
| // F[p36]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p36 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p36.de), |
| .d (hw2reg.ip1.p36.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p36_qs) |
| ); |
| |
| |
| // F[p37]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p37 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p37.de), |
| .d (hw2reg.ip1.p37.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p37_qs) |
| ); |
| |
| |
| // F[p38]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p38 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p38.de), |
| .d (hw2reg.ip1.p38.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p38_qs) |
| ); |
| |
| |
| // F[p39]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p39 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p39.de), |
| .d (hw2reg.ip1.p39.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p39_qs) |
| ); |
| |
| |
| // F[p40]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p40 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p40.de), |
| .d (hw2reg.ip1.p40.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p40_qs) |
| ); |
| |
| |
| // F[p41]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p41 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p41.de), |
| .d (hw2reg.ip1.p41.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p41_qs) |
| ); |
| |
| |
| // F[p42]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p42 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p42.de), |
| .d (hw2reg.ip1.p42.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p42_qs) |
| ); |
| |
| |
| // F[p43]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p43 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p43.de), |
| .d (hw2reg.ip1.p43.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p43_qs) |
| ); |
| |
| |
| // F[p44]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p44 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p44.de), |
| .d (hw2reg.ip1.p44.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p44_qs) |
| ); |
| |
| |
| // F[p45]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p45 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p45.de), |
| .d (hw2reg.ip1.p45.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p45_qs) |
| ); |
| |
| |
| // F[p46]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p46 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p46.de), |
| .d (hw2reg.ip1.p46.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p46_qs) |
| ); |
| |
| |
| // F[p47]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p47 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p47.de), |
| .d (hw2reg.ip1.p47.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p47_qs) |
| ); |
| |
| |
| // F[p48]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p48 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p48.de), |
| .d (hw2reg.ip1.p48.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p48_qs) |
| ); |
| |
| |
| // F[p49]: 17:17 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p49 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p49.de), |
| .d (hw2reg.ip1.p49.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p49_qs) |
| ); |
| |
| |
| // F[p50]: 18:18 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p50 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p50.de), |
| .d (hw2reg.ip1.p50.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p50_qs) |
| ); |
| |
| |
| // F[p51]: 19:19 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RO"), |
| .RESVAL (1'h0) |
| ) u_ip1_p51 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| .we (1'b0), |
| .wd ('0 ), |
| |
| // from internal hardware |
| .de (hw2reg.ip1.p51.de), |
| .d (hw2reg.ip1.p51.d ), |
| |
| // to internal hardware |
| .qe (), |
| .q (), |
| |
| // to register interface (read) |
| .qs (ip1_p51_qs) |
| ); |
| |
| |
| // R[le0]: V(False) |
| |
| // F[le0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le0_we), |
| .wd (le0_le0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le0.q ), |
| |
| // to register interface (read) |
| .qs (le0_le0_qs) |
| ); |
| |
| |
| // F[le1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le1_we), |
| .wd (le0_le1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le1.q ), |
| |
| // to register interface (read) |
| .qs (le0_le1_qs) |
| ); |
| |
| |
| // F[le2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le2_we), |
| .wd (le0_le2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le2.q ), |
| |
| // to register interface (read) |
| .qs (le0_le2_qs) |
| ); |
| |
| |
| // F[le3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le3_we), |
| .wd (le0_le3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le3.q ), |
| |
| // to register interface (read) |
| .qs (le0_le3_qs) |
| ); |
| |
| |
| // F[le4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le4_we), |
| .wd (le0_le4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le4.q ), |
| |
| // to register interface (read) |
| .qs (le0_le4_qs) |
| ); |
| |
| |
| // F[le5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le5_we), |
| .wd (le0_le5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le5.q ), |
| |
| // to register interface (read) |
| .qs (le0_le5_qs) |
| ); |
| |
| |
| // F[le6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le6 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le6_we), |
| .wd (le0_le6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le6.q ), |
| |
| // to register interface (read) |
| .qs (le0_le6_qs) |
| ); |
| |
| |
| // F[le7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le7 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le7_we), |
| .wd (le0_le7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le7.q ), |
| |
| // to register interface (read) |
| .qs (le0_le7_qs) |
| ); |
| |
| |
| // F[le8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le8 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le8_we), |
| .wd (le0_le8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le8.q ), |
| |
| // to register interface (read) |
| .qs (le0_le8_qs) |
| ); |
| |
| |
| // F[le9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le9 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le9_we), |
| .wd (le0_le9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le9.q ), |
| |
| // to register interface (read) |
| .qs (le0_le9_qs) |
| ); |
| |
| |
| // F[le10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le10 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le10_we), |
| .wd (le0_le10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le10.q ), |
| |
| // to register interface (read) |
| .qs (le0_le10_qs) |
| ); |
| |
| |
| // F[le11]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le11 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le11_we), |
| .wd (le0_le11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le11.q ), |
| |
| // to register interface (read) |
| .qs (le0_le11_qs) |
| ); |
| |
| |
| // F[le12]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le12 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le12_we), |
| .wd (le0_le12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le12.q ), |
| |
| // to register interface (read) |
| .qs (le0_le12_qs) |
| ); |
| |
| |
| // F[le13]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le13 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le13_we), |
| .wd (le0_le13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le13.q ), |
| |
| // to register interface (read) |
| .qs (le0_le13_qs) |
| ); |
| |
| |
| // F[le14]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le14 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le14_we), |
| .wd (le0_le14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le14.q ), |
| |
| // to register interface (read) |
| .qs (le0_le14_qs) |
| ); |
| |
| |
| // F[le15]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le15 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le15_we), |
| .wd (le0_le15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le15.q ), |
| |
| // to register interface (read) |
| .qs (le0_le15_qs) |
| ); |
| |
| |
| // F[le16]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le16 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le16_we), |
| .wd (le0_le16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le16.q ), |
| |
| // to register interface (read) |
| .qs (le0_le16_qs) |
| ); |
| |
| |
| // F[le17]: 17:17 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le17 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le17_we), |
| .wd (le0_le17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le17.q ), |
| |
| // to register interface (read) |
| .qs (le0_le17_qs) |
| ); |
| |
| |
| // F[le18]: 18:18 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le18 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le18_we), |
| .wd (le0_le18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le18.q ), |
| |
| // to register interface (read) |
| .qs (le0_le18_qs) |
| ); |
| |
| |
| // F[le19]: 19:19 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le19 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le19_we), |
| .wd (le0_le19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le19.q ), |
| |
| // to register interface (read) |
| .qs (le0_le19_qs) |
| ); |
| |
| |
| // F[le20]: 20:20 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le20 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le20_we), |
| .wd (le0_le20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le20.q ), |
| |
| // to register interface (read) |
| .qs (le0_le20_qs) |
| ); |
| |
| |
| // F[le21]: 21:21 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le21 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le21_we), |
| .wd (le0_le21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le21.q ), |
| |
| // to register interface (read) |
| .qs (le0_le21_qs) |
| ); |
| |
| |
| // F[le22]: 22:22 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le22 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le22_we), |
| .wd (le0_le22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le22.q ), |
| |
| // to register interface (read) |
| .qs (le0_le22_qs) |
| ); |
| |
| |
| // F[le23]: 23:23 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le23 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le23_we), |
| .wd (le0_le23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le23.q ), |
| |
| // to register interface (read) |
| .qs (le0_le23_qs) |
| ); |
| |
| |
| // F[le24]: 24:24 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le24 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le24_we), |
| .wd (le0_le24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le24.q ), |
| |
| // to register interface (read) |
| .qs (le0_le24_qs) |
| ); |
| |
| |
| // F[le25]: 25:25 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le25 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le25_we), |
| .wd (le0_le25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le25.q ), |
| |
| // to register interface (read) |
| .qs (le0_le25_qs) |
| ); |
| |
| |
| // F[le26]: 26:26 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le26 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le26_we), |
| .wd (le0_le26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le26.q ), |
| |
| // to register interface (read) |
| .qs (le0_le26_qs) |
| ); |
| |
| |
| // F[le27]: 27:27 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le27 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le27_we), |
| .wd (le0_le27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le27.q ), |
| |
| // to register interface (read) |
| .qs (le0_le27_qs) |
| ); |
| |
| |
| // F[le28]: 28:28 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le28 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le28_we), |
| .wd (le0_le28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le28.q ), |
| |
| // to register interface (read) |
| .qs (le0_le28_qs) |
| ); |
| |
| |
| // F[le29]: 29:29 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le29 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le29_we), |
| .wd (le0_le29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le29.q ), |
| |
| // to register interface (read) |
| .qs (le0_le29_qs) |
| ); |
| |
| |
| // F[le30]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le30 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le30_we), |
| .wd (le0_le30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le30.q ), |
| |
| // to register interface (read) |
| .qs (le0_le30_qs) |
| ); |
| |
| |
| // F[le31]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le0_le31 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le0_le31_we), |
| .wd (le0_le31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le0.le31.q ), |
| |
| // to register interface (read) |
| .qs (le0_le31_qs) |
| ); |
| |
| |
| // R[le1]: V(False) |
| |
| // F[le32]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le32 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le32_we), |
| .wd (le1_le32_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le32.q ), |
| |
| // to register interface (read) |
| .qs (le1_le32_qs) |
| ); |
| |
| |
| // F[le33]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le33 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le33_we), |
| .wd (le1_le33_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le33.q ), |
| |
| // to register interface (read) |
| .qs (le1_le33_qs) |
| ); |
| |
| |
| // F[le34]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le34 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le34_we), |
| .wd (le1_le34_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le34.q ), |
| |
| // to register interface (read) |
| .qs (le1_le34_qs) |
| ); |
| |
| |
| // F[le35]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le35 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le35_we), |
| .wd (le1_le35_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le35.q ), |
| |
| // to register interface (read) |
| .qs (le1_le35_qs) |
| ); |
| |
| |
| // F[le36]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le36 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le36_we), |
| .wd (le1_le36_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le36.q ), |
| |
| // to register interface (read) |
| .qs (le1_le36_qs) |
| ); |
| |
| |
| // F[le37]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le37 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le37_we), |
| .wd (le1_le37_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le37.q ), |
| |
| // to register interface (read) |
| .qs (le1_le37_qs) |
| ); |
| |
| |
| // F[le38]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le38 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le38_we), |
| .wd (le1_le38_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le38.q ), |
| |
| // to register interface (read) |
| .qs (le1_le38_qs) |
| ); |
| |
| |
| // F[le39]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le39 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le39_we), |
| .wd (le1_le39_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le39.q ), |
| |
| // to register interface (read) |
| .qs (le1_le39_qs) |
| ); |
| |
| |
| // F[le40]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le40 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le40_we), |
| .wd (le1_le40_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le40.q ), |
| |
| // to register interface (read) |
| .qs (le1_le40_qs) |
| ); |
| |
| |
| // F[le41]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le41 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le41_we), |
| .wd (le1_le41_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le41.q ), |
| |
| // to register interface (read) |
| .qs (le1_le41_qs) |
| ); |
| |
| |
| // F[le42]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le42 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le42_we), |
| .wd (le1_le42_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le42.q ), |
| |
| // to register interface (read) |
| .qs (le1_le42_qs) |
| ); |
| |
| |
| // F[le43]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le43 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le43_we), |
| .wd (le1_le43_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le43.q ), |
| |
| // to register interface (read) |
| .qs (le1_le43_qs) |
| ); |
| |
| |
| // F[le44]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le44 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le44_we), |
| .wd (le1_le44_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le44.q ), |
| |
| // to register interface (read) |
| .qs (le1_le44_qs) |
| ); |
| |
| |
| // F[le45]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le45 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le45_we), |
| .wd (le1_le45_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le45.q ), |
| |
| // to register interface (read) |
| .qs (le1_le45_qs) |
| ); |
| |
| |
| // F[le46]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le46 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le46_we), |
| .wd (le1_le46_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le46.q ), |
| |
| // to register interface (read) |
| .qs (le1_le46_qs) |
| ); |
| |
| |
| // F[le47]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le47 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le47_we), |
| .wd (le1_le47_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le47.q ), |
| |
| // to register interface (read) |
| .qs (le1_le47_qs) |
| ); |
| |
| |
| // F[le48]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le48 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le48_we), |
| .wd (le1_le48_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le48.q ), |
| |
| // to register interface (read) |
| .qs (le1_le48_qs) |
| ); |
| |
| |
| // F[le49]: 17:17 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le49 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le49_we), |
| .wd (le1_le49_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le49.q ), |
| |
| // to register interface (read) |
| .qs (le1_le49_qs) |
| ); |
| |
| |
| // F[le50]: 18:18 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le50 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le50_we), |
| .wd (le1_le50_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le50.q ), |
| |
| // to register interface (read) |
| .qs (le1_le50_qs) |
| ); |
| |
| |
| // F[le51]: 19:19 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_le1_le51 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (le1_le51_we), |
| .wd (le1_le51_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.le1.le51.q ), |
| |
| // to register interface (read) |
| .qs (le1_le51_qs) |
| ); |
| |
| |
| // R[prio0]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio0_we), |
| .wd (prio0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio0.q ), |
| |
| // to register interface (read) |
| .qs (prio0_qs) |
| ); |
| |
| |
| // R[prio1]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio1_we), |
| .wd (prio1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio1.q ), |
| |
| // to register interface (read) |
| .qs (prio1_qs) |
| ); |
| |
| |
| // R[prio2]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio2_we), |
| .wd (prio2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio2.q ), |
| |
| // to register interface (read) |
| .qs (prio2_qs) |
| ); |
| |
| |
| // R[prio3]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio3_we), |
| .wd (prio3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio3.q ), |
| |
| // to register interface (read) |
| .qs (prio3_qs) |
| ); |
| |
| |
| // R[prio4]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio4_we), |
| .wd (prio4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio4.q ), |
| |
| // to register interface (read) |
| .qs (prio4_qs) |
| ); |
| |
| |
| // R[prio5]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio5_we), |
| .wd (prio5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio5.q ), |
| |
| // to register interface (read) |
| .qs (prio5_qs) |
| ); |
| |
| |
| // R[prio6]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio6 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio6_we), |
| .wd (prio6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio6.q ), |
| |
| // to register interface (read) |
| .qs (prio6_qs) |
| ); |
| |
| |
| // R[prio7]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio7 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio7_we), |
| .wd (prio7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio7.q ), |
| |
| // to register interface (read) |
| .qs (prio7_qs) |
| ); |
| |
| |
| // R[prio8]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio8 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio8_we), |
| .wd (prio8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio8.q ), |
| |
| // to register interface (read) |
| .qs (prio8_qs) |
| ); |
| |
| |
| // R[prio9]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio9 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio9_we), |
| .wd (prio9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio9.q ), |
| |
| // to register interface (read) |
| .qs (prio9_qs) |
| ); |
| |
| |
| // R[prio10]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio10 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio10_we), |
| .wd (prio10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio10.q ), |
| |
| // to register interface (read) |
| .qs (prio10_qs) |
| ); |
| |
| |
| // R[prio11]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio11 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio11_we), |
| .wd (prio11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio11.q ), |
| |
| // to register interface (read) |
| .qs (prio11_qs) |
| ); |
| |
| |
| // R[prio12]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio12 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio12_we), |
| .wd (prio12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio12.q ), |
| |
| // to register interface (read) |
| .qs (prio12_qs) |
| ); |
| |
| |
| // R[prio13]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio13 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio13_we), |
| .wd (prio13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio13.q ), |
| |
| // to register interface (read) |
| .qs (prio13_qs) |
| ); |
| |
| |
| // R[prio14]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio14 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio14_we), |
| .wd (prio14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio14.q ), |
| |
| // to register interface (read) |
| .qs (prio14_qs) |
| ); |
| |
| |
| // R[prio15]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio15 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio15_we), |
| .wd (prio15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio15.q ), |
| |
| // to register interface (read) |
| .qs (prio15_qs) |
| ); |
| |
| |
| // R[prio16]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio16 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio16_we), |
| .wd (prio16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio16.q ), |
| |
| // to register interface (read) |
| .qs (prio16_qs) |
| ); |
| |
| |
| // R[prio17]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio17 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio17_we), |
| .wd (prio17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio17.q ), |
| |
| // to register interface (read) |
| .qs (prio17_qs) |
| ); |
| |
| |
| // R[prio18]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio18 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio18_we), |
| .wd (prio18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio18.q ), |
| |
| // to register interface (read) |
| .qs (prio18_qs) |
| ); |
| |
| |
| // R[prio19]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio19 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio19_we), |
| .wd (prio19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio19.q ), |
| |
| // to register interface (read) |
| .qs (prio19_qs) |
| ); |
| |
| |
| // R[prio20]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio20 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio20_we), |
| .wd (prio20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio20.q ), |
| |
| // to register interface (read) |
| .qs (prio20_qs) |
| ); |
| |
| |
| // R[prio21]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio21 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio21_we), |
| .wd (prio21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio21.q ), |
| |
| // to register interface (read) |
| .qs (prio21_qs) |
| ); |
| |
| |
| // R[prio22]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio22 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio22_we), |
| .wd (prio22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio22.q ), |
| |
| // to register interface (read) |
| .qs (prio22_qs) |
| ); |
| |
| |
| // R[prio23]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio23 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio23_we), |
| .wd (prio23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio23.q ), |
| |
| // to register interface (read) |
| .qs (prio23_qs) |
| ); |
| |
| |
| // R[prio24]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio24 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio24_we), |
| .wd (prio24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio24.q ), |
| |
| // to register interface (read) |
| .qs (prio24_qs) |
| ); |
| |
| |
| // R[prio25]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio25 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio25_we), |
| .wd (prio25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio25.q ), |
| |
| // to register interface (read) |
| .qs (prio25_qs) |
| ); |
| |
| |
| // R[prio26]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio26 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio26_we), |
| .wd (prio26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio26.q ), |
| |
| // to register interface (read) |
| .qs (prio26_qs) |
| ); |
| |
| |
| // R[prio27]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio27 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio27_we), |
| .wd (prio27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio27.q ), |
| |
| // to register interface (read) |
| .qs (prio27_qs) |
| ); |
| |
| |
| // R[prio28]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio28 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio28_we), |
| .wd (prio28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio28.q ), |
| |
| // to register interface (read) |
| .qs (prio28_qs) |
| ); |
| |
| |
| // R[prio29]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio29 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio29_we), |
| .wd (prio29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio29.q ), |
| |
| // to register interface (read) |
| .qs (prio29_qs) |
| ); |
| |
| |
| // R[prio30]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio30 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio30_we), |
| .wd (prio30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio30.q ), |
| |
| // to register interface (read) |
| .qs (prio30_qs) |
| ); |
| |
| |
| // R[prio31]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio31 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio31_we), |
| .wd (prio31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio31.q ), |
| |
| // to register interface (read) |
| .qs (prio31_qs) |
| ); |
| |
| |
| // R[prio32]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio32 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio32_we), |
| .wd (prio32_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio32.q ), |
| |
| // to register interface (read) |
| .qs (prio32_qs) |
| ); |
| |
| |
| // R[prio33]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio33 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio33_we), |
| .wd (prio33_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio33.q ), |
| |
| // to register interface (read) |
| .qs (prio33_qs) |
| ); |
| |
| |
| // R[prio34]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio34 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio34_we), |
| .wd (prio34_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio34.q ), |
| |
| // to register interface (read) |
| .qs (prio34_qs) |
| ); |
| |
| |
| // R[prio35]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio35 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio35_we), |
| .wd (prio35_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio35.q ), |
| |
| // to register interface (read) |
| .qs (prio35_qs) |
| ); |
| |
| |
| // R[prio36]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio36 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio36_we), |
| .wd (prio36_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio36.q ), |
| |
| // to register interface (read) |
| .qs (prio36_qs) |
| ); |
| |
| |
| // R[prio37]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio37 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio37_we), |
| .wd (prio37_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio37.q ), |
| |
| // to register interface (read) |
| .qs (prio37_qs) |
| ); |
| |
| |
| // R[prio38]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio38 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio38_we), |
| .wd (prio38_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio38.q ), |
| |
| // to register interface (read) |
| .qs (prio38_qs) |
| ); |
| |
| |
| // R[prio39]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio39 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio39_we), |
| .wd (prio39_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio39.q ), |
| |
| // to register interface (read) |
| .qs (prio39_qs) |
| ); |
| |
| |
| // R[prio40]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio40 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio40_we), |
| .wd (prio40_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio40.q ), |
| |
| // to register interface (read) |
| .qs (prio40_qs) |
| ); |
| |
| |
| // R[prio41]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio41 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio41_we), |
| .wd (prio41_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio41.q ), |
| |
| // to register interface (read) |
| .qs (prio41_qs) |
| ); |
| |
| |
| // R[prio42]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio42 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio42_we), |
| .wd (prio42_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio42.q ), |
| |
| // to register interface (read) |
| .qs (prio42_qs) |
| ); |
| |
| |
| // R[prio43]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio43 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio43_we), |
| .wd (prio43_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio43.q ), |
| |
| // to register interface (read) |
| .qs (prio43_qs) |
| ); |
| |
| |
| // R[prio44]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio44 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio44_we), |
| .wd (prio44_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio44.q ), |
| |
| // to register interface (read) |
| .qs (prio44_qs) |
| ); |
| |
| |
| // R[prio45]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio45 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio45_we), |
| .wd (prio45_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio45.q ), |
| |
| // to register interface (read) |
| .qs (prio45_qs) |
| ); |
| |
| |
| // R[prio46]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio46 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio46_we), |
| .wd (prio46_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio46.q ), |
| |
| // to register interface (read) |
| .qs (prio46_qs) |
| ); |
| |
| |
| // R[prio47]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio47 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio47_we), |
| .wd (prio47_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio47.q ), |
| |
| // to register interface (read) |
| .qs (prio47_qs) |
| ); |
| |
| |
| // R[prio48]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio48 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio48_we), |
| .wd (prio48_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio48.q ), |
| |
| // to register interface (read) |
| .qs (prio48_qs) |
| ); |
| |
| |
| // R[prio49]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio49 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio49_we), |
| .wd (prio49_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio49.q ), |
| |
| // to register interface (read) |
| .qs (prio49_qs) |
| ); |
| |
| |
| // R[prio50]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio50 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio50_we), |
| .wd (prio50_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio50.q ), |
| |
| // to register interface (read) |
| .qs (prio50_qs) |
| ); |
| |
| |
| // R[prio51]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_prio51 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (prio51_we), |
| .wd (prio51_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.prio51.q ), |
| |
| // to register interface (read) |
| .qs (prio51_qs) |
| ); |
| |
| |
| // R[ie00]: V(False) |
| |
| // F[e0]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e0_we), |
| .wd (ie00_e0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e0.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e0_qs) |
| ); |
| |
| |
| // F[e1]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e1 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e1_we), |
| .wd (ie00_e1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e1.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e1_qs) |
| ); |
| |
| |
| // F[e2]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e2 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e2_we), |
| .wd (ie00_e2_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e2.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e2_qs) |
| ); |
| |
| |
| // F[e3]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e3 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e3_we), |
| .wd (ie00_e3_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e3.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e3_qs) |
| ); |
| |
| |
| // F[e4]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e4 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e4_we), |
| .wd (ie00_e4_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e4.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e4_qs) |
| ); |
| |
| |
| // F[e5]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e5 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e5_we), |
| .wd (ie00_e5_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e5.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e5_qs) |
| ); |
| |
| |
| // F[e6]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e6 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e6_we), |
| .wd (ie00_e6_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e6.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e6_qs) |
| ); |
| |
| |
| // F[e7]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e7 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e7_we), |
| .wd (ie00_e7_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e7.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e7_qs) |
| ); |
| |
| |
| // F[e8]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e8 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e8_we), |
| .wd (ie00_e8_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e8.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e8_qs) |
| ); |
| |
| |
| // F[e9]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e9 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e9_we), |
| .wd (ie00_e9_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e9.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e9_qs) |
| ); |
| |
| |
| // F[e10]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e10 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e10_we), |
| .wd (ie00_e10_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e10.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e10_qs) |
| ); |
| |
| |
| // F[e11]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e11 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e11_we), |
| .wd (ie00_e11_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e11.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e11_qs) |
| ); |
| |
| |
| // F[e12]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e12 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e12_we), |
| .wd (ie00_e12_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e12.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e12_qs) |
| ); |
| |
| |
| // F[e13]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e13 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e13_we), |
| .wd (ie00_e13_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e13.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e13_qs) |
| ); |
| |
| |
| // F[e14]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e14 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e14_we), |
| .wd (ie00_e14_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e14.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e14_qs) |
| ); |
| |
| |
| // F[e15]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e15 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e15_we), |
| .wd (ie00_e15_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e15.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e15_qs) |
| ); |
| |
| |
| // F[e16]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e16 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e16_we), |
| .wd (ie00_e16_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e16.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e16_qs) |
| ); |
| |
| |
| // F[e17]: 17:17 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e17 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e17_we), |
| .wd (ie00_e17_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e17.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e17_qs) |
| ); |
| |
| |
| // F[e18]: 18:18 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e18 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e18_we), |
| .wd (ie00_e18_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e18.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e18_qs) |
| ); |
| |
| |
| // F[e19]: 19:19 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e19 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e19_we), |
| .wd (ie00_e19_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e19.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e19_qs) |
| ); |
| |
| |
| // F[e20]: 20:20 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e20 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e20_we), |
| .wd (ie00_e20_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e20.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e20_qs) |
| ); |
| |
| |
| // F[e21]: 21:21 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e21 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e21_we), |
| .wd (ie00_e21_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e21.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e21_qs) |
| ); |
| |
| |
| // F[e22]: 22:22 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e22 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e22_we), |
| .wd (ie00_e22_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e22.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e22_qs) |
| ); |
| |
| |
| // F[e23]: 23:23 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e23 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e23_we), |
| .wd (ie00_e23_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e23.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e23_qs) |
| ); |
| |
| |
| // F[e24]: 24:24 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e24 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e24_we), |
| .wd (ie00_e24_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e24.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e24_qs) |
| ); |
| |
| |
| // F[e25]: 25:25 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e25 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e25_we), |
| .wd (ie00_e25_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e25.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e25_qs) |
| ); |
| |
| |
| // F[e26]: 26:26 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e26 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e26_we), |
| .wd (ie00_e26_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e26.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e26_qs) |
| ); |
| |
| |
| // F[e27]: 27:27 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e27 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e27_we), |
| .wd (ie00_e27_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e27.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e27_qs) |
| ); |
| |
| |
| // F[e28]: 28:28 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e28 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e28_we), |
| .wd (ie00_e28_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e28.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e28_qs) |
| ); |
| |
| |
| // F[e29]: 29:29 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e29 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e29_we), |
| .wd (ie00_e29_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e29.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e29_qs) |
| ); |
| |
| |
| // F[e30]: 30:30 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e30 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e30_we), |
| .wd (ie00_e30_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e30.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e30_qs) |
| ); |
| |
| |
| // F[e31]: 31:31 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie00_e31 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie00_e31_we), |
| .wd (ie00_e31_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie00.e31.q ), |
| |
| // to register interface (read) |
| .qs (ie00_e31_qs) |
| ); |
| |
| |
| // R[ie01]: V(False) |
| |
| // F[e32]: 0:0 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e32 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e32_we), |
| .wd (ie01_e32_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e32.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e32_qs) |
| ); |
| |
| |
| // F[e33]: 1:1 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e33 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e33_we), |
| .wd (ie01_e33_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e33.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e33_qs) |
| ); |
| |
| |
| // F[e34]: 2:2 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e34 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e34_we), |
| .wd (ie01_e34_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e34.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e34_qs) |
| ); |
| |
| |
| // F[e35]: 3:3 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e35 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e35_we), |
| .wd (ie01_e35_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e35.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e35_qs) |
| ); |
| |
| |
| // F[e36]: 4:4 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e36 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e36_we), |
| .wd (ie01_e36_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e36.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e36_qs) |
| ); |
| |
| |
| // F[e37]: 5:5 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e37 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e37_we), |
| .wd (ie01_e37_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e37.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e37_qs) |
| ); |
| |
| |
| // F[e38]: 6:6 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e38 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e38_we), |
| .wd (ie01_e38_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e38.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e38_qs) |
| ); |
| |
| |
| // F[e39]: 7:7 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e39 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e39_we), |
| .wd (ie01_e39_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e39.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e39_qs) |
| ); |
| |
| |
| // F[e40]: 8:8 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e40 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e40_we), |
| .wd (ie01_e40_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e40.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e40_qs) |
| ); |
| |
| |
| // F[e41]: 9:9 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e41 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e41_we), |
| .wd (ie01_e41_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e41.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e41_qs) |
| ); |
| |
| |
| // F[e42]: 10:10 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e42 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e42_we), |
| .wd (ie01_e42_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e42.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e42_qs) |
| ); |
| |
| |
| // F[e43]: 11:11 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e43 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e43_we), |
| .wd (ie01_e43_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e43.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e43_qs) |
| ); |
| |
| |
| // F[e44]: 12:12 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e44 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e44_we), |
| .wd (ie01_e44_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e44.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e44_qs) |
| ); |
| |
| |
| // F[e45]: 13:13 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e45 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e45_we), |
| .wd (ie01_e45_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e45.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e45_qs) |
| ); |
| |
| |
| // F[e46]: 14:14 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e46 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e46_we), |
| .wd (ie01_e46_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e46.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e46_qs) |
| ); |
| |
| |
| // F[e47]: 15:15 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e47 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e47_we), |
| .wd (ie01_e47_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e47.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e47_qs) |
| ); |
| |
| |
| // F[e48]: 16:16 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e48 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e48_we), |
| .wd (ie01_e48_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e48.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e48_qs) |
| ); |
| |
| |
| // F[e49]: 17:17 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e49 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e49_we), |
| .wd (ie01_e49_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e49.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e49_qs) |
| ); |
| |
| |
| // F[e50]: 18:18 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e50 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e50_we), |
| .wd (ie01_e50_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e50.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e50_qs) |
| ); |
| |
| |
| // F[e51]: 19:19 |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_ie01_e51 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (ie01_e51_we), |
| .wd (ie01_e51_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.ie01.e51.q ), |
| |
| // to register interface (read) |
| .qs (ie01_e51_qs) |
| ); |
| |
| |
| // R[threshold0]: V(False) |
| |
| prim_subreg #( |
| .DW (2), |
| .SWACCESS("RW"), |
| .RESVAL (2'h0) |
| ) u_threshold0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (threshold0_we), |
| .wd (threshold0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.threshold0.q ), |
| |
| // to register interface (read) |
| .qs (threshold0_qs) |
| ); |
| |
| |
| // R[cc0]: V(True) |
| |
| prim_subreg_ext #( |
| .DW (6) |
| ) u_cc0 ( |
| .re (cc0_re), |
| .we (cc0_we), |
| .wd (cc0_wd), |
| .d (hw2reg.cc0.d), |
| .qre (reg2hw.cc0.re), |
| .qe (reg2hw.cc0.qe), |
| .q (reg2hw.cc0.q ), |
| .qs (cc0_qs) |
| ); |
| |
| |
| // R[msip0]: V(False) |
| |
| prim_subreg #( |
| .DW (1), |
| .SWACCESS("RW"), |
| .RESVAL (1'h0) |
| ) u_msip0 ( |
| .clk_i (clk_i ), |
| .rst_ni (rst_ni ), |
| |
| // from register interface |
| .we (msip0_we), |
| .wd (msip0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0 ), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.msip0.q ), |
| |
| // to register interface (read) |
| .qs (msip0_qs) |
| ); |
| |
| |
| |
| logic [60:0] addr_hit; |
| always_comb begin |
| addr_hit = '0; |
| addr_hit[0] = (reg_addr == RV_PLIC_IP0_OFFSET); |
| addr_hit[1] = (reg_addr == RV_PLIC_IP1_OFFSET); |
| addr_hit[2] = (reg_addr == RV_PLIC_LE0_OFFSET); |
| addr_hit[3] = (reg_addr == RV_PLIC_LE1_OFFSET); |
| addr_hit[4] = (reg_addr == RV_PLIC_PRIO0_OFFSET); |
| addr_hit[5] = (reg_addr == RV_PLIC_PRIO1_OFFSET); |
| addr_hit[6] = (reg_addr == RV_PLIC_PRIO2_OFFSET); |
| addr_hit[7] = (reg_addr == RV_PLIC_PRIO3_OFFSET); |
| addr_hit[8] = (reg_addr == RV_PLIC_PRIO4_OFFSET); |
| addr_hit[9] = (reg_addr == RV_PLIC_PRIO5_OFFSET); |
| addr_hit[10] = (reg_addr == RV_PLIC_PRIO6_OFFSET); |
| addr_hit[11] = (reg_addr == RV_PLIC_PRIO7_OFFSET); |
| addr_hit[12] = (reg_addr == RV_PLIC_PRIO8_OFFSET); |
| addr_hit[13] = (reg_addr == RV_PLIC_PRIO9_OFFSET); |
| addr_hit[14] = (reg_addr == RV_PLIC_PRIO10_OFFSET); |
| addr_hit[15] = (reg_addr == RV_PLIC_PRIO11_OFFSET); |
| addr_hit[16] = (reg_addr == RV_PLIC_PRIO12_OFFSET); |
| addr_hit[17] = (reg_addr == RV_PLIC_PRIO13_OFFSET); |
| addr_hit[18] = (reg_addr == RV_PLIC_PRIO14_OFFSET); |
| addr_hit[19] = (reg_addr == RV_PLIC_PRIO15_OFFSET); |
| addr_hit[20] = (reg_addr == RV_PLIC_PRIO16_OFFSET); |
| addr_hit[21] = (reg_addr == RV_PLIC_PRIO17_OFFSET); |
| addr_hit[22] = (reg_addr == RV_PLIC_PRIO18_OFFSET); |
| addr_hit[23] = (reg_addr == RV_PLIC_PRIO19_OFFSET); |
| addr_hit[24] = (reg_addr == RV_PLIC_PRIO20_OFFSET); |
| addr_hit[25] = (reg_addr == RV_PLIC_PRIO21_OFFSET); |
| addr_hit[26] = (reg_addr == RV_PLIC_PRIO22_OFFSET); |
| addr_hit[27] = (reg_addr == RV_PLIC_PRIO23_OFFSET); |
| addr_hit[28] = (reg_addr == RV_PLIC_PRIO24_OFFSET); |
| addr_hit[29] = (reg_addr == RV_PLIC_PRIO25_OFFSET); |
| addr_hit[30] = (reg_addr == RV_PLIC_PRIO26_OFFSET); |
| addr_hit[31] = (reg_addr == RV_PLIC_PRIO27_OFFSET); |
| addr_hit[32] = (reg_addr == RV_PLIC_PRIO28_OFFSET); |
| addr_hit[33] = (reg_addr == RV_PLIC_PRIO29_OFFSET); |
| addr_hit[34] = (reg_addr == RV_PLIC_PRIO30_OFFSET); |
| addr_hit[35] = (reg_addr == RV_PLIC_PRIO31_OFFSET); |
| addr_hit[36] = (reg_addr == RV_PLIC_PRIO32_OFFSET); |
| addr_hit[37] = (reg_addr == RV_PLIC_PRIO33_OFFSET); |
| addr_hit[38] = (reg_addr == RV_PLIC_PRIO34_OFFSET); |
| addr_hit[39] = (reg_addr == RV_PLIC_PRIO35_OFFSET); |
| addr_hit[40] = (reg_addr == RV_PLIC_PRIO36_OFFSET); |
| addr_hit[41] = (reg_addr == RV_PLIC_PRIO37_OFFSET); |
| addr_hit[42] = (reg_addr == RV_PLIC_PRIO38_OFFSET); |
| addr_hit[43] = (reg_addr == RV_PLIC_PRIO39_OFFSET); |
| addr_hit[44] = (reg_addr == RV_PLIC_PRIO40_OFFSET); |
| addr_hit[45] = (reg_addr == RV_PLIC_PRIO41_OFFSET); |
| addr_hit[46] = (reg_addr == RV_PLIC_PRIO42_OFFSET); |
| addr_hit[47] = (reg_addr == RV_PLIC_PRIO43_OFFSET); |
| addr_hit[48] = (reg_addr == RV_PLIC_PRIO44_OFFSET); |
| addr_hit[49] = (reg_addr == RV_PLIC_PRIO45_OFFSET); |
| addr_hit[50] = (reg_addr == RV_PLIC_PRIO46_OFFSET); |
| addr_hit[51] = (reg_addr == RV_PLIC_PRIO47_OFFSET); |
| addr_hit[52] = (reg_addr == RV_PLIC_PRIO48_OFFSET); |
| addr_hit[53] = (reg_addr == RV_PLIC_PRIO49_OFFSET); |
| addr_hit[54] = (reg_addr == RV_PLIC_PRIO50_OFFSET); |
| addr_hit[55] = (reg_addr == RV_PLIC_PRIO51_OFFSET); |
| addr_hit[56] = (reg_addr == RV_PLIC_IE00_OFFSET); |
| addr_hit[57] = (reg_addr == RV_PLIC_IE01_OFFSET); |
| addr_hit[58] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); |
| addr_hit[59] = (reg_addr == RV_PLIC_CC0_OFFSET); |
| addr_hit[60] = (reg_addr == RV_PLIC_MSIP0_OFFSET); |
| end |
| |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| if (!rst_ni) begin |
| addrmiss <= 1'b0; |
| end else if (reg_re || reg_we) begin |
| addrmiss <= ~|addr_hit; |
| end |
| end |
| |
| // Write Enable signal |
| |
| |
| |
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| |
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| |
| |
| |
| |
| assign le0_le0_we = addr_hit[2] && reg_we; |
| assign le0_le0_wd = reg_wdata[0]; |
| |
| assign le0_le1_we = addr_hit[2] && reg_we; |
| assign le0_le1_wd = reg_wdata[1]; |
| |
| assign le0_le2_we = addr_hit[2] && reg_we; |
| assign le0_le2_wd = reg_wdata[2]; |
| |
| assign le0_le3_we = addr_hit[2] && reg_we; |
| assign le0_le3_wd = reg_wdata[3]; |
| |
| assign le0_le4_we = addr_hit[2] && reg_we; |
| assign le0_le4_wd = reg_wdata[4]; |
| |
| assign le0_le5_we = addr_hit[2] && reg_we; |
| assign le0_le5_wd = reg_wdata[5]; |
| |
| assign le0_le6_we = addr_hit[2] && reg_we; |
| assign le0_le6_wd = reg_wdata[6]; |
| |
| assign le0_le7_we = addr_hit[2] && reg_we; |
| assign le0_le7_wd = reg_wdata[7]; |
| |
| assign le0_le8_we = addr_hit[2] && reg_we; |
| assign le0_le8_wd = reg_wdata[8]; |
| |
| assign le0_le9_we = addr_hit[2] && reg_we; |
| assign le0_le9_wd = reg_wdata[9]; |
| |
| assign le0_le10_we = addr_hit[2] && reg_we; |
| assign le0_le10_wd = reg_wdata[10]; |
| |
| assign le0_le11_we = addr_hit[2] && reg_we; |
| assign le0_le11_wd = reg_wdata[11]; |
| |
| assign le0_le12_we = addr_hit[2] && reg_we; |
| assign le0_le12_wd = reg_wdata[12]; |
| |
| assign le0_le13_we = addr_hit[2] && reg_we; |
| assign le0_le13_wd = reg_wdata[13]; |
| |
| assign le0_le14_we = addr_hit[2] && reg_we; |
| assign le0_le14_wd = reg_wdata[14]; |
| |
| assign le0_le15_we = addr_hit[2] && reg_we; |
| assign le0_le15_wd = reg_wdata[15]; |
| |
| assign le0_le16_we = addr_hit[2] && reg_we; |
| assign le0_le16_wd = reg_wdata[16]; |
| |
| assign le0_le17_we = addr_hit[2] && reg_we; |
| assign le0_le17_wd = reg_wdata[17]; |
| |
| assign le0_le18_we = addr_hit[2] && reg_we; |
| assign le0_le18_wd = reg_wdata[18]; |
| |
| assign le0_le19_we = addr_hit[2] && reg_we; |
| assign le0_le19_wd = reg_wdata[19]; |
| |
| assign le0_le20_we = addr_hit[2] && reg_we; |
| assign le0_le20_wd = reg_wdata[20]; |
| |
| assign le0_le21_we = addr_hit[2] && reg_we; |
| assign le0_le21_wd = reg_wdata[21]; |
| |
| assign le0_le22_we = addr_hit[2] && reg_we; |
| assign le0_le22_wd = reg_wdata[22]; |
| |
| assign le0_le23_we = addr_hit[2] && reg_we; |
| assign le0_le23_wd = reg_wdata[23]; |
| |
| assign le0_le24_we = addr_hit[2] && reg_we; |
| assign le0_le24_wd = reg_wdata[24]; |
| |
| assign le0_le25_we = addr_hit[2] && reg_we; |
| assign le0_le25_wd = reg_wdata[25]; |
| |
| assign le0_le26_we = addr_hit[2] && reg_we; |
| assign le0_le26_wd = reg_wdata[26]; |
| |
| assign le0_le27_we = addr_hit[2] && reg_we; |
| assign le0_le27_wd = reg_wdata[27]; |
| |
| assign le0_le28_we = addr_hit[2] && reg_we; |
| assign le0_le28_wd = reg_wdata[28]; |
| |
| assign le0_le29_we = addr_hit[2] && reg_we; |
| assign le0_le29_wd = reg_wdata[29]; |
| |
| assign le0_le30_we = addr_hit[2] && reg_we; |
| assign le0_le30_wd = reg_wdata[30]; |
| |
| assign le0_le31_we = addr_hit[2] && reg_we; |
| assign le0_le31_wd = reg_wdata[31]; |
| |
| assign le1_le32_we = addr_hit[3] && reg_we; |
| assign le1_le32_wd = reg_wdata[0]; |
| |
| assign le1_le33_we = addr_hit[3] && reg_we; |
| assign le1_le33_wd = reg_wdata[1]; |
| |
| assign le1_le34_we = addr_hit[3] && reg_we; |
| assign le1_le34_wd = reg_wdata[2]; |
| |
| assign le1_le35_we = addr_hit[3] && reg_we; |
| assign le1_le35_wd = reg_wdata[3]; |
| |
| assign le1_le36_we = addr_hit[3] && reg_we; |
| assign le1_le36_wd = reg_wdata[4]; |
| |
| assign le1_le37_we = addr_hit[3] && reg_we; |
| assign le1_le37_wd = reg_wdata[5]; |
| |
| assign le1_le38_we = addr_hit[3] && reg_we; |
| assign le1_le38_wd = reg_wdata[6]; |
| |
| assign le1_le39_we = addr_hit[3] && reg_we; |
| assign le1_le39_wd = reg_wdata[7]; |
| |
| assign le1_le40_we = addr_hit[3] && reg_we; |
| assign le1_le40_wd = reg_wdata[8]; |
| |
| assign le1_le41_we = addr_hit[3] && reg_we; |
| assign le1_le41_wd = reg_wdata[9]; |
| |
| assign le1_le42_we = addr_hit[3] && reg_we; |
| assign le1_le42_wd = reg_wdata[10]; |
| |
| assign le1_le43_we = addr_hit[3] && reg_we; |
| assign le1_le43_wd = reg_wdata[11]; |
| |
| assign le1_le44_we = addr_hit[3] && reg_we; |
| assign le1_le44_wd = reg_wdata[12]; |
| |
| assign le1_le45_we = addr_hit[3] && reg_we; |
| assign le1_le45_wd = reg_wdata[13]; |
| |
| assign le1_le46_we = addr_hit[3] && reg_we; |
| assign le1_le46_wd = reg_wdata[14]; |
| |
| assign le1_le47_we = addr_hit[3] && reg_we; |
| assign le1_le47_wd = reg_wdata[15]; |
| |
| assign le1_le48_we = addr_hit[3] && reg_we; |
| assign le1_le48_wd = reg_wdata[16]; |
| |
| assign le1_le49_we = addr_hit[3] && reg_we; |
| assign le1_le49_wd = reg_wdata[17]; |
| |
| assign le1_le50_we = addr_hit[3] && reg_we; |
| assign le1_le50_wd = reg_wdata[18]; |
| |
| assign le1_le51_we = addr_hit[3] && reg_we; |
| assign le1_le51_wd = reg_wdata[19]; |
| |
| assign prio0_we = addr_hit[4] && reg_we; |
| assign prio0_wd = reg_wdata[1:0]; |
| |
| assign prio1_we = addr_hit[5] && reg_we; |
| assign prio1_wd = reg_wdata[1:0]; |
| |
| assign prio2_we = addr_hit[6] && reg_we; |
| assign prio2_wd = reg_wdata[1:0]; |
| |
| assign prio3_we = addr_hit[7] && reg_we; |
| assign prio3_wd = reg_wdata[1:0]; |
| |
| assign prio4_we = addr_hit[8] && reg_we; |
| assign prio4_wd = reg_wdata[1:0]; |
| |
| assign prio5_we = addr_hit[9] && reg_we; |
| assign prio5_wd = reg_wdata[1:0]; |
| |
| assign prio6_we = addr_hit[10] && reg_we; |
| assign prio6_wd = reg_wdata[1:0]; |
| |
| assign prio7_we = addr_hit[11] && reg_we; |
| assign prio7_wd = reg_wdata[1:0]; |
| |
| assign prio8_we = addr_hit[12] && reg_we; |
| assign prio8_wd = reg_wdata[1:0]; |
| |
| assign prio9_we = addr_hit[13] && reg_we; |
| assign prio9_wd = reg_wdata[1:0]; |
| |
| assign prio10_we = addr_hit[14] && reg_we; |
| assign prio10_wd = reg_wdata[1:0]; |
| |
| assign prio11_we = addr_hit[15] && reg_we; |
| assign prio11_wd = reg_wdata[1:0]; |
| |
| assign prio12_we = addr_hit[16] && reg_we; |
| assign prio12_wd = reg_wdata[1:0]; |
| |
| assign prio13_we = addr_hit[17] && reg_we; |
| assign prio13_wd = reg_wdata[1:0]; |
| |
| assign prio14_we = addr_hit[18] && reg_we; |
| assign prio14_wd = reg_wdata[1:0]; |
| |
| assign prio15_we = addr_hit[19] && reg_we; |
| assign prio15_wd = reg_wdata[1:0]; |
| |
| assign prio16_we = addr_hit[20] && reg_we; |
| assign prio16_wd = reg_wdata[1:0]; |
| |
| assign prio17_we = addr_hit[21] && reg_we; |
| assign prio17_wd = reg_wdata[1:0]; |
| |
| assign prio18_we = addr_hit[22] && reg_we; |
| assign prio18_wd = reg_wdata[1:0]; |
| |
| assign prio19_we = addr_hit[23] && reg_we; |
| assign prio19_wd = reg_wdata[1:0]; |
| |
| assign prio20_we = addr_hit[24] && reg_we; |
| assign prio20_wd = reg_wdata[1:0]; |
| |
| assign prio21_we = addr_hit[25] && reg_we; |
| assign prio21_wd = reg_wdata[1:0]; |
| |
| assign prio22_we = addr_hit[26] && reg_we; |
| assign prio22_wd = reg_wdata[1:0]; |
| |
| assign prio23_we = addr_hit[27] && reg_we; |
| assign prio23_wd = reg_wdata[1:0]; |
| |
| assign prio24_we = addr_hit[28] && reg_we; |
| assign prio24_wd = reg_wdata[1:0]; |
| |
| assign prio25_we = addr_hit[29] && reg_we; |
| assign prio25_wd = reg_wdata[1:0]; |
| |
| assign prio26_we = addr_hit[30] && reg_we; |
| assign prio26_wd = reg_wdata[1:0]; |
| |
| assign prio27_we = addr_hit[31] && reg_we; |
| assign prio27_wd = reg_wdata[1:0]; |
| |
| assign prio28_we = addr_hit[32] && reg_we; |
| assign prio28_wd = reg_wdata[1:0]; |
| |
| assign prio29_we = addr_hit[33] && reg_we; |
| assign prio29_wd = reg_wdata[1:0]; |
| |
| assign prio30_we = addr_hit[34] && reg_we; |
| assign prio30_wd = reg_wdata[1:0]; |
| |
| assign prio31_we = addr_hit[35] && reg_we; |
| assign prio31_wd = reg_wdata[1:0]; |
| |
| assign prio32_we = addr_hit[36] && reg_we; |
| assign prio32_wd = reg_wdata[1:0]; |
| |
| assign prio33_we = addr_hit[37] && reg_we; |
| assign prio33_wd = reg_wdata[1:0]; |
| |
| assign prio34_we = addr_hit[38] && reg_we; |
| assign prio34_wd = reg_wdata[1:0]; |
| |
| assign prio35_we = addr_hit[39] && reg_we; |
| assign prio35_wd = reg_wdata[1:0]; |
| |
| assign prio36_we = addr_hit[40] && reg_we; |
| assign prio36_wd = reg_wdata[1:0]; |
| |
| assign prio37_we = addr_hit[41] && reg_we; |
| assign prio37_wd = reg_wdata[1:0]; |
| |
| assign prio38_we = addr_hit[42] && reg_we; |
| assign prio38_wd = reg_wdata[1:0]; |
| |
| assign prio39_we = addr_hit[43] && reg_we; |
| assign prio39_wd = reg_wdata[1:0]; |
| |
| assign prio40_we = addr_hit[44] && reg_we; |
| assign prio40_wd = reg_wdata[1:0]; |
| |
| assign prio41_we = addr_hit[45] && reg_we; |
| assign prio41_wd = reg_wdata[1:0]; |
| |
| assign prio42_we = addr_hit[46] && reg_we; |
| assign prio42_wd = reg_wdata[1:0]; |
| |
| assign prio43_we = addr_hit[47] && reg_we; |
| assign prio43_wd = reg_wdata[1:0]; |
| |
| assign prio44_we = addr_hit[48] && reg_we; |
| assign prio44_wd = reg_wdata[1:0]; |
| |
| assign prio45_we = addr_hit[49] && reg_we; |
| assign prio45_wd = reg_wdata[1:0]; |
| |
| assign prio46_we = addr_hit[50] && reg_we; |
| assign prio46_wd = reg_wdata[1:0]; |
| |
| assign prio47_we = addr_hit[51] && reg_we; |
| assign prio47_wd = reg_wdata[1:0]; |
| |
| assign prio48_we = addr_hit[52] && reg_we; |
| assign prio48_wd = reg_wdata[1:0]; |
| |
| assign prio49_we = addr_hit[53] && reg_we; |
| assign prio49_wd = reg_wdata[1:0]; |
| |
| assign prio50_we = addr_hit[54] && reg_we; |
| assign prio50_wd = reg_wdata[1:0]; |
| |
| assign prio51_we = addr_hit[55] && reg_we; |
| assign prio51_wd = reg_wdata[1:0]; |
| |
| assign ie00_e0_we = addr_hit[56] && reg_we; |
| assign ie00_e0_wd = reg_wdata[0]; |
| |
| assign ie00_e1_we = addr_hit[56] && reg_we; |
| assign ie00_e1_wd = reg_wdata[1]; |
| |
| assign ie00_e2_we = addr_hit[56] && reg_we; |
| assign ie00_e2_wd = reg_wdata[2]; |
| |
| assign ie00_e3_we = addr_hit[56] && reg_we; |
| assign ie00_e3_wd = reg_wdata[3]; |
| |
| assign ie00_e4_we = addr_hit[56] && reg_we; |
| assign ie00_e4_wd = reg_wdata[4]; |
| |
| assign ie00_e5_we = addr_hit[56] && reg_we; |
| assign ie00_e5_wd = reg_wdata[5]; |
| |
| assign ie00_e6_we = addr_hit[56] && reg_we; |
| assign ie00_e6_wd = reg_wdata[6]; |
| |
| assign ie00_e7_we = addr_hit[56] && reg_we; |
| assign ie00_e7_wd = reg_wdata[7]; |
| |
| assign ie00_e8_we = addr_hit[56] && reg_we; |
| assign ie00_e8_wd = reg_wdata[8]; |
| |
| assign ie00_e9_we = addr_hit[56] && reg_we; |
| assign ie00_e9_wd = reg_wdata[9]; |
| |
| assign ie00_e10_we = addr_hit[56] && reg_we; |
| assign ie00_e10_wd = reg_wdata[10]; |
| |
| assign ie00_e11_we = addr_hit[56] && reg_we; |
| assign ie00_e11_wd = reg_wdata[11]; |
| |
| assign ie00_e12_we = addr_hit[56] && reg_we; |
| assign ie00_e12_wd = reg_wdata[12]; |
| |
| assign ie00_e13_we = addr_hit[56] && reg_we; |
| assign ie00_e13_wd = reg_wdata[13]; |
| |
| assign ie00_e14_we = addr_hit[56] && reg_we; |
| assign ie00_e14_wd = reg_wdata[14]; |
| |
| assign ie00_e15_we = addr_hit[56] && reg_we; |
| assign ie00_e15_wd = reg_wdata[15]; |
| |
| assign ie00_e16_we = addr_hit[56] && reg_we; |
| assign ie00_e16_wd = reg_wdata[16]; |
| |
| assign ie00_e17_we = addr_hit[56] && reg_we; |
| assign ie00_e17_wd = reg_wdata[17]; |
| |
| assign ie00_e18_we = addr_hit[56] && reg_we; |
| assign ie00_e18_wd = reg_wdata[18]; |
| |
| assign ie00_e19_we = addr_hit[56] && reg_we; |
| assign ie00_e19_wd = reg_wdata[19]; |
| |
| assign ie00_e20_we = addr_hit[56] && reg_we; |
| assign ie00_e20_wd = reg_wdata[20]; |
| |
| assign ie00_e21_we = addr_hit[56] && reg_we; |
| assign ie00_e21_wd = reg_wdata[21]; |
| |
| assign ie00_e22_we = addr_hit[56] && reg_we; |
| assign ie00_e22_wd = reg_wdata[22]; |
| |
| assign ie00_e23_we = addr_hit[56] && reg_we; |
| assign ie00_e23_wd = reg_wdata[23]; |
| |
| assign ie00_e24_we = addr_hit[56] && reg_we; |
| assign ie00_e24_wd = reg_wdata[24]; |
| |
| assign ie00_e25_we = addr_hit[56] && reg_we; |
| assign ie00_e25_wd = reg_wdata[25]; |
| |
| assign ie00_e26_we = addr_hit[56] && reg_we; |
| assign ie00_e26_wd = reg_wdata[26]; |
| |
| assign ie00_e27_we = addr_hit[56] && reg_we; |
| assign ie00_e27_wd = reg_wdata[27]; |
| |
| assign ie00_e28_we = addr_hit[56] && reg_we; |
| assign ie00_e28_wd = reg_wdata[28]; |
| |
| assign ie00_e29_we = addr_hit[56] && reg_we; |
| assign ie00_e29_wd = reg_wdata[29]; |
| |
| assign ie00_e30_we = addr_hit[56] && reg_we; |
| assign ie00_e30_wd = reg_wdata[30]; |
| |
| assign ie00_e31_we = addr_hit[56] && reg_we; |
| assign ie00_e31_wd = reg_wdata[31]; |
| |
| assign ie01_e32_we = addr_hit[57] && reg_we; |
| assign ie01_e32_wd = reg_wdata[0]; |
| |
| assign ie01_e33_we = addr_hit[57] && reg_we; |
| assign ie01_e33_wd = reg_wdata[1]; |
| |
| assign ie01_e34_we = addr_hit[57] && reg_we; |
| assign ie01_e34_wd = reg_wdata[2]; |
| |
| assign ie01_e35_we = addr_hit[57] && reg_we; |
| assign ie01_e35_wd = reg_wdata[3]; |
| |
| assign ie01_e36_we = addr_hit[57] && reg_we; |
| assign ie01_e36_wd = reg_wdata[4]; |
| |
| assign ie01_e37_we = addr_hit[57] && reg_we; |
| assign ie01_e37_wd = reg_wdata[5]; |
| |
| assign ie01_e38_we = addr_hit[57] && reg_we; |
| assign ie01_e38_wd = reg_wdata[6]; |
| |
| assign ie01_e39_we = addr_hit[57] && reg_we; |
| assign ie01_e39_wd = reg_wdata[7]; |
| |
| assign ie01_e40_we = addr_hit[57] && reg_we; |
| assign ie01_e40_wd = reg_wdata[8]; |
| |
| assign ie01_e41_we = addr_hit[57] && reg_we; |
| assign ie01_e41_wd = reg_wdata[9]; |
| |
| assign ie01_e42_we = addr_hit[57] && reg_we; |
| assign ie01_e42_wd = reg_wdata[10]; |
| |
| assign ie01_e43_we = addr_hit[57] && reg_we; |
| assign ie01_e43_wd = reg_wdata[11]; |
| |
| assign ie01_e44_we = addr_hit[57] && reg_we; |
| assign ie01_e44_wd = reg_wdata[12]; |
| |
| assign ie01_e45_we = addr_hit[57] && reg_we; |
| assign ie01_e45_wd = reg_wdata[13]; |
| |
| assign ie01_e46_we = addr_hit[57] && reg_we; |
| assign ie01_e46_wd = reg_wdata[14]; |
| |
| assign ie01_e47_we = addr_hit[57] && reg_we; |
| assign ie01_e47_wd = reg_wdata[15]; |
| |
| assign ie01_e48_we = addr_hit[57] && reg_we; |
| assign ie01_e48_wd = reg_wdata[16]; |
| |
| assign ie01_e49_we = addr_hit[57] && reg_we; |
| assign ie01_e49_wd = reg_wdata[17]; |
| |
| assign ie01_e50_we = addr_hit[57] && reg_we; |
| assign ie01_e50_wd = reg_wdata[18]; |
| |
| assign ie01_e51_we = addr_hit[57] && reg_we; |
| assign ie01_e51_wd = reg_wdata[19]; |
| |
| assign threshold0_we = addr_hit[58] && reg_we; |
| assign threshold0_wd = reg_wdata[1:0]; |
| |
| assign cc0_we = addr_hit[59] && reg_we; |
| assign cc0_wd = reg_wdata[5:0]; |
| assign cc0_re = addr_hit[59] && reg_re; |
| |
| assign msip0_we = addr_hit[60] && reg_we; |
| assign msip0_wd = reg_wdata[0]; |
| |
| // Read data return |
| always_comb begin |
| reg_rdata_next = '0; |
| unique case (1'b1) |
| addr_hit[0]: begin |
| reg_rdata_next[0] = ip0_p0_qs; |
| reg_rdata_next[1] = ip0_p1_qs; |
| reg_rdata_next[2] = ip0_p2_qs; |
| reg_rdata_next[3] = ip0_p3_qs; |
| reg_rdata_next[4] = ip0_p4_qs; |
| reg_rdata_next[5] = ip0_p5_qs; |
| reg_rdata_next[6] = ip0_p6_qs; |
| reg_rdata_next[7] = ip0_p7_qs; |
| reg_rdata_next[8] = ip0_p8_qs; |
| reg_rdata_next[9] = ip0_p9_qs; |
| reg_rdata_next[10] = ip0_p10_qs; |
| reg_rdata_next[11] = ip0_p11_qs; |
| reg_rdata_next[12] = ip0_p12_qs; |
| reg_rdata_next[13] = ip0_p13_qs; |
| reg_rdata_next[14] = ip0_p14_qs; |
| reg_rdata_next[15] = ip0_p15_qs; |
| reg_rdata_next[16] = ip0_p16_qs; |
| reg_rdata_next[17] = ip0_p17_qs; |
| reg_rdata_next[18] = ip0_p18_qs; |
| reg_rdata_next[19] = ip0_p19_qs; |
| reg_rdata_next[20] = ip0_p20_qs; |
| reg_rdata_next[21] = ip0_p21_qs; |
| reg_rdata_next[22] = ip0_p22_qs; |
| reg_rdata_next[23] = ip0_p23_qs; |
| reg_rdata_next[24] = ip0_p24_qs; |
| reg_rdata_next[25] = ip0_p25_qs; |
| reg_rdata_next[26] = ip0_p26_qs; |
| reg_rdata_next[27] = ip0_p27_qs; |
| reg_rdata_next[28] = ip0_p28_qs; |
| reg_rdata_next[29] = ip0_p29_qs; |
| reg_rdata_next[30] = ip0_p30_qs; |
| reg_rdata_next[31] = ip0_p31_qs; |
| end |
| |
| addr_hit[1]: begin |
| reg_rdata_next[0] = ip1_p32_qs; |
| reg_rdata_next[1] = ip1_p33_qs; |
| reg_rdata_next[2] = ip1_p34_qs; |
| reg_rdata_next[3] = ip1_p35_qs; |
| reg_rdata_next[4] = ip1_p36_qs; |
| reg_rdata_next[5] = ip1_p37_qs; |
| reg_rdata_next[6] = ip1_p38_qs; |
| reg_rdata_next[7] = ip1_p39_qs; |
| reg_rdata_next[8] = ip1_p40_qs; |
| reg_rdata_next[9] = ip1_p41_qs; |
| reg_rdata_next[10] = ip1_p42_qs; |
| reg_rdata_next[11] = ip1_p43_qs; |
| reg_rdata_next[12] = ip1_p44_qs; |
| reg_rdata_next[13] = ip1_p45_qs; |
| reg_rdata_next[14] = ip1_p46_qs; |
| reg_rdata_next[15] = ip1_p47_qs; |
| reg_rdata_next[16] = ip1_p48_qs; |
| reg_rdata_next[17] = ip1_p49_qs; |
| reg_rdata_next[18] = ip1_p50_qs; |
| reg_rdata_next[19] = ip1_p51_qs; |
| end |
| |
| addr_hit[2]: begin |
| reg_rdata_next[0] = le0_le0_qs; |
| reg_rdata_next[1] = le0_le1_qs; |
| reg_rdata_next[2] = le0_le2_qs; |
| reg_rdata_next[3] = le0_le3_qs; |
| reg_rdata_next[4] = le0_le4_qs; |
| reg_rdata_next[5] = le0_le5_qs; |
| reg_rdata_next[6] = le0_le6_qs; |
| reg_rdata_next[7] = le0_le7_qs; |
| reg_rdata_next[8] = le0_le8_qs; |
| reg_rdata_next[9] = le0_le9_qs; |
| reg_rdata_next[10] = le0_le10_qs; |
| reg_rdata_next[11] = le0_le11_qs; |
| reg_rdata_next[12] = le0_le12_qs; |
| reg_rdata_next[13] = le0_le13_qs; |
| reg_rdata_next[14] = le0_le14_qs; |
| reg_rdata_next[15] = le0_le15_qs; |
| reg_rdata_next[16] = le0_le16_qs; |
| reg_rdata_next[17] = le0_le17_qs; |
| reg_rdata_next[18] = le0_le18_qs; |
| reg_rdata_next[19] = le0_le19_qs; |
| reg_rdata_next[20] = le0_le20_qs; |
| reg_rdata_next[21] = le0_le21_qs; |
| reg_rdata_next[22] = le0_le22_qs; |
| reg_rdata_next[23] = le0_le23_qs; |
| reg_rdata_next[24] = le0_le24_qs; |
| reg_rdata_next[25] = le0_le25_qs; |
| reg_rdata_next[26] = le0_le26_qs; |
| reg_rdata_next[27] = le0_le27_qs; |
| reg_rdata_next[28] = le0_le28_qs; |
| reg_rdata_next[29] = le0_le29_qs; |
| reg_rdata_next[30] = le0_le30_qs; |
| reg_rdata_next[31] = le0_le31_qs; |
| end |
| |
| addr_hit[3]: begin |
| reg_rdata_next[0] = le1_le32_qs; |
| reg_rdata_next[1] = le1_le33_qs; |
| reg_rdata_next[2] = le1_le34_qs; |
| reg_rdata_next[3] = le1_le35_qs; |
| reg_rdata_next[4] = le1_le36_qs; |
| reg_rdata_next[5] = le1_le37_qs; |
| reg_rdata_next[6] = le1_le38_qs; |
| reg_rdata_next[7] = le1_le39_qs; |
| reg_rdata_next[8] = le1_le40_qs; |
| reg_rdata_next[9] = le1_le41_qs; |
| reg_rdata_next[10] = le1_le42_qs; |
| reg_rdata_next[11] = le1_le43_qs; |
| reg_rdata_next[12] = le1_le44_qs; |
| reg_rdata_next[13] = le1_le45_qs; |
| reg_rdata_next[14] = le1_le46_qs; |
| reg_rdata_next[15] = le1_le47_qs; |
| reg_rdata_next[16] = le1_le48_qs; |
| reg_rdata_next[17] = le1_le49_qs; |
| reg_rdata_next[18] = le1_le50_qs; |
| reg_rdata_next[19] = le1_le51_qs; |
| end |
| |
| addr_hit[4]: begin |
| reg_rdata_next[1:0] = prio0_qs; |
| end |
| |
| addr_hit[5]: begin |
| reg_rdata_next[1:0] = prio1_qs; |
| end |
| |
| addr_hit[6]: begin |
| reg_rdata_next[1:0] = prio2_qs; |
| end |
| |
| addr_hit[7]: begin |
| reg_rdata_next[1:0] = prio3_qs; |
| end |
| |
| addr_hit[8]: begin |
| reg_rdata_next[1:0] = prio4_qs; |
| end |
| |
| addr_hit[9]: begin |
| reg_rdata_next[1:0] = prio5_qs; |
| end |
| |
| addr_hit[10]: begin |
| reg_rdata_next[1:0] = prio6_qs; |
| end |
| |
| addr_hit[11]: begin |
| reg_rdata_next[1:0] = prio7_qs; |
| end |
| |
| addr_hit[12]: begin |
| reg_rdata_next[1:0] = prio8_qs; |
| end |
| |
| addr_hit[13]: begin |
| reg_rdata_next[1:0] = prio9_qs; |
| end |
| |
| addr_hit[14]: begin |
| reg_rdata_next[1:0] = prio10_qs; |
| end |
| |
| addr_hit[15]: begin |
| reg_rdata_next[1:0] = prio11_qs; |
| end |
| |
| addr_hit[16]: begin |
| reg_rdata_next[1:0] = prio12_qs; |
| end |
| |
| addr_hit[17]: begin |
| reg_rdata_next[1:0] = prio13_qs; |
| end |
| |
| addr_hit[18]: begin |
| reg_rdata_next[1:0] = prio14_qs; |
| end |
| |
| addr_hit[19]: begin |
| reg_rdata_next[1:0] = prio15_qs; |
| end |
| |
| addr_hit[20]: begin |
| reg_rdata_next[1:0] = prio16_qs; |
| end |
| |
| addr_hit[21]: begin |
| reg_rdata_next[1:0] = prio17_qs; |
| end |
| |
| addr_hit[22]: begin |
| reg_rdata_next[1:0] = prio18_qs; |
| end |
| |
| addr_hit[23]: begin |
| reg_rdata_next[1:0] = prio19_qs; |
| end |
| |
| addr_hit[24]: begin |
| reg_rdata_next[1:0] = prio20_qs; |
| end |
| |
| addr_hit[25]: begin |
| reg_rdata_next[1:0] = prio21_qs; |
| end |
| |
| addr_hit[26]: begin |
| reg_rdata_next[1:0] = prio22_qs; |
| end |
| |
| addr_hit[27]: begin |
| reg_rdata_next[1:0] = prio23_qs; |
| end |
| |
| addr_hit[28]: begin |
| reg_rdata_next[1:0] = prio24_qs; |
| end |
| |
| addr_hit[29]: begin |
| reg_rdata_next[1:0] = prio25_qs; |
| end |
| |
| addr_hit[30]: begin |
| reg_rdata_next[1:0] = prio26_qs; |
| end |
| |
| addr_hit[31]: begin |
| reg_rdata_next[1:0] = prio27_qs; |
| end |
| |
| addr_hit[32]: begin |
| reg_rdata_next[1:0] = prio28_qs; |
| end |
| |
| addr_hit[33]: begin |
| reg_rdata_next[1:0] = prio29_qs; |
| end |
| |
| addr_hit[34]: begin |
| reg_rdata_next[1:0] = prio30_qs; |
| end |
| |
| addr_hit[35]: begin |
| reg_rdata_next[1:0] = prio31_qs; |
| end |
| |
| addr_hit[36]: begin |
| reg_rdata_next[1:0] = prio32_qs; |
| end |
| |
| addr_hit[37]: begin |
| reg_rdata_next[1:0] = prio33_qs; |
| end |
| |
| addr_hit[38]: begin |
| reg_rdata_next[1:0] = prio34_qs; |
| end |
| |
| addr_hit[39]: begin |
| reg_rdata_next[1:0] = prio35_qs; |
| end |
| |
| addr_hit[40]: begin |
| reg_rdata_next[1:0] = prio36_qs; |
| end |
| |
| addr_hit[41]: begin |
| reg_rdata_next[1:0] = prio37_qs; |
| end |
| |
| addr_hit[42]: begin |
| reg_rdata_next[1:0] = prio38_qs; |
| end |
| |
| addr_hit[43]: begin |
| reg_rdata_next[1:0] = prio39_qs; |
| end |
| |
| addr_hit[44]: begin |
| reg_rdata_next[1:0] = prio40_qs; |
| end |
| |
| addr_hit[45]: begin |
| reg_rdata_next[1:0] = prio41_qs; |
| end |
| |
| addr_hit[46]: begin |
| reg_rdata_next[1:0] = prio42_qs; |
| end |
| |
| addr_hit[47]: begin |
| reg_rdata_next[1:0] = prio43_qs; |
| end |
| |
| addr_hit[48]: begin |
| reg_rdata_next[1:0] = prio44_qs; |
| end |
| |
| addr_hit[49]: begin |
| reg_rdata_next[1:0] = prio45_qs; |
| end |
| |
| addr_hit[50]: begin |
| reg_rdata_next[1:0] = prio46_qs; |
| end |
| |
| addr_hit[51]: begin |
| reg_rdata_next[1:0] = prio47_qs; |
| end |
| |
| addr_hit[52]: begin |
| reg_rdata_next[1:0] = prio48_qs; |
| end |
| |
| addr_hit[53]: begin |
| reg_rdata_next[1:0] = prio49_qs; |
| end |
| |
| addr_hit[54]: begin |
| reg_rdata_next[1:0] = prio50_qs; |
| end |
| |
| addr_hit[55]: begin |
| reg_rdata_next[1:0] = prio51_qs; |
| end |
| |
| addr_hit[56]: begin |
| reg_rdata_next[0] = ie00_e0_qs; |
| reg_rdata_next[1] = ie00_e1_qs; |
| reg_rdata_next[2] = ie00_e2_qs; |
| reg_rdata_next[3] = ie00_e3_qs; |
| reg_rdata_next[4] = ie00_e4_qs; |
| reg_rdata_next[5] = ie00_e5_qs; |
| reg_rdata_next[6] = ie00_e6_qs; |
| reg_rdata_next[7] = ie00_e7_qs; |
| reg_rdata_next[8] = ie00_e8_qs; |
| reg_rdata_next[9] = ie00_e9_qs; |
| reg_rdata_next[10] = ie00_e10_qs; |
| reg_rdata_next[11] = ie00_e11_qs; |
| reg_rdata_next[12] = ie00_e12_qs; |
| reg_rdata_next[13] = ie00_e13_qs; |
| reg_rdata_next[14] = ie00_e14_qs; |
| reg_rdata_next[15] = ie00_e15_qs; |
| reg_rdata_next[16] = ie00_e16_qs; |
| reg_rdata_next[17] = ie00_e17_qs; |
| reg_rdata_next[18] = ie00_e18_qs; |
| reg_rdata_next[19] = ie00_e19_qs; |
| reg_rdata_next[20] = ie00_e20_qs; |
| reg_rdata_next[21] = ie00_e21_qs; |
| reg_rdata_next[22] = ie00_e22_qs; |
| reg_rdata_next[23] = ie00_e23_qs; |
| reg_rdata_next[24] = ie00_e24_qs; |
| reg_rdata_next[25] = ie00_e25_qs; |
| reg_rdata_next[26] = ie00_e26_qs; |
| reg_rdata_next[27] = ie00_e27_qs; |
| reg_rdata_next[28] = ie00_e28_qs; |
| reg_rdata_next[29] = ie00_e29_qs; |
| reg_rdata_next[30] = ie00_e30_qs; |
| reg_rdata_next[31] = ie00_e31_qs; |
| end |
| |
| addr_hit[57]: begin |
| reg_rdata_next[0] = ie01_e32_qs; |
| reg_rdata_next[1] = ie01_e33_qs; |
| reg_rdata_next[2] = ie01_e34_qs; |
| reg_rdata_next[3] = ie01_e35_qs; |
| reg_rdata_next[4] = ie01_e36_qs; |
| reg_rdata_next[5] = ie01_e37_qs; |
| reg_rdata_next[6] = ie01_e38_qs; |
| reg_rdata_next[7] = ie01_e39_qs; |
| reg_rdata_next[8] = ie01_e40_qs; |
| reg_rdata_next[9] = ie01_e41_qs; |
| reg_rdata_next[10] = ie01_e42_qs; |
| reg_rdata_next[11] = ie01_e43_qs; |
| reg_rdata_next[12] = ie01_e44_qs; |
| reg_rdata_next[13] = ie01_e45_qs; |
| reg_rdata_next[14] = ie01_e46_qs; |
| reg_rdata_next[15] = ie01_e47_qs; |
| reg_rdata_next[16] = ie01_e48_qs; |
| reg_rdata_next[17] = ie01_e49_qs; |
| reg_rdata_next[18] = ie01_e50_qs; |
| reg_rdata_next[19] = ie01_e51_qs; |
| end |
| |
| addr_hit[58]: begin |
| reg_rdata_next[1:0] = threshold0_qs; |
| end |
| |
| addr_hit[59]: begin |
| reg_rdata_next[5:0] = cc0_qs; |
| end |
| |
| addr_hit[60]: begin |
| reg_rdata_next[0] = msip0_qs; |
| end |
| |
| default: begin |
| reg_rdata_next = '1; |
| end |
| endcase |
| end |
| |
| // Assertions for Register Interface |
| `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) |
| `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) |
| |
| `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni) |
| |
| `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) |
| |
| `ASSERT(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni) |
| |
| endmodule |
