[sysrst_ctrl] Consolidate input CDC flops, overhaul signal naming
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson b/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
index dc668b0..addb988 100644
--- a/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
+++ b/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson
@@ -22,12 +22,12 @@
}
],
wakeup_list: [
- { name: "gsc_wk",
+ { name: "aon_gsc_wk",
desc: "user directed wakeup",
}
],
reset_request_list: [
- { name: "gsc_rst",
+ { name: "aon_gsc_rst",
desc: "user directed reset"
},
],
@@ -44,6 +44,12 @@
desc: "Number of timer bits",
local: "true",
}
+ { name: "DetTimerWidth",
+ type: "int",
+ default: "32",
+ desc: "Number of detection timer bits",
+ local: "true",
+ }
],
available_input_list: [
{ name: "ac_present", desc: "A/C power is present" }
@@ -64,14 +70,14 @@
{ name: "z3_wakeup", desc: "To enter Z3 mode and exit from Z4 sleep mode" }
],
inter_signal_list: [
- { name: "gsc_wk",
+ { name: "aon_gsc_wk",
package: "",
struct: "logic",
act: "req"
type: "uni",
width: "1"
}
- { name: "gsc_rst",
+ { name: "aon_gsc_rst",
package: "",
struct: "logic",
act: "req"
@@ -103,7 +109,7 @@
resval: "2000",
async: "clk_aon_i",
fields: [
- { bits: "15:0",
+ { bits: "TimerWidth-1:0",
name: "ec_rst_pulse",
desc: "Configure the pulse width of ec_rst_l. 10-200ms, each step is 5us(200KHz clock)",
}
@@ -117,7 +123,7 @@
resval: "8000",
async: "clk_aon_i",
fields: [
- { bits: "15:0",
+ { bits: "TimerWidth-1:0",
name: "ulp_ac_debounce_timer",
desc: "Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)",
}
@@ -131,7 +137,7 @@
resval: "8000",
async: "clk_aon_i",
fields: [
- { bits: "15:0",
+ { bits: "TimerWidth-1:0",
name: "ulp_lid_debounce_timer",
desc: "Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)",
}
@@ -145,7 +151,7 @@
resval: "8000",
async: "clk_aon_i",
fields: [
- { bits: "15:0",
+ { bits: "TimerWidth-1:0",
name: "ulp_pwrb_debounce_timer",
desc: "Configure the debounce timer. 10-200ms, each step is 5us(200KHz clock)",
}
@@ -185,6 +191,7 @@
swaccess: "rw1c",
hwaccess: "hrw",
resval: "0",
+ async: "clk_aon_i",
tags: [ // the value of these regs is determined by the
// value on the pins, hence it cannot be predicted.
"excl:CsrNonInitTests:CsrExclCheck"],
@@ -512,7 +519,7 @@
resval: "0",
async: "clk_aon_i",
fields: [
- { bits: "15:0",
+ { bits: "TimerWidth-1:0",
name: "debounce_timer",
desc: "Define the timer valure so that pwrb_in is not oscillating for 0-200ms, each step is 5us(200KHz clock)",
}
@@ -611,7 +618,7 @@
resval: "0",
async: "clk_aon_i",
fields: [
- { bits: "31:0",
+ { bits: "DetTimerWidth-1:0",
name: "detection_timer",
desc: "0-60s, each step is 5us(200KHz clock)",
}
@@ -659,6 +666,7 @@
swaccess: "rw1c",
hwaccess: "hwo",
resval: "0",
+ async: "clk_aon_i",
tags: [ // the value of these regs is determined by the
// value on the pins, hence it cannot be predicted.
"excl:CsrNonInitTests:CsrExclCheck"],
@@ -686,6 +694,7 @@
swaccess: "rw1c",
hwaccess: "hwo",
resval: "0",
+ async: "clk_aon_i",
tags: [ // the value of these regs is determined by the
// value on the pins, hence it cannot be predicted.
"excl:CsrNonInitTests:CsrExclCheck"],
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv
index 0a8d0b1..3553544 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl.sv
@@ -11,15 +11,12 @@
#(
parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
) (
- input clk_i,//Always-on 24MHz clock(config)
- input clk_aon_i,//Always-on 200KHz clock(logic)
- input rst_ni,//power-on reset for the 24MHz clock(config)
- input rst_aon_ni,//power-on reset for the 200KHz clock(logic)
- output gsc_wk_o, //GSC wake to pwrmgr
- output gsc_rst_o,//GSC reset to rstmgr
- output intr_sysrst_ctrl_o,//sysrst_ctrl interrupt to PLIC
+ input clk_i, // Always-on 24MHz clock(config)
+ input clk_aon_i, // Always-on 200KHz clock(logic)
+ input rst_ni, // power-on reset for the 24MHz clock(config)
+ input rst_aon_ni, // power-on reset for the 200KHz clock(logic)
- //Regster interface
+ // Register interface
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
@@ -27,21 +24,26 @@
input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
- //DIO
- input cio_ac_present_i,//AC power is present
- input cio_ec_rst_in_l_i,//EC reset is asserted by some other system agent
- input cio_key0_in_i,//VolUp button in tablet; column output from the EC in a laptop
- input cio_key1_in_i,//VolDown button in tablet; row input from keyboard matrix in a laptop
- input cio_key2_in_i,//TBD button in tablet; row input from keyboard matrix in a laptop
- input cio_pwrb_in_i,//Power button in both tablet and laptop
- input cio_lid_open_i,//lid is open from GMR
- output logic cio_bat_disable_o,//Battery is disconnected
- output logic cio_ec_rst_out_l_o,//EC reset is asserted by sysrst_ctrl
- output logic cio_key0_out_o,//Passthrough from key0_in, can be configured to invert
- output logic cio_key1_out_o,//Passthrough from key1_in, can be configured to invert
- output logic cio_key2_out_o,//Passthrough from key2_in, can be configured to invert
- output logic cio_pwrb_out_o,//Passthrough from pwrb_in, can be configured to invert
- output logic cio_z3_wakeup_o,//Exit from Z4 sleep mode and enter Z3 mode
+ // Wake, reset and interrupt requests
+ output logic aon_gsc_wk_o, // GSC wake to pwrmgr
+ output logic aon_gsc_rst_o, // GSC reset to rstmgr
+ output logic intr_sysrst_ctrl_o, // sysrst_ctrl interrupt to PLIC
+
+ // IOs
+ input cio_ac_present_i, // AC power is present
+ input cio_ec_rst_in_l_i, // EC reset is asserted by some other system agent
+ input cio_key0_in_i, // VolUp button in tablet; column output from the EC in a laptop
+ input cio_key1_in_i, // VolDown button in tablet; row input from keyboard matrix in a laptop
+ input cio_key2_in_i, // TBD button in tablet; row input from keyboard matrix in a laptop
+ input cio_pwrb_in_i, // Power button in both tablet and laptop
+ input cio_lid_open_i, // lid is open from GMR
+ output logic cio_bat_disable_o, // Battery is disconnected
+ output logic cio_ec_rst_out_l_o, // EC reset is asserted by sysrst_ctrl
+ output logic cio_key0_out_o, // Passthrough from key0_in, can be configured to invert
+ output logic cio_key1_out_o, // Passthrough from key1_in, can be configured to invert
+ output logic cio_key2_out_o, // Passthrough from key2_in, can be configured to invert
+ output logic cio_pwrb_out_o, // Passthrough from pwrb_in, can be configured to invert
+ output logic cio_z3_wakeup_o, // Exit from Z4 sleep mode and enter Z3 mode
output logic cio_bat_disable_en_o,
output logic cio_ec_rst_out_l_en_o,
output logic cio_key0_out_en_o,
@@ -51,28 +53,15 @@
output logic cio_z3_wakeup_en_o
);
+ /////////////////////////
+ // Alerts and CSR Node //
+ /////////////////////////
+
import sysrst_ctrl_reg_pkg::* ;
sysrst_ctrl_reg2hw_t reg2hw;
sysrst_ctrl_hw2reg_t hw2reg;
- logic pwrb_int, key0_int, key1_int, key2_int, ac_present_int, lid_open_int;
- logic pwrb_out_hw, key0_out_hw, key1_out_hw, key2_out_hw, ec_rst_l_hw, bat_disable_hw;
- logic z3_wakeup_hw;
- logic pwrb_out_int, key0_out_int, key1_out_int, key2_out_int, bat_disable_int, z3_wakeup_int;
- logic sysrst_ctrl_combo_intr, sysrst_ctrl_key_intr;
- logic ulp_wakeup_pulse_int;
-
- //Always-on pins
- assign cio_ec_rst_out_l_en_o = 1'b1;
- assign cio_pwrb_out_en_o = 1'b1;
- assign cio_key0_out_en_o = 1'b1;
- assign cio_key1_out_en_o = 1'b1;
- assign cio_key2_out_en_o = 1'b1;
- assign cio_bat_disable_en_o = 1'b1;
- assign cio_z3_wakeup_en_o = 1'b1;
-
- // Alerts
logic [NumAlerts-1:0] alert_test, alerts;
assign alert_test = {
reg2hw.alert_test.q &
@@ -95,7 +84,6 @@
);
end
- // Register module
sysrst_ctrl_reg_top u_reg (
.clk_i,
.rst_ni,
@@ -109,165 +97,260 @@
.devmode_i (1'b1)
);
- //Instantiate the autoblock module
- sysrst_ctrl_autoblock u_autoblock (
+ ///////////////////////////////////////
+ // Input inversion and Synchronizers //
+ ///////////////////////////////////////
+
+ // Optionally invert some of the input signals
+ logic pwrb_int, key0_int, key1_int, key2_int, ac_present_int, lid_open_int, ec_rst_l_int;
+ assign pwrb_int = reg2hw.key_invert_ctl.pwrb_in.q ^ cio_pwrb_in_i;
+ assign key0_int = reg2hw.key_invert_ctl.key0_in.q ^ cio_key0_in_i;
+ assign key1_int = reg2hw.key_invert_ctl.key1_in.q ^ cio_key1_in_i;
+ assign key2_int = reg2hw.key_invert_ctl.key2_in.q ^ cio_key2_in_i;
+ assign ac_present_int = reg2hw.key_invert_ctl.ac_present.q ^ cio_ac_present_i;
+ assign lid_open_int = reg2hw.key_invert_ctl.lid_open.q ^ cio_lid_open_i;
+ // Uninverted input
+ assign ec_rst_l_int = cio_ec_rst_in_l_i;
+
+ // Synchronize input signals to AON clock
+ logic aon_pwrb_int, aon_key0_int, aon_key1_int, aon_key2_int;
+ logic aon_ac_present_int, aon_lid_open_int, aon_ec_rst_l_int;
+ prim_flop_2sync # (
+ .Width(7)
+ ) u_prim_flop_2sync_input (
+ .clk_i(clk_aon_i),
+ .rst_ni(rst_aon_ni),
+ .d_i({pwrb_int,
+ key0_int,
+ key1_int,
+ key2_int,
+ ac_present_int,
+ lid_open_int,
+ ec_rst_l_int}),
+ .q_o({aon_pwrb_int,
+ aon_key0_int,
+ aon_key1_int,
+ aon_key2_int,
+ aon_ac_present_int,
+ aon_lid_open_int,
+ aon_ec_rst_l_int})
+ );
+
+ ///////////////
+ // Autoblock //
+ ///////////////
+
+ // This module operates on both synchronized and unsynchronized signals.
+ // I.e., the passthrough signals are NOT synchronnous to the AON clock.
+ logic pwrb_out_hw, key0_out_hw, key1_out_hw, key2_out_hw;
+ sysrst_ctrl_autoblock u_sysrst_ctrl_autoblock (
.clk_aon_i,
.rst_aon_ni,
+ // (Optionally) inverted input signals on AON clock
+ .aon_pwrb_int_i(aon_pwrb_int),
+ // (Optionally) inverted input signals (not synced to AON clock)
.pwrb_int_i(pwrb_int),
.key0_int_i(key0_int),
.key1_int_i(key1_int),
.key2_int_i(key2_int),
- .auto_block_debounce_ctl_i(reg2hw.auto_block_debounce_ctl),
- .auto_block_out_ctl_i(reg2hw.auto_block_out_ctl),
+ // CSRs synced to AON clock
+ .aon_auto_block_debounce_ctl_i(reg2hw.auto_block_debounce_ctl),
+ .aon_auto_block_out_ctl_i(reg2hw.auto_block_out_ctl),
+ // Output signals to pin override logic (not synced to AON clock)
.pwrb_out_hw_o(pwrb_out_hw),
.key0_out_hw_o(key0_out_hw),
.key1_out_hw_o(key1_out_hw),
.key2_out_hw_o(key2_out_hw)
);
- //Instantiate the ULP module
- sysrst_ctrl_ulp u_ulp (
- .clk_aon_i,
- .rst_aon_ni,
- .pwrb_int_i(pwrb_int),
- .lid_open_int_i(lid_open_int),
- .ac_present_int_i(ac_present_int),
+ /////////
+ // ULP //
+ /////////
+
+ // This module runs on the AON clock entirely.
+ // Hence, its local signals are not prefixed with aon_*.
+ logic aon_z3_wakeup_hw;
+ logic aon_ulp_wakeup_pulse_int;
+ sysrst_ctrl_ulp u_sysrst_ctrl_ulp (
+ .clk_i(clk_aon_i),
+ .rst_ni(rst_aon_ni),
+ // (Optionally) inverted input signals on AON clock
+ .pwrb_int_i(aon_pwrb_int),
+ .lid_open_int_i(aon_lid_open_int),
+ .ac_present_int_i(aon_ac_present_int),
+ // CSRs synced to AON clock
.ulp_ac_debounce_ctl_i(reg2hw.ulp_ac_debounce_ctl),
.ulp_lid_debounce_ctl_i(reg2hw.ulp_lid_debounce_ctl),
.ulp_pwrb_debounce_ctl_i(reg2hw.ulp_pwrb_debounce_ctl),
.ulp_ctl_i(reg2hw.ulp_ctl),
.ulp_status_o(hw2reg.ulp_status),
- .ulp_wakeup_pulse_o(ulp_wakeup_pulse_int),
- .z3_wakeup_hw_o(z3_wakeup_hw)
+ // wakeup pulses on AON clock
+ .ulp_wakeup_pulse_o(aon_ulp_wakeup_pulse_int),
+ .z3_wakeup_hw_o(aon_z3_wakeup_hw)
);
- //Instantiate the pin inversion module
- sysrst_ctrl_inv u_inversion (
- .cio_pwrb_in_i,
- .cio_key0_in_i,
- .cio_key1_in_i,
- .cio_key2_in_i,
- .cio_ac_present_i,
- .cio_lid_open_i,
- .pwrb_out_int_i(pwrb_out_int),
- .key0_out_int_i(key0_out_int),
- .key1_out_int_i(key1_out_int),
- .key2_out_int_i(key2_out_int),
- .bat_disable_int_i(bat_disable_int),
- .z3_wakeup_int_i(z3_wakeup_int),
- .key_invert_ctl_i(reg2hw.key_invert_ctl),
- .pwrb_int_o(pwrb_int),
- .key0_int_o(key0_int),
- .key1_int_o(key1_int),
- .key2_int_o(key2_int),
- .ac_present_int_o(ac_present_int),
- .lid_open_int_o(lid_open_int),
- .cio_bat_disable_o,
- .cio_pwrb_out_o,
- .cio_key0_out_o,
- .cio_key1_out_o,
- .cio_key2_out_o,
- .cio_z3_wakeup_o
- );
+ /////////////////////////////
+ // Key triggered interrups //
+ /////////////////////////////
- //Instantiate the pin visibility and override module
- sysrst_ctrl_pin u_pin_vis_ovd (
- .clk_i,
- .rst_ni,
- .cio_pwrb_in_i,
- .cio_key0_in_i,
- .cio_key1_in_i,
- .cio_key2_in_i,
- .cio_ac_present_i,
- .cio_ec_rst_in_l_i,
- .cio_lid_open_i,
- .pwrb_out_hw_i(pwrb_out_hw),
- .key0_out_hw_i(key0_out_hw),
- .key1_out_hw_i(key1_out_hw),
- .key2_out_hw_i(key2_out_hw),
- .bat_disable_hw_i(bat_disable_hw),
- .ec_rst_l_hw_i(ec_rst_l_hw),
- .z3_wakeup_hw_i(z3_wakeup_hw),
- .pin_allowed_ctl_i(reg2hw.pin_allowed_ctl),
- .pin_out_ctl_i(reg2hw.pin_out_ctl),
- .pin_out_value_i(reg2hw.pin_out_value),
- .pin_in_value_o(hw2reg.pin_in_value),
- .pwrb_out_int_o(pwrb_out_int),
- .key0_out_int_o(key0_out_int),
- .key1_out_int_o(key1_out_int),
- .key2_out_int_o(key2_out_int),
- .bat_disable_int_o(bat_disable_int),
- .z3_wakeup_int_o(z3_wakeup_int),
- .cio_ec_rst_out_l_o
- );
-
- //Instantiate key-triggered interrupt module
- sysrst_ctrl_keyintr u_keyintr (
- .clk_i,
- .rst_ni,
- .clk_aon_i,
- .rst_aon_ni,
- .pwrb_int_i(pwrb_int),
- .key0_int_i(key0_int),
- .key1_int_i(key1_int),
- .key2_int_i(key2_int),
- .ac_present_int_i(ac_present_int),
- .cio_ec_rst_in_l_i,
+ // This module runs on the AON clock entirely.
+ // Hence, its local signals are not prefixed with aon_*.
+ logic aon_sysrst_ctrl_key_intr;
+ sysrst_ctrl_keyintr u_sysrst_ctrl_keyintr (
+ .clk_i(clk_aon_i),
+ .rst_ni(rst_aon_ni),
+ // (Optionally) inverted input signals on AON clock
+ .pwrb_int_i(aon_pwrb_int),
+ .key0_int_i(aon_key0_int),
+ .key1_int_i(aon_key1_int),
+ .key2_int_i(aon_key2_int),
+ .ac_present_int_i(aon_ac_present_int),
+ .ec_rst_l_int_i(aon_ec_rst_l_int),
+ // CSRs synced to AON clock
.key_intr_ctl_i(reg2hw.key_intr_ctl),
.key_intr_debounce_ctl_i(reg2hw.key_intr_debounce_ctl),
.key_intr_status_o(hw2reg.key_intr_status),
- .sysrst_ctrl_key_intr_o(sysrst_ctrl_key_intr)
+ // IRQ running on AON clock
+ .sysrst_ctrl_key_intr_o(aon_sysrst_ctrl_key_intr)
);
- //Instantiate combo module
- sysrst_ctrl_combo u_combo (
- .clk_i,
- .rst_ni,
- .clk_aon_i,
- .rst_aon_ni,
- .pwrb_int_i(pwrb_int),
- .key0_int_i(key0_int),
- .key1_int_i(key1_int),
- .key2_int_i(key2_int),
- .ac_present_int_i(ac_present_int),
- .cio_ec_rst_in_l_i,
+ /////////////////////
+ // Combo detection //
+ /////////////////////
+
+ // This module runs on the AON clock entirely.
+ // Hence, its local signals are not prefixed with aon_*.
+ logic aon_sysrst_ctrl_combo_intr, aon_bat_disable_hw, aon_ec_rst_l_hw;
+ sysrst_ctrl_combo u_sysrst_ctrl_combo (
+ .clk_i(clk_aon_i),
+ .rst_ni(rst_aon_ni),
+ // (Optionally) inverted input signals on AON clock
+ .pwrb_int_i(aon_pwrb_int),
+ .key0_int_i(aon_key0_int),
+ .key1_int_i(aon_key1_int),
+ .key2_int_i(aon_key2_int),
+ .ac_present_int_i(aon_ac_present_int),
+ .ec_rst_l_int_i(aon_ec_rst_l_int),
+ // CSRs synced to AON clock
.ec_rst_ctl_i(reg2hw.ec_rst_ctl),
.key_intr_debounce_ctl_i(reg2hw.key_intr_debounce_ctl),
.com_sel_ctl_i(reg2hw.com_sel_ctl),
.com_det_ctl_i(reg2hw.com_det_ctl),
.com_out_ctl_i(reg2hw.com_out_ctl),
.combo_intr_status_o(hw2reg.combo_intr_status),
- .sysrst_ctrl_combo_intr_o(sysrst_ctrl_combo_intr),
- .bat_disable_hw_o(bat_disable_hw),
- .gsc_rst_o,
- .ec_rst_l_hw_o(ec_rst_l_hw)
+ // Output signals on AON clock
+ .sysrst_ctrl_combo_intr_o(aon_sysrst_ctrl_combo_intr),
+ .bat_disable_hw_o(aon_bat_disable_hw),
+ .gsc_rst_o(aon_gsc_rst_o),
+ .ec_rst_l_hw_o(aon_ec_rst_l_hw)
);
- // TODO: does ulp_wakeup_pulse_int have to be on the AON domain or not?
- // GSC wakeup signal to pwrmgr
- // see #6323
- assign gsc_wk_o = reg2hw.wk_status.q;
- assign hw2reg.wk_status.de = ulp_wakeup_pulse_int ||
- sysrst_ctrl_combo_intr || sysrst_ctrl_key_intr;
- assign hw2reg.wk_status.d = 1'b1;
+ ///////////////////////////////
+ // Pin visibility / override //
+ ///////////////////////////////
- //Instantiate the interrupt module
- sysrst_ctrl_intr u_intr (
+ // This module operates on both synchronized and unsynchronized signals.
+ // I.e., the passthrough signals are NOT synchronnous to the AON clock.
+ logic pwrb_out_int, key0_out_int, key1_out_int, key2_out_int, aon_bat_disable_out_int;
+ logic aon_z3_wakeup_out_int, aon_ec_rst_out_int;
+ sysrst_ctrl_pin u_sysrst_ctrl_pin (
.clk_i,
.rst_ni,
- .sysrst_ctrl_combo_intr_i(sysrst_ctrl_combo_intr),
- .sysrst_ctrl_key_intr_i(sysrst_ctrl_key_intr),
- .intr_state_i(reg2hw.intr_state),
- .intr_enable_i(reg2hw.intr_enable),
- .intr_test_i(reg2hw.intr_test),
- .intr_state_o(hw2reg.intr_state),
- .sysrst_ctrl_intr_o(intr_sysrst_ctrl_o)
+ // Raw input signals (not synced to AON clock)
+ .cio_pwrb_in_i,
+ .cio_key0_in_i,
+ .cio_key1_in_i,
+ .cio_key2_in_i,
+ .cio_ac_present_i,
+ .cio_ec_rst_in_l_i,
+ .cio_lid_open_i,
+ // Signals from autoblock (not synced to AON clock)
+ .pwrb_out_hw_i(pwrb_out_hw),
+ .key0_out_hw_i(key0_out_hw),
+ .key1_out_hw_i(key1_out_hw),
+ .key2_out_hw_i(key2_out_hw),
+ // Generated signals, running on AON clock
+ .aon_bat_disable_hw_i(aon_bat_disable_hw),
+ .aon_ec_rst_l_hw_i(aon_ec_rst_l_hw),
+ .aon_z3_wakeup_hw_i(aon_z3_wakeup_hw),
+ // CSRs synced to AON clock
+ .aon_pin_allowed_ctl_i(reg2hw.pin_allowed_ctl),
+ .aon_pin_out_ctl_i(reg2hw.pin_out_ctl),
+ .aon_pin_out_value_i(reg2hw.pin_out_value),
+ // CSRs synced to bus clock
+ .pin_in_value_o(hw2reg.pin_in_value),
+ // Output signals (not synced to AON clock)
+ .pwrb_out_int_o(pwrb_out_int),
+ .key0_out_int_o(key0_out_int),
+ .key1_out_int_o(key1_out_int),
+ .key2_out_int_o(key2_out_int),
+ // Output signals running on AON clock
+ .aon_bat_disable_out_int_o(aon_bat_disable_out_int),
+ .aon_z3_wakeup_out_int_o(aon_z3_wakeup_out_int),
+ .aon_ec_rst_out_int_l_o(aon_ec_rst_out_int)
+ );
+
+ // Optionally invert some of the output signals
+ assign cio_pwrb_out_o = reg2hw.key_invert_ctl.pwrb_out.q ^ pwrb_out_int;
+ assign cio_key0_out_o = reg2hw.key_invert_ctl.key0_out.q ^ key0_out_int;
+ assign cio_key1_out_o = reg2hw.key_invert_ctl.key1_out.q ^ key1_out_int;
+ assign cio_key2_out_o = reg2hw.key_invert_ctl.key2_out.q ^ key2_out_int;
+ assign cio_bat_disable_o = reg2hw.key_invert_ctl.bat_disable.q ^ aon_bat_disable_out_int;
+ assign cio_z3_wakeup_o = reg2hw.key_invert_ctl.z3_wakeup.q ^ aon_z3_wakeup_out_int;
+ // uninverted output
+ assign cio_ec_rst_out_l_o = aon_ec_rst_out_int;
+
+ // These outputs are always enabled
+ assign cio_pwrb_out_en_o = 1'b1;
+ assign cio_key0_out_en_o = 1'b1;
+ assign cio_key1_out_en_o = 1'b1;
+ assign cio_key2_out_en_o = 1'b1;
+ assign cio_bat_disable_en_o = 1'b1;
+ assign cio_z3_wakeup_en_o = 1'b1;
+ assign cio_ec_rst_out_l_en_o = 1'b1;
+
+ ///////////////////////////
+ // Interrupt agreggation //
+ ///////////////////////////
+
+ // GSC wakeup signal to pwrmgr, CSRs and signals on AON domain (see #6323)
+ assign aon_gsc_wk_o = reg2hw.wk_status.q;
+ assign hw2reg.wk_status.de = aon_ulp_wakeup_pulse_int ||
+ aon_sysrst_ctrl_combo_intr ||
+ aon_sysrst_ctrl_key_intr;
+ assign hw2reg.wk_status.d = 1'b1;
+
+ // sync the wakeup request (level) to bus clock to trigger an IRQ.
+ logic gsc_wk;
+ prim_flop_2sync #(
+ .Width(1)
+ ) u_prim_flop_2sync (
+ .clk_i,
+ .rst_ni,
+ .d_i(aon_gsc_wk_o),
+ .q_o(gsc_wk)
+ );
+
+ // Instantiate the interrupt module
+ prim_intr_hw #(
+ .Width(1)
+ ) u_prim_intr_hw (
+ .clk_i,
+ .rst_ni,
+ .event_intr_i (gsc_wk),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.d),
+ .intr_o (intr_sysrst_ctrl_o)
);
// All outputs should be known value after reset
`ASSERT_KNOWN(IntrSysRstCtrlOKnown, intr_sysrst_ctrl_o)
- `ASSERT_KNOWN(GSCWkOKnown, gsc_wk_o)
- `ASSERT_KNOWN(GSCRstOKnown, gsc_rst_o)
+ `ASSERT_KNOWN(GSCWkOKnown, aon_gsc_wk_o)
+ `ASSERT_KNOWN(GSCRstOKnown, aon_gsc_rst_o)
`ASSERT_KNOWN(TlODValidKnown, tl_o.d_valid)
`ASSERT_KNOWN(TlOAReadyKnown, tl_o.a_ready)
`ASSERT_KNOWN(AlertKnownO_A, alert_tx_o)
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_autoblock.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_autoblock.sv
index e1afb27..a74db30 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_autoblock.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_autoblock.sv
@@ -7,53 +7,43 @@
module sysrst_ctrl_autoblock import sysrst_ctrl_reg_pkg::*; (
input clk_aon_i,
input rst_aon_ni,
-
+ // (Optionally) inverted input signals on AON clock
+ input aon_pwrb_int_i,
+ // (Optionally) inverted input signals (not synced to AON clock)
input pwrb_int_i,
input key0_int_i,
input key1_int_i,
input key2_int_i,
-
- input sysrst_ctrl_reg2hw_auto_block_debounce_ctl_reg_t auto_block_debounce_ctl_i,
- input sysrst_ctrl_reg2hw_auto_block_out_ctl_reg_t auto_block_out_ctl_i,
-
+ // CSRs synced to AON clock
+ input sysrst_ctrl_reg2hw_auto_block_debounce_ctl_reg_t aon_auto_block_debounce_ctl_i,
+ input sysrst_ctrl_reg2hw_auto_block_out_ctl_reg_t aon_auto_block_out_ctl_i,
+ // Output signals to pin override logic (not synced to AON clock)
output pwrb_out_hw_o,
output key0_out_hw_o,
output key1_out_hw_o,
output key2_out_hw_o
);
- logic ab_cond_met;
- logic pwrb_int;
-
- //synchronize between GPIO and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1)
- ) u_pwrb_in_i (
+ logic aon_ab_cond_met;
+ sysrst_ctrl_timerfsm # (
+ .TimerWidth(TimerWidth)
+ ) u_ab_fsm (
.clk_i(clk_aon_i),
.rst_ni(rst_aon_ni),
- .d_i(pwrb_int_i),
- .q_o(pwrb_int)
- );
-
- sysrst_ctrl_timerfsm # (
- .TIMERBIT(16)
- ) u_ab_fsm (
- .clk_aon_i,
- .rst_aon_ni,
- .trigger_i(pwrb_int),
- .cfg_timer_i(auto_block_debounce_ctl_i.debounce_timer.q),
+ .trigger_i(aon_pwrb_int_i),
+ .cfg_timer_i(aon_auto_block_debounce_ctl_i.debounce_timer.q),
.cfg_l2h_en_i(1'b0),
- .cfg_h2l_en_i(auto_block_debounce_ctl_i.auto_block_enable.q),
+ .cfg_h2l_en_i(aon_auto_block_debounce_ctl_i.auto_block_enable.q),
.timer_l2h_cond_met(),
- .timer_h2l_cond_met(ab_cond_met)
+ .timer_h2l_cond_met(aon_ab_cond_met)
);
- assign pwrb_out_hw_o = pwrb_int;
- assign key0_out_hw_o = (ab_cond_met & auto_block_out_ctl_i.key0_out_sel.q) ?
- auto_block_out_ctl_i.key0_out_value.q : key0_int_i;
- assign key1_out_hw_o = (ab_cond_met & auto_block_out_ctl_i.key1_out_sel.q) ?
- auto_block_out_ctl_i.key1_out_value.q : key1_int_i;
- assign key2_out_hw_o = (ab_cond_met & auto_block_out_ctl_i.key2_out_sel.q) ?
- auto_block_out_ctl_i.key2_out_value.q : key2_int_i;
+ assign pwrb_out_hw_o = pwrb_int_i;
+ assign key0_out_hw_o = (aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q) ?
+ aon_auto_block_out_ctl_i.key0_out_value.q : key0_int_i;
+ assign key1_out_hw_o = (aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q) ?
+ aon_auto_block_out_ctl_i.key1_out_value.q : key1_int_i;
+ assign key2_out_hw_o = (aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q) ?
+ aon_auto_block_out_ctl_i.key2_out_value.q : key2_int_i;
endmodule
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv
index 1c6000c..3875b52 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv
@@ -5,27 +5,24 @@
// Description: sysrst_ctrl combo Module
//
module sysrst_ctrl_combo import sysrst_ctrl_reg_pkg::*; (
- input clk_aon_i,
- input rst_aon_ni,
input clk_i,
input rst_ni,
-
+ // (Optionally) inverted input signals on AON clock
input pwrb_int_i,
input key0_int_i,
input key1_int_i,
input key2_int_i,
input ac_present_int_i,
- input cio_ec_rst_in_l_i,
-
- input sysrst_ctrl_reg2hw_ec_rst_ctl_reg_t ec_rst_ctl_i,
- input sysrst_ctrl_reg2hw_key_intr_debounce_ctl_reg_t key_intr_debounce_ctl_i,
+ input ec_rst_l_int_i,
+ // CSRs synced to AON clock
+ input sysrst_ctrl_reg2hw_ec_rst_ctl_reg_t ec_rst_ctl_i,
+ input sysrst_ctrl_reg2hw_key_intr_debounce_ctl_reg_t key_intr_debounce_ctl_i,
input sysrst_ctrl_reg2hw_com_sel_ctl_mreg_t [NumCombo-1:0] com_sel_ctl_i,
input sysrst_ctrl_reg2hw_com_det_ctl_mreg_t [NumCombo-1:0] com_det_ctl_i,
input sysrst_ctrl_reg2hw_com_out_ctl_mreg_t [NumCombo-1:0] com_out_ctl_i,
-
- output sysrst_ctrl_hw2reg_combo_intr_status_reg_t combo_intr_status_o,
+ output sysrst_ctrl_hw2reg_combo_intr_status_reg_t combo_intr_status_o,
+ // Output signals on AON clock
output sysrst_ctrl_combo_intr_o,
-
output bat_disable_hw_o,
output gsc_rst_o,
output ec_rst_l_hw_o
@@ -33,144 +30,68 @@
// There are four possible combos
// Each key combo can select different triggers
- logic pwrb_int;
- logic key0_int, key1_int, key2_int;
- logic ac_present_int;
-
- logic [NumCombo-1:0] trigger_h;
- logic [NumCombo-1:0] trigger_l;
- logic [NumCombo-1:0] cfg_combo_en;
- logic [NumCombo-1:0] combo_det;
-
logic [NumCombo-1:0] combo_bat_disable;
- logic [NumCombo-1:0] combo_intr_pulse;
- logic [NumCombo-1:0] combo_intr_pulse_synced;
logic [NumCombo-1:0] combo_ec_rst_l;
logic [NumCombo-1:0] combo_gsc_rst;
-
- logic ec_rst_l_int;
-
-
- //synchronize between GPIO and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1)
- ) u_ec_rst_l_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(cio_ec_rst_in_l_i),
- .q_o(ec_rst_l_int)
- );
-
- //synchronize between GPIO and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1)
- ) u_pwrb_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pwrb_int_i),
- .q_o(pwrb_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_key0_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key0_int_i),
- .q_o(key0_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_key1_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key1_int_i),
- .q_o(key1_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_key2_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key2_int_i),
- .q_o(key2_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_ac_present_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(ac_present_int_i),
- .q_o(ac_present_int)
- );
+ logic [NumCombo-1:0] combo_intr_pulse;
for (genvar k = 0 ; k < NumCombo ; k++) begin : gen_combo_trigger
- // generate the trigger for each combo
+ // Generate the trigger for each combo
+ logic trigger_h, trigger_l;
sysrst_ctrl_combotrg u_combo_trg (
.cfg_in0_sel(com_sel_ctl_i[k].pwrb_in_sel.q),
.cfg_in1_sel(com_sel_ctl_i[k].key0_in_sel.q),
.cfg_in2_sel(com_sel_ctl_i[k].key1_in_sel.q),
.cfg_in3_sel(com_sel_ctl_i[k].key2_in_sel.q),
.cfg_in4_sel(com_sel_ctl_i[k].ac_present_sel.q),
- .in0(pwrb_int),
- .in1(key0_int),
- .in2(key1_int),
- .in3(key2_int),
- .in4(ac_present_int),
- .trigger_h_o(trigger_h[k]),
- .trigger_l_o(trigger_l[k])
+ .in0(pwrb_int_i),
+ .in1(key0_int_i),
+ .in2(key1_int_i),
+ .in3(key2_int_i),
+ .in4(ac_present_int_i),
+ .trigger_h_o(trigger_h),
+ .trigger_l_o(trigger_l)
);
- assign cfg_combo_en[k] = com_sel_ctl_i[k].pwrb_in_sel.q |
- com_sel_ctl_i[k].key0_in_sel.q |
- com_sel_ctl_i[k].key1_in_sel.q |
- com_sel_ctl_i[k].key2_in_sel.q |
- com_sel_ctl_i[k].ac_present_sel.q;
+ logic cfg_combo_en;
+ assign cfg_combo_en = com_sel_ctl_i[k].pwrb_in_sel.q |
+ com_sel_ctl_i[k].key0_in_sel.q |
+ com_sel_ctl_i[k].key1_in_sel.q |
+ com_sel_ctl_i[k].key2_in_sel.q |
+ com_sel_ctl_i[k].ac_present_sel.q;
//Instantiate the combo detection state machine
+ logic combo_det;
sysrst_ctrl_combofsm # (
- .TIMER1BIT(16),
- .TIMER2BIT(32)
+ .Timer1Width(TimerWidth),
+ .Timer2Width(DetTimerWidth)
) u_combo_fsm (
- .clk_aon_i,
- .rst_aon_ni,
- .trigger_h_i(trigger_h[k]),
- .trigger_l_i(trigger_l[k]),
+ .clk_i,
+ .rst_ni,
+ .trigger_h_i(trigger_h),
+ .trigger_l_i(trigger_l),
.cfg_timer1_i(key_intr_debounce_ctl_i.q),
.cfg_timer2_i(com_det_ctl_i[k].q),
- .cfg_h2l_en_i(cfg_combo_en[k]),
- .timer_h2l_cond_met(combo_det[k])
+ .cfg_h2l_en_i(cfg_combo_en),
+ .timer_h2l_cond_met_o(combo_det)
);
//Instantiate the combo action module
sysrst_ctrl_comboact u_combo_act (
- .clk_aon_i,
- .rst_aon_ni,
- .cfg_intr_en(com_out_ctl_i[k].interrupt.q),
- .cfg_bat_disable_en(com_out_ctl_i[k].bat_disable.q),
- .cfg_ec_rst_en(com_out_ctl_i[k].ec_rst.q),
- .cfg_gsc_rst_en(com_out_ctl_i[k].gsc_rst.q),
- .combo_det(combo_det[k]),
- .ec_rst_l_i(ec_rst_l_int),
+ .clk_i,
+ .rst_ni,
+ .cfg_intr_en_i(com_out_ctl_i[k].interrupt.q),
+ .cfg_bat_disable_en_i(com_out_ctl_i[k].bat_disable.q),
+ .cfg_ec_rst_en_i(com_out_ctl_i[k].ec_rst.q),
+ .cfg_gsc_rst_en_i(com_out_ctl_i[k].gsc_rst.q),
+ .combo_det_i(combo_det),
+ .ec_rst_l_i(ec_rst_l_int_i),
.ec_rst_ctl_i(ec_rst_ctl_i),
- .combo_intr_pulse(combo_intr_pulse[k]),
+ .combo_intr_pulse_o(combo_intr_pulse[k]),
.bat_disable_o(combo_bat_disable[k]),
.gsc_rst_o(combo_gsc_rst[k]),
.ec_rst_l_o(combo_ec_rst_l[k])
);
-
- // Synchronize IRQ pulsefrom 200KHz always-onclock to 24MHz cfg clock
- prim_pulse_sync u_combo0_intr (
- .clk_src_i (clk_aon_i),
- .clk_dst_i (clk_i),
- .rst_src_ni (rst_aon_ni),
- .rst_dst_ni (rst_ni),
- .src_pulse_i (combo_intr_pulse[k]),
- .dst_pulse_o (combo_intr_pulse_synced[k])
- );
end
// bat_disable
@@ -185,9 +106,9 @@
assign {combo_intr_status_o.combo3_h2l.de,
combo_intr_status_o.combo2_h2l.de,
combo_intr_status_o.combo1_h2l.de,
- combo_intr_status_o.combo0_h2l.de} = combo_intr_pulse_synced;
+ combo_intr_status_o.combo0_h2l.de} = combo_intr_pulse;
- assign sysrst_ctrl_combo_intr_o = |combo_intr_pulse_synced;
+ assign sysrst_ctrl_combo_intr_o = |combo_intr_pulse;
assign combo_intr_status_o.combo0_h2l.d = 1'b1;
assign combo_intr_status_o.combo1_h2l.d = 1'b1;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_comboact.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_comboact.sv
index 44158e1..5aa2914 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_comboact.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_comboact.sv
@@ -5,19 +5,19 @@
// Description: sysrst_ctrl combo action Module
//
module sysrst_ctrl_comboact import sysrst_ctrl_reg_pkg::*; (
- input clk_aon_i,
- input rst_aon_ni,
+ input clk_i,
+ input rst_ni,
- input cfg_intr_en,
- input cfg_bat_disable_en,
- input cfg_ec_rst_en,
- input cfg_gsc_rst_en,
- input combo_det,
+ input cfg_intr_en_i,
+ input cfg_bat_disable_en_i,
+ input cfg_ec_rst_en_i,
+ input cfg_gsc_rst_en_i,
+ input combo_det_i,
input ec_rst_l_i,
input sysrst_ctrl_reg2hw_ec_rst_ctl_reg_t ec_rst_ctl_i,
- output combo_intr_pulse,
+ output combo_intr_pulse_o,
output bat_disable_o,
output gsc_rst_o,
output ec_rst_l_o
@@ -31,28 +31,28 @@
logic combo_ec_rst_pulse;
logic ec_rst_l_q, ec_rst_l_d;
- logic [15:0] timer_cnt_d, timer_cnt_q;
+ logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
logic timer_cnt_clr, timer_cnt_en;
logic ec_rst_l_int, ec_rst_l_det;
//delay the level signal to generate a pulse
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: u_combo_det
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: u_combo_det
+ if (!rst_ni) begin
combo_det_q <= 1'b0;
end else begin
- combo_det_q <= combo_det;
+ combo_det_q <= combo_det_i;
end
end
//bat_disable logic
- assign combo_bat_disable_pulse = cfg_bat_disable_en && (combo_det_q == 1'b0) &&
- (combo_det == 1'b1);
+ assign combo_bat_disable_pulse = cfg_bat_disable_en_i && (combo_det_q == 1'b0) &&
+ (combo_det_i == 1'b1);
assign bat_disable_d = combo_bat_disable_pulse ? 1'b1 : bat_disable_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: u_combo_bat_disable
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: u_combo_bat_disable
+ if (!rst_ni) begin
bat_disable_q <= 1'b0;
end else begin
bat_disable_q <= bat_disable_d;
@@ -62,11 +62,11 @@
assign bat_disable_o = bat_disable_q;
//Interrupt logic
- assign combo_intr_pulse = cfg_intr_en && (combo_det_q == 1'b0) && (combo_det == 1'b1);
+ assign combo_intr_pulse_o = cfg_intr_en_i && (combo_det_q == 1'b0) && (combo_det_i == 1'b1);
//ec_rst_logic
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: u_ec_rst_l_int
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: u_ec_rst_l_int
+ if (!rst_ni) begin
ec_rst_l_int <= 1'b1;//active low signal
end else begin
ec_rst_l_int <= ec_rst_l_i;
@@ -77,14 +77,14 @@
assign ec_rst_l_det = (ec_rst_l_int == 1'b1) && (ec_rst_l_i == 1'b0);
//combo with EC RST CFG enable
- assign combo_ec_rst_pulse = cfg_ec_rst_en && (combo_det_q == 1'b0) && (combo_det == 1'b1);
+ assign combo_ec_rst_pulse = cfg_ec_rst_en_i && (combo_det_q == 1'b0) && (combo_det_i == 1'b1);
//GSC reset will also reset EC
assign ec_rst_l_d = (combo_ec_rst_pulse | combo_gsc_pulse | ec_rst_l_det) ? 1'b0 :
timer_cnt_clr ? 1'b1 : ec_rst_l_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: u_combo_ec_rst_l
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: u_combo_ec_rst_l
+ if (!rst_ni) begin
ec_rst_l_q <= 1'b0;//asserted when power-on-reset is asserted
end else begin
ec_rst_l_q <= ec_rst_l_d;
@@ -97,8 +97,8 @@
assign timer_cnt_d = (timer_cnt_en) ? timer_cnt_q + 1'b1 : timer_cnt_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: timer_cnt_regs
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: timer_cnt_regs
+ if (!rst_ni) begin
timer_cnt_q <= '0;
end
else if (timer_cnt_clr) begin
@@ -111,12 +111,12 @@
assign ec_rst_l_o = ec_rst_l_q;
//gsc_rst_logic
- assign combo_gsc_pulse = cfg_gsc_rst_en && (combo_det_q == 1'b0) && (combo_det == 1'b1);
+ assign combo_gsc_pulse = cfg_gsc_rst_en_i && (combo_det_q == 1'b0) && (combo_det_i == 1'b1);
assign gsc_rst_d = combo_gsc_pulse ? 1'b1 : gsc_rst_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: u_combo_gsc_rst
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: u_combo_gsc_rst
+ if (!rst_ni) begin
gsc_rst_q <= 1'b0;
end else begin
gsc_rst_q <= gsc_rst_d;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combofsm.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combofsm.sv
index fb7aa16..0aa9d25 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combofsm.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combofsm.sv
@@ -5,38 +5,38 @@
// Description sysrst_ctrl combo detection FSM module
module sysrst_ctrl_combofsm #(
- parameter int unsigned TIMER1BIT = 16,
- parameter int unsigned TIMER2BIT = 32
+ parameter int unsigned Timer1Width = 16,
+ parameter int unsigned Timer2Width = 32
) (
- input clk_aon_i,
- input rst_aon_ni,
- input trigger_h_i,//input vector is all "1"
- input trigger_l_i,//input vector is all "0"
- input [TIMER1BIT-1:0] cfg_timer1_i,//debounce
- input [TIMER2BIT-1:0] cfg_timer2_i,//detection
- input cfg_h2l_en_i,
- output logic timer_h2l_cond_met
+ input clk_i,
+ input rst_ni,
+ input trigger_h_i,//input vector is all "1"
+ input trigger_l_i,//input vector is all "0"
+ input [Timer1Width-1:0] cfg_timer1_i,//debounce
+ input [Timer2Width-1:0] cfg_timer2_i,//detection
+ input cfg_h2l_en_i,
+ output logic timer_h2l_cond_met_o
);
logic trigger_h_q, trigger_l_q;
logic trigger_h2l, trigger_l2h, trigger_l2l;
- logic [TIMER1BIT-1:0] timer1_cnt_d, timer1_cnt_q;
+ logic [Timer1Width-1:0] timer1_cnt_d, timer1_cnt_q;
logic timer1_cnt_clr, timer1_cnt_en;
- logic [TIMER2BIT-1:0] timer2_cnt_d, timer2_cnt_q;
+ logic [Timer2Width-1:0] timer2_cnt_d, timer2_cnt_q;
logic timer2_cnt_clr, timer2_cnt_en;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_trigger_h_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_trigger_h_reg
+ if (!rst_ni) begin
trigger_h_q <= 1'b0;
end else begin
trigger_h_q <= trigger_h_i;
end
end
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_trigger_l_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_trigger_l_reg
+ if (!rst_ni) begin
trigger_l_q <= 1'b0;
end else begin
trigger_l_q <= trigger_l_i;
@@ -65,8 +65,8 @@
timer_state_e timer_state_q, timer_state_d;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_timer_state_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_timer_state_reg
+ if (!rst_ni) begin
timer_state_q <= IDLE;
end else begin
timer_state_q <= timer_state_d;
@@ -76,8 +76,8 @@
assign timer1_cnt_d = (timer1_cnt_en) ? timer1_cnt_q + 1'b1 : timer1_cnt_q;
assign timer2_cnt_d = (timer2_cnt_en) ? timer2_cnt_q + 1'b1 : timer2_cnt_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_timer1_cnt_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_timer1_cnt_reg
+ if (!rst_ni) begin
timer1_cnt_q <= '0;
end
else if (timer1_cnt_clr) begin
@@ -87,8 +87,8 @@
end
end
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_timer2_cnt_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_timer2_cnt_reg
+ if (!rst_ni) begin
timer2_cnt_q <= '0;
end
else if (timer2_cnt_clr) begin
@@ -101,7 +101,7 @@
always_comb begin: p_timer_fsm
timer_state_d = timer_state_q;
//outputs
- timer_h2l_cond_met = 1'b0;
+ timer_h2l_cond_met_o = 1'b0;
timer1_cnt_clr = 1'b0;
timer1_cnt_en = 1'b0;
timer2_cnt_clr = 1'b0;
@@ -144,7 +144,7 @@
DONE: begin
if (trigger_l2l) begin
- timer_h2l_cond_met = 1'b1;
+ timer_h2l_cond_met_o = 1'b1;
end
else if (trigger_l2h) begin
timer_state_d = IDLE;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_intr.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_intr.sv
deleted file mode 100644
index 0307e39..0000000
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_intr.sv
+++ /dev/null
@@ -1,37 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: sysrst_ctrl interrupt Module
-//
-module sysrst_ctrl_intr import sysrst_ctrl_reg_pkg::*; (
- input clk_i,
- input rst_ni,
- input sysrst_ctrl_combo_intr_i,
- input sysrst_ctrl_key_intr_i,
- input sysrst_ctrl_reg2hw_intr_state_reg_t intr_state_i,
- input sysrst_ctrl_reg2hw_intr_enable_reg_t intr_enable_i,
- input sysrst_ctrl_reg2hw_intr_test_reg_t intr_test_i,
- output sysrst_ctrl_hw2reg_intr_state_reg_t intr_state_o,
- output sysrst_ctrl_intr_o
-);
-
- logic sysrst_ctrl_event;
-
- assign sysrst_ctrl_event = sysrst_ctrl_combo_intr_i | sysrst_ctrl_key_intr_i;
-
- // instantiate interrupt hardware primitive
- prim_intr_hw #(.Width(1)) u_sysrst_ctrl_intr_o (
- .clk_i(clk_i),
- .rst_ni(rst_ni),
- .event_intr_i (sysrst_ctrl_event),
- .reg2hw_intr_enable_q_i (intr_enable_i.q),
- .reg2hw_intr_test_q_i (intr_test_i.q),
- .reg2hw_intr_test_qe_i (intr_test_i.qe),
- .reg2hw_intr_state_q_i (intr_state_i.q),
- .hw2reg_intr_state_de_o (intr_state_o.de),
- .hw2reg_intr_state_d_o (intr_state_o.d),
- .intr_o (sysrst_ctrl_intr_o)
- );
-
-endmodule
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_inv.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_inv.sv
deleted file mode 100644
index 62af05f..0000000
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_inv.sv
+++ /dev/null
@@ -1,55 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Description: sysrst_ctrl pin inversion Module
-//
-
-module sysrst_ctrl_inv import sysrst_ctrl_reg_pkg::*; (
- input cio_pwrb_in_i,
- input cio_key0_in_i,
- input cio_key1_in_i,
- input cio_key2_in_i,
- input cio_ac_present_i,
- input cio_lid_open_i,
-
- input pwrb_out_int_i,
- input key0_out_int_i,
- input key1_out_int_i,
- input key2_out_int_i,
- input bat_disable_int_i,
- input z3_wakeup_int_i,
-
- input sysrst_ctrl_reg2hw_key_invert_ctl_reg_t key_invert_ctl_i,
-
- output pwrb_int_o,
- output key0_int_o,
- output key1_int_o,
- output key2_int_o,
- output ac_present_int_o,
- output lid_open_int_o,
-
- output cio_bat_disable_o,
- output cio_pwrb_out_o,
- output cio_key0_out_o,
- output cio_key1_out_o,
- output cio_key2_out_o,
- output cio_z3_wakeup_o
-
-);
-
- assign cio_pwrb_out_o = key_invert_ctl_i.pwrb_out.q ^ pwrb_out_int_i;
- assign cio_key0_out_o = key_invert_ctl_i.key0_out.q ^ key0_out_int_i;
- assign cio_key1_out_o = key_invert_ctl_i.key1_out.q ^ key1_out_int_i;
- assign cio_key2_out_o = key_invert_ctl_i.key2_out.q ^ key2_out_int_i;
- assign cio_bat_disable_o = key_invert_ctl_i.bat_disable.q ^ bat_disable_int_i;
- assign cio_z3_wakeup_o = key_invert_ctl_i.z3_wakeup.q ^ z3_wakeup_int_i;
-
- assign pwrb_int_o = key_invert_ctl_i.pwrb_in.q ^ cio_pwrb_in_i;
- assign key0_int_o = key_invert_ctl_i.key0_in.q ^ cio_key0_in_i;
- assign key1_int_o = key_invert_ctl_i.key1_in.q ^ cio_key1_in_i;
- assign key2_int_o = key_invert_ctl_i.key2_in.q ^ cio_key2_in_i;
- assign ac_present_int_o = key_invert_ctl_i.ac_present.q ^ cio_ac_present_i;
- assign lid_open_int_o = key_invert_ctl_i.lid_open.q ^ cio_lid_open_i;
-
-endmodule
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyfsm.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyfsm.sv
index a21c54e..5955b0d 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyfsm.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyfsm.sv
@@ -7,14 +7,14 @@
module sysrst_ctrl_keyfsm #(
parameter int unsigned TimerWidth = 16
) (
- input clk_aon_i,
- input rst_aon_ni,
+ input clk_i,
+ input rst_ni,
input trigger_i,
input [TimerWidth-1:0] cfg_timer_i,
input cfg_l2h_en_i,
input cfg_h2l_en_i,
- output logic timer_l2h_cond_met,
- output logic timer_h2l_cond_met
+ output logic timer_l2h_cond_met_o,
+ output logic timer_h2l_cond_met_o
);
@@ -25,8 +25,8 @@
logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
logic timer_cnt_clr, timer_cnt_en;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_trigger_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_trigger_reg
+ if (!rst_ni) begin
trigger_q <= 1'b0;
end else begin
trigger_q <= trigger_i;
@@ -58,8 +58,8 @@
timer_state_e timer_state_q, timer_state_d;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_timer_state_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_timer_state_reg
+ if (!rst_ni) begin
timer_state_q <= IDLE;
end else begin
timer_state_q <= timer_state_d;
@@ -68,8 +68,8 @@
assign timer_cnt_d = (timer_cnt_en) ? timer_cnt_q + 1'b1 : timer_cnt_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_timer_cnt_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_timer_cnt_reg
+ if (!rst_ni) begin
timer_cnt_q <= '0;
end
else if (timer_cnt_clr) begin
@@ -82,8 +82,8 @@
always_comb begin: timer_fsm
timer_state_d = timer_state_q;
//outputs
- timer_l2h_cond_met = 1'b0;
- timer_h2l_cond_met = 1'b0;
+ timer_l2h_cond_met_o = 1'b0;
+ timer_h2l_cond_met_o = 1'b0;
timer_cnt_clr = 1'b0;
timer_cnt_en = 1'b0;
@@ -113,7 +113,7 @@
DONEL2H: begin
if (trigger_h2h) begin
- timer_l2h_cond_met = 1'b1;
+ timer_l2h_cond_met_o = 1'b1;
end
else if (!cfg_h2l_en_i && trigger_h2l) begin
timer_state_d = IDLE;
@@ -139,7 +139,7 @@
DONEH2L: begin
if (trigger_l2l) begin
- timer_h2l_cond_met = 1'b1;
+ timer_h2l_cond_met_o = 1'b1;
end
else if (!cfg_l2h_en_i && trigger_l2h) begin
timer_state_d = IDLE;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyintr.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyintr.sv
index e2aae36..9c74d4d 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyintr.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_keyintr.sv
@@ -5,95 +5,31 @@
// Description: sysrst_ctrl key-triggered interrupt Module
//
module sysrst_ctrl_keyintr import sysrst_ctrl_reg_pkg::*; (
- input clk_aon_i,
- input rst_aon_ni,
input clk_i,
input rst_ni,
-
+ // (Optionally) inverted input signals on AON clock
input pwrb_int_i,
input key0_int_i,
input key1_int_i,
input key2_int_i,
input ac_present_int_i,
- input cio_ec_rst_in_l_i,
-
- input sysrst_ctrl_reg2hw_key_intr_ctl_reg_t key_intr_ctl_i,
+ input ec_rst_l_int_i,
+ // CSRs synced to AON clock
+ input sysrst_ctrl_reg2hw_key_intr_ctl_reg_t key_intr_ctl_i,
input sysrst_ctrl_reg2hw_key_intr_debounce_ctl_reg_t key_intr_debounce_ctl_i,
-
- output sysrst_ctrl_hw2reg_key_intr_status_reg_t key_intr_status_o,
+ output sysrst_ctrl_hw2reg_key_intr_status_reg_t key_intr_status_o,
+ // IRQ running on bus clock
output sysrst_ctrl_key_intr_o
-
);
- logic pwrb_int;
- logic key0_int, key1_int, key2_int;
- logic ac_present_int;
- logic ec_rst_l_int;
-
- //synchronize between GPIO and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1)
- ) u_pwrb_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pwrb_int_i),
- .q_o(pwrb_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_key0_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key0_int_i),
- .q_o(key0_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_key1_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key1_int_i),
- .q_o(key1_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_key2_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(key2_int_i),
- .q_o(key2_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_ac_present_int_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(ac_present_int_i),
- .q_o(ac_present_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_ec_rst_l_int (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(cio_ec_rst_in_l_i),
- .q_o(ec_rst_l_int)
- );
-
- localparam int TimerWidth = 16;
localparam int NumKeyIntr = 6;
logic [NumKeyIntr-1:0] triggers, l2h_en, h2l_en;
- assign triggers = {pwrb_int,
- key0_int,
- key1_int,
- key2_int,
- ac_present_int,
- ec_rst_l_int};
+ assign triggers = {pwrb_int_i,
+ key0_int_i,
+ key1_int_i,
+ key2_int_i,
+ ac_present_int_i,
+ ec_rst_l_int_i};
assign l2h_en = {key_intr_ctl_i.pwrb_in_l2h.q,
key_intr_ctl_i.key0_in_l2h.q,
key_intr_ctl_i.key1_in_l2h.q,
@@ -107,27 +43,27 @@
key_intr_ctl_i.ac_present_h2l.q,
key_intr_ctl_i.ec_rst_l_h2l.q};
- logic [NumKeyIntr-1:0] l2h_met_pulse_synced, h2l_met_pulse_synced;
+ logic [NumKeyIntr-1:0] l2h_met_pulse, h2l_met_pulse;
for (genvar k = 0; k < NumKeyIntr; k ++) begin : gen_keyfsm
// Instantiate the key state machine
logic l2h_met_d, h2l_met_d;
sysrst_ctrl_keyfsm # (
.TimerWidth(TimerWidth)
) u_pwrbintr_fsm (
- .clk_aon_i,
- .rst_aon_ni,
+ .clk_i,
+ .rst_ni,
.trigger_i(triggers[k]),
.cfg_timer_i(key_intr_debounce_ctl_i.q),
.cfg_l2h_en_i(l2h_en[k]),
.cfg_h2l_en_i(h2l_en[k]),
- .timer_l2h_cond_met(l2h_met_d),
- .timer_h2l_cond_met(h2l_met_d)
+ .timer_l2h_cond_met_o(l2h_met_d),
+ .timer_h2l_cond_met_o(h2l_met_d)
);
// generate a pulses for interrupt status CSR
logic l2h_met_q, h2l_met_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin : p_pulse_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin : p_pulse_reg
+ if (!rst_ni) begin
l2h_met_q <= '0;
h2l_met_q <= '0;
end else begin
@@ -136,26 +72,8 @@
end
end
- logic l2h_met_pulse, h2l_met_pulse;
- assign l2h_met_pulse = l2h_met_d & ~l2h_met_q;
- assign h2l_met_pulse = ~h2l_met_d & h2l_met_q;
-
- prim_pulse_sync u_prim_pulse_sync_l2h (
- .clk_src_i (clk_aon_i),
- .rst_src_ni (rst_aon_ni),
- .src_pulse_i(l2h_met_pulse),
- .clk_dst_i (clk_i),
- .rst_dst_ni (rst_ni),
- .dst_pulse_o(l2h_met_pulse_synced[k])
- );
- prim_pulse_sync u_prim_pulse_sync_h2l (
- .clk_src_i (clk_aon_i),
- .rst_src_ni (rst_aon_ni),
- .src_pulse_i(h2l_met_pulse),
- .clk_dst_i (clk_i),
- .rst_dst_ni (rst_ni),
- .dst_pulse_o(h2l_met_pulse_synced[k])
- );
+ assign l2h_met_pulse[k] = l2h_met_d & ~l2h_met_q;
+ assign h2l_met_pulse[k] = ~h2l_met_d & h2l_met_q;
end
// Assign to CSRs
@@ -164,18 +82,18 @@
key_intr_status_o.key1_in_l2h.de,
key_intr_status_o.key2_in_l2h.de,
key_intr_status_o.ac_present_l2h.de,
- key_intr_status_o.ec_rst_l_l2h.de} = l2h_met_pulse_synced;
+ key_intr_status_o.ec_rst_l_l2h.de} = l2h_met_pulse;
assign {key_intr_status_o.pwrb_h2l.de,
key_intr_status_o.key0_in_h2l.de,
key_intr_status_o.key1_in_h2l.de,
key_intr_status_o.key2_in_h2l.de,
key_intr_status_o.ac_present_h2l.de,
- key_intr_status_o.ec_rst_l_h2l.de} = h2l_met_pulse_synced;
+ key_intr_status_o.ec_rst_l_h2l.de} = h2l_met_pulse;
// Send out aggregated interrupt pulse
- assign sysrst_ctrl_key_intr_o = |l2h_met_pulse_synced |
- |h2l_met_pulse_synced;
+ assign sysrst_ctrl_key_intr_o = |l2h_met_pulse |
+ |h2l_met_pulse;
// To write into interrupt status register
assign key_intr_status_o.pwrb_h2l.d = 1'b1;
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_pin.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_pin.sv
index 2a893a7..9dcd2f3 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_pin.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_pin.sv
@@ -8,7 +8,7 @@
module sysrst_ctrl_pin import sysrst_ctrl_reg_pkg::*; (
input clk_i,
input rst_ni,
-
+ // Raw input signals (not synced to AON clock)
input cio_pwrb_in_i,
input cio_key0_in_i,
input cio_key1_in_i,
@@ -16,28 +16,30 @@
input cio_ac_present_i,
input cio_ec_rst_in_l_i,
input cio_lid_open_i,
-
+ // Signals from autoblock (not synced to AON clock)
input pwrb_out_hw_i,
input key0_out_hw_i,
input key1_out_hw_i,
input key2_out_hw_i,
- input bat_disable_hw_i,
- input ec_rst_l_hw_i,
- input z3_wakeup_hw_i,
-
- input sysrst_ctrl_reg2hw_pin_allowed_ctl_reg_t pin_allowed_ctl_i,
- input sysrst_ctrl_reg2hw_pin_out_ctl_reg_t pin_out_ctl_i,
- input sysrst_ctrl_reg2hw_pin_out_value_reg_t pin_out_value_i,
-
+ // Generated signals, running on AON clock
+ input aon_bat_disable_hw_i,
+ input aon_ec_rst_l_hw_i,
+ input aon_z3_wakeup_hw_i,
+ // CSRs synced to AON clock
+ input sysrst_ctrl_reg2hw_pin_allowed_ctl_reg_t aon_pin_allowed_ctl_i,
+ input sysrst_ctrl_reg2hw_pin_out_ctl_reg_t aon_pin_out_ctl_i,
+ input sysrst_ctrl_reg2hw_pin_out_value_reg_t aon_pin_out_value_i,
+ // CSRs synced to bus clock
output sysrst_ctrl_hw2reg_pin_in_value_reg_t pin_in_value_o,
-
+ // Output signals (not synced to AON clock)
output pwrb_out_int_o,
output key0_out_int_o,
output key1_out_int_o,
output key2_out_int_o,
- output bat_disable_int_o,
- output z3_wakeup_int_o,
- output cio_ec_rst_out_l_o
+ // Output signals running on AON clock
+ output aon_bat_disable_out_int_o,
+ output aon_z3_wakeup_out_int_o,
+ output aon_ec_rst_out_int_l_o
);
@@ -74,54 +76,54 @@
// Pin override logic.
localparam int NumSignals = 7;
- logic [NumSignals-1:0] inputs, outputs, enabled, values, allowed0, allowed1;
+ logic [NumSignals-1:0] inputs, outputs, aon_enabled, aon_values, aon_allowed0, aon_allowed1;
assign inputs = {pwrb_out_hw_i,
key0_out_hw_i,
key1_out_hw_i,
key2_out_hw_i,
- z3_wakeup_hw_i,
- bat_disable_hw_i,
- ec_rst_l_hw_i};
- assign enabled = {pin_out_ctl_i.pwrb_out.q,
- pin_out_ctl_i.key0_out.q,
- pin_out_ctl_i.key1_out.q,
- pin_out_ctl_i.key2_out.q,
- pin_out_ctl_i.z3_wakeup.q,
- pin_out_ctl_i.bat_disable.q,
- pin_out_ctl_i.ec_rst_l.q};
- assign values = {pin_out_value_i.pwrb_out.q,
- pin_out_value_i.key0_out.q,
- pin_out_value_i.key1_out.q,
- pin_out_value_i.key2_out.q,
- pin_out_value_i.z3_wakeup.q,
- pin_out_value_i.bat_disable.q,
- pin_out_value_i.ec_rst_l.q};
- assign allowed0 = {pin_allowed_ctl_i.pwrb_out_0.q,
- pin_allowed_ctl_i.key0_out_0.q,
- pin_allowed_ctl_i.key1_out_0.q,
- pin_allowed_ctl_i.key2_out_0.q,
- pin_allowed_ctl_i.z3_wakeup_0.q,
- pin_allowed_ctl_i.bat_disable_0.q,
- pin_allowed_ctl_i.ec_rst_l_0.q};
- assign allowed1 = {pin_allowed_ctl_i.pwrb_out_1.q,
- pin_allowed_ctl_i.key0_out_1.q,
- pin_allowed_ctl_i.key1_out_1.q,
- pin_allowed_ctl_i.key2_out_1.q,
- pin_allowed_ctl_i.z3_wakeup_1.q,
- pin_allowed_ctl_i.bat_disable_1.q,
- pin_allowed_ctl_i.ec_rst_l_1.q};
+ aon_z3_wakeup_hw_i,
+ aon_bat_disable_hw_i,
+ aon_ec_rst_l_hw_i};
+ assign aon_enabled = {aon_pin_out_ctl_i.pwrb_out.q,
+ aon_pin_out_ctl_i.key0_out.q,
+ aon_pin_out_ctl_i.key1_out.q,
+ aon_pin_out_ctl_i.key2_out.q,
+ aon_pin_out_ctl_i.z3_wakeup.q,
+ aon_pin_out_ctl_i.bat_disable.q,
+ aon_pin_out_ctl_i.ec_rst_l.q};
+ assign aon_values = {aon_pin_out_value_i.pwrb_out.q,
+ aon_pin_out_value_i.key0_out.q,
+ aon_pin_out_value_i.key1_out.q,
+ aon_pin_out_value_i.key2_out.q,
+ aon_pin_out_value_i.z3_wakeup.q,
+ aon_pin_out_value_i.bat_disable.q,
+ aon_pin_out_value_i.ec_rst_l.q};
+ assign aon_allowed0 = {aon_pin_allowed_ctl_i.pwrb_out_0.q,
+ aon_pin_allowed_ctl_i.key0_out_0.q,
+ aon_pin_allowed_ctl_i.key1_out_0.q,
+ aon_pin_allowed_ctl_i.key2_out_0.q,
+ aon_pin_allowed_ctl_i.z3_wakeup_0.q,
+ aon_pin_allowed_ctl_i.bat_disable_0.q,
+ aon_pin_allowed_ctl_i.ec_rst_l_0.q};
+ assign aon_allowed1 = {aon_pin_allowed_ctl_i.pwrb_out_1.q,
+ aon_pin_allowed_ctl_i.key0_out_1.q,
+ aon_pin_allowed_ctl_i.key1_out_1.q,
+ aon_pin_allowed_ctl_i.key2_out_1.q,
+ aon_pin_allowed_ctl_i.z3_wakeup_1.q,
+ aon_pin_allowed_ctl_i.bat_disable_1.q,
+ aon_pin_allowed_ctl_i.ec_rst_l_1.q};
for (genvar k = 0; k < NumSignals; k++) begin : gen_override_logic
- assign outputs[k] = (enabled[k] && allowed0[k] && !values[k]) ? 1'b0 :
- (enabled[k] && allowed1[k] && values[k]) ? 1'b1 : inputs[k];
+ assign outputs[k] = (aon_enabled[k] && aon_allowed0[k] && !aon_values[k]) ? 1'b0 :
+ (aon_enabled[k] && aon_allowed1[k] && aon_values[k]) ? 1'b1 : inputs[k];
end
assign {pwrb_out_int_o,
key0_out_int_o,
key1_out_int_o,
key2_out_int_o,
- z3_wakeup_int_o,
- bat_disable_int_o,
- cio_ec_rst_out_l_o} = outputs;
+ aon_z3_wakeup_out_int_o,
+ aon_bat_disable_out_int_o,
+ aon_ec_rst_out_int_l_o} = outputs;
endmodule
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_pkg.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_pkg.sv
index 7d57efa..b972689 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_pkg.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_pkg.sv
@@ -9,6 +9,7 @@
// Param list
parameter int NumCombo = 4;
parameter int TimerWidth = 16;
+ parameter int DetTimerWidth = 32;
parameter int NumAlerts = 1;
// Address widths within the block
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv
index e6d402f..d88c4d2 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv
@@ -160,6 +160,7 @@
logic wk_status_we;
logic wk_status_qs;
logic wk_status_wd;
+ logic wk_status_busy;
logic key_invert_ctl_we;
logic key_invert_ctl_key0_in_qs;
logic key_invert_ctl_key0_in_wd;
@@ -493,37 +494,53 @@
logic combo_intr_status_we;
logic combo_intr_status_combo0_h2l_qs;
logic combo_intr_status_combo0_h2l_wd;
+ logic combo_intr_status_combo0_h2l_busy;
logic combo_intr_status_combo1_h2l_qs;
logic combo_intr_status_combo1_h2l_wd;
+ logic combo_intr_status_combo1_h2l_busy;
logic combo_intr_status_combo2_h2l_qs;
logic combo_intr_status_combo2_h2l_wd;
+ logic combo_intr_status_combo2_h2l_busy;
logic combo_intr_status_combo3_h2l_qs;
logic combo_intr_status_combo3_h2l_wd;
+ logic combo_intr_status_combo3_h2l_busy;
logic key_intr_status_we;
logic key_intr_status_pwrb_h2l_qs;
logic key_intr_status_pwrb_h2l_wd;
+ logic key_intr_status_pwrb_h2l_busy;
logic key_intr_status_key0_in_h2l_qs;
logic key_intr_status_key0_in_h2l_wd;
+ logic key_intr_status_key0_in_h2l_busy;
logic key_intr_status_key1_in_h2l_qs;
logic key_intr_status_key1_in_h2l_wd;
+ logic key_intr_status_key1_in_h2l_busy;
logic key_intr_status_key2_in_h2l_qs;
logic key_intr_status_key2_in_h2l_wd;
+ logic key_intr_status_key2_in_h2l_busy;
logic key_intr_status_ac_present_h2l_qs;
logic key_intr_status_ac_present_h2l_wd;
+ logic key_intr_status_ac_present_h2l_busy;
logic key_intr_status_ec_rst_l_h2l_qs;
logic key_intr_status_ec_rst_l_h2l_wd;
+ logic key_intr_status_ec_rst_l_h2l_busy;
logic key_intr_status_pwrb_l2h_qs;
logic key_intr_status_pwrb_l2h_wd;
+ logic key_intr_status_pwrb_l2h_busy;
logic key_intr_status_key0_in_l2h_qs;
logic key_intr_status_key0_in_l2h_wd;
+ logic key_intr_status_key0_in_l2h_busy;
logic key_intr_status_key1_in_l2h_qs;
logic key_intr_status_key1_in_l2h_wd;
+ logic key_intr_status_key1_in_l2h_busy;
logic key_intr_status_key2_in_l2h_qs;
logic key_intr_status_key2_in_l2h_wd;
+ logic key_intr_status_key2_in_l2h_busy;
logic key_intr_status_ac_present_l2h_qs;
logic key_intr_status_ac_present_l2h_wd;
+ logic key_intr_status_ac_present_l2h_busy;
logic key_intr_status_ec_rst_l_l2h_qs;
logic key_intr_status_ec_rst_l_l2h_wd;
+ logic key_intr_status_ec_rst_l_l2h_busy;
// Register instances
// R[intr_state]: V(False)
@@ -779,28 +796,24 @@
// R[wk_status]: V(False)
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_wk_status (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (wk_status_we),
- .wd (wk_status_wd),
-
- // from internal hardware
- .de (hw2reg.wk_status.de),
- .d (hw2reg.wk_status.d),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.wk_status.q),
-
- // to register interface (read)
- .qs (wk_status_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (wk_status_we),
+ .src_wd_i (wk_status_wd),
+ .dst_de_i (hw2reg.wk_status.de),
+ .dst_d_i (hw2reg.wk_status.d),
+ .src_busy_o (wk_status_busy),
+ .src_qs_o (wk_status_qs),
+ .dst_qe_o (),
+ .q (reg2hw.wk_status.q)
);
@@ -3262,420 +3275,356 @@
// R[combo_intr_status]: V(False)
// F[combo0_h2l]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_combo_intr_status_combo0_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (combo_intr_status_we),
- .wd (combo_intr_status_combo0_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.combo_intr_status.combo0_h2l.de),
- .d (hw2reg.combo_intr_status.combo0_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (combo_intr_status_combo0_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (combo_intr_status_we),
+ .src_wd_i (combo_intr_status_combo0_h2l_wd),
+ .dst_de_i (hw2reg.combo_intr_status.combo0_h2l.de),
+ .dst_d_i (hw2reg.combo_intr_status.combo0_h2l.d),
+ .src_busy_o (combo_intr_status_combo0_h2l_busy),
+ .src_qs_o (combo_intr_status_combo0_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[combo1_h2l]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_combo_intr_status_combo1_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (combo_intr_status_we),
- .wd (combo_intr_status_combo1_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.combo_intr_status.combo1_h2l.de),
- .d (hw2reg.combo_intr_status.combo1_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (combo_intr_status_combo1_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (combo_intr_status_we),
+ .src_wd_i (combo_intr_status_combo1_h2l_wd),
+ .dst_de_i (hw2reg.combo_intr_status.combo1_h2l.de),
+ .dst_d_i (hw2reg.combo_intr_status.combo1_h2l.d),
+ .src_busy_o (combo_intr_status_combo1_h2l_busy),
+ .src_qs_o (combo_intr_status_combo1_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[combo2_h2l]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_combo_intr_status_combo2_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (combo_intr_status_we),
- .wd (combo_intr_status_combo2_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.combo_intr_status.combo2_h2l.de),
- .d (hw2reg.combo_intr_status.combo2_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (combo_intr_status_combo2_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (combo_intr_status_we),
+ .src_wd_i (combo_intr_status_combo2_h2l_wd),
+ .dst_de_i (hw2reg.combo_intr_status.combo2_h2l.de),
+ .dst_d_i (hw2reg.combo_intr_status.combo2_h2l.d),
+ .src_busy_o (combo_intr_status_combo2_h2l_busy),
+ .src_qs_o (combo_intr_status_combo2_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[combo3_h2l]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_combo_intr_status_combo3_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (combo_intr_status_we),
- .wd (combo_intr_status_combo3_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.combo_intr_status.combo3_h2l.de),
- .d (hw2reg.combo_intr_status.combo3_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (combo_intr_status_combo3_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (combo_intr_status_we),
+ .src_wd_i (combo_intr_status_combo3_h2l_wd),
+ .dst_de_i (hw2reg.combo_intr_status.combo3_h2l.de),
+ .dst_d_i (hw2reg.combo_intr_status.combo3_h2l.d),
+ .src_busy_o (combo_intr_status_combo3_h2l_busy),
+ .src_qs_o (combo_intr_status_combo3_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// R[key_intr_status]: V(False)
// F[pwrb_h2l]: 0:0
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_pwrb_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_pwrb_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.pwrb_h2l.de),
- .d (hw2reg.key_intr_status.pwrb_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_pwrb_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_pwrb_h2l_wd),
+ .dst_de_i (hw2reg.key_intr_status.pwrb_h2l.de),
+ .dst_d_i (hw2reg.key_intr_status.pwrb_h2l.d),
+ .src_busy_o (key_intr_status_pwrb_h2l_busy),
+ .src_qs_o (key_intr_status_pwrb_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[key0_in_h2l]: 1:1
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_key0_in_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_key0_in_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.key0_in_h2l.de),
- .d (hw2reg.key_intr_status.key0_in_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_key0_in_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_key0_in_h2l_wd),
+ .dst_de_i (hw2reg.key_intr_status.key0_in_h2l.de),
+ .dst_d_i (hw2reg.key_intr_status.key0_in_h2l.d),
+ .src_busy_o (key_intr_status_key0_in_h2l_busy),
+ .src_qs_o (key_intr_status_key0_in_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[key1_in_h2l]: 2:2
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_key1_in_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_key1_in_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.key1_in_h2l.de),
- .d (hw2reg.key_intr_status.key1_in_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_key1_in_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_key1_in_h2l_wd),
+ .dst_de_i (hw2reg.key_intr_status.key1_in_h2l.de),
+ .dst_d_i (hw2reg.key_intr_status.key1_in_h2l.d),
+ .src_busy_o (key_intr_status_key1_in_h2l_busy),
+ .src_qs_o (key_intr_status_key1_in_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[key2_in_h2l]: 3:3
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_key2_in_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_key2_in_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.key2_in_h2l.de),
- .d (hw2reg.key_intr_status.key2_in_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_key2_in_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_key2_in_h2l_wd),
+ .dst_de_i (hw2reg.key_intr_status.key2_in_h2l.de),
+ .dst_d_i (hw2reg.key_intr_status.key2_in_h2l.d),
+ .src_busy_o (key_intr_status_key2_in_h2l_busy),
+ .src_qs_o (key_intr_status_key2_in_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[ac_present_h2l]: 4:4
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_ac_present_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_ac_present_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.ac_present_h2l.de),
- .d (hw2reg.key_intr_status.ac_present_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_ac_present_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_ac_present_h2l_wd),
+ .dst_de_i (hw2reg.key_intr_status.ac_present_h2l.de),
+ .dst_d_i (hw2reg.key_intr_status.ac_present_h2l.d),
+ .src_busy_o (key_intr_status_ac_present_h2l_busy),
+ .src_qs_o (key_intr_status_ac_present_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[ec_rst_l_h2l]: 5:5
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_ec_rst_l_h2l (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_ec_rst_l_h2l_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.ec_rst_l_h2l.de),
- .d (hw2reg.key_intr_status.ec_rst_l_h2l.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_ec_rst_l_h2l_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_ec_rst_l_h2l_wd),
+ .dst_de_i (hw2reg.key_intr_status.ec_rst_l_h2l.de),
+ .dst_d_i (hw2reg.key_intr_status.ec_rst_l_h2l.d),
+ .src_busy_o (key_intr_status_ec_rst_l_h2l_busy),
+ .src_qs_o (key_intr_status_ec_rst_l_h2l_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[pwrb_l2h]: 6:6
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_pwrb_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_pwrb_l2h_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.pwrb_l2h.de),
- .d (hw2reg.key_intr_status.pwrb_l2h.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_pwrb_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_pwrb_l2h_wd),
+ .dst_de_i (hw2reg.key_intr_status.pwrb_l2h.de),
+ .dst_d_i (hw2reg.key_intr_status.pwrb_l2h.d),
+ .src_busy_o (key_intr_status_pwrb_l2h_busy),
+ .src_qs_o (key_intr_status_pwrb_l2h_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[key0_in_l2h]: 7:7
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_key0_in_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_key0_in_l2h_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.key0_in_l2h.de),
- .d (hw2reg.key_intr_status.key0_in_l2h.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_key0_in_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_key0_in_l2h_wd),
+ .dst_de_i (hw2reg.key_intr_status.key0_in_l2h.de),
+ .dst_d_i (hw2reg.key_intr_status.key0_in_l2h.d),
+ .src_busy_o (key_intr_status_key0_in_l2h_busy),
+ .src_qs_o (key_intr_status_key0_in_l2h_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[key1_in_l2h]: 8:8
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_key1_in_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_key1_in_l2h_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.key1_in_l2h.de),
- .d (hw2reg.key_intr_status.key1_in_l2h.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_key1_in_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_key1_in_l2h_wd),
+ .dst_de_i (hw2reg.key_intr_status.key1_in_l2h.de),
+ .dst_d_i (hw2reg.key_intr_status.key1_in_l2h.d),
+ .src_busy_o (key_intr_status_key1_in_l2h_busy),
+ .src_qs_o (key_intr_status_key1_in_l2h_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[key2_in_l2h]: 9:9
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_key2_in_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_key2_in_l2h_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.key2_in_l2h.de),
- .d (hw2reg.key_intr_status.key2_in_l2h.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_key2_in_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_key2_in_l2h_wd),
+ .dst_de_i (hw2reg.key_intr_status.key2_in_l2h.de),
+ .dst_d_i (hw2reg.key_intr_status.key2_in_l2h.d),
+ .src_busy_o (key_intr_status_key2_in_l2h_busy),
+ .src_qs_o (key_intr_status_key2_in_l2h_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[ac_present_l2h]: 10:10
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_ac_present_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_ac_present_l2h_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.ac_present_l2h.de),
- .d (hw2reg.key_intr_status.ac_present_l2h.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_ac_present_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_ac_present_l2h_wd),
+ .dst_de_i (hw2reg.key_intr_status.ac_present_l2h.de),
+ .dst_d_i (hw2reg.key_intr_status.ac_present_l2h.d),
+ .src_busy_o (key_intr_status_ac_present_l2h_busy),
+ .src_qs_o (key_intr_status_ac_present_l2h_qs),
+ .dst_qe_o (),
+ .q ()
);
// F[ec_rst_l_l2h]: 11:11
- prim_subreg #(
+ prim_subreg_async #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessW1C),
.RESVAL (1'h0)
) u_key_intr_status_ec_rst_l_l2h (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (key_intr_status_we),
- .wd (key_intr_status_ec_rst_l_l2h_wd),
-
- // from internal hardware
- .de (hw2reg.key_intr_status.ec_rst_l_l2h.de),
- .d (hw2reg.key_intr_status.ec_rst_l_l2h.d),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (key_intr_status_ec_rst_l_l2h_qs)
+ .clk_src_i (clk_i),
+ .rst_src_ni (rst_ni),
+ .clk_dst_i (clk_aon_i),
+ .rst_dst_ni (rst_aon_ni),
+ .src_update_i (sync_aon_update),
+ .src_we_i (key_intr_status_we),
+ .src_wd_i (key_intr_status_ec_rst_l_l2h_wd),
+ .dst_de_i (hw2reg.key_intr_status.ec_rst_l_l2h.de),
+ .dst_d_i (hw2reg.key_intr_status.ec_rst_l_l2h.d),
+ .src_busy_o (key_intr_status_ec_rst_l_l2h_busy),
+ .src_qs_o (key_intr_status_ec_rst_l_l2h_qs),
+ .dst_qe_o (),
+ .q ()
);
@@ -4328,6 +4277,9 @@
addr_hit[10]: begin
reg_busy = ulp_status_busy;
end
+ addr_hit[11]: begin
+ reg_busy = wk_status_busy;
+ end
addr_hit[12]: begin
reg_busy =
key_invert_ctl_key0_in_busy |
@@ -4484,6 +4436,28 @@
com_out_ctl_3_ec_rst_3_busy |
com_out_ctl_3_gsc_rst_3_busy;
end
+ addr_hit[33]: begin
+ reg_busy =
+ combo_intr_status_combo0_h2l_busy |
+ combo_intr_status_combo1_h2l_busy |
+ combo_intr_status_combo2_h2l_busy |
+ combo_intr_status_combo3_h2l_busy;
+ end
+ addr_hit[34]: begin
+ reg_busy =
+ key_intr_status_pwrb_h2l_busy |
+ key_intr_status_key0_in_h2l_busy |
+ key_intr_status_key1_in_h2l_busy |
+ key_intr_status_key2_in_h2l_busy |
+ key_intr_status_ac_present_h2l_busy |
+ key_intr_status_ec_rst_l_h2l_busy |
+ key_intr_status_pwrb_l2h_busy |
+ key_intr_status_key0_in_l2h_busy |
+ key_intr_status_key1_in_l2h_busy |
+ key_intr_status_key2_in_l2h_busy |
+ key_intr_status_ac_present_l2h_busy |
+ key_intr_status_ec_rst_l_l2h_busy;
+ end
default: begin
reg_busy = '0;
end
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_timerfsm.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_timerfsm.sv
index 5248587..d18c0cb 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_timerfsm.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_timerfsm.sv
@@ -5,12 +5,12 @@
// Description sysrst_ctrl timer-based FSM module
module sysrst_ctrl_timerfsm #(
- parameter int unsigned TIMERBIT = 16
+ parameter int unsigned TimerWidth = 16
) (
- input clk_aon_i,
- input rst_aon_ni,
+ input clk_i,
+ input rst_ni,
input trigger_i,
- input [TIMERBIT-1:0] cfg_timer_i,
+ input [TimerWidth-1:0] cfg_timer_i,
input cfg_l2h_en_i,
input cfg_h2l_en_i,
output logic timer_l2h_cond_met,
@@ -22,11 +22,11 @@
logic trigger_h2l, trigger_l2h, trigger_h2h, trigger_l2l;
//logic trigger_tgl, trigger_sty;
- logic [TIMERBIT-1:0] timer_cnt_d, timer_cnt_q;
+ logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
logic timer_cnt_clr, timer_cnt_en;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_trigger_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_trigger_reg
+ if (!rst_ni) begin
trigger_q <= 1'b0;
end else begin
trigger_q <= trigger_i;
@@ -56,8 +56,8 @@
timer_state_e timer_state_q, timer_state_d;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_timer_state_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_timer_state_reg
+ if (!rst_ni) begin
timer_state_q <= IDLE;
end else begin
timer_state_q <= timer_state_d;
@@ -66,8 +66,8 @@
assign timer_cnt_d = (timer_cnt_en) ? timer_cnt_q + 1'b1 : timer_cnt_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_timer_cnt_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_timer_cnt_reg
+ if (!rst_ni) begin
timer_cnt_q <= '0;
end
else if (timer_cnt_clr) begin
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulp.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulp.sv
index 0f3e4d7..c04f2a9 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulp.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulp.sv
@@ -5,98 +5,67 @@
// Description sysrst_ctrl ULP module
module sysrst_ctrl_ulp import sysrst_ctrl_reg_pkg::*; (
- input clk_aon_i,
- input rst_aon_ni,
-
+ input clk_i,
+ input rst_ni,
+ // (Optionally) inverted input signals on AON clock
input lid_open_int_i,
input ac_present_int_i,
input pwrb_int_i,
-
+ // CSRs synced to AON clock
input sysrst_ctrl_reg2hw_ulp_ac_debounce_ctl_reg_t ulp_ac_debounce_ctl_i,
input sysrst_ctrl_reg2hw_ulp_lid_debounce_ctl_reg_t ulp_lid_debounce_ctl_i,
input sysrst_ctrl_reg2hw_ulp_pwrb_debounce_ctl_reg_t ulp_pwrb_debounce_ctl_i,
input sysrst_ctrl_reg2hw_ulp_ctl_reg_t ulp_ctl_i,
-
output sysrst_ctrl_hw2reg_ulp_status_reg_t ulp_status_o,
+ // Wakeup pulses on AON clock
output ulp_wakeup_pulse_o,
output z3_wakeup_hw_o
);
- logic pwrb_int;
- logic lid_open_int;
- logic ac_present_int;
-
- //synchronize between GPIO and always-on(200KHz)
- prim_flop_2sync # (
- .Width(1)
- ) u_pwrb_in_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(pwrb_int_i),
- .q_o(pwrb_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_lid_open_in_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(lid_open_int_i),
- .q_o(lid_open_int)
- );
-
- prim_flop_2sync # (
- .Width(1)
- ) u_ac_present_in_i (
- .clk_i(clk_aon_i),
- .rst_ni(rst_aon_ni),
- .d_i(ac_present_int_i),
- .q_o(ac_present_int)
- );
+ logic pwrb_cond_met_d, pwrb_cond_met_q;
+ logic lid_open_cond_met_d, lid_open_cond_met_q;
+ logic ac_present_cond_met_d, ac_present_cond_met_q;
sysrst_ctrl_ulpfsm # (
- .EDGE_TYPE("HL"),
- .TIMERBIT(16)
+ .EdgeType("HL"),
+ .TimerWidth(TimerWidth)
) u_pwrb_ulpfsm (
- .clk_aon_i,
- .rst_aon_ni,
- .trigger_i(pwrb_int),
+ .clk_i,
+ .rst_ni,
+ .trigger_i(pwrb_int_i),
.cfg_timer_i(ulp_pwrb_debounce_ctl_i.q),
.cfg_en_i(ulp_ctl_i.q),
.timer_cond_met_o(pwrb_cond_met_d)
);
sysrst_ctrl_ulpfsm # (
- .EDGE_TYPE("LH"),
- .TIMERBIT(16)
+ .EdgeType("LH"),
+ .TimerWidth(TimerWidth)
) u_lid_open_ulpfsm (
- .clk_aon_i,
- .rst_aon_ni,
- .trigger_i(lid_open_int),
+ .clk_i,
+ .rst_ni,
+ .trigger_i(lid_open_int_i),
.cfg_timer_i(ulp_lid_debounce_ctl_i.q),
.cfg_en_i(ulp_ctl_i.q),
.timer_cond_met_o(lid_open_cond_met_d)
);
sysrst_ctrl_ulpfsm # (
- .EDGE_TYPE("H"),
- .TIMERBIT(16)
+ .EdgeType("H"),
+ .TimerWidth(TimerWidth)
) u_ac_present_ulpfsm (
- .clk_aon_i,
- .rst_aon_ni,
- .trigger_i(ac_present_int),
+ .clk_i,
+ .rst_ni,
+ .trigger_i(ac_present_int_i),
.cfg_timer_i(ulp_ac_debounce_ctl_i.q),
.cfg_en_i(ulp_ctl_i.q),
.timer_cond_met_o(ac_present_cond_met_d)
);
- //delay the level signal to generate a pulse
- logic pwrb_cond_met_d, pwrb_cond_met_q;
- logic lid_open_cond_met_d, lid_open_cond_met_q;
- logic ac_present_cond_met_d, ac_present_cond_met_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_ulp_cond_met
- if (!rst_aon_ni) begin
+ // delay the level signal to generate a pulse
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_ulp_cond_met
+ if (!rst_ni) begin
pwrb_cond_met_q <= 1'b0;
lid_open_cond_met_q <= 1'b0;
ac_present_cond_met_q <= 1'b0;
@@ -115,15 +84,15 @@
assign ac_present_det_pulse = ac_present_cond_met_d & ~ac_present_cond_met_q;
// aggregate pulses
- assign ulp_wakeup_pulse_o = ulp_ctl_i.q & (pwrb_det_pulse |
+ assign ulp_wakeup_pulse_o = ulp_ctl_i.q & (pwrb_det_pulse |
lid_open_det_pulse |
ac_present_det_pulse);
- assign z3_wakeup_hw_o = pwrb_cond_met_d |
+ assign z3_wakeup_hw_o = pwrb_cond_met_d |
lid_open_cond_met_d |
ac_present_cond_met_d;
- assign ulp_status_o.d = 1'b1;
+ assign ulp_status_o.d = 1'b1;
assign ulp_status_o.de = ulp_wakeup_pulse_o;
endmodule
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulpfsm.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulpfsm.sv
index fc4bece..0580400 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulpfsm.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_ulpfsm.sv
@@ -5,26 +5,25 @@
// Description sysrst_ctrl ULP FSM module
module sysrst_ctrl_ulpfsm #(
- parameter bit [15:0] EDGE_TYPE = "H", // can be LH, HL and H
- parameter int unsigned TIMERBIT = 16
- ) (
- input clk_aon_i,
- input rst_aon_ni,
- input trigger_i,
- input [TIMERBIT-1:0] cfg_timer_i,
- input cfg_en_i,
- output logic timer_cond_met_o
-
+ parameter bit [15:0] EdgeType = "H", // can be LH, HL and H
+ parameter int unsigned TimerWidth = 16
+) (
+ input clk_i,
+ input rst_ni,
+ input trigger_i,
+ input [TimerWidth-1:0] cfg_timer_i,
+ input cfg_en_i,
+ output logic timer_cond_met_o
);
logic trigger_q;
logic trigger, trigger_stable;
- logic [TIMERBIT-1:0] timer_cnt_d, timer_cnt_q;
+ logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q;
logic timer_cnt_clr, timer_cnt_en;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_trigger_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_trigger_reg
+ if (!rst_ni) begin
trigger_q <= 1'b0;
end
else if (!cfg_en_i) begin
@@ -34,10 +33,10 @@
end
end
- if (EDGE_TYPE == "LH") begin : gen_trigger_l2h
+ if (EdgeType == "LH") begin : gen_trigger_l2h
assign trigger = (trigger_q == 1'b0) && (trigger_i == 1'b1);
assign trigger_stable = (trigger_q == trigger_i) && (trigger_i == 1'b1);
- end else if (EDGE_TYPE == "HL") begin : gen_trigger_h2l
+ end else if (EdgeType == "HL") begin : gen_trigger_h2l
assign trigger = (trigger_q == 1'b1) && (trigger_i == 1'b0);
assign trigger_stable = (trigger_q == trigger_i) && (trigger_i == 1'b0);
end else begin: gen_trigger_h
@@ -60,8 +59,8 @@
timer_state_e timer_state_q, timer_state_d;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_timer_state_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_timer_state_reg
+ if (!rst_ni) begin
timer_state_q <= IDLE_ST;
end
else begin
@@ -71,8 +70,8 @@
assign timer_cnt_d = (timer_cnt_en) ? timer_cnt_q + 1'b1 : timer_cnt_q;
- always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin: p_timer_cnt_reg
- if (!rst_aon_ni) begin
+ always_ff @(posedge clk_i or negedge rst_ni) begin: p_timer_cnt_reg
+ if (!rst_ni) begin
timer_cnt_q <= '0;
end
else if (timer_cnt_clr ) begin
diff --git a/hw/ip/sysrst_ctrl/sysrst_ctrl.core b/hw/ip/sysrst_ctrl/sysrst_ctrl.core
index b295b92..9fdcf2a 100644
--- a/hw/ip/sysrst_ctrl/sysrst_ctrl.core
+++ b/hw/ip/sysrst_ctrl/sysrst_ctrl.core
@@ -16,8 +16,6 @@
- rtl/sysrst_ctrl_autoblock.sv
- rtl/sysrst_ctrl_comboact.sv
- rtl/sysrst_ctrl_combotrg.sv
- - rtl/sysrst_ctrl_intr.sv
- - rtl/sysrst_ctrl_inv.sv
- rtl/sysrst_ctrl_pin.sv
- rtl/sysrst_ctrl_keyintr.sv
- rtl/sysrst_ctrl_timerfsm.sv
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 46b3a95..544d1ba 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -2709,7 +2709,7 @@
inter_signal_list:
[
{
- name: gsc_wk
+ name: aon_gsc_wk
struct: logic
type: uni
act: req
@@ -2721,7 +2721,7 @@
index: 0
}
{
- name: gsc_rst
+ name: aon_gsc_rst
struct: logic
type: uni
act: req
@@ -6701,7 +6701,7 @@
]
pwrmgr_aon.wakeups:
[
- sysrst_ctrl_aon.gsc_wk
+ sysrst_ctrl_aon.aon_gsc_wk
adc_ctrl_aon.debug_cable_wakeup
pinmux_aon.aon_wkup_req
pinmux_aon.usb_wkup_req
@@ -6709,7 +6709,7 @@
]
pwrmgr_aon.rstreqs:
[
- sysrst_ctrl_aon.gsc_rst
+ sysrst_ctrl_aon.aon_gsc_rst
aon_timer_aon.aon_timer_rst_req
]
main.tl_rv_core_ibex__corei:
@@ -11506,7 +11506,7 @@
wakeups:
[
{
- name: gsc_wk
+ name: aon_gsc_wk
width: "1"
module: sysrst_ctrl_aon
}
@@ -11534,7 +11534,7 @@
reset_requests:
[
{
- name: gsc_rst
+ name: aon_gsc_rst
width: "1"
module: sysrst_ctrl_aon
}
@@ -14576,7 +14576,7 @@
index: -1
}
{
- name: gsc_wk
+ name: aon_gsc_wk
struct: logic
type: uni
act: req
@@ -14588,7 +14588,7 @@
index: 0
}
{
- name: gsc_rst
+ name: aon_gsc_rst
struct: logic
type: uni
act: req
diff --git a/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson b/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson
index 791be24..26b110f 100644
--- a/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson
+++ b/hw/top_earlgrey/ip/pwrmgr/data/autogen/pwrmgr.hjson
@@ -144,8 +144,8 @@
local: "true"
},
- { name: "GSC_WK_IDX",
- desc: "Vector index for gsc_wk, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO",
+ { name: "AON_GSC_WK_IDX",
+ desc: "Vector index for aon_gsc_wk, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO",
type: "int",
default: "0",
local: "true"
diff --git a/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv
index aa4bb58..ba848f5 100644
--- a/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_pkg.sv
@@ -8,7 +8,7 @@
// Param list
parameter int NumWkups = 5;
- parameter int GSC_WK_IDX = 0;
+ parameter int AON_GSC_WK_IDX = 0;
parameter int DEBUG_CABLE_WAKEUP_IDX = 1;
parameter int AON_WKUP_REQ_IDX = 2;
parameter int USB_WKUP_REQ_IDX = 3;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 0a21d99..01f5d36 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -1701,8 +1701,8 @@
.alert_rx_i ( alert_rx[23:23] ),
// Inter-module signals
- .gsc_wk_o(pwrmgr_aon_wakeups[0]),
- .gsc_rst_o(pwrmgr_aon_rstreqs[0]),
+ .aon_gsc_wk_o(pwrmgr_aon_wakeups[0]),
+ .aon_gsc_rst_o(pwrmgr_aon_rstreqs[0]),
.tl_i(sysrst_ctrl_aon_tl_req),
.tl_o(sysrst_ctrl_aon_tl_rsp),
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 62926be..f7b0321 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1606,7 +1606,7 @@
* Power Manager Wakeup Signals
*/
typedef enum top_earlgrey_power_manager_wake_ups {
- kTopEarlgreyPowerManagerWakeUpsSysrstCtrlAonGscWk = 0, /**< */
+ kTopEarlgreyPowerManagerWakeUpsSysrstCtrlAonAonGscWk = 0, /**< */
kTopEarlgreyPowerManagerWakeUpsAdcCtrlAonDebugCableWakeup = 1, /**< */
kTopEarlgreyPowerManagerWakeUpsPinmuxAonAonWkupReq = 2, /**< */
kTopEarlgreyPowerManagerWakeUpsPinmuxAonUsbWkupReq = 3, /**< */
@@ -1632,7 +1632,7 @@
* Power Manager Reset Request Signals
*/
typedef enum top_earlgrey_power_manager_reset_requests {
- kTopEarlgreyPowerManagerResetRequestsSysrstCtrlAonGscRst = 0, /**< */
+ kTopEarlgreyPowerManagerResetRequestsSysrstCtrlAonAonGscRst = 0, /**< */
kTopEarlgreyPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 1, /**< */
kTopEarlgreyPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */
} top_earlgrey_power_manager_reset_requests_t;
diff --git a/sw/device/lib/dif/dif_pwrmgr.c b/sw/device/lib/dif/dif_pwrmgr.c
index 80b2b4f..d64e4c2 100644
--- a/sw/device/lib/dif/dif_pwrmgr.c
+++ b/sw/device/lib/dif/dif_pwrmgr.c
@@ -69,7 +69,7 @@
(1u << PWRMGR_WAKEUP_EN_EN_0_BIT),
"Layout of WAKEUP_EN register changed.");
static_assert(kDifPwrmgrWakeupRequestSourceOne ==
- (1u << PWRMGR_PARAM_GSC_WK_IDX),
+ (1u << PWRMGR_PARAM_AON_GSC_WK_IDX),
"Layout of WAKE_INFO register changed.");
static_assert(kDifPwrmgrWakeupRequestSourceTwo ==
(1u << PWRMGR_PARAM_DEBUG_CABLE_WAKEUP_IDX),
