util/docgen/examples/uart.hjson

{
  name: "UART",
  clock_primary: "clk_fixed",
  bus_device: "tlul",
  regwidth: "64",
  registers: [
    {name: "RDATA", desc: "UART read data",
      swaccess: "ro", fields: [
      {bits: "7:0", resval: "0x0"}
    ]},
    {name: "WDATA", desc: "UART write data", swaccess: "wo", fields: [
      {bits: "7:0", resval: "0x0"}
    ]},
    {name: "NCO", desc: "Baud clock rate control", swaccess: "rw", fields: [
      {bits: "15:0", resval: "0b0"}
    ]},
    {name: "CTRL", desc: "UART control register", swaccess: "rw", fields: [
      {bits: "0", name: "TX", desc: '''
        TX enable has a really long description that will go on over
	several lines and really want to wrap to be seen well in the
	source format.
	'''
	}
      {bits: "1", name: "RX", desc: "RX enable"}
      {bits: "2", name: "CTS", desc: "CTS hardware flow-control enable"}
      {bits: "3", name: "RTS", desc: "RTS hardware flow-control enable"}
      {bits: "4", name: "SLPBK", desc: "System loopback enable"}
      {bits: "5", name: "LLPBK", desc: "Line loopback enable"}
      {bits: "6", name: "RCOS", desc: "Oversample enable for RX and CTS"}
      {bits: "7", name: "NF", desc: "RX noise filter enable"}
      {bits: "8", name: "PARITY_EN", desc: "Parity enable"}
      {bits: "9", name: "PARITY_ODD", desc: "1 for odd parity, 0 for even."}
    ]}
    {name: "ICTRL", desc: "UART Interrupt control register", swaccess: "rw",
     fields: [
      {bits: "0", name: "TX", desc: "TX interrupt enable" }
      {bits: "1", name: "RX", desc: "RX interrupt enable"}
      {bits: "2", name: "TXO", desc: "TX overflow interrupt enable"}
      {bits: "3", name: "RXO", desc: "RX overflow interrupt enable"}
      {bits: "4", name: "RXF", desc: "RX frame error interrupt enable"}
      {bits: "5", name: "RXB", desc: "RX break error interrupt enable"}
      {bits: "7:6", name: "RXBLVL", desc: '''
       Trigger level for rx break detection. Sets the number of character
       times the line must be low to detect a break
       ''',
       enum: [
       	       { value: "0", name: "break2", desc: "2 characters" },
       	       { value: "1", name: "break4", desc: "4 characters" },
       	       { value: "2", name: "break8", desc: "8 characters" },
       	       { value: "3", name: "break16", desc: "16 characters" }
	     ]
      }
      {bits: "8", name: "RXTO", desc: "RX timeout interrupt enable"}
      {bits: "9", name: "RXPE", desc: "RX parity error interrupt enable"}
    ]}
    {name: "STATE", desc: "UART state register", swaccess: "ro",
     fields: [
      {bits: "0", name: "TX", desc: "TX buffer full" }
      {bits: "1", name: "RX", desc: "RX buffer full"}
      {bits: "2", name: "TXO", desc: "TX buffer overflow"}
      {bits: "3", name: "RXO", desc: "RX buffer overflow"}
      {bits: "4", name: "TXEMPTY", desc: "TX buffer empty"}
      {bits: "5", name: "TXIDLE", desc: "TX idle"}
      {bits: "6", name: "RXIDLE", desc: "RX idle"}
      {bits: "7", name: "RXEMPTY", desc: "RX fifo empty"}
    ]}
    // I suspect STATECLR should be r0w1c or something
    {name: "STATECLR", desc: "UART state register", swaccess: "rw",
     fields: [
      {bits: "19", name: "TXO", desc: "Clear TX buffer overflow"}
      {bits: "20", name: "RXO", desc: "Clear RX buffer overflow"}
    ]}
    {name: "ISTATE", desc: "UART Interrupt state register", swaccess: "ro",
     fields: [
      {bits: "0", name: "TX", desc: "TX interrupt state" }
      {bits: "1", name: "RX", desc: "RX interrupt state"}
      {bits: "2", name: "TXO", desc: "TX overflow interrupt state"}
      {bits: "3", name: "RXO", desc: "RX overflow interrupt state"}
      {bits: "4", name: "RXF", desc: "RX frame error interrupt state"}
      {bits: "5", name: "RXB", desc: "RX break error interrupt state"}
      {bits: "6", name: "RXTO", desc: "RX timeout interrupt state"}
      {bits: "7", name: "RXPE", desc: "RX parity error interrupt state"}
    ]}
    {name: "ISTATECLR", desc: "UART Interrupt clear register",
     swaccess: "r0w1c",
     fields: [
      {bits: "0", name: "TX", desc: "Clear TX interrupt" }
      {bits: "1", name: "RX", desc: "Clear RX interrupt"}
      {bits: "2", name: "TXO", desc: "Clear TX overflow interrupt"}
      {bits: "3", name: "RXO", desc: "Clear RX overflow interrupt"}
      {bits: "4", name: "RXF", desc: "Clear RX frame error interrupt"}
      {bits: "5", name: "RXB", desc: "Clear RX break error interrupt"}
      {bits: "6", name: "RXTO", desc: "Clear RX timeout interrupt"}
      {bits: "7", name: "RXPE", desc: "Clear RX parity error interrupt"}
    ]}
    {name: "FIFO", desc: "UART FIFO control register", swaccess: "rw",
     fields: [
      {bits: "0", name: "RXRST", swaccess: "r0w1c", desc: "RX fifo reset" }
      {bits: "1", name: "TXRST", swaccess: "r0w1c", desc: "TX fifo reset" }
      {bits: "4:2", name: "RXILVL",
       desc: "Trigger level for RX interrupts"
       enum: [
       	       { value: "0", name: "rxlvl1", desc: "1 character" },
       	       { value: "1", name: "rxlvl4", desc: "4 characters" },
       	       { value: "2", name: "rxlvl8", desc: "8 characters" },
       	       { value: "3", name: "rxlvl16", desc: "16 characters" }
       	       { value: "4", name: "rxlvl30", desc: "30 characters" }
	       // TODO expect generator to make others reserved
	     ]
      }
      {bits: "6:5", name: "TXILVL",
       desc: "Trigger level for TX interrupts"
       enum: [
       	       { value: "0", name: "txlvl1", desc: "1 character" },
       	       { value: "1", name: "txlvl4", desc: "4 characters" },
       	       { value: "2", name: "txlvl8", desc: "8 characters" },
       	       { value: "3", name: "txlvl16", desc: "16 characters" }
	     ]
      }
    ]}
    {name: "RFIFO", desc: "UART FIFO status register", swaccess: "ro",
     fields: [
      {bits: "5:0", name: "TXLVL", desc: "Current fill level of TX fifo" }
      {bits: "11:6", name: "RXLVL", desc: "Current fill level of RX fifo" }
    ]}
    {name: "OVRD", desc: "UART override control register", swaccess: "rw",
     fields: [
      {bits: "0", name: "TXEN", desc: "Override the TX signal" }
      {bits: "1", name: "TXVAL", desc: "Value for TX Override" }
      {bits: "2", name: "RTSEN", desc: "Override the RTS signal" }
      {bits: "3", name: "RTSVAL", desc: "Value for RTS Override" }
    ]}    
    {name: "VAL", desc: "UART oversampled values", swaccess: "ro",
     fields: [
      {bits: "15:0", name: "RX", desc: '''
       Last 16 oversampled values of RX. Most recent bit is bit 0, oldest 15.
      ''' }
      {bits: "31:16", name: "CTS", desc: '''
       Last 16 oversampled values of CTS. Most recent bit is bit 16, oldest 31.
      ''' }
    ]}
    {name: "RXTO", desc: "UART RX timeout control", swaccess: "rw",
     fields: [
      {bits: "0", name: "EN", desc: "Enable RX timeout feature" }
      {bits: "24:1", name: "VAL", desc: "RX timeout value in UART bit times" }
    ]}    
    { skipto: "0x0f00" }
    {name: "ITCR", desc: "UART Integration test control", swaccess: "rw",
     fields: [
      {bits: "0", name: "", desc: "-" }
    ]}    
    {name: "ITOP", desc: "UART Integration test overrides", swaccess: "rw",
     fields: [
      {bits: "0", name: "TX", desc: "Drive txint when UART_ITCR asserted" }
      {bits: "1", name: "RX", desc: "Drive rxint when UART_ITCR asserted" }
      {bits: "2", name: "TXO", desc: "Drive txoint when UART_ITCR asserted" }
      {bits: "3", name: "RXO", desc: "Drive rxoint when UART_ITCR asserted" }
      {bits: "4", name: "RXF", desc: "Drive rxfint when UART_ITCR asserted" }
      {bits: "5", name: "RXB", desc: "Drive rxbint when UART_ITCR asserted" }
      {bits: "6", name: "RXTO", desc: "Drive rxtoint when UART_ITCR asserted" }
      {bits: "7", name: "RXPE", desc: "Drive rxpeint when UART_ITCR asserted" }
    ]}
    {name: "DVREG", desc: "DV-accessible test register", swaccess: "rw",
     fields: [
      {bits: "56:0", name: "", desc: "-" }
    ]}    
  ]
}