| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// |
| // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: |
| // |
| // util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson \ |
| // -o hw/top_earlgrey/ \ |
| // --hjson-only \ |
| // --rnd_cnst_seed 4881560218908238235 |
| { |
| name: earlgrey |
| type: top |
| rnd_cnst_seed: 4881560218908238235 |
| datawidth: "32" |
| power: |
| { |
| domains: |
| [ |
| Aon |
| "0" |
| ] |
| default: "0" |
| } |
| clocks: |
| { |
| hier_paths: |
| { |
| top: clkmgr_aon_clocks. |
| ext: "" |
| } |
| srcs: |
| [ |
| { |
| name: main |
| aon: no |
| freq: "100000000" |
| } |
| { |
| name: io |
| aon: no |
| freq: "96000000" |
| } |
| { |
| name: usb |
| aon: no |
| freq: "48000000" |
| } |
| { |
| name: aon |
| aon: yes |
| freq: "200000" |
| } |
| ] |
| derived_srcs: |
| [ |
| { |
| name: io_div2 |
| aon: no |
| freq: "48000000" |
| div: "2" |
| src: io |
| } |
| { |
| name: io_div4 |
| aon: no |
| freq: "24000000" |
| div: "4" |
| src: io |
| } |
| ] |
| groups: |
| [ |
| { |
| name: powerup |
| src: top |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_io_div4_powerup: io_div4 |
| clk_aon_powerup: aon |
| clk_main_powerup: main |
| clk_io_powerup: io |
| clk_usb_powerup: usb |
| clk_io_div2_powerup: io_div2 |
| } |
| } |
| { |
| name: trans |
| src: top |
| sw_cg: hint |
| unique: yes |
| clocks: |
| { |
| clk_main_aes: main |
| clk_main_hmac: main |
| clk_main_kmac: main |
| clk_main_otbn: main |
| clk_io_div4_otbn: io_div4 |
| } |
| } |
| { |
| name: infra |
| src: top |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_io_div4_infra: io_div4 |
| clk_main_infra: main |
| } |
| } |
| { |
| name: secure |
| src: top |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_io_div4_secure: io_div4 |
| clk_aon_secure: aon |
| clk_main_secure: main |
| } |
| } |
| { |
| name: peri |
| src: top |
| sw_cg: yes |
| unique: no |
| clocks: |
| { |
| clk_io_div4_peri: io_div4 |
| clk_io_div2_peri: io_div2 |
| clk_io_peri: io |
| clk_aon_peri: aon |
| clk_usb_peri: usb |
| } |
| } |
| { |
| name: timers |
| src: top |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_io_div4_timers: io_div4 |
| clk_main_timers: main |
| clk_aon_timers: aon |
| } |
| } |
| { |
| name: proc |
| src: no |
| sw_cg: no |
| unique: no |
| clocks: |
| { |
| clk_proc_main: main |
| } |
| } |
| ] |
| } |
| resets: |
| { |
| hier_paths: |
| { |
| top: rstmgr_aon_resets. |
| ext: "" |
| } |
| nodes: |
| [ |
| { |
| name: rst_ni |
| gen: false |
| type: ext |
| domains: [] |
| shadowed: false |
| sw: false |
| path: rst_ni |
| } |
| { |
| name: por_aon |
| gen: false |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_aon_n |
| clock: aon |
| } |
| { |
| name: lc_src |
| gen: false |
| type: int |
| domains: [] |
| shadowed: false |
| sw: false |
| path: "" |
| clock: io_div4 |
| } |
| { |
| name: sys_src |
| gen: false |
| type: int |
| domains: [] |
| shadowed: false |
| sw: false |
| path: "" |
| clock: io_div4 |
| } |
| { |
| name: por |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_n |
| parent: por_aon |
| clock: main |
| } |
| { |
| name: por_io |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_io_n |
| parent: por_aon |
| clock: io |
| } |
| { |
| name: por_io_div2 |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_io_div2_n |
| parent: por_aon |
| clock: io_div2 |
| } |
| { |
| name: por_io_div4 |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_io_div4_n |
| parent: por_aon |
| clock: io_div4 |
| } |
| { |
| name: por_usb |
| gen: true |
| type: top |
| domains: |
| [ |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_por_usb_n |
| parent: por_aon |
| clock: usb |
| } |
| { |
| name: lc |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_lc_n |
| parent: lc_src |
| clock: main |
| } |
| { |
| name: lc_io_div4 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_lc_io_div4_n |
| parent: lc_src |
| clock: io_div4 |
| } |
| { |
| name: sys |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: true |
| sw: false |
| path: rstmgr_aon_resets.rst_sys_n |
| parent: sys_src |
| clock: main |
| } |
| { |
| name: sys_io_div4 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| Aon |
| ] |
| shadowed: true |
| sw: false |
| path: rstmgr_aon_resets.rst_sys_io_div4_n |
| parent: sys_src |
| clock: io_div4 |
| } |
| { |
| name: sys_aon |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| Aon |
| ] |
| shadowed: false |
| sw: false |
| path: rstmgr_aon_resets.rst_sys_aon_n |
| parent: sys_src |
| clock: aon |
| } |
| { |
| name: spi_device |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_spi_device_n |
| parent: sys_src |
| clock: io_div2 |
| } |
| { |
| name: spi_host0 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_spi_host0_n |
| parent: sys_src |
| clock: io |
| } |
| { |
| name: spi_host1 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_spi_host1_n |
| parent: sys_src |
| clock: io_div2 |
| } |
| { |
| name: usb |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_usb_n |
| parent: sys_src |
| clock: usb |
| } |
| { |
| name: i2c0 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_i2c0_n |
| parent: sys_src |
| clock: io_div2 |
| } |
| { |
| name: i2c1 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_i2c1_n |
| parent: sys_src |
| clock: io_div2 |
| } |
| { |
| name: i2c2 |
| gen: true |
| type: top |
| domains: |
| [ |
| "0" |
| ] |
| shadowed: false |
| sw: true |
| path: rstmgr_aon_resets.rst_i2c2_n |
| parent: sys_src |
| clock: io_div2 |
| } |
| ] |
| } |
| num_cores: "1" |
| module: |
| [ |
| { |
| name: uart0 |
| type: uart |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| clock_group: secure |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart0 |
| default: "" |
| end_idx: -1 |
| top_signame: uart0_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40000000 |
| } |
| } |
| { |
| name: uart1 |
| type: uart |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| clock_group: secure |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart1 |
| default: "" |
| end_idx: -1 |
| top_signame: uart1_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40010000 |
| } |
| } |
| { |
| name: uart2 |
| type: uart |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| clock_group: secure |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart2 |
| default: "" |
| end_idx: -1 |
| top_signame: uart2_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40020000 |
| } |
| } |
| { |
| name: uart3 |
| type: uart |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| clock_group: secure |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart3 |
| default: "" |
| end_idx: -1 |
| top_signame: uart3_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40030000 |
| } |
| } |
| { |
| name: gpio |
| type: gpio |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: gpio |
| default: "" |
| end_idx: -1 |
| top_signame: gpio_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40040000 |
| } |
| } |
| { |
| name: spi_device |
| type: spi_device |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| scan_clk_i: io_div2 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: spi_device |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| scan_clk_i: clkmgr_aon_clocks.clk_io_div2_peri |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: ram_cfg |
| struct: ram_2p_cfg |
| package: prim_ram_2p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| top_signame: ast_ram_2p_cfg |
| index: -1 |
| } |
| { |
| name: passthrough |
| struct: passthrough |
| package: spi_device_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| end_idx: -1 |
| top_signame: spi_device_passthrough |
| index: -1 |
| } |
| { |
| name: mbist_en |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: spi_device |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| end_idx: -1 |
| top_signame: spi_device_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40050000 |
| } |
| } |
| { |
| name: spi_host0 |
| type: spi_host |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_core_i: io |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: spi_host0 |
| rst_core_ni: spi_host0 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| clk_core_i: clkmgr_aon_clocks.clk_io_peri |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: passthrough |
| struct: passthrough |
| package: spi_device_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host0 |
| default: "" |
| top_signame: spi_device_passthrough |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host0 |
| default: "" |
| end_idx: -1 |
| top_signame: spi_host0_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40060000 |
| } |
| } |
| { |
| name: spi_host1 |
| type: spi_host |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_core_i: io_div2 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: spi_host1 |
| rst_core_ni: spi_host1 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| clk_core_i: clkmgr_aon_clocks.clk_io_div2_peri |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: passthrough |
| struct: passthrough |
| package: spi_device_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host1 |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host1 |
| default: "" |
| end_idx: -1 |
| top_signame: spi_host1_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40070000 |
| } |
| } |
| { |
| name: i2c0 |
| type: i2c |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: i2c0 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: i2c0 |
| default: "" |
| end_idx: -1 |
| top_signame: i2c0_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40080000 |
| } |
| } |
| { |
| name: i2c1 |
| type: i2c |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: i2c1 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: i2c1 |
| default: "" |
| end_idx: -1 |
| top_signame: i2c1_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40090000 |
| } |
| } |
| { |
| name: i2c2 |
| type: i2c |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: i2c2 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: i2c2 |
| default: "" |
| end_idx: -1 |
| top_signame: i2c2_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x400A0000 |
| } |
| } |
| { |
| name: pattgen |
| type: pattgen |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pattgen |
| default: "" |
| end_idx: -1 |
| top_signame: pattgen_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x400E0000 |
| } |
| } |
| { |
| name: rv_timer |
| type: rv_timer |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: timers |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_timers |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_timer |
| default: "" |
| end_idx: -1 |
| top_signame: rv_timer_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40100000 |
| } |
| } |
| { |
| name: usbdev |
| type: usbdev |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| clk_usb_48mhz_i: usb |
| } |
| clock_group: peri |
| clock_reset_export: |
| [ |
| ast |
| ] |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| rst_aon_ni: sys_aon |
| rst_usb_48mhz_ni: usb |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_peri |
| clk_usb_48mhz_i: clkmgr_aon_clocks.clk_usb_peri |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: usb_ref_val |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_ref_val |
| index: -1 |
| } |
| { |
| name: usb_ref_pulse |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_ref_pulse |
| index: -1 |
| } |
| { |
| name: usb_out_of_rst |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_out_of_rst |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_en |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_aon_wake_en |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_ack |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_aon_wake_ack |
| index: -1 |
| } |
| { |
| name: usb_suspend |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_suspend |
| index: -1 |
| } |
| { |
| name: usb_state_debug |
| struct: awk_state |
| package: usbdev_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| top_signame: pinmux_aon_usb_state_debug |
| index: -1 |
| } |
| { |
| name: ram_cfg |
| struct: ram_2p_cfg |
| package: prim_ram_2p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| top_signame: ast_ram_2p_cfg |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| end_idx: -1 |
| top_signame: usbdev_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40110000 |
| } |
| } |
| { |
| name: otp_ctrl |
| type: otp_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_edn_i: main |
| } |
| clock_group: timers |
| reset_connections: |
| { |
| rst_ni: lc_io_div4 |
| rst_edn_ni: sys |
| } |
| base_addrs: |
| { |
| core: 0x40130000 |
| prim: 0x40132000 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_timers |
| clk_edn_i: clkmgr_aon_clocks.clk_main_timers |
| } |
| domain: "0" |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: MemInitFile |
| desc: VMEM file to initialize the OTP macro. |
| type: "" |
| default: '''""''' |
| expose: "true" |
| name_top: OtpCtrlMemInitFile |
| } |
| { |
| name: RndCnstLfsrSeed |
| desc: Compile-time random bits for initial LFSR seed |
| type: otp_ctrl_pkg::lfsr_seed_t |
| randcount: 40 |
| randtype: data |
| name_top: RndCnstOtpCtrlLfsrSeed |
| default: 0xf45def7861 |
| randwidth: 40 |
| } |
| { |
| name: RndCnstLfsrPerm |
| desc: Compile-time random permutation for LFSR output |
| type: otp_ctrl_pkg::lfsr_perm_t |
| randcount: 40 |
| randtype: perm |
| name_top: RndCnstOtpCtrlLfsrPerm |
| default: 0x5d294061e29a7c404f4593035a19097666e37072064153623855022d39e0 |
| randwidth: 240 |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: otp_ast_pwr_seq |
| struct: otp_ast_req |
| package: otp_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| external: true |
| top_signame: otp_ctrl_otp_ast_pwr_seq |
| index: -1 |
| } |
| { |
| name: otp_ast_pwr_seq_h |
| struct: otp_ast_rsp |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| external: true |
| top_signame: otp_ctrl_otp_ast_pwr_seq_h |
| index: -1 |
| } |
| { |
| name: otp_alert |
| struct: ast_dif |
| package: ast_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| external: true |
| top_signame: otp_alert |
| index: -1 |
| } |
| { |
| name: edn |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| top_signame: edn0_edn |
| index: 1 |
| } |
| { |
| name: pwr_otp |
| struct: pwr_otp |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: pwrmgr_aon_pwr_otp |
| index: -1 |
| } |
| { |
| name: lc_otp_program |
| struct: lc_otp_program |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_otp_program |
| index: -1 |
| } |
| { |
| name: otp_lc_data |
| struct: otp_lc_data |
| package: otp_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: otp_ctrl_otp_lc_data |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_creator_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_creator_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_seed_hw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_seed_hw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_check_byp_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_check_byp_en |
| index: -1 |
| } |
| { |
| name: otp_keymgr_key |
| struct: otp_keymgr_key |
| package: otp_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: otp_ctrl_otp_keymgr_key |
| index: -1 |
| } |
| { |
| name: flash_otp_key |
| struct: flash_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: flash_ctrl_otp |
| index: -1 |
| } |
| { |
| name: sram_otp_key |
| struct: sram_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 2 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: otp_ctrl_sram_otp_key |
| index: -1 |
| } |
| { |
| name: otbn_otp_key |
| struct: otbn_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_signame: otp_ctrl_otbn_otp_key |
| index: -1 |
| } |
| { |
| name: otp_hw_cfg |
| struct: otp_hw_cfg |
| package: otp_ctrl_part_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: otp_ctrl_otp_hw_cfg |
| index: -1 |
| } |
| { |
| name: core_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: otp_ctrl_core_tl |
| index: -1 |
| } |
| { |
| name: prim_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: otp_ctrl_prim_tl |
| index: -1 |
| } |
| ] |
| } |
| { |
| name: lc_ctrl |
| type: lc_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_kmac_i: main |
| } |
| clock_group: timers |
| reset_connections: |
| { |
| rst_ni: lc_io_div4 |
| rst_kmac_ni: sys |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_timers |
| clk_kmac_i: clkmgr_aon_clocks.clk_main_timers |
| } |
| domain: "0" |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: RndCnstLcKeymgrDivInvalid |
| desc: Compile-time random bits for lc state group diversification value |
| type: lc_ctrl_pkg::lc_keymgr_div_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstLcCtrlLcKeymgrDivInvalid |
| default: 0xfdb92558e2d9c5d24440722325a93144 |
| randwidth: 128 |
| } |
| { |
| name: RndCnstLcKeymgrDivTestDevRma |
| desc: Compile-time random bits for lc state group diversification value |
| type: lc_ctrl_pkg::lc_keymgr_div_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstLcCtrlLcKeymgrDivTestDevRma |
| default: 0x6faf88f22bccd612d1c09f5c02b2c8d1 |
| randwidth: 128 |
| } |
| { |
| name: RndCnstLcKeymgrDivProduction |
| desc: Compile-time random bits for lc state group diversification value |
| type: lc_ctrl_pkg::lc_keymgr_div_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstLcCtrlLcKeymgrDivProduction |
| default: 0x79ee911ce801484ba8373086f9dd4eee |
| randwidth: 128 |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: pinmux_aon_lc_jtag |
| index: -1 |
| } |
| { |
| name: esc_scrap_state0_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 1 |
| } |
| { |
| name: esc_scrap_state0_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 1 |
| } |
| { |
| name: esc_scrap_state1_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 2 |
| } |
| { |
| name: esc_scrap_state1_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 2 |
| } |
| { |
| name: pwr_lc |
| struct: pwr_lc |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: pwrmgr_aon_pwr_lc |
| index: -1 |
| } |
| { |
| name: otp_lc_data |
| struct: otp_lc_data |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT |
| inst_name: lc_ctrl |
| top_signame: otp_ctrl_otp_lc_data |
| index: -1 |
| } |
| { |
| name: lc_otp_program |
| struct: lc_otp_program |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_signame: lc_ctrl_lc_otp_program |
| index: -1 |
| } |
| { |
| name: kmac_data |
| struct: app |
| package: kmac_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: kmac_app |
| index: 1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_nvm_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_nvm_debug_en |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: lc_cpu_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_cpu_en |
| index: -1 |
| } |
| { |
| name: lc_keymgr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_keymgr_en |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_clk_byp_req |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_clk_byp_ack |
| index: -1 |
| } |
| { |
| name: lc_flash_rma_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| top_signame: flash_ctrl_rma_req |
| index: -1 |
| } |
| { |
| name: lc_flash_rma_seed |
| struct: lc_flash_rma_seed |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: flash_ctrl_rma_seed |
| index: -1 |
| } |
| { |
| name: lc_flash_rma_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| top_signame: flash_ctrl_rma_ack |
| index: -1 |
| } |
| { |
| name: lc_check_byp_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_check_byp_en |
| index: -1 |
| } |
| { |
| name: lc_creator_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_creator_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_owner_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_owner_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_iso_part_sw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_wr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_iso_part_sw_wr_en |
| index: -1 |
| } |
| { |
| name: lc_seed_hw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_seed_hw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_keymgr_div |
| struct: lc_keymgr_div |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_keymgr_div |
| index: -1 |
| } |
| { |
| name: otp_device_id |
| struct: otp_device_id |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: lc_ctrl_otp_device_id |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: lc_ctrl_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40140000 |
| } |
| } |
| { |
| name: alert_handler |
| type: alert_handler |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_edn_i: main |
| } |
| clock_group: timers |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| rst_edn_ni: sys |
| } |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_timers |
| clk_edn_i: clkmgr_aon_clocks.clk_main_timers |
| } |
| domain: "0" |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: RndCnstLfsrSeed |
| desc: Compile-time random bits for initial LFSR seed |
| type: alert_pkg::lfsr_seed_t |
| randcount: 32 |
| randtype: data |
| name_top: RndCnstAlertHandlerLfsrSeed |
| default: 0x7b93136f |
| randwidth: 32 |
| } |
| { |
| name: RndCnstLfsrPerm |
| desc: Compile-time random permutation for LFSR output |
| type: alert_pkg::lfsr_perm_t |
| randcount: 32 |
| randtype: perm |
| name_top: RndCnstAlertHandlerLfsrPerm |
| default: 0xaf33379628b29df3261a1e1be933ab38a840eee0 |
| randwidth: 160 |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: crashdump |
| struct: alert_crashdump |
| package: alert_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: alert_handler_crashdump |
| index: -1 |
| } |
| { |
| name: edn |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: alert_handler |
| default: "" |
| top_signame: edn0_edn |
| index: 4 |
| } |
| { |
| name: esc_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 4 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: alert_handler_esc_rx |
| index: -1 |
| } |
| { |
| name: esc_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 4 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: alert_handler_esc_tx |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_signame: alert_handler_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40150000 |
| } |
| } |
| { |
| name: pwrmgr_aon |
| type: pwrmgr |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_slow_i: aon |
| } |
| clock_group: powerup |
| reset_connections: |
| { |
| rst_ni: por |
| rst_slow_ni: por_aon |
| } |
| domain: Aon |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_slow_i: clkmgr_aon_clocks.clk_aon_powerup |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: pwr_ast |
| struct: pwr_ast |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| external: true |
| top_signame: pwrmgr_ast |
| index: -1 |
| } |
| { |
| name: pwr_rst |
| struct: pwr_rst |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_rst |
| index: -1 |
| } |
| { |
| name: pwr_clk |
| struct: pwr_clk |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_clk |
| index: -1 |
| } |
| { |
| name: pwr_otp |
| struct: pwr_otp |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_otp |
| index: -1 |
| } |
| { |
| name: pwr_lc |
| struct: pwr_lc |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_lc |
| index: -1 |
| } |
| { |
| name: pwr_flash |
| struct: pwr_flash |
| package: pwrmgr_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_pwr_flash |
| index: -1 |
| } |
| { |
| name: esc_rst_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 3 |
| } |
| { |
| name: esc_rst_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 3 |
| } |
| { |
| name: pwr_cpu |
| struct: pwr_cpu |
| package: pwrmgr_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: rv_core_ibex_pwrmgr |
| index: -1 |
| } |
| { |
| name: wakeups |
| struct: logic |
| type: uni |
| act: rcv |
| width: 5 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: pwrmgr_aon_wakeups |
| index: -1 |
| } |
| { |
| name: rstreqs |
| struct: logic |
| type: uni |
| act: rcv |
| width: 2 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: pwrmgr_aon_rstreqs |
| index: -1 |
| } |
| { |
| name: strap |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_strap |
| index: -1 |
| } |
| { |
| name: low_power |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_low_power |
| index: -1 |
| } |
| { |
| name: rom_ctrl |
| struct: pwrmgr_data |
| package: rom_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: rom_ctrl_pwrmgr_data |
| index: -1 |
| } |
| { |
| name: fetch_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_fetch_en |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40400000 |
| } |
| } |
| { |
| name: rstmgr_aon |
| type: rstmgr |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| clk_main_i: main |
| clk_io_i: io |
| clk_usb_i: usb |
| clk_io_div2_i: io_div2 |
| clk_io_div4_i: io_div4 |
| } |
| clock_group: powerup |
| reset_connections: |
| { |
| rst_ni: rst_ni |
| } |
| domain: Aon |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup |
| clk_main_i: clkmgr_aon_clocks.clk_main_powerup |
| clk_io_i: clkmgr_aon_clocks.clk_io_powerup |
| clk_usb_i: clkmgr_aon_clocks.clk_usb_powerup |
| clk_io_div2_i: clkmgr_aon_clocks.clk_io_div2_powerup |
| clk_io_div4_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: pwr |
| struct: pwr_rst |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| package: pwrmgr_pkg |
| top_signame: pwrmgr_aon_pwr_rst |
| index: -1 |
| } |
| { |
| name: resets |
| struct: rstmgr_out |
| package: rstmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: rstmgr_aon_resets |
| index: -1 |
| } |
| { |
| name: rst_cpu_n |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| package: "" |
| top_signame: rv_core_ibex_rst_cpu_n |
| index: -1 |
| } |
| { |
| name: ndmreset_req |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| package: "" |
| top_signame: rv_dm_ndmreset_req |
| index: -1 |
| } |
| { |
| name: alert_dump |
| struct: alert_crashdump |
| package: alert_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: alert_handler_crashdump |
| index: -1 |
| } |
| { |
| name: cpu_dump |
| struct: crash_dump |
| package: ibex_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: rv_core_ibex_crash_dump |
| index: -1 |
| } |
| { |
| name: resets_ast |
| struct: rstmgr_ast_out |
| package: rstmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| external: true |
| top_signame: rsts_ast |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: rstmgr_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40410000 |
| } |
| } |
| { |
| name: clkmgr_aon |
| type: clkmgr |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: powerup |
| reset_connections: |
| { |
| rst_ni: por_io_div4 |
| rst_main_ni: por |
| rst_io_ni: por_io |
| rst_usb_ni: por_usb |
| rst_io_div2_ni: por_io_div2 |
| rst_io_div4_ni: por_io_div4 |
| } |
| domain: Aon |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: clocks |
| struct: clkmgr_out |
| package: clkmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: clkmgr_aon_clocks |
| index: -1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: ast_clk_byp_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: ast_clk_byp_req |
| index: -1 |
| } |
| { |
| name: ast_clk_byp_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: ast_clk_byp_ack |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_clk_byp_req |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_clk_byp_ack |
| index: -1 |
| } |
| { |
| name: jitter_en |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_main_jitter_en |
| index: -1 |
| } |
| { |
| name: clk_main |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_main |
| index: -1 |
| } |
| { |
| name: clk_io |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_io |
| index: -1 |
| } |
| { |
| name: clk_usb |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_usb |
| index: -1 |
| } |
| { |
| name: clk_aon |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_aon |
| index: -1 |
| } |
| { |
| name: clocks_ast |
| struct: clkmgr_ast_out |
| package: clkmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: clks_ast |
| index: -1 |
| } |
| { |
| name: pwr |
| struct: pwr_clk |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: pwrmgr_pkg |
| top_signame: pwrmgr_aon_pwr_clk |
| index: -1 |
| } |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: rcv |
| width: 5 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| end_idx: 4 |
| top_type: partial-one-to-N |
| top_signame: clkmgr_aon_idle |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: clkmgr_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40420000 |
| } |
| } |
| { |
| name: sysrst_ctrl_aon |
| type: sysrst_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| rst_aon_ni: sys_aon |
| } |
| domain: Aon |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_secure |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: gsc_wk |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sysrst_ctrl_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 0 |
| } |
| { |
| name: gsc_rst |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sysrst_ctrl_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_rstreqs |
| index: 0 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sysrst_ctrl_aon |
| default: "" |
| end_idx: -1 |
| top_signame: sysrst_ctrl_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40430000 |
| } |
| } |
| { |
| name: adc_ctrl_aon |
| type: adc_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| } |
| clock_group: peri |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| rst_slow_ni: sys_aon |
| } |
| clock_reset_export: |
| [ |
| ast |
| ] |
| domain: Aon |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_peri |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_peri |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: adc |
| struct: adc_ast |
| package: ast_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: adc_ctrl_aon |
| default: "" |
| external: true |
| top_signame: adc |
| index: -1 |
| } |
| { |
| name: debug_cable_wakeup |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: adc_ctrl_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: adc_ctrl_aon |
| default: "" |
| end_idx: -1 |
| top_signame: adc_ctrl_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40440000 |
| } |
| } |
| { |
| name: pwm_aon |
| type: pwm |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_core_i: aon |
| } |
| clock_group: powerup |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| rst_core_ni: sys_aon |
| } |
| domain: Aon |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_core_i: clkmgr_aon_clocks.clk_aon_powerup |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pwm_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwm_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40450000 |
| } |
| } |
| { |
| name: pinmux_aon |
| type: pinmux |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| } |
| clock_group: powerup |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| rst_aon_ni: sys_aon |
| } |
| domain: Aon |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_powerup |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup |
| } |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: TargetCfg |
| desc: Target specific pinmux configuration. |
| type: pinmux_pkg::target_cfg_t |
| default: pinmux_pkg::DefaultTargetCfg |
| expose: "true" |
| name_top: PinmuxAonTargetCfg |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: pinmux_aon |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: pinmux_aon |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pinmux_aon_lc_jtag |
| index: -1 |
| } |
| { |
| name: rv_jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pinmux_aon_rv_jtag |
| index: -1 |
| } |
| { |
| name: dft_jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| top_signame: pinmux_aon_dft_jtag |
| index: -1 |
| } |
| { |
| name: dft_strap_test |
| struct: dft_strap_test_req |
| package: pinmux_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: pinmux_aon |
| external: true |
| top_signame: dft_strap_test |
| index: -1 |
| } |
| { |
| name: dft_hold_tap_sel |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: pinmux_aon |
| package: "" |
| external: true |
| top_signame: dft_hold_tap_sel |
| index: -1 |
| } |
| { |
| name: sleep_en |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_low_power |
| index: -1 |
| } |
| { |
| name: strap_en |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_strap |
| index: -1 |
| } |
| { |
| name: aon_wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 2 |
| } |
| { |
| name: usb_wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 3 |
| } |
| { |
| name: usb_out_of_rst |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_out_of_rst |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_en |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_aon_wake_en |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_ack |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_aon_wake_ack |
| index: -1 |
| } |
| { |
| name: usb_suspend |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_suspend |
| index: -1 |
| } |
| { |
| name: usb_state_debug |
| struct: awk_state |
| package: usbdev_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pinmux_aon_usb_state_debug |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pinmux_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40460000 |
| } |
| } |
| { |
| name: aon_timer_aon |
| type: aon_timer |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_aon_i: aon |
| } |
| clock_group: timers |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| rst_aon_ni: sys_aon |
| } |
| domain: Aon |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_timers |
| clk_aon_i: clkmgr_aon_clocks.clk_aon_timers |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: aon_timer_wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: aon_timer_aon |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 4 |
| } |
| { |
| name: aon_timer_rst_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: aon_timer_aon |
| package: "" |
| top_signame: pwrmgr_aon_rstreqs |
| index: 1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: aon_timer_aon |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: sleep_mode |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: aon_timer_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_low_power |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: aon_timer_aon |
| default: "" |
| end_idx: -1 |
| top_signame: aon_timer_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40470000 |
| } |
| } |
| { |
| name: ast |
| type: ast |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: secure |
| clock_reset_export: |
| [ |
| ast |
| ] |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| attr: reggen_only |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: ast |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40480000 |
| } |
| } |
| { |
| name: sensor_ctrl_aon |
| type: sensor_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: secure |
| clock_reset_export: |
| [ |
| ast |
| ] |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| domain: Aon |
| attr: reggen_top |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_secure |
| } |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: ast_alert |
| struct: ast_alert |
| package: ast_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| external: true |
| top_signame: sensor_ctrl_ast_alert |
| index: -1 |
| } |
| { |
| name: ast_status |
| struct: ast_status |
| package: ast_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| external: true |
| top_signame: sensor_ctrl_ast_status |
| index: -1 |
| } |
| { |
| name: ast_init_done |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: ast_init_done |
| index: -1 |
| } |
| { |
| name: ast2pinmux |
| struct: logic |
| type: uni |
| act: rcv |
| width: 9 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: ast2pinmux |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| end_idx: -1 |
| top_signame: sensor_ctrl_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40490000 |
| } |
| } |
| { |
| name: sram_ctrl_ret_aon |
| type: sram_ctrl |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| clk_otp_i: io_div4 |
| } |
| clock_group: infra |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| rst_otp_ni: lc_io_div4 |
| } |
| domain: Aon |
| param_decl: |
| { |
| InstrExec: "0" |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_infra |
| clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra |
| } |
| memory: {} |
| param_list: |
| [ |
| { |
| name: RndCnstSramKey |
| desc: Compile-time random reset value for SRAM scrambling key. |
| type: otp_ctrl_pkg::sram_key_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstSramCtrlRetAonSramKey |
| default: 0x738f30d9006289a1d7d9d0ce1dd7d7c |
| randwidth: 128 |
| } |
| { |
| name: RndCnstSramNonce |
| desc: Compile-time random reset value for SRAM scrambling nonce. |
| type: otp_ctrl_pkg::sram_nonce_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstSramCtrlRetAonSramNonce |
| default: 0xfe8f673fba39bb679d58aa91aeb2691c |
| randwidth: 128 |
| } |
| { |
| name: RndCnstSramLfsrPerm |
| desc: Compile-time random permutation for LFSR output |
| type: sram_ctrl_pkg::lfsr_perm_t |
| randcount: 32 |
| randtype: perm |
| name_top: RndCnstSramCtrlRetAonSramLfsrPerm |
| default: 0x25da5869dc96fe354f1da55e9123cb082c63b331 |
| randwidth: 160 |
| } |
| { |
| name: InstrExec |
| desc: Support execution from SRAM |
| type: bit |
| default: "0" |
| expose: "true" |
| name_top: SramCtrlRetAonInstrExec |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: sram_otp_key |
| struct: sram_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_ret_aon |
| top_signame: otp_ctrl_sram_otp_key |
| index: 1 |
| } |
| { |
| name: sram_scr |
| struct: sram_scr |
| package: sram_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_ret_aon |
| end_idx: -1 |
| top_signame: sram_ctrl_ret_aon_sram_scr |
| index: -1 |
| } |
| { |
| name: sram_scr_init |
| struct: sram_scr_init |
| package: sram_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_ret_aon |
| end_idx: -1 |
| top_signame: sram_ctrl_ret_aon_sram_scr_init |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: sram_ctrl_ret_aon |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: sram_ctrl_ret_aon |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: otp_en_sram_ifetch |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_ret_aon |
| top_signame: sram_ctrl_ret_aon_otp_en_sram_ifetch |
| index: -1 |
| } |
| { |
| name: en_ifetch |
| struct: tl_instr_en |
| package: tlul_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sram_ctrl_ret_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: sram_ctrl_ret_aon_en_ifetch |
| index: -1 |
| } |
| { |
| name: intg_error |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: sram_ctrl_ret_aon |
| default: "" |
| package: "" |
| top_signame: ram_ret_aon_intg_error |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sram_ctrl_ret_aon |
| default: "" |
| end_idx: -1 |
| top_signame: sram_ctrl_ret_aon_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x40500000 |
| } |
| } |
| { |
| name: flash_ctrl |
| type: flash_ctrl |
| clock_srcs: |
| { |
| clk_i: main |
| clk_otp_i: io_div4 |
| } |
| clock_group: infra |
| reset_connections: |
| { |
| rst_ni: lc |
| rst_otp_ni: lc_io_div4 |
| } |
| base_addrs: |
| { |
| core: 0x41000000 |
| prim: 0x41008000 |
| } |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_infra |
| clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra |
| } |
| domain: "0" |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: RndCnstAddrKey |
| desc: Compile-time random bits for default address key |
| type: flash_ctrl_pkg::flash_key_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstFlashCtrlAddrKey |
| default: 0x369ae283eec5e43d4b16446726a27b8f |
| randwidth: 128 |
| } |
| { |
| name: RndCnstDataKey |
| desc: Compile-time random bits for default data key |
| type: flash_ctrl_pkg::flash_key_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstFlashCtrlDataKey |
| default: 0x1a07eb42a37dbfb7be9bb6e69a7d3c5f |
| randwidth: 128 |
| } |
| { |
| name: RndCnstLfsrSeed |
| desc: Compile-time random bits for initial LFSR seed |
| type: flash_ctrl_pkg::lfsr_seed_t |
| randcount: 32 |
| randtype: data |
| name_top: RndCnstFlashCtrlLfsrSeed |
| default: 0x96f534d |
| randwidth: 32 |
| } |
| { |
| name: RndCnstLfsrPerm |
| desc: Compile-time random permutation for LFSR output |
| type: flash_ctrl_pkg::lfsr_perm_t |
| randcount: 32 |
| randtype: perm |
| name_top: RndCnstFlashCtrlLfsrPerm |
| default: 0xc0fb0f38e6bd6744364b005ec493761479f5173a |
| randwidth: 160 |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: flash |
| struct: flash |
| package: flash_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: flash_ctrl_flash |
| index: -1 |
| } |
| { |
| name: otp |
| struct: flash_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: flash_ctrl_otp |
| index: -1 |
| } |
| { |
| name: lc_creator_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_creator_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_owner_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_owner_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_iso_part_sw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_wr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_iso_part_sw_wr_en |
| index: -1 |
| } |
| { |
| name: lc_seed_hw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_seed_hw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: rma_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: flash_ctrl_rma_req |
| index: -1 |
| } |
| { |
| name: rma_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: flash_ctrl_rma_ack |
| index: -1 |
| } |
| { |
| name: rma_seed |
| struct: lc_flash_rma_seed |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: flash_ctrl_rma_seed |
| index: -1 |
| } |
| { |
| name: pwrmgr |
| struct: pwr_flash |
| package: pwrmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: pwrmgr_aon_pwr_flash |
| index: -1 |
| } |
| { |
| name: keymgr |
| struct: keymgr_flash |
| package: flash_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: flash_ctrl_keymgr |
| index: -1 |
| } |
| { |
| name: core_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: flash_ctrl_core_tl |
| index: -1 |
| } |
| { |
| name: prim_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: flash_ctrl_prim_tl |
| index: -1 |
| } |
| ] |
| } |
| { |
| name: rv_dm |
| type: rv_dm |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: infra |
| reset_connections: |
| { |
| rst_ni: lc |
| } |
| base_addrs: |
| { |
| rom: 0x00010000 |
| regs: 0x41200000 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_infra |
| } |
| domain: "0" |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: IdcodeValue |
| desc: RISC-V debug module JTAG ID code. |
| type: logic [31:0] |
| default: 32'h 0000_0001 |
| expose: "true" |
| name_top: RvDmIdcodeValue |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| top_signame: pinmux_aon_rv_jtag |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: rv_dm |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: unavailable |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: 1'b0 |
| inst_name: rv_dm |
| index: -1 |
| } |
| { |
| name: ndmreset_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_dm_ndmreset_req |
| index: -1 |
| } |
| { |
| name: dmactive |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_dm |
| index: -1 |
| } |
| { |
| name: debug_req |
| struct: logic [rv_dm_reg_pkg::NrHarts-1:0] |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_dm_debug_req |
| index: -1 |
| } |
| { |
| name: sba_tl_h |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| top_signame: main_tl_rv_dm__sba |
| index: -1 |
| } |
| { |
| name: regs_tl_d |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| end_idx: -1 |
| top_signame: rv_dm_regs_tl_d |
| index: -1 |
| } |
| { |
| name: rom_tl_d |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| end_idx: -1 |
| top_signame: rv_dm_rom_tl_d |
| index: -1 |
| } |
| ] |
| } |
| { |
| name: rv_plic |
| type: rv_plic |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: sys |
| } |
| attr: templated |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_secure |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: irq |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_plic |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_plic_irq |
| index: -1 |
| } |
| { |
| name: irq_id |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_plic |
| index: -1 |
| } |
| { |
| name: msip |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_plic |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_plic_msip |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_plic |
| default: "" |
| end_idx: -1 |
| top_signame: rv_plic_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x41010000 |
| } |
| } |
| { |
| name: aes |
| type: aes |
| clock_srcs: |
| { |
| clk_i: main |
| clk_edn_i: main |
| } |
| clock_group: trans |
| reset_connections: |
| { |
| rst_ni: sys |
| rst_edn_ni: sys |
| } |
| param_decl: |
| { |
| Masking: "1" |
| SBoxImpl: aes_pkg::SBoxImplDom |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_aes |
| clk_edn_i: clkmgr_aon_clocks.clk_main_aes |
| } |
| domain: "0" |
| memory: {} |
| param_list: |
| [ |
| { |
| name: AES192Enable |
| desc: Disable (0) or enable (1) support for 192-bit key lengths (AES-192). |
| type: bit |
| default: 1'b1 |
| expose: "false" |
| name_top: AesAES192Enable |
| } |
| { |
| name: Masking |
| desc: |
| ''' |
| Disable (0) or enable (1) first-order masking of the AES cipher core. |
| Masking requires the use of a masked S-Box, see SBoxImpl parameter. |
| ''' |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: AesMasking |
| } |
| { |
| name: SBoxImpl |
| desc: Selection of the S-Box implementation. See aes_pkg.sv. |
| type: aes_pkg::sbox_impl_e |
| default: aes_pkg::SBoxImplDom |
| expose: "true" |
| name_top: AesSBoxImpl |
| } |
| { |
| name: SecStartTriggerDelay |
| desc: |
| ''' |
| Manual start trigger delay, useful for SCA measurements. |
| A value of e.g. 40 allows the processor to go into sleep before AES starts operation. |
| ''' |
| type: int unsigned |
| default: "0" |
| expose: "true" |
| name_top: SecAesStartTriggerDelay |
| } |
| { |
| name: SecAllowForcingMasks |
| desc: |
| ''' |
| Forbid (0) or allow (1) forcing the mask to zero via FORCE_ZERO_MASK bit in the Control Register. |
| Useful for SCA measurements. |
| Meaningful only if masking is enabled. |
| ''' |
| type: bit |
| default: 1'b0 |
| expose: "true" |
| name_top: SecAesAllowForcingMasks |
| } |
| { |
| name: SecSkipPRNGReseeding |
| desc: |
| ''' |
| Perform (0) or skip (1) PRNG reseeding requests, useful for SCA measurements only. |
| The current SCA setup doesn't provide sufficient resources to implement the infrastructure required for PRNG reseeding (CSRNG, EDN). |
| To enable SCA resistance evaluations, we need to skip reseeding requests on the SCA platform. |
| ''' |
| type: bit |
| default: 1'b0 |
| expose: "true" |
| name_top: SecAesSkipPRNGReseeding |
| } |
| { |
| name: RndCnstClearingLfsrSeed |
| desc: Default seed of the PRNG used for register clearing. |
| type: aes_pkg::clearing_lfsr_seed_t |
| randcount: 64 |
| randtype: data |
| name_top: RndCnstAesClearingLfsrSeed |
| default: 0xed204633871cb178 |
| randwidth: 64 |
| } |
| { |
| name: RndCnstClearingLfsrPerm |
| desc: Permutation applied to the LFSR of the PRNG used for clearing. |
| type: aes_pkg::clearing_lfsr_perm_t |
| randcount: 64 |
| randtype: perm |
| name_top: RndCnstAesClearingLfsrPerm |
| default: 0x99b01e35560f2eb97e3047685d6b7bd87b029229da078df923f7d0f46154c34ba9d43c734af2a1eaa8e0f3270944e4d9 |
| randwidth: 384 |
| } |
| { |
| name: RndCnstClearingSharePerm |
| desc: Permutation applied to the clearing PRNG output for clearing the second share of registers. |
| type: aes_pkg::clearing_lfsr_perm_t |
| randcount: 64 |
| randtype: perm |
| name_top: RndCnstAesClearingSharePerm |
| default: 0x7d9cf783c36c02e6cbd0c89a7299bac245b9fb80c85367bb5e53c511341509877fb72286f4e9e3047871a354afad126a |
| randwidth: 384 |
| } |
| { |
| name: RndCnstMaskingLfsrSeed |
| desc: Default seed of the PRNG used for masking. |
| type: aes_pkg::masking_lfsr_seed_t |
| randcount: 160 |
| randtype: data |
| name_top: RndCnstAesMaskingLfsrSeed |
| default: 0xd6e49c544ba9dcdff0245e84d6f5f03ecaef7217 |
| randwidth: 160 |
| } |
| { |
| name: RndCnstMskgChunkLfsrPerm |
| desc: Permutation applied to the LFSR chunks of the PRNG used for masking. |
| type: aes_pkg::mskg_chunk_lfsr_perm_t |
| randcount: 32 |
| randtype: perm |
| name_top: RndCnstAesMskgChunkLfsrPerm |
| default: 0x46fa4bd6dc82beb0a4e30305aa371e9c64e2bf26 |
| randwidth: 160 |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: aes |
| default: "" |
| package: "" |
| top_signame: clkmgr_aon_idle |
| index: 0 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: aes |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: edn |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: aes |
| default: "" |
| top_signame: edn0_edn |
| index: 5 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: aes |
| default: "" |
| end_idx: -1 |
| top_signame: aes_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x41100000 |
| } |
| } |
| { |
| name: hmac |
| type: hmac |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: trans |
| reset_connections: |
| { |
| rst_ni: sys |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_hmac |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: hmac |
| default: "" |
| package: "" |
| top_signame: clkmgr_aon_idle |
| index: 1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: hmac |
| default: "" |
| end_idx: -1 |
| top_signame: hmac_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x41110000 |
| } |
| } |
| { |
| name: kmac |
| type: kmac |
| param_decl: |
| { |
| EnMasking: "1" |
| ReuseShare: "0" |
| } |
| clock_srcs: |
| { |
| clk_i: main |
| clk_edn_i: main |
| } |
| clock_group: trans |
| reset_connections: |
| { |
| rst_ni: sys |
| rst_edn_ni: sys |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_kmac |
| clk_edn_i: clkmgr_aon_clocks.clk_main_kmac |
| } |
| domain: "0" |
| memory: {} |
| param_list: |
| [ |
| { |
| name: EnMasking |
| desc: |
| ''' |
| Disable(0) or enable(1) first-order masking of Keccak round. |
| |
| If masking is enabled, ReuseShare parameter will impact the design. |
| ''' |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: KmacEnMasking |
| } |
| { |
| name: ReuseShare |
| desc: |
| ''' |
| If enabled (1), the internal Keccak round logic will re-use the |
| adjacent shares as entropy in Domain-Oriented Masking AND logic. |
| It improves the throughput of Keccak, as it only requires small |
| amount of entropy rather than 1600 bit per round. |
| |
| This feature is not implemented yet. |
| ''' |
| type: int |
| default: "0" |
| expose: "true" |
| name_top: KmacReuseShare |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: keymgr_key |
| struct: hw_key_req |
| package: keymgr_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: kmac |
| default: "" |
| top_signame: keymgr_kmac_key |
| index: -1 |
| } |
| { |
| name: app |
| struct: app |
| package: kmac_pkg |
| type: req_rsp |
| act: rsp |
| width: 3 |
| inst_name: kmac |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: kmac_app |
| index: -1 |
| } |
| { |
| name: entropy |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: kmac |
| default: "" |
| top_signame: edn0_edn |
| index: 3 |
| } |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: kmac |
| default: "" |
| package: "" |
| top_signame: clkmgr_aon_idle |
| index: 2 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: kmac |
| default: "" |
| end_idx: -1 |
| top_signame: kmac_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x41120000 |
| } |
| } |
| { |
| name: keymgr |
| type: keymgr |
| clock_srcs: |
| { |
| clk_i: main |
| clk_edn_i: main |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: sys |
| rst_edn_ni: sys |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_secure |
| clk_edn_i: clkmgr_aon_clocks.clk_main_secure |
| } |
| domain: "0" |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: RndCnstLfsrSeed |
| desc: Compile-time random bits for initial LFSR seed |
| type: keymgr_pkg::lfsr_seed_t |
| randcount: 64 |
| randtype: data |
| name_top: RndCnstKeymgrLfsrSeed |
| default: 0x8536e02c38ed5edf |
| randwidth: 64 |
| } |
| { |
| name: RndCnstLfsrPerm |
| desc: Compile-time random permutation for LFSR output |
| type: keymgr_pkg::lfsr_perm_t |
| randcount: 64 |
| randtype: perm |
| name_top: RndCnstKeymgrLfsrPerm |
| default: 0x6a27354364ad3bf532784c2725d903ee51f44fabb76f9fb3b2ff7145729959f821ae81803e317863c98b30854d042a6a |
| randwidth: 384 |
| } |
| { |
| name: RndCnstRandPerm |
| desc: Compile-time random permutation for entropy used in share overriding |
| type: keymgr_pkg::rand_perm_t |
| randcount: 32 |
| randtype: perm |
| name_top: RndCnstKeymgrRandPerm |
| default: 0x239b10b10987253b015a36f15153fe5dcf92f46f |
| randwidth: 160 |
| } |
| { |
| name: RndCnstRevisionSeed |
| desc: Compile-time random bits for revision seed |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrRevisionSeed |
| default: 0xcb8bed0d3e48713de5986d0027d13a3a480b63b97279d8d378486795de27f2cf |
| randwidth: 256 |
| } |
| { |
| name: RndCnstCreatorIdentitySeed |
| desc: Compile-time random bits for creator identity seed |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrCreatorIdentitySeed |
| default: 0x8127b8ee31063c01e9be104c7777ecc6d68e333feddeac133f24dd2e11738ceb |
| randwidth: 256 |
| } |
| { |
| name: RndCnstOwnerIntIdentitySeed |
| desc: Compile-time random bits for owner intermediate identity seed |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrOwnerIntIdentitySeed |
| default: 0xfcc7cc4ec8d98b59e767a253b29311c3e284411ee572a3934ffe951d3b79c1b3 |
| randwidth: 256 |
| } |
| { |
| name: RndCnstOwnerIdentitySeed |
| desc: Compile-time random bits for owner identity seed |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrOwnerIdentitySeed |
| default: 0x18800440bd414d266de08fc479f858040892b0f3729f7ab9dafe7f2472fb41c8 |
| randwidth: 256 |
| } |
| { |
| name: RndCnstSoftOutputSeed |
| desc: Compile-time random bits for software generation seed |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrSoftOutputSeed |
| default: 0x653fadb4aee4626498a4c647603c2154be52121d214556318c84c8ec175dab2f |
| randwidth: 256 |
| } |
| { |
| name: RndCnstHardOutputSeed |
| desc: Compile-time random bits for hardware generation seed |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrHardOutputSeed |
| default: 0xd5c72146d889aca6973a13272144f3eefeedd9d57e3f829a880463a023ca0c5e |
| randwidth: 256 |
| } |
| { |
| name: RndCnstAesSeed |
| desc: Compile-time random bits for generation seed when aes destination selected |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrAesSeed |
| default: 0x7663f6d1fbe7e4402c0329cac3b7d06751f2882df8f3259134067e7a112ffdb3 |
| randwidth: 256 |
| } |
| { |
| name: RndCnstHmacSeed |
| desc: Compile-time random bits for generation seed when hmac destination selected |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrHmacSeed |
| default: 0xbc5f1a8862845852761603352213b7a034816103a781d0a4f5a0a911c1bcafe |
| randwidth: 256 |
| } |
| { |
| name: RndCnstKmacSeed |
| desc: Compile-time random bits for generation seed when kmac destination selected |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrKmacSeed |
| default: 0x63dd2af7ca1c6ae78efcbdc6ada112f1235ee7dba5042c13061068c02cef00b7 |
| randwidth: 256 |
| } |
| { |
| name: RndCnstOtbnSeed |
| desc: Compile-time random bits for generation seed when otbn destination selected |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrOtbnSeed |
| default: 0x56289223d7e05db35983fe5a262a6e3ab1655d42b3090ae475a2df4171fdfd7c |
| randwidth: 256 |
| } |
| { |
| name: RndCnstNoneSeed |
| desc: Compile-time random bits for generation seed when no destination selected |
| type: keymgr_pkg::seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstKeymgrNoneSeed |
| default: 0xe9d1b1f891dcab64f5a52883a710b72b92e47f6e0845f450ead8f3095ff32c32 |
| randwidth: 256 |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: edn |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: edn0_edn |
| index: 0 |
| } |
| { |
| name: aes_key |
| struct: hw_key_req |
| package: keymgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: keymgr |
| index: -1 |
| } |
| { |
| name: hmac_key |
| struct: hw_key_req |
| package: keymgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: keymgr |
| index: -1 |
| } |
| { |
| name: kmac_key |
| struct: hw_key_req |
| package: keymgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: keymgr_kmac_key |
| index: -1 |
| } |
| { |
| name: otbn_key |
| struct: otbn_key_req |
| package: keymgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: keymgr |
| index: -1 |
| } |
| { |
| name: kmac_data |
| struct: app |
| package: kmac_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: kmac_app |
| index: 0 |
| } |
| { |
| name: otp_key |
| struct: otp_keymgr_key |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: otp_ctrl_otp_keymgr_key |
| index: -1 |
| } |
| { |
| name: otp_device_id |
| struct: otp_device_id |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: keymgr_otp_device_id |
| index: -1 |
| } |
| { |
| name: flash |
| struct: keymgr_flash |
| package: flash_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: flash_ctrl_keymgr |
| index: -1 |
| } |
| { |
| name: lc_keymgr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::On |
| inst_name: keymgr |
| top_signame: lc_ctrl_lc_keymgr_en |
| index: -1 |
| } |
| { |
| name: lc_keymgr_div |
| struct: lc_keymgr_div |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: lc_ctrl_lc_keymgr_div |
| index: -1 |
| } |
| { |
| name: rom_digest |
| struct: keymgr_data |
| package: rom_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: rom_ctrl_keymgr_data |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| end_idx: -1 |
| top_signame: keymgr_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x41130000 |
| } |
| } |
| { |
| name: csrng |
| type: csrng |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: sys |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_secure |
| } |
| domain: "0" |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: RndCnstCsKeymgrDivNonProduction |
| desc: Compile-time random bits for csrng state group diversification value |
| type: csrng_pkg::cs_keymgr_div_t |
| randcount: 384 |
| randtype: data |
| name_top: RndCnstCsrngCsKeymgrDivNonProduction |
| default: 0xb6fee0311af608b7123f603c251a36ab2e658548c5420be549da272d96ae771b3a1955e3d4549f3608232d03f93eed0f |
| randwidth: 384 |
| } |
| { |
| name: RndCnstCsKeymgrDivProduction |
| desc: Compile-time random bits for csrng state group diversification value |
| type: csrng_pkg::cs_keymgr_div_t |
| randcount: 384 |
| randtype: data |
| name_top: RndCnstCsrngCsKeymgrDivProduction |
| default: 0xcb942155264f8c121b7387a0a07db44fe8c330ca072829f9970f91074501568220e25ba7743095f2c1194fb74487a86 |
| randwidth: 384 |
| } |
| { |
| name: SBoxImpl |
| desc: Selection of the S-Box implementation. See aes_pkg.sv. |
| type: aes_pkg::sbox_impl_e |
| default: aes_pkg::SBoxImplCanright |
| expose: "true" |
| name_top: CsrngSBoxImpl |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: csrng_cmd |
| struct: csrng |
| package: csrng_pkg |
| type: req_rsp |
| act: rsp |
| width: 2 |
| inst_name: csrng |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: csrng_csrng_cmd |
| index: -1 |
| } |
| { |
| name: entropy_src_hw_if |
| struct: entropy_src_hw_if |
| package: entropy_src_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: csrng |
| default: "" |
| end_idx: -1 |
| top_signame: csrng_entropy_src_hw_if |
| index: -1 |
| } |
| { |
| name: cs_aes_halt |
| struct: cs_aes_halt |
| package: entropy_src_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: csrng |
| default: "" |
| end_idx: -1 |
| top_signame: csrng_cs_aes_halt |
| index: -1 |
| } |
| { |
| name: otp_en_csrng_sw_app_read |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: csrng |
| default: "" |
| top_signame: csrng_otp_en_csrng_sw_app_read |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: csrng |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: csrng |
| default: "" |
| end_idx: -1 |
| top_signame: csrng_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x41150000 |
| } |
| } |
| { |
| name: entropy_src |
| type: entropy_src |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: sys |
| } |
| clock_reset_export: |
| [ |
| ast |
| ] |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_secure |
| } |
| domain: "0" |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: Stub |
| desc: Stub out the core of entropy_src logic |
| type: bit |
| default: "0" |
| expose: "true" |
| name_top: EntropySrcStub |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: entropy_src_hw_if |
| struct: entropy_src_hw_if |
| package: entropy_src_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| top_signame: csrng_entropy_src_hw_if |
| index: -1 |
| } |
| { |
| name: cs_aes_halt |
| struct: cs_aes_halt |
| package: entropy_src_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| top_signame: csrng_cs_aes_halt |
| index: -1 |
| } |
| { |
| name: entropy_src_rng |
| struct: entropy_src_rng |
| package: entropy_src_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| external: true |
| top_signame: es_rng |
| index: -1 |
| } |
| { |
| name: entropy_src_xht |
| struct: entropy_src_xht |
| package: entropy_src_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: entropy_src |
| index: -1 |
| } |
| { |
| name: otp_en_entropy_src_fw_read |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| top_signame: entropy_src_otp_en_entropy_src_fw_read |
| index: -1 |
| } |
| { |
| name: otp_en_entropy_src_fw_over |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| top_signame: entropy_src_otp_en_entropy_src_fw_over |
| index: -1 |
| } |
| { |
| name: rng_fips |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| package: "" |
| external: true |
| top_signame: es_rng_fips |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| end_idx: -1 |
| top_signame: entropy_src_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x41160000 |
| } |
| } |
| { |
| name: edn0 |
| type: edn |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: sys |
| } |
| clock_reset_export: |
| [ |
| ast |
| ] |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_secure |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: csrng_cmd |
| desc: EDN supports a signal CSRNG application interface. |
| struct: csrng |
| package: csrng_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: edn0 |
| default: "" |
| top_signame: csrng_csrng_cmd |
| index: 0 |
| } |
| { |
| name: edn |
| desc: |
| ''' |
| The collection of peripheral ports supported by edn. The width (4) |
| indicates the number of peripheral ports on a single instance. |
| Due to limitations in the parametrization of top-level interconnects |
| this value is not currently parameterizable. However, the number |
| of peripheral ports may change in a future revision. |
| ''' |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: rsp |
| width: 7 |
| default: "'0" |
| inst_name: edn0 |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: edn0_edn |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: edn0 |
| default: "" |
| end_idx: -1 |
| top_signame: edn0_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x41170000 |
| } |
| } |
| { |
| name: edn1 |
| type: edn |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: sys |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_secure |
| } |
| domain: "0" |
| param_decl: {} |
| param_list: [] |
| inter_signal_list: |
| [ |
| { |
| name: csrng_cmd |
| desc: EDN supports a signal CSRNG application interface. |
| struct: csrng |
| package: csrng_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: edn1 |
| default: "" |
| top_signame: csrng_csrng_cmd |
| index: 1 |
| } |
| { |
| name: edn |
| desc: |
| ''' |
| The collection of peripheral ports supported by edn. The width (4) |
| indicates the number of peripheral ports on a single instance. |
| Due to limitations in the parametrization of top-level interconnects |
| this value is not currently parameterizable. However, the number |
| of peripheral ports may change in a future revision. |
| ''' |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: rsp |
| width: 7 |
| default: "'0" |
| inst_name: edn1 |
| end_idx: 1 |
| top_type: partial-one-to-N |
| top_signame: edn1_edn |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: edn1 |
| default: "" |
| end_idx: -1 |
| top_signame: edn1_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x41180000 |
| } |
| } |
| { |
| name: sram_ctrl_main |
| type: sram_ctrl |
| clock_srcs: |
| { |
| clk_i: main |
| clk_otp_i: io_div4 |
| } |
| clock_group: secure |
| reset_connections: |
| { |
| rst_ni: sys |
| rst_otp_ni: lc_io_div4 |
| } |
| param_decl: |
| { |
| InstrExec: "1" |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_secure |
| clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure |
| } |
| domain: "0" |
| memory: {} |
| param_list: |
| [ |
| { |
| name: RndCnstSramKey |
| desc: Compile-time random reset value for SRAM scrambling key. |
| type: otp_ctrl_pkg::sram_key_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstSramCtrlMainSramKey |
| default: 0x1dd6e62190d79f1230d02f643ac42fa7 |
| randwidth: 128 |
| } |
| { |
| name: RndCnstSramNonce |
| desc: Compile-time random reset value for SRAM scrambling nonce. |
| type: otp_ctrl_pkg::sram_nonce_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstSramCtrlMainSramNonce |
| default: 0x5120695530d16a94098e681252f1c774 |
| randwidth: 128 |
| } |
| { |
| name: RndCnstSramLfsrPerm |
| desc: Compile-time random permutation for LFSR output |
| type: sram_ctrl_pkg::lfsr_perm_t |
| randcount: 32 |
| randtype: perm |
| name_top: RndCnstSramCtrlMainSramLfsrPerm |
| default: 0x2dc87cedcba3e48e7595fc2221a74051acdc4fc1 |
| randwidth: 160 |
| } |
| { |
| name: InstrExec |
| desc: Support execution from SRAM |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: SramCtrlMainInstrExec |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: sram_otp_key |
| struct: sram_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_main |
| top_signame: otp_ctrl_sram_otp_key |
| index: 0 |
| } |
| { |
| name: sram_scr |
| struct: sram_scr |
| package: sram_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_main |
| end_idx: -1 |
| top_signame: sram_ctrl_main_sram_scr |
| index: -1 |
| } |
| { |
| name: sram_scr_init |
| struct: sram_scr_init |
| package: sram_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_main |
| end_idx: -1 |
| top_signame: sram_ctrl_main_sram_scr_init |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: sram_ctrl_main |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: sram_ctrl_main |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: otp_en_sram_ifetch |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_main |
| top_signame: sram_ctrl_main_otp_en_sram_ifetch |
| index: -1 |
| } |
| { |
| name: en_ifetch |
| struct: tl_instr_en |
| package: tlul_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sram_ctrl_main |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: sram_ctrl_main_en_ifetch |
| index: -1 |
| } |
| { |
| name: intg_error |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: sram_ctrl_main |
| default: "" |
| package: "" |
| top_signame: ram_main_intg_error |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sram_ctrl_main |
| default: "" |
| end_idx: -1 |
| top_signame: sram_ctrl_main_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x411C0000 |
| } |
| } |
| { |
| name: otbn |
| type: otbn |
| clock_srcs: |
| { |
| clk_i: main |
| clk_edn_i: main |
| clk_otp_i: io_div4 |
| } |
| clock_group: trans |
| reset_connections: |
| { |
| rst_ni: sys |
| rst_edn_ni: sys |
| rst_otp_ni: lc_io_div4 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_otbn |
| clk_edn_i: clkmgr_aon_clocks.clk_main_otbn |
| clk_otp_i: clkmgr_aon_clocks.clk_io_div4_otbn |
| } |
| domain: "0" |
| param_decl: {} |
| memory: {} |
| param_list: |
| [ |
| { |
| name: Stub |
| desc: Stub out the core of Otbn logic |
| type: bit |
| default: "0" |
| expose: "true" |
| name_top: OtbnStub |
| } |
| { |
| name: RegFile |
| desc: Selection of the register file implementation. See otbn_pkg.sv. |
| type: otbn_pkg::regfile_e |
| default: otbn_pkg::RegFileFF |
| expose: "true" |
| name_top: OtbnRegFile |
| } |
| { |
| name: RndCnstUrndLfsrSeed |
| desc: Default seed of the PRNG used for URND. |
| type: otbn_pkg::urnd_lfsr_seed_t |
| randcount: 256 |
| randtype: data |
| name_top: RndCnstOtbnUrndLfsrSeed |
| default: 0x983d914e80a925bc15891b60c560a7fb75457e09e258c252c3083125be14e22d |
| randwidth: 256 |
| } |
| { |
| name: RndCnstUrndChunkLfsrPerm |
| desc: Permutation applied to the LFSR chunks of the PRNG used for URND. |
| type: otbn_pkg::urnd_chunk_lfsr_perm_t |
| randcount: 64 |
| randtype: perm |
| name_top: RndCnstOtbnUrndChunkLfsrPerm |
| default: 0x7e95af64caa87b2e1aed74700fc12c9793c18dcd269ce74beab6096c81addee885340fbd2900a4513cff852d47560db1 |
| randwidth: 384 |
| } |
| { |
| name: RndCnstOtbnKey |
| desc: Compile-time random reset value for IMem/DMem scrambling key. |
| type: otp_ctrl_pkg::otbn_key_t |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstOtbnOtbnKey |
| default: 0xfd9c13ac08496db56fbc4894d38bd867 |
| randwidth: 128 |
| } |
| { |
| name: RndCnstOtbnNonce |
| desc: Compile-time random reset value for IMem/DMem scrambling nonce. |
| type: otp_ctrl_pkg::otbn_nonce_t |
| randcount: 64 |
| randtype: data |
| name_top: RndCnstOtbnOtbnNonce |
| default: 0x9e4da0e3ff9f3036 |
| randwidth: 64 |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: otbn_otp_key |
| struct: otbn_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otbn |
| top_signame: otp_ctrl_otbn_otp_key |
| index: -1 |
| } |
| { |
| name: edn_rnd |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: otbn |
| default: "" |
| top_signame: edn1_edn |
| index: 0 |
| } |
| { |
| name: edn_urnd |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: otbn |
| default: "" |
| top_signame: edn0_edn |
| index: 6 |
| } |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: otbn |
| default: "" |
| package: "" |
| top_signame: clkmgr_aon_idle |
| index: 3 |
| } |
| { |
| name: ram_cfg |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: otbn |
| default: "" |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otbn |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: otbn |
| default: "" |
| end_idx: -1 |
| top_signame: otbn_tl |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| null: 0x411D0000 |
| } |
| } |
| { |
| name: rom_ctrl |
| type: rom_ctrl |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: infra |
| reset_connections: |
| { |
| rst_ni: sys |
| } |
| base_addrs: |
| { |
| rom: 0x00008000 |
| regs: 0x411e0000 |
| } |
| memory: |
| { |
| rom: |
| { |
| label: rom |
| swaccess: rx |
| size: 0x4000 |
| } |
| } |
| param_decl: |
| { |
| SecDisableScrambling: 1'b0 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_infra |
| } |
| domain: "0" |
| param_list: |
| [ |
| { |
| name: BootRomInitFile |
| desc: Contents of mask ROM |
| type: "" |
| default: '''""''' |
| expose: "true" |
| name_top: RomCtrlBootRomInitFile |
| } |
| { |
| name: RndCnstScrNonce |
| desc: Fixed nonce used for address / data scrambling |
| type: bit [63:0] |
| randcount: 64 |
| randtype: data |
| name_top: RndCnstRomCtrlScrNonce |
| default: 0x5d7717a4b76a8aff |
| randwidth: 64 |
| } |
| { |
| name: RndCnstScrKey |
| desc: Randomised constant used as a scrambling key for ROM data |
| type: bit [127:0] |
| randcount: 128 |
| randtype: data |
| name_top: RndCnstRomCtrlScrKey |
| default: 0xb798ab7845c3feab0d2f4c7cf730a567 |
| randwidth: 128 |
| } |
| { |
| name: SecDisableScrambling |
| desc: |
| ''' |
| Disable scrambling and checking in rom_ctrl, turning the block into a |
| simple ROM wrapper. This isn't intended for real chips, but is useful |
| for small FPGA targets where there's not space for the PRINCE |
| primitives. |
| ''' |
| type: bit |
| default: 1'b0 |
| expose: "true" |
| name_top: SecRomCtrlDisableScrambling |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: rom_cfg |
| struct: rom_cfg |
| package: prim_rom_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| top_signame: ast_rom_cfg |
| index: -1 |
| } |
| { |
| name: pwrmgr_data |
| struct: pwrmgr_data |
| package: rom_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rom_ctrl_pwrmgr_data |
| index: -1 |
| } |
| { |
| name: keymgr_data |
| struct: keymgr_data |
| package: rom_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rom_ctrl_keymgr_data |
| index: -1 |
| } |
| { |
| name: kmac_data |
| struct: app |
| package: kmac_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| top_signame: kmac_app |
| index: 2 |
| } |
| { |
| name: regs_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: rom_ctrl_regs_tl |
| index: -1 |
| } |
| { |
| name: rom_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: rom_ctrl_rom_tl |
| index: -1 |
| } |
| ] |
| } |
| { |
| name: rv_core_ibex |
| type: rv_core_ibex |
| param_decl: |
| { |
| PMPEnable: "1" |
| PMPGranularity: "0" |
| PMPNumRegions: "16" |
| MHPMCounterNum: "10" |
| MHPMCounterWidth: "32" |
| RV32E: "0" |
| RV32M: ibex_pkg::RV32MSingleCycle |
| RV32B: ibex_pkg::RV32BNone |
| RegFile: ibex_pkg::RegFileFF |
| BranchTargetALU: "1" |
| WritebackStage: "1" |
| ICache: "1" |
| ICacheECC: "1" |
| BranchPredictor: "0" |
| DbgTriggerEn: "1" |
| SecureIbex: "1" |
| DmHaltAddr: tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0] |
| DmExceptionAddr: tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::ExceptionAddress[31:0] |
| PipeLine: "0" |
| } |
| clock_srcs: |
| { |
| clk_i: main |
| clk_esc_i: io_div4 |
| } |
| clock_group: infra |
| reset_connections: |
| { |
| rst_ni: sys |
| rst_esc_ni: lc_io_div4 |
| } |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_infra |
| clk_esc_i: clkmgr_aon_clocks.clk_io_div4_infra |
| } |
| domain: "0" |
| memory: {} |
| param_list: |
| [ |
| { |
| name: PMPEnable |
| desc: Enable PMP |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: RvCoreIbexPMPEnable |
| } |
| { |
| name: PMPGranularity |
| type: int unsigned |
| default: "0" |
| expose: "true" |
| name_top: RvCoreIbexPMPGranularity |
| } |
| { |
| name: PMPNumRegions |
| type: int unsigned |
| default: "16" |
| expose: "true" |
| name_top: RvCoreIbexPMPNumRegions |
| } |
| { |
| name: MHPMCounterNum |
| type: int unsigned |
| default: "10" |
| expose: "true" |
| name_top: RvCoreIbexMHPMCounterNum |
| } |
| { |
| name: MHPMCounterWidth |
| type: int unsigned |
| default: "32" |
| expose: "true" |
| name_top: RvCoreIbexMHPMCounterWidth |
| } |
| { |
| name: RV32E |
| type: bit |
| default: "0" |
| expose: "true" |
| name_top: RvCoreIbexRV32E |
| } |
| { |
| name: RV32M |
| type: ibex_pkg::rv32m_e |
| default: ibex_pkg::RV32MSingleCycle |
| expose: "true" |
| name_top: RvCoreIbexRV32M |
| } |
| { |
| name: RV32B |
| type: ibex_pkg::rv32b_e |
| default: ibex_pkg::RV32BNone |
| expose: "true" |
| name_top: RvCoreIbexRV32B |
| } |
| { |
| name: RegFile |
| type: ibex_pkg::regfile_e |
| default: ibex_pkg::RegFileFF |
| expose: "true" |
| name_top: RvCoreIbexRegFile |
| } |
| { |
| name: BranchTargetALU |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: RvCoreIbexBranchTargetALU |
| } |
| { |
| name: WritebackStage |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: RvCoreIbexWritebackStage |
| } |
| { |
| name: ICache |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: RvCoreIbexICache |
| } |
| { |
| name: ICacheECC |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: RvCoreIbexICacheECC |
| } |
| { |
| name: BranchPredictor |
| type: bit |
| default: "0" |
| expose: "true" |
| name_top: RvCoreIbexBranchPredictor |
| } |
| { |
| name: DbgTriggerEn |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: RvCoreIbexDbgTriggerEn |
| } |
| { |
| name: SecureIbex |
| type: bit |
| default: "1" |
| expose: "true" |
| name_top: SecRvCoreIbexureIbex |
| } |
| { |
| name: DmHaltAddr |
| type: int unsigned |
| default: tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0] |
| expose: "true" |
| name_top: RvCoreIbexDmHaltAddr |
| } |
| { |
| name: DmExceptionAddr |
| type: int unsigned |
| default: tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::ExceptionAddress[31:0] |
| expose: "true" |
| name_top: RvCoreIbexDmExceptionAddr |
| } |
| { |
| name: PipeLine |
| type: bit |
| default: "0" |
| expose: "true" |
| name_top: RvCoreIbexPipeLine |
| } |
| ] |
| inter_signal_list: |
| [ |
| { |
| name: rst_cpu_n |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_core_ibex_rst_cpu_n |
| index: -1 |
| } |
| { |
| name: ram_cfg |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| } |
| { |
| name: hart_id |
| struct: logic |
| type: uni |
| act: rcv |
| width: 32 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_core_ibex_hart_id |
| index: -1 |
| } |
| { |
| name: boot_addr |
| struct: logic |
| type: uni |
| act: rcv |
| width: 32 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_core_ibex_boot_addr |
| index: -1 |
| } |
| { |
| name: irq_software |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_plic_msip |
| index: -1 |
| } |
| { |
| name: irq_timer |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_core_ibex_irq_timer |
| index: -1 |
| } |
| { |
| name: irq_external |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_plic_irq |
| index: -1 |
| } |
| { |
| name: esc_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 0 |
| } |
| { |
| name: esc_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 0 |
| } |
| { |
| name: debug_req |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_dm_debug_req |
| index: -1 |
| } |
| { |
| name: crash_dump |
| struct: crash_dump |
| package: ibex_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_core_ibex_crash_dump |
| index: -1 |
| } |
| { |
| name: lc_cpu_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: lc_ctrl_lc_cpu_en |
| index: -1 |
| } |
| { |
| name: pwrmgr_cpu_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: pwrmgr_aon_fetch_en |
| index: -1 |
| } |
| { |
| name: pwrmgr |
| struct: pwr_cpu |
| package: pwrmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_core_ibex_pwrmgr |
| index: -1 |
| } |
| { |
| name: corei_tl_h |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: main_tl_rv_core_ibex__corei |
| index: -1 |
| } |
| { |
| name: cored_tl_h |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: main_tl_rv_core_ibex__cored |
| index: -1 |
| } |
| { |
| name: cfg_tl_d |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| end_idx: -1 |
| top_signame: rv_core_ibex_cfg_tl_d |
| index: -1 |
| } |
| ] |
| base_addrs: |
| { |
| cfg: 0x411F0000 |
| } |
| } |
| ] |
| memory: |
| [ |
| { |
| name: ram_main |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: infra |
| reset_connections: |
| { |
| rst_ni: sys |
| } |
| type: ram_1p_scr |
| base_addr: 0x10000000 |
| size: 0x20000 |
| byte_write: "true" |
| integ_width: 7 |
| exec: "1" |
| inter_signal_list: |
| [ |
| { |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| name: tl |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_signame: ram_main_tl |
| index: -1 |
| } |
| { |
| struct: sram_scr |
| package: sram_ctrl_pkg |
| type: req_rsp |
| name: sram_scr |
| act: rsp |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_main_sram_scr |
| index: -1 |
| } |
| { |
| struct: sram_scr_init |
| package: sram_ctrl_pkg |
| type: req_rsp |
| name: sram_scr_init |
| act: rsp |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_main_sram_scr_init |
| index: -1 |
| } |
| { |
| struct: tl_instr_en |
| package: tlul_pkg |
| type: uni |
| name: en_ifetch |
| act: rcv |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_main_en_ifetch |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| name: intg_error |
| act: req |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ram_main_intg_error |
| index: -1 |
| } |
| { |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| name: cfg |
| act: rcv |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| } |
| ] |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_infra |
| } |
| domain: "0" |
| } |
| { |
| name: ram_ret_aon |
| clock_srcs: |
| { |
| clk_i: io_div4 |
| } |
| clock_group: infra |
| reset_connections: |
| { |
| rst_ni: sys_io_div4 |
| } |
| domain: Aon |
| type: ram_1p_scr |
| base_addr: 0x40600000 |
| size: 0x1000 |
| byte_write: "true" |
| integ_width: 7 |
| exec: "0" |
| inter_signal_list: |
| [ |
| { |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| name: tl |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_signame: ram_ret_aon_tl |
| index: -1 |
| } |
| { |
| struct: sram_scr |
| package: sram_ctrl_pkg |
| type: req_rsp |
| name: sram_scr |
| act: rsp |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_ret_aon_sram_scr |
| index: -1 |
| } |
| { |
| struct: sram_scr_init |
| package: sram_ctrl_pkg |
| type: req_rsp |
| name: sram_scr_init |
| act: rsp |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_ret_aon_sram_scr_init |
| index: -1 |
| } |
| { |
| struct: tl_instr_en |
| package: tlul_pkg |
| type: uni |
| name: en_ifetch |
| act: rcv |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_ret_aon_en_ifetch |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| name: intg_error |
| act: req |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ram_ret_aon_intg_error |
| index: -1 |
| } |
| { |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| name: cfg |
| act: rcv |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| } |
| ] |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_io_div4_infra |
| } |
| } |
| { |
| name: eflash |
| clock_srcs: |
| { |
| clk_i: main |
| } |
| clock_group: infra |
| reset_connections: |
| { |
| rst_ni: lc |
| } |
| type: eflash |
| base_addr: 0x20000000 |
| banks: 2 |
| pages_per_bank: 256 |
| program_resolution: 8 |
| swaccess: ro |
| inter_signal_list: |
| [ |
| { |
| struct: flash |
| type: req_rsp |
| name: flash_ctrl |
| act: rsp |
| inst_name: eflash |
| width: 1 |
| default: "" |
| package: flash_ctrl_pkg |
| top_signame: flash_ctrl_flash |
| index: -1 |
| } |
| { |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| name: tl |
| inst_name: eflash |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_signame: eflash_tl |
| index: -1 |
| } |
| { |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| name: lc_nvm_debug_en |
| inst_name: eflash |
| width: 1 |
| default: "" |
| top_signame: lc_ctrl_lc_nvm_debug_en |
| index: -1 |
| } |
| { |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| name: flash_bist_enable |
| inst_name: eflash |
| width: 1 |
| default: "" |
| external: true |
| top_signame: flash_bist_enable |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| act: rcv |
| name: flash_power_down_h |
| inst_name: eflash |
| width: 1 |
| default: "" |
| external: true |
| top_signame: flash_power_down_h |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| act: rcv |
| name: flash_power_ready_h |
| inst_name: eflash |
| width: 1 |
| default: "" |
| external: true |
| top_signame: flash_power_ready_h |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| width: "4" |
| type: uni |
| act: rcv |
| name: flash_test_mode_a |
| inst_name: eflash |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| act: rcv |
| name: flash_test_voltage_h |
| inst_name: eflash |
| index: -1 |
| } |
| { |
| struct: ast_dif |
| package: ast_pkg |
| type: uni |
| act: req |
| name: flash_alert |
| inst_name: eflash |
| width: 1 |
| default: "" |
| external: true |
| top_signame: flash_alert |
| index: -1 |
| } |
| ] |
| clock_connections: |
| { |
| clk_i: clkmgr_aon_clocks.clk_main_infra |
| } |
| words_per_page: 256 |
| data_width: 64 |
| metadata_width: 12 |
| info_types: 3 |
| infos_per_bank: |
| [ |
| 10 |
| 1 |
| 2 |
| ] |
| size: 0x100000 |
| pgm_resolution_bytes: 64 |
| domain: "0" |
| } |
| ] |
| port: |
| [ |
| { |
| name: ast |
| inter_signal_list: |
| [ |
| { |
| struct: edn |
| type: req_rsp |
| name: edn |
| act: rsp |
| package: edn_pkg |
| inst_name: ast |
| width: 1 |
| default: "" |
| top_signame: edn0_edn |
| index: 2 |
| external: true |
| } |
| { |
| struct: lc_tx |
| type: uni |
| name: lc_dft_en |
| act: req |
| package: lc_ctrl_pkg |
| inst_name: ast |
| width: 1 |
| default: "" |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| external: true |
| } |
| { |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| name: ram_1p_cfg |
| act: rcv |
| inst_name: ast |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| external: true |
| } |
| { |
| struct: ram_2p_cfg |
| package: prim_ram_2p_pkg |
| type: uni |
| name: ram_2p_cfg |
| act: rcv |
| inst_name: ast |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ast_ram_2p_cfg |
| index: -1 |
| external: true |
| } |
| { |
| struct: rom_cfg |
| package: prim_rom_pkg |
| type: uni |
| name: rom_cfg |
| act: rcv |
| inst_name: ast |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ast_rom_cfg |
| index: -1 |
| external: true |
| } |
| ] |
| } |
| ] |
| inter_module: |
| { |
| connect: |
| { |
| ast.ram_1p_cfg: |
| [ |
| otbn.ram_cfg |
| ram_main.cfg |
| ram_ret_aon.cfg |
| rv_core_ibex.ram_cfg |
| ] |
| ast.ram_2p_cfg: |
| [ |
| spi_device.ram_cfg |
| usbdev.ram_cfg |
| ] |
| ast.rom_cfg: |
| [ |
| rom_ctrl.rom_cfg |
| ] |
| alert_handler.crashdump: |
| [ |
| rstmgr_aon.alert_dump |
| ] |
| alert_handler.esc_rx: |
| [ |
| rv_core_ibex.esc_rx |
| lc_ctrl.esc_scrap_state0_rx |
| lc_ctrl.esc_scrap_state1_rx |
| pwrmgr_aon.esc_rst_rx |
| ] |
| alert_handler.esc_tx: |
| [ |
| rv_core_ibex.esc_tx |
| lc_ctrl.esc_scrap_state0_tx |
| lc_ctrl.esc_scrap_state1_tx |
| pwrmgr_aon.esc_rst_tx |
| ] |
| csrng.csrng_cmd: |
| [ |
| edn0.csrng_cmd |
| edn1.csrng_cmd |
| ] |
| csrng.entropy_src_hw_if: |
| [ |
| entropy_src.entropy_src_hw_if |
| ] |
| csrng.cs_aes_halt: |
| [ |
| entropy_src.cs_aes_halt |
| ] |
| flash_ctrl.flash: |
| [ |
| eflash.flash_ctrl |
| ] |
| flash_ctrl.keymgr: |
| [ |
| keymgr.flash |
| ] |
| flash_ctrl.otp: |
| [ |
| otp_ctrl.flash_otp_key |
| ] |
| flash_ctrl.rma_req: |
| [ |
| lc_ctrl.lc_flash_rma_req |
| ] |
| flash_ctrl.rma_ack: |
| [ |
| lc_ctrl.lc_flash_rma_ack |
| ] |
| flash_ctrl.rma_seed: |
| [ |
| lc_ctrl.lc_flash_rma_seed |
| ] |
| sram_ctrl_main.sram_scr: |
| [ |
| ram_main.sram_scr |
| ] |
| sram_ctrl_main.sram_scr_init: |
| [ |
| ram_main.sram_scr_init |
| ] |
| sram_ctrl_ret_aon.sram_scr: |
| [ |
| ram_ret_aon.sram_scr |
| ] |
| sram_ctrl_ret_aon.sram_scr_init: |
| [ |
| ram_ret_aon.sram_scr_init |
| ] |
| sram_ctrl_main.en_ifetch: |
| [ |
| ram_main.en_ifetch |
| ] |
| sram_ctrl_ret_aon.en_ifetch: |
| [ |
| ram_ret_aon.en_ifetch |
| ] |
| ram_main.intg_error: |
| [ |
| sram_ctrl_main.intg_error |
| ] |
| ram_ret_aon.intg_error: |
| [ |
| sram_ctrl_ret_aon.intg_error |
| ] |
| otp_ctrl.sram_otp_key: |
| [ |
| sram_ctrl_main.sram_otp_key |
| sram_ctrl_ret_aon.sram_otp_key |
| ] |
| pwrmgr_aon.pwr_flash: |
| [ |
| flash_ctrl.pwrmgr |
| ] |
| pwrmgr_aon.pwr_rst: |
| [ |
| rstmgr_aon.pwr |
| ] |
| pwrmgr_aon.pwr_clk: |
| [ |
| clkmgr_aon.pwr |
| ] |
| pwrmgr_aon.pwr_otp: |
| [ |
| otp_ctrl.pwr_otp |
| ] |
| pwrmgr_aon.pwr_lc: |
| [ |
| lc_ctrl.pwr_lc |
| ] |
| pwrmgr_aon.strap: |
| [ |
| pinmux_aon.strap_en |
| ] |
| pwrmgr_aon.low_power: |
| [ |
| pinmux_aon.sleep_en |
| aon_timer_aon.sleep_mode |
| ] |
| pwrmgr_aon.fetch_en: |
| [ |
| rv_core_ibex.pwrmgr_cpu_en |
| ] |
| rom_ctrl.pwrmgr_data: |
| [ |
| pwrmgr_aon.rom_ctrl |
| ] |
| rom_ctrl.keymgr_data: |
| [ |
| keymgr.rom_digest |
| ] |
| usbdev.usb_out_of_rst: |
| [ |
| pinmux_aon.usb_out_of_rst |
| ] |
| usbdev.usb_aon_wake_en: |
| [ |
| pinmux_aon.usb_aon_wake_en |
| ] |
| usbdev.usb_aon_wake_ack: |
| [ |
| pinmux_aon.usb_aon_wake_ack |
| ] |
| usbdev.usb_suspend: |
| [ |
| pinmux_aon.usb_suspend |
| ] |
| pinmux_aon.usb_state_debug: |
| [ |
| usbdev.usb_state_debug |
| ] |
| edn0.edn: |
| [ |
| keymgr.edn |
| otp_ctrl.edn |
| ast.edn |
| kmac.entropy |
| alert_handler.edn |
| aes.edn |
| otbn.edn_urnd |
| ] |
| edn1.edn: |
| [ |
| otbn.edn_rnd |
| ] |
| otp_ctrl.otbn_otp_key: |
| [ |
| otbn.otbn_otp_key |
| ] |
| otp_ctrl.otp_keymgr_key: |
| [ |
| keymgr.otp_key |
| ] |
| keymgr.kmac_key: |
| [ |
| kmac.keymgr_key |
| ] |
| kmac.app: |
| [ |
| keymgr.kmac_data |
| lc_ctrl.kmac_data |
| rom_ctrl.kmac_data |
| ] |
| clkmgr_aon.idle: |
| [ |
| aes.idle |
| hmac.idle |
| kmac.idle |
| otbn.idle |
| ] |
| pinmux_aon.lc_jtag: |
| [ |
| lc_ctrl.jtag |
| ] |
| pinmux_aon.rv_jtag: |
| [ |
| rv_dm.jtag |
| ] |
| otp_ctrl.otp_lc_data: |
| [ |
| lc_ctrl.otp_lc_data |
| ] |
| lc_ctrl.lc_otp_program: |
| [ |
| otp_ctrl.lc_otp_program |
| ] |
| lc_ctrl.lc_keymgr_div: |
| [ |
| keymgr.lc_keymgr_div |
| ] |
| lc_ctrl.lc_dft_en: |
| [ |
| otp_ctrl.lc_dft_en |
| pinmux_aon.lc_dft_en |
| ast.lc_dft_en |
| clkmgr_aon.lc_dft_en |
| ] |
| lc_ctrl.lc_nvm_debug_en: |
| [ |
| eflash.lc_nvm_debug_en |
| ] |
| lc_ctrl.lc_hw_debug_en: |
| [ |
| sram_ctrl_main.lc_hw_debug_en |
| sram_ctrl_ret_aon.lc_hw_debug_en |
| pinmux_aon.lc_hw_debug_en |
| csrng.lc_hw_debug_en |
| rv_dm.lc_hw_debug_en |
| ] |
| lc_ctrl.lc_cpu_en: |
| [ |
| rv_core_ibex.lc_cpu_en |
| ] |
| lc_ctrl.lc_keymgr_en: |
| [ |
| keymgr.lc_keymgr_en |
| ] |
| lc_ctrl.lc_escalate_en: |
| [ |
| aes.lc_escalate_en |
| otbn.lc_escalate_en |
| otp_ctrl.lc_escalate_en |
| sram_ctrl_main.lc_escalate_en |
| sram_ctrl_ret_aon.lc_escalate_en |
| aon_timer_aon.lc_escalate_en |
| flash_ctrl.lc_escalate_en |
| ] |
| lc_ctrl.lc_check_byp_en: |
| [ |
| otp_ctrl.lc_check_byp_en |
| ] |
| lc_ctrl.lc_clk_byp_req: |
| [ |
| clkmgr_aon.lc_clk_byp_req |
| ] |
| lc_ctrl.lc_clk_byp_ack: |
| [ |
| clkmgr_aon.lc_clk_byp_ack |
| ] |
| lc_ctrl.lc_creator_seed_sw_rw_en: |
| [ |
| otp_ctrl.lc_creator_seed_sw_rw_en |
| flash_ctrl.lc_creator_seed_sw_rw_en |
| ] |
| lc_ctrl.lc_owner_seed_sw_rw_en: |
| [ |
| flash_ctrl.lc_owner_seed_sw_rw_en |
| ] |
| lc_ctrl.lc_iso_part_sw_rd_en: |
| [ |
| flash_ctrl.lc_iso_part_sw_rd_en |
| ] |
| lc_ctrl.lc_iso_part_sw_wr_en: |
| [ |
| flash_ctrl.lc_iso_part_sw_wr_en |
| ] |
| lc_ctrl.lc_seed_hw_rd_en: |
| [ |
| otp_ctrl.lc_seed_hw_rd_en |
| flash_ctrl.lc_seed_hw_rd_en |
| ] |
| rv_plic.msip: |
| [ |
| rv_core_ibex.irq_software |
| ] |
| rv_plic.irq: |
| [ |
| rv_core_ibex.irq_external |
| ] |
| rv_dm.debug_req: |
| [ |
| rv_core_ibex.debug_req |
| ] |
| rv_core_ibex.rst_cpu_n: |
| [ |
| rstmgr_aon.rst_cpu_n |
| ] |
| rv_core_ibex.crash_dump: |
| [ |
| rstmgr_aon.cpu_dump |
| ] |
| rv_core_ibex.pwrmgr: |
| [ |
| pwrmgr_aon.pwr_cpu |
| ] |
| spi_device.passthrough: |
| [ |
| spi_host0.passthrough |
| ] |
| rv_dm.ndmreset_req: |
| [ |
| rstmgr_aon.ndmreset_req |
| ] |
| pwrmgr_aon.wakeups: |
| [ |
| sysrst_ctrl_aon.gsc_wk |
| adc_ctrl_aon.debug_cable_wakeup |
| pinmux_aon.aon_wkup_req |
| pinmux_aon.usb_wkup_req |
| aon_timer_aon.aon_timer_wkup_req |
| ] |
| pwrmgr_aon.rstreqs: |
| [ |
| sysrst_ctrl_aon.gsc_rst |
| aon_timer_aon.aon_timer_rst_req |
| ] |
| main.tl_rv_core_ibex__corei: |
| [ |
| rv_core_ibex.corei_tl_h |
| ] |
| main.tl_rv_core_ibex__cored: |
| [ |
| rv_core_ibex.cored_tl_h |
| ] |
| main.tl_rv_dm__sba: |
| [ |
| rv_dm.sba_tl_h |
| ] |
| rv_dm.regs_tl_d: |
| [ |
| main.tl_rv_dm__regs |
| ] |
| rv_dm.rom_tl_d: |
| [ |
| main.tl_rv_dm__rom |
| ] |
| rom_ctrl.rom_tl: |
| [ |
| main.tl_rom_ctrl__rom |
| ] |
| rom_ctrl.regs_tl: |
| [ |
| main.tl_rom_ctrl__regs |
| ] |
| ram_main.tl: |
| [ |
| main.tl_ram_main |
| ] |
| eflash.tl: |
| [ |
| main.tl_eflash |
| ] |
| main.tl_peri: |
| [ |
| peri.tl_main |
| ] |
| flash_ctrl.core_tl: |
| [ |
| main.tl_flash_ctrl__core |
| ] |
| flash_ctrl.prim_tl: |
| [ |
| main.tl_flash_ctrl__prim |
| ] |
| hmac.tl: |
| [ |
| main.tl_hmac |
| ] |
| kmac.tl: |
| [ |
| main.tl_kmac |
| ] |
| aes.tl: |
| [ |
| main.tl_aes |
| ] |
| entropy_src.tl: |
| [ |
| main.tl_entropy_src |
| ] |
| csrng.tl: |
| [ |
| main.tl_csrng |
| ] |
| edn0.tl: |
| [ |
| main.tl_edn0 |
| ] |
| edn1.tl: |
| [ |
| main.tl_edn1 |
| ] |
| rv_plic.tl: |
| [ |
| main.tl_rv_plic |
| ] |
| otbn.tl: |
| [ |
| main.tl_otbn |
| ] |
| keymgr.tl: |
| [ |
| main.tl_keymgr |
| ] |
| rv_core_ibex.cfg_tl_d: |
| [ |
| main.tl_rv_core_ibex__cfg |
| ] |
| sram_ctrl_main.tl: |
| [ |
| main.tl_sram_ctrl_main |
| ] |
| uart0.tl: |
| [ |
| peri.tl_uart0 |
| ] |
| uart1.tl: |
| [ |
| peri.tl_uart1 |
| ] |
| uart2.tl: |
| [ |
| peri.tl_uart2 |
| ] |
| uart3.tl: |
| [ |
| peri.tl_uart3 |
| ] |
| i2c0.tl: |
| [ |
| peri.tl_i2c0 |
| ] |
| i2c1.tl: |
| [ |
| peri.tl_i2c1 |
| ] |
| i2c2.tl: |
| [ |
| peri.tl_i2c2 |
| ] |
| pattgen.tl: |
| [ |
| peri.tl_pattgen |
| ] |
| pwm_aon.tl: |
| [ |
| peri.tl_pwm_aon |
| ] |
| gpio.tl: |
| [ |
| peri.tl_gpio |
| ] |
| spi_device.tl: |
| [ |
| peri.tl_spi_device |
| ] |
| spi_host0.tl: |
| [ |
| peri.tl_spi_host0 |
| ] |
| spi_host1.tl: |
| [ |
| peri.tl_spi_host1 |
| ] |
| rv_timer.tl: |
| [ |
| peri.tl_rv_timer |
| ] |
| usbdev.tl: |
| [ |
| peri.tl_usbdev |
| ] |
| pwrmgr_aon.tl: |
| [ |
| peri.tl_pwrmgr_aon |
| ] |
| rstmgr_aon.tl: |
| [ |
| peri.tl_rstmgr_aon |
| ] |
| clkmgr_aon.tl: |
| [ |
| peri.tl_clkmgr_aon |
| ] |
| pinmux_aon.tl: |
| [ |
| peri.tl_pinmux_aon |
| ] |
| ram_ret_aon.tl: |
| [ |
| peri.tl_ram_ret_aon |
| ] |
| otp_ctrl.core_tl: |
| [ |
| peri.tl_otp_ctrl__core |
| ] |
| otp_ctrl.prim_tl: |
| [ |
| peri.tl_otp_ctrl__prim |
| ] |
| lc_ctrl.tl: |
| [ |
| peri.tl_lc_ctrl |
| ] |
| sensor_ctrl_aon.tl: |
| [ |
| peri.tl_sensor_ctrl_aon |
| ] |
| alert_handler.tl: |
| [ |
| peri.tl_alert_handler |
| ] |
| sram_ctrl_ret_aon.tl: |
| [ |
| peri.tl_sram_ctrl_ret_aon |
| ] |
| aon_timer_aon.tl: |
| [ |
| peri.tl_aon_timer_aon |
| ] |
| sysrst_ctrl_aon.tl: |
| [ |
| peri.tl_sysrst_ctrl_aon |
| ] |
| adc_ctrl_aon.tl: |
| [ |
| peri.tl_adc_ctrl_aon |
| ] |
| } |
| top: |
| [ |
| rstmgr_aon.resets |
| clkmgr_aon.clocks |
| rv_core_ibex.irq_timer |
| rv_core_ibex.hart_id |
| rv_core_ibex.boot_addr |
| pinmux_aon.dft_jtag |
| otp_ctrl.otp_hw_cfg |
| csrng.otp_en_csrng_sw_app_read |
| entropy_src.otp_en_entropy_src_fw_read |
| entropy_src.otp_en_entropy_src_fw_over |
| lc_ctrl.otp_device_id |
| keymgr.otp_device_id |
| sram_ctrl_main.otp_en_sram_ifetch |
| sram_ctrl_ret_aon.otp_en_sram_ifetch |
| ] |
| external: |
| { |
| adc_ctrl_aon.adc: adc |
| ast.edn: "" |
| ast.lc_dft_en: "" |
| ast.ram_1p_cfg: ram_1p_cfg |
| ast.ram_2p_cfg: ram_2p_cfg |
| ast.rom_cfg: rom_cfg |
| clkmgr_aon.clk_main: clk_main |
| clkmgr_aon.clk_io: clk_io |
| clkmgr_aon.clk_usb: clk_usb |
| clkmgr_aon.clk_aon: clk_aon |
| clkmgr_aon.jitter_en: clk_main_jitter_en |
| clkmgr_aon.ast_clk_byp_req: ast_clk_byp_req |
| clkmgr_aon.ast_clk_byp_ack: ast_clk_byp_ack |
| eflash.flash_alert: flash_alert |
| eflash.flash_bist_enable: flash_bist_enable |
| eflash.flash_power_down_h: flash_power_down_h |
| eflash.flash_power_ready_h: flash_power_ready_h |
| entropy_src.entropy_src_rng: es_rng |
| entropy_src.rng_fips: es_rng_fips |
| peri.tl_ast: ast_tl |
| pinmux_aon.dft_strap_test: dft_strap_test |
| pinmux_aon.dft_hold_tap_sel: dft_hold_tap_sel |
| pwrmgr_aon.pwr_ast: pwrmgr_ast |
| otp_ctrl.otp_ast_pwr_seq: "" |
| otp_ctrl.otp_ast_pwr_seq_h: "" |
| otp_ctrl.otp_alert: otp_alert |
| sensor_ctrl_aon.ast_alert: sensor_ctrl_ast_alert |
| sensor_ctrl_aon.ast_status: sensor_ctrl_ast_status |
| sensor_ctrl_aon.ast2pinmux: ast2pinmux |
| sensor_ctrl_aon.ast_init_done: ast_init_done |
| usbdev.usb_ref_val: "" |
| usbdev.usb_ref_pulse: "" |
| clkmgr_aon.clocks_ast: clks_ast |
| rstmgr_aon.resets_ast: rsts_ast |
| } |
| } |
| xbar: |
| [ |
| { |
| name: main |
| clock_srcs: |
| { |
| clk_main_i: main |
| clk_fixed_i: io_div4 |
| } |
| clock_group: infra |
| reset: rst_main_ni |
| reset_connections: |
| { |
| rst_main_ni: sys |
| rst_fixed_ni: sys_io_div4 |
| } |
| clock_connections: |
| { |
| clk_main_i: clkmgr_aon_clocks.clk_main_infra |
| clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra |
| } |
| domain: "0" |
| connections: |
| { |
| rv_core_ibex.corei: |
| [ |
| rom_ctrl.rom |
| rv_dm.rom |
| ram_main |
| eflash |
| ] |
| rv_core_ibex.cored: |
| [ |
| rom_ctrl.rom |
| rom_ctrl.regs |
| rv_dm.rom |
| rv_dm.regs |
| ram_main |
| eflash |
| peri |
| flash_ctrl.core |
| flash_ctrl.prim |
| aes |
| entropy_src |
| csrng |
| edn0 |
| edn1 |
| hmac |
| rv_plic |
| otbn |
| keymgr |
| kmac |
| sram_ctrl_main |
| rv_core_ibex.cfg |
| ] |
| rv_dm.sba: |
| [ |
| rom_ctrl.rom |
| rom_ctrl.regs |
| rv_dm.regs |
| ram_main |
| eflash |
| peri |
| flash_ctrl.core |
| flash_ctrl.prim |
| aes |
| entropy_src |
| csrng |
| edn0 |
| edn1 |
| hmac |
| rv_plic |
| otbn |
| keymgr |
| kmac |
| sram_ctrl_main |
| rv_core_ibex.cfg |
| ] |
| } |
| nodes: |
| [ |
| { |
| name: rv_core_ibex.corei |
| type: host |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline: "false" |
| xbar: false |
| stub: false |
| inst_type: "" |
| pipeline_byp: "true" |
| } |
| { |
| name: rv_core_ibex.cored |
| type: host |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline: "false" |
| xbar: false |
| stub: false |
| inst_type: "" |
| pipeline_byp: "true" |
| } |
| { |
| name: rv_dm.sba |
| type: host |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| xbar: false |
| stub: false |
| inst_type: "" |
| pipeline: "true" |
| } |
| { |
| name: rv_dm.regs |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: rv_dm |
| addr_range: |
| [ |
| { |
| base_addr: 0x41200000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: rv_dm.rom |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: rv_dm |
| addr_range: |
| [ |
| { |
| base_addr: 0x10000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: rom_ctrl.rom |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline: "false" |
| inst_type: rom_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x8000 |
| size_byte: 0x4000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: rom_ctrl.regs |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline: "false" |
| inst_type: rom_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x411e0000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: ram_main |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline: "false" |
| inst_type: ram_1p_scr |
| addr_range: |
| [ |
| { |
| base_addr: 0x10000000 |
| size_byte: 0x20000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: eflash |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline: "false" |
| inst_type: eflash |
| addr_range: |
| [ |
| { |
| base_addr: 0x20000000 |
| size_byte: 0x100000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: peri |
| type: device |
| clock: clk_fixed_i |
| reset: rst_fixed_ni |
| pipeline_byp: "false" |
| xbar: true |
| stub: false |
| pipeline: "true" |
| addr_range: |
| [ |
| { |
| base_addr: 0x40000000 |
| size_byte: 0x800000 |
| } |
| ] |
| } |
| { |
| name: flash_ctrl.core |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: flash_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x41000000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: flash_ctrl.prim |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: flash_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x41008000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: hmac |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: hmac |
| addr_range: |
| [ |
| { |
| base_addr: 0x41110000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: kmac |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: kmac |
| addr_range: |
| [ |
| { |
| base_addr: 0x41120000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: aes |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: aes |
| addr_range: |
| [ |
| { |
| base_addr: 0x41100000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: entropy_src |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: entropy_src |
| addr_range: |
| [ |
| { |
| base_addr: 0x41160000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: csrng |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: csrng |
| addr_range: |
| [ |
| { |
| base_addr: 0x41150000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: edn0 |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: edn |
| addr_range: |
| [ |
| { |
| base_addr: 0x41170000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: edn1 |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: edn |
| addr_range: |
| [ |
| { |
| base_addr: 0x41180000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: rv_plic |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| inst_type: rv_plic |
| pipeline_byp: "false" |
| addr_range: |
| [ |
| { |
| base_addr: 0x41010000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: otbn |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: otbn |
| addr_range: |
| [ |
| { |
| base_addr: 0x411d0000 |
| size_byte: 0x10000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: keymgr |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: keymgr |
| addr_range: |
| [ |
| { |
| base_addr: 0x41130000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: rv_core_ibex.cfg |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline_byp: "false" |
| inst_type: rv_core_ibex |
| addr_range: |
| [ |
| { |
| base_addr: 0x411f0000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline: "true" |
| } |
| { |
| name: sram_ctrl_main |
| type: device |
| clock: clk_main_i |
| reset: rst_main_ni |
| pipeline: "false" |
| inst_type: sram_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x411c0000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| ] |
| clock: clk_main_i |
| type: xbar |
| inter_signal_list: |
| [ |
| { |
| name: tl_rv_core_ibex__corei |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: main |
| default: "" |
| end_idx: -1 |
| top_signame: main_tl_rv_core_ibex__corei |
| index: -1 |
| } |
| { |
| name: tl_rv_core_ibex__cored |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: main |
| default: "" |
| end_idx: -1 |
| top_signame: main_tl_rv_core_ibex__cored |
| index: -1 |
| } |
| { |
| name: tl_rv_dm__sba |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: main |
| default: "" |
| end_idx: -1 |
| top_signame: main_tl_rv_dm__sba |
| index: -1 |
| } |
| { |
| name: tl_rv_dm__regs |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rv_dm_regs_tl_d |
| index: -1 |
| } |
| { |
| name: tl_rv_dm__rom |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rv_dm_rom_tl_d |
| index: -1 |
| } |
| { |
| name: tl_rom_ctrl__rom |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rom_ctrl_rom_tl |
| index: -1 |
| } |
| { |
| name: tl_rom_ctrl__regs |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rom_ctrl_regs_tl |
| index: -1 |
| } |
| { |
| name: tl_ram_main |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: ram_main_tl |
| index: -1 |
| } |
| { |
| name: tl_eflash |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: eflash_tl |
| index: -1 |
| } |
| { |
| name: tl_peri |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| end_idx: -1 |
| top_signame: main_tl_peri |
| index: -1 |
| } |
| { |
| name: tl_flash_ctrl__core |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: flash_ctrl_core_tl |
| index: -1 |
| } |
| { |
| name: tl_flash_ctrl__prim |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: flash_ctrl_prim_tl |
| index: -1 |
| } |
| { |
| name: tl_hmac |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: hmac_tl |
| index: -1 |
| } |
| { |
| name: tl_kmac |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: kmac_tl |
| index: -1 |
| } |
| { |
| name: tl_aes |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: aes_tl |
| index: -1 |
| } |
| { |
| name: tl_entropy_src |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: entropy_src_tl |
| index: -1 |
| } |
| { |
| name: tl_csrng |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: csrng_tl |
| index: -1 |
| } |
| { |
| name: tl_edn0 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: edn0_tl |
| index: -1 |
| } |
| { |
| name: tl_edn1 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: edn1_tl |
| index: -1 |
| } |
| { |
| name: tl_rv_plic |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rv_plic_tl |
| index: -1 |
| } |
| { |
| name: tl_otbn |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: otbn_tl |
| index: -1 |
| } |
| { |
| name: tl_keymgr |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: keymgr_tl |
| index: -1 |
| } |
| { |
| name: tl_rv_core_ibex__cfg |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rv_core_ibex_cfg_tl_d |
| index: -1 |
| } |
| { |
| name: tl_sram_ctrl_main |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: sram_ctrl_main_tl |
| index: -1 |
| } |
| ] |
| } |
| { |
| name: peri |
| clock_srcs: |
| { |
| clk_peri_i: io_div4 |
| } |
| clock_group: infra |
| reset: rst_peri_ni |
| reset_connections: |
| { |
| rst_peri_ni: sys_io_div4 |
| } |
| clock_connections: |
| { |
| clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra |
| } |
| domain: "0" |
| connections: |
| { |
| main: |
| [ |
| uart0 |
| uart1 |
| uart2 |
| uart3 |
| i2c0 |
| i2c1 |
| i2c2 |
| pattgen |
| gpio |
| spi_device |
| spi_host0 |
| spi_host1 |
| rv_timer |
| usbdev |
| pwrmgr_aon |
| rstmgr_aon |
| clkmgr_aon |
| pinmux_aon |
| ram_ret_aon |
| otp_ctrl.core |
| otp_ctrl.prim |
| lc_ctrl |
| sensor_ctrl_aon |
| alert_handler |
| ast |
| sram_ctrl_ret_aon |
| aon_timer_aon |
| adc_ctrl_aon |
| sysrst_ctrl_aon |
| pwm_aon |
| ] |
| } |
| nodes: |
| [ |
| { |
| name: main |
| type: host |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| xbar: true |
| pipeline: "false" |
| stub: false |
| inst_type: "" |
| pipeline_byp: "true" |
| } |
| { |
| name: uart0 |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: uart |
| addr_range: |
| [ |
| { |
| base_addr: 0x40000000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: uart1 |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: uart |
| addr_range: |
| [ |
| { |
| base_addr: 0x40010000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: uart2 |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: uart |
| addr_range: |
| [ |
| { |
| base_addr: 0x40020000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: uart3 |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: uart |
| addr_range: |
| [ |
| { |
| base_addr: 0x40030000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: i2c0 |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: i2c |
| addr_range: |
| [ |
| { |
| base_addr: 0x40080000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: i2c1 |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: i2c |
| addr_range: |
| [ |
| { |
| base_addr: 0x40090000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: i2c2 |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: i2c |
| addr_range: |
| [ |
| { |
| base_addr: 0x400a0000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: pattgen |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: pattgen |
| addr_range: |
| [ |
| { |
| base_addr: 0x400e0000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: pwm_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: pwm |
| addr_range: |
| [ |
| { |
| base_addr: 0x40450000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: gpio |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: gpio |
| addr_range: |
| [ |
| { |
| base_addr: 0x40040000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: spi_device |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: spi_device |
| addr_range: |
| [ |
| { |
| base_addr: 0x40050000 |
| size_byte: 0x2000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: spi_host0 |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: spi_host |
| addr_range: |
| [ |
| { |
| base_addr: 0x40060000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: spi_host1 |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: spi_host |
| addr_range: |
| [ |
| { |
| base_addr: 0x40070000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: rv_timer |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: rv_timer |
| addr_range: |
| [ |
| { |
| base_addr: 0x40100000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: usbdev |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: usbdev |
| addr_range: |
| [ |
| { |
| base_addr: 0x40110000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: pwrmgr_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: pwrmgr |
| addr_range: |
| [ |
| { |
| base_addr: 0x40400000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: rstmgr_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: rstmgr |
| addr_range: |
| [ |
| { |
| base_addr: 0x40410000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: clkmgr_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: clkmgr |
| addr_range: |
| [ |
| { |
| base_addr: 0x40420000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: pinmux_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: pinmux |
| addr_range: |
| [ |
| { |
| base_addr: 0x40460000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: ram_ret_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: ram_1p_scr |
| addr_range: |
| [ |
| { |
| base_addr: 0x40600000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: otp_ctrl.core |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: otp_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x40130000 |
| size_byte: 0x2000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: otp_ctrl.prim |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: otp_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x40132000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: lc_ctrl |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: lc_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x40140000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: sensor_ctrl_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: sensor_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x40490000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: alert_handler |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: alert_handler |
| addr_range: |
| [ |
| { |
| base_addr: 0x40150000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: sram_ctrl_ret_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: sram_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x40500000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: aon_timer_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: aon_timer |
| addr_range: |
| [ |
| { |
| base_addr: 0x40470000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: sysrst_ctrl_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: sysrst_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x40430000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: adc_ctrl_aon |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: adc_ctrl |
| addr_range: |
| [ |
| { |
| base_addr: 0x40440000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: false |
| pipeline_byp: "true" |
| } |
| { |
| name: ast |
| type: device |
| clock: clk_peri_i |
| reset: rst_peri_ni |
| pipeline: "false" |
| inst_type: ast |
| addr_range: |
| [ |
| { |
| base_addr: 0x40480000 |
| size_byte: 0x1000 |
| } |
| ] |
| xbar: false |
| stub: true |
| pipeline_byp: "true" |
| } |
| ] |
| clock: clk_peri_i |
| type: xbar |
| inter_signal_list: |
| [ |
| { |
| name: tl_main |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: main_tl_peri |
| index: -1 |
| } |
| { |
| name: tl_uart0 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: uart0_tl |
| index: -1 |
| } |
| { |
| name: tl_uart1 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: uart1_tl |
| index: -1 |
| } |
| { |
| name: tl_uart2 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: uart2_tl |
| index: -1 |
| } |
| { |
| name: tl_uart3 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: uart3_tl |
| index: -1 |
| } |
| { |
| name: tl_i2c0 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: i2c0_tl |
| index: -1 |
| } |
| { |
| name: tl_i2c1 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: i2c1_tl |
| index: -1 |
| } |
| { |
| name: tl_i2c2 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: i2c2_tl |
| index: -1 |
| } |
| { |
| name: tl_pattgen |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: pattgen_tl |
| index: -1 |
| } |
| { |
| name: tl_pwm_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: pwm_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_gpio |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: gpio_tl |
| index: -1 |
| } |
| { |
| name: tl_spi_device |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: spi_device_tl |
| index: -1 |
| } |
| { |
| name: tl_spi_host0 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: spi_host0_tl |
| index: -1 |
| } |
| { |
| name: tl_spi_host1 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: spi_host1_tl |
| index: -1 |
| } |
| { |
| name: tl_rv_timer |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: rv_timer_tl |
| index: -1 |
| } |
| { |
| name: tl_usbdev |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: usbdev_tl |
| index: -1 |
| } |
| { |
| name: tl_pwrmgr_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: pwrmgr_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_rstmgr_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: rstmgr_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_clkmgr_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: clkmgr_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_pinmux_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: pinmux_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_ram_ret_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: ram_ret_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_otp_ctrl__core |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: otp_ctrl_core_tl |
| index: -1 |
| } |
| { |
| name: tl_otp_ctrl__prim |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: otp_ctrl_prim_tl |
| index: -1 |
| } |
| { |
| name: tl_lc_ctrl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: lc_ctrl_tl |
| index: -1 |
| } |
| { |
| name: tl_sensor_ctrl_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: sensor_ctrl_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_alert_handler |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: alert_handler_tl |
| index: -1 |
| } |
| { |
| name: tl_sram_ctrl_ret_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: sram_ctrl_ret_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_aon_timer_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: aon_timer_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_sysrst_ctrl_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: sysrst_ctrl_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_adc_ctrl_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: adc_ctrl_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_ast |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| external: true |
| top_signame: ast_tl |
| index: -1 |
| } |
| ] |
| } |
| ] |
| pinout: |
| { |
| banks: |
| [ |
| VCC |
| AVCC |
| VIOA |
| VIOB |
| ] |
| pads: |
| [ |
| { |
| name: POR_N |
| type: InputStd |
| bank: VCC |
| connection: manual |
| desc: System reset |
| idx: 0 |
| } |
| { |
| name: USB_P |
| type: BidirTol |
| bank: VCC |
| connection: manual |
| desc: USB P signal |
| idx: 1 |
| } |
| { |
| name: USB_N |
| type: BidirTol |
| bank: VCC |
| connection: manual |
| desc: USB N signal |
| idx: 2 |
| } |
| { |
| name: CC1 |
| type: InputStd |
| bank: AVCC |
| connection: manual |
| desc: ADC input 1 |
| idx: 3 |
| } |
| { |
| name: CC2 |
| type: InputStd |
| bank: AVCC |
| connection: manual |
| desc: ADC input 2 |
| idx: 4 |
| } |
| { |
| name: FLASH_TEST_VOLT |
| type: AnalogIn0 |
| bank: VCC |
| connection: manual |
| desc: Flash test voltage input |
| idx: 5 |
| } |
| { |
| name: FLASH_TEST_MODE0 |
| type: InputStd |
| bank: VCC |
| connection: manual |
| desc: Flash test mode signal |
| idx: 6 |
| } |
| { |
| name: FLASH_TEST_MODE1 |
| type: InputStd |
| bank: VCC |
| connection: manual |
| desc: Flash test mode signal |
| idx: 7 |
| } |
| { |
| name: OTP_EXT_VOLT |
| type: AnalogIn1 |
| bank: VCC |
| connection: manual |
| desc: OTP external voltage input |
| idx: 8 |
| } |
| { |
| name: SPI_HOST_D0 |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI host data |
| idx: 9 |
| } |
| { |
| name: SPI_HOST_D1 |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI host data |
| idx: 10 |
| } |
| { |
| name: SPI_HOST_D2 |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI host data |
| idx: 11 |
| } |
| { |
| name: SPI_HOST_D3 |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI host data |
| idx: 12 |
| } |
| { |
| name: SPI_HOST_CLK |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI host clock |
| idx: 13 |
| } |
| { |
| name: SPI_HOST_CS_L |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI host chip select |
| idx: 14 |
| } |
| { |
| name: SPI_DEV_D0 |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI device data |
| idx: 15 |
| } |
| { |
| name: SPI_DEV_D1 |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI device data |
| idx: 16 |
| } |
| { |
| name: SPI_DEV_D2 |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI device data |
| idx: 17 |
| } |
| { |
| name: SPI_DEV_D3 |
| type: BidirStd |
| bank: VIOA |
| connection: direct |
| desc: SPI device data |
| idx: 18 |
| } |
| { |
| name: SPI_DEV_CLK |
| type: InputStd |
| bank: VIOA |
| connection: direct |
| desc: SPI device clock |
| idx: 19 |
| } |
| { |
| name: SPI_DEV_CS_L |
| type: InputStd |
| bank: VIOA |
| connection: direct |
| desc: SPI device chip select |
| idx: 20 |
| } |
| { |
| name: IOA0 |
| type: BidirStd |
| bank: VIOA |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 0 |
| } |
| { |
| name: IOA1 |
| type: BidirStd |
| bank: VIOA |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 1 |
| } |
| { |
| name: IOA2 |
| type: BidirStd |
| bank: VIOA |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 2 |
| } |
| { |
| name: IOA3 |
| type: BidirStd |
| bank: VIOA |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 3 |
| } |
| { |
| name: IOA4 |
| type: BidirStd |
| bank: VIOA |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 4 |
| } |
| { |
| name: IOA5 |
| type: BidirStd |
| bank: VIOA |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 5 |
| } |
| { |
| name: IOA6 |
| type: BidirOd |
| bank: VIOA |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 6 |
| } |
| { |
| name: IOA7 |
| type: BidirOd |
| bank: VIOA |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 7 |
| } |
| { |
| name: IOA8 |
| type: BidirOd |
| bank: VIOA |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 8 |
| } |
| { |
| name: IOB0 |
| type: BidirStd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 9 |
| } |
| { |
| name: IOB1 |
| type: BidirStd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 10 |
| } |
| { |
| name: IOB2 |
| type: BidirStd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 11 |
| } |
| { |
| name: IOB3 |
| type: BidirStd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 12 |
| } |
| { |
| name: IOB4 |
| type: BidirStd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 13 |
| } |
| { |
| name: IOB5 |
| type: BidirStd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 14 |
| } |
| { |
| name: IOB6 |
| type: BidirStd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 15 |
| } |
| { |
| name: IOB7 |
| type: BidirStd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 16 |
| } |
| { |
| name: IOB8 |
| type: BidirStd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 17 |
| } |
| { |
| name: IOB9 |
| type: BidirOd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 18 |
| } |
| { |
| name: IOB10 |
| type: BidirOd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 19 |
| } |
| { |
| name: IOB11 |
| type: BidirOd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 20 |
| } |
| { |
| name: IOB12 |
| type: BidirOd |
| bank: VIOB |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 21 |
| } |
| { |
| name: IOC0 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 22 |
| } |
| { |
| name: IOC1 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 23 |
| } |
| { |
| name: IOC2 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 24 |
| } |
| { |
| name: IOC3 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 25 |
| } |
| { |
| name: IOC4 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 26 |
| } |
| { |
| name: IOC5 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 27 |
| } |
| { |
| name: IOC6 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 28 |
| } |
| { |
| name: IOC7 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 29 |
| } |
| { |
| name: IOC8 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 30 |
| } |
| { |
| name: IOC9 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 31 |
| } |
| { |
| name: IOC10 |
| type: BidirOd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 32 |
| } |
| { |
| name: IOC11 |
| type: BidirOd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 33 |
| } |
| { |
| name: IOC12 |
| type: BidirOd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 34 |
| } |
| { |
| name: IOR0 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 35 |
| } |
| { |
| name: IOR1 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 36 |
| } |
| { |
| name: IOR2 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 37 |
| } |
| { |
| name: IOR3 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 38 |
| } |
| { |
| name: IOR4 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 39 |
| } |
| { |
| name: IOR5 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 40 |
| } |
| { |
| name: IOR6 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 41 |
| } |
| { |
| name: IOR7 |
| type: BidirStd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 42 |
| } |
| { |
| name: IOR8 |
| type: BidirOd |
| bank: VCC |
| connection: direct |
| desc: Dedicated sysrst_ctrl output (ec_rst_l) |
| idx: 21 |
| } |
| { |
| name: IOR9 |
| type: BidirOd |
| bank: VCC |
| connection: direct |
| desc: Dedicated sysrst_ctrl output (pwrb_out) |
| idx: 22 |
| } |
| { |
| name: IOR10 |
| type: BidirOd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 43 |
| } |
| { |
| name: IOR11 |
| type: BidirOd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 44 |
| } |
| { |
| name: IOR12 |
| type: BidirOd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 45 |
| } |
| { |
| name: IOR13 |
| type: BidirOd |
| bank: VCC |
| connection: muxed |
| desc: Muxed IO pad |
| idx: 46 |
| } |
| ] |
| } |
| pinmux: |
| { |
| signals: |
| [ |
| { |
| instance: spi_host0 |
| port: sck |
| connection: direct |
| pad: SPI_HOST_CLK |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: spi_host0 |
| port: csb |
| connection: direct |
| pad: SPI_HOST_CS_L |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: spi_host0 |
| port: sd[0] |
| connection: direct |
| pad: SPI_HOST_D0 |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: spi_host0 |
| port: sd[1] |
| connection: direct |
| pad: SPI_HOST_D1 |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: spi_host0 |
| port: sd[2] |
| connection: direct |
| pad: SPI_HOST_D2 |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: spi_host0 |
| port: sd[3] |
| connection: direct |
| pad: SPI_HOST_D3 |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: spi_device |
| port: sck |
| connection: direct |
| pad: SPI_DEV_CLK |
| desc: "" |
| attr: InputStd |
| } |
| { |
| instance: spi_device |
| port: csb |
| connection: direct |
| pad: SPI_DEV_CS_L |
| desc: "" |
| attr: InputStd |
| } |
| { |
| instance: spi_device |
| port: sd[0] |
| connection: direct |
| pad: SPI_DEV_D0 |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: spi_device |
| port: sd[1] |
| connection: direct |
| pad: SPI_DEV_D1 |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: spi_device |
| port: sd[2] |
| connection: direct |
| pad: SPI_DEV_D2 |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: spi_device |
| port: sd[3] |
| connection: direct |
| pad: SPI_DEV_D3 |
| desc: "" |
| attr: BidirStd |
| } |
| { |
| instance: usbdev |
| port: d |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: usbdev |
| port: dp |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: usbdev |
| port: dn |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: usbdev |
| port: sense |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: usbdev |
| port: se0 |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: usbdev |
| port: dp_pullup |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: usbdev |
| port: dn_pullup |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: usbdev |
| port: tx_mode_se |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: usbdev |
| port: suspend |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: usbdev |
| port: rx_enable |
| connection: manual |
| pad: "" |
| desc: "" |
| attr: BidirTol |
| } |
| { |
| instance: gpio |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: uart0 |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: uart1 |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: uart2 |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: uart3 |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: i2c0 |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: i2c1 |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: i2c2 |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: pattgen |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: spi_host1 |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: flash_ctrl |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sensor_ctrl_aon |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: pwm_aon |
| port: "" |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: ac_present |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: ec_rst_in_l |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: key0_in |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: key1_in |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: key2_in |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: pwrb_in |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: bat_disable |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: ec_rst_out_l |
| connection: direct |
| pad: IOR8 |
| desc: "" |
| attr: BidirOd |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: key0_out |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: key1_out |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: key2_out |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: pwrb_out |
| connection: direct |
| pad: IOR9 |
| desc: "" |
| attr: BidirOd |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: lid_open |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| { |
| instance: sysrst_ctrl_aon |
| port: z3_wakeup |
| connection: muxed |
| pad: "" |
| desc: "" |
| attr: "" |
| } |
| ] |
| num_wkup_detect: 8 |
| wkup_cnt_width: 8 |
| ios: |
| [ |
| { |
| name: spi_host0_sd |
| width: 4 |
| type: inout |
| idx: 0 |
| pad: SPI_HOST_D0 |
| attr: BidirStd |
| connection: direct |
| glob_idx: 0 |
| } |
| { |
| name: spi_host0_sd |
| width: 4 |
| type: inout |
| idx: 1 |
| pad: SPI_HOST_D1 |
| attr: BidirStd |
| connection: direct |
| glob_idx: 1 |
| } |
| { |
| name: spi_host0_sd |
| width: 4 |
| type: inout |
| idx: 2 |
| pad: SPI_HOST_D2 |
| attr: BidirStd |
| connection: direct |
| glob_idx: 2 |
| } |
| { |
| name: spi_host0_sd |
| width: 4 |
| type: inout |
| idx: 3 |
| pad: SPI_HOST_D3 |
| attr: BidirStd |
| connection: direct |
| glob_idx: 3 |
| } |
| { |
| name: spi_device_sd |
| width: 4 |
| type: inout |
| idx: 0 |
| pad: SPI_DEV_D0 |
| attr: BidirStd |
| connection: direct |
| glob_idx: 4 |
| } |
| { |
| name: spi_device_sd |
| width: 4 |
| type: inout |
| idx: 1 |
| pad: SPI_DEV_D1 |
| attr: BidirStd |
| connection: direct |
| glob_idx: 5 |
| } |
| { |
| name: spi_device_sd |
| width: 4 |
| type: inout |
| idx: 2 |
| pad: SPI_DEV_D2 |
| attr: BidirStd |
| connection: direct |
| glob_idx: 6 |
| } |
| { |
| name: spi_device_sd |
| width: 4 |
| type: inout |
| idx: 3 |
| pad: SPI_DEV_D3 |
| attr: BidirStd |
| connection: direct |
| glob_idx: 7 |
| } |
| { |
| name: usbdev_d |
| width: 1 |
| type: inout |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 8 |
| } |
| { |
| name: usbdev_dp |
| width: 1 |
| type: inout |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 9 |
| } |
| { |
| name: usbdev_dn |
| width: 1 |
| type: inout |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 10 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 0 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 0 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 1 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 2 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 2 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 3 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 3 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 4 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 4 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 5 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 5 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 6 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 6 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 7 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 7 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 8 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 8 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 9 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 9 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 10 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 10 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 11 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 11 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 12 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 12 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 13 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 13 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 14 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 14 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 15 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 15 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 16 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 16 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 17 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 17 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 18 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 18 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 19 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 19 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 20 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 20 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 21 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 21 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 22 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 22 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 23 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 23 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 24 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 24 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 25 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 25 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 26 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 26 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 27 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 27 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 28 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 28 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 29 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 29 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 30 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 30 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: inout |
| idx: 31 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 31 |
| } |
| { |
| name: i2c0_sda |
| width: 1 |
| type: inout |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 32 |
| } |
| { |
| name: i2c0_scl |
| width: 1 |
| type: inout |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 33 |
| } |
| { |
| name: i2c1_sda |
| width: 1 |
| type: inout |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 34 |
| } |
| { |
| name: i2c1_scl |
| width: 1 |
| type: inout |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 35 |
| } |
| { |
| name: i2c2_sda |
| width: 1 |
| type: inout |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 36 |
| } |
| { |
| name: i2c2_scl |
| width: 1 |
| type: inout |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 37 |
| } |
| { |
| name: spi_host1_sd |
| width: 4 |
| type: inout |
| idx: 0 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 38 |
| } |
| { |
| name: spi_host1_sd |
| width: 4 |
| type: inout |
| idx: 1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 39 |
| } |
| { |
| name: spi_host1_sd |
| width: 4 |
| type: inout |
| idx: 2 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 40 |
| } |
| { |
| name: spi_host1_sd |
| width: 4 |
| type: inout |
| idx: 3 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 41 |
| } |
| { |
| name: spi_device_sck |
| width: 1 |
| type: input |
| idx: -1 |
| pad: SPI_DEV_CLK |
| attr: InputStd |
| connection: direct |
| glob_idx: 11 |
| } |
| { |
| name: spi_device_csb |
| width: 1 |
| type: input |
| idx: -1 |
| pad: SPI_DEV_CS_L |
| attr: InputStd |
| connection: direct |
| glob_idx: 12 |
| } |
| { |
| name: usbdev_sense |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 13 |
| } |
| { |
| name: uart0_rx |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 42 |
| } |
| { |
| name: uart1_rx |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 43 |
| } |
| { |
| name: uart2_rx |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 44 |
| } |
| { |
| name: uart3_rx |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 45 |
| } |
| { |
| name: flash_ctrl_tck |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 46 |
| } |
| { |
| name: flash_ctrl_tms |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 47 |
| } |
| { |
| name: flash_ctrl_tdi |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 48 |
| } |
| { |
| name: sysrst_ctrl_aon_ac_present |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 49 |
| } |
| { |
| name: sysrst_ctrl_aon_ec_rst_in_l |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 50 |
| } |
| { |
| name: sysrst_ctrl_aon_key0_in |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 51 |
| } |
| { |
| name: sysrst_ctrl_aon_key1_in |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 52 |
| } |
| { |
| name: sysrst_ctrl_aon_key2_in |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 53 |
| } |
| { |
| name: sysrst_ctrl_aon_pwrb_in |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 54 |
| } |
| { |
| name: sysrst_ctrl_aon_lid_open |
| width: 1 |
| type: input |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 55 |
| } |
| { |
| name: spi_host0_sck |
| width: 1 |
| type: output |
| idx: -1 |
| pad: SPI_HOST_CLK |
| attr: BidirStd |
| connection: direct |
| glob_idx: 14 |
| } |
| { |
| name: spi_host0_csb |
| width: 1 |
| type: output |
| idx: -1 |
| pad: SPI_HOST_CS_L |
| attr: BidirStd |
| connection: direct |
| glob_idx: 15 |
| } |
| { |
| name: usbdev_se0 |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 16 |
| } |
| { |
| name: usbdev_dp_pullup |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 17 |
| } |
| { |
| name: usbdev_dn_pullup |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 18 |
| } |
| { |
| name: usbdev_tx_mode_se |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 19 |
| } |
| { |
| name: usbdev_suspend |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 20 |
| } |
| { |
| name: usbdev_rx_enable |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: BidirTol |
| connection: manual |
| glob_idx: 21 |
| } |
| { |
| name: uart0_tx |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 42 |
| } |
| { |
| name: uart1_tx |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 43 |
| } |
| { |
| name: uart2_tx |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 44 |
| } |
| { |
| name: uart3_tx |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 45 |
| } |
| { |
| name: pattgen_pda0_tx |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 46 |
| } |
| { |
| name: pattgen_pcl0_tx |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 47 |
| } |
| { |
| name: pattgen_pda1_tx |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 48 |
| } |
| { |
| name: pattgen_pcl1_tx |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 49 |
| } |
| { |
| name: spi_host1_sck |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 50 |
| } |
| { |
| name: spi_host1_csb |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 51 |
| } |
| { |
| name: flash_ctrl_tdo |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 52 |
| } |
| { |
| name: sensor_ctrl_aon_ast_debug_out |
| width: 9 |
| type: output |
| idx: 0 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 53 |
| } |
| { |
| name: sensor_ctrl_aon_ast_debug_out |
| width: 9 |
| type: output |
| idx: 1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 54 |
| } |
| { |
| name: sensor_ctrl_aon_ast_debug_out |
| width: 9 |
| type: output |
| idx: 2 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 55 |
| } |
| { |
| name: sensor_ctrl_aon_ast_debug_out |
| width: 9 |
| type: output |
| idx: 3 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 56 |
| } |
| { |
| name: sensor_ctrl_aon_ast_debug_out |
| width: 9 |
| type: output |
| idx: 4 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 57 |
| } |
| { |
| name: sensor_ctrl_aon_ast_debug_out |
| width: 9 |
| type: output |
| idx: 5 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 58 |
| } |
| { |
| name: sensor_ctrl_aon_ast_debug_out |
| width: 9 |
| type: output |
| idx: 6 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 59 |
| } |
| { |
| name: sensor_ctrl_aon_ast_debug_out |
| width: 9 |
| type: output |
| idx: 7 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 60 |
| } |
| { |
| name: sensor_ctrl_aon_ast_debug_out |
| width: 9 |
| type: output |
| idx: 8 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 61 |
| } |
| { |
| name: pwm_aon_pwm |
| width: 6 |
| type: output |
| idx: 0 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 62 |
| } |
| { |
| name: pwm_aon_pwm |
| width: 6 |
| type: output |
| idx: 1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 63 |
| } |
| { |
| name: pwm_aon_pwm |
| width: 6 |
| type: output |
| idx: 2 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 64 |
| } |
| { |
| name: pwm_aon_pwm |
| width: 6 |
| type: output |
| idx: 3 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 65 |
| } |
| { |
| name: pwm_aon_pwm |
| width: 6 |
| type: output |
| idx: 4 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 66 |
| } |
| { |
| name: pwm_aon_pwm |
| width: 6 |
| type: output |
| idx: 5 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 67 |
| } |
| { |
| name: sysrst_ctrl_aon_bat_disable |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 68 |
| } |
| { |
| name: sysrst_ctrl_aon_ec_rst_out_l |
| width: 1 |
| type: output |
| idx: -1 |
| pad: IOR8 |
| attr: BidirOd |
| connection: direct |
| glob_idx: 22 |
| } |
| { |
| name: sysrst_ctrl_aon_key0_out |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 69 |
| } |
| { |
| name: sysrst_ctrl_aon_key1_out |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 70 |
| } |
| { |
| name: sysrst_ctrl_aon_key2_out |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 71 |
| } |
| { |
| name: sysrst_ctrl_aon_pwrb_out |
| width: 1 |
| type: output |
| idx: -1 |
| pad: IOR9 |
| attr: BidirOd |
| connection: direct |
| glob_idx: 23 |
| } |
| { |
| name: sysrst_ctrl_aon_z3_wakeup |
| width: 1 |
| type: output |
| idx: -1 |
| pad: "" |
| attr: "" |
| connection: muxed |
| glob_idx: 72 |
| } |
| ] |
| io_counts: |
| { |
| dedicated: |
| { |
| inouts: 11 |
| inputs: 3 |
| outputs: 10 |
| pads: 23 |
| } |
| muxed: |
| { |
| inouts: 42 |
| inputs: 14 |
| outputs: 31 |
| pads: 47 |
| } |
| } |
| } |
| targets: |
| [ |
| { |
| name: asic |
| pinout: |
| { |
| remove_pads: [] |
| add_pads: [] |
| } |
| pinmux: |
| { |
| special_signals: |
| [ |
| { |
| name: tap0 |
| pad: IOC8 |
| desc: TAP strap signal. |
| idx: 30 |
| } |
| { |
| name: tap1 |
| pad: IOC5 |
| desc: TAP strap signal. |
| idx: 27 |
| } |
| { |
| name: dft0 |
| pad: IOC3 |
| desc: DFT strap signal. |
| idx: 25 |
| } |
| { |
| name: dft1 |
| pad: IOC4 |
| desc: DFT strap signal. |
| idx: 26 |
| } |
| { |
| name: tck |
| pad: IOR3 |
| desc: JTAG tck signal. |
| idx: 38 |
| } |
| { |
| name: tms |
| pad: IOR0 |
| desc: JTAG tms signal. |
| idx: 35 |
| } |
| { |
| name: trst_n |
| pad: IOR4 |
| desc: JTAG trst_n signal. |
| idx: 39 |
| } |
| { |
| name: tdi |
| pad: IOR2 |
| desc: JTAG tdi signal. |
| idx: 37 |
| } |
| { |
| name: tdo |
| pad: IOR1 |
| desc: JTAG tdo signal. |
| idx: 36 |
| } |
| ] |
| } |
| } |
| { |
| name: cw310 |
| pinout: |
| { |
| remove_pads: |
| [ |
| CC1 |
| CC2 |
| SPI_DEV_D2 |
| SPI_DEV_D3 |
| SPI_HOST_CLK |
| SPI_HOST_CS_L |
| SPI_HOST_D0 |
| SPI_HOST_D1 |
| SPI_HOST_D2 |
| SPI_HOST_D3 |
| FLASH_TEST_VOLT |
| OTP_EXT_VOLT |
| FLASH_TEST_MODE0 |
| FLASH_TEST_MODE1 |
| IOB10 |
| IOB11 |
| IOB12 |
| IOC0 |
| IOC1 |
| IOC12 |
| IOR0 |
| IOR1 |
| IOR2 |
| IOR3 |
| IOR4 |
| IOR5 |
| IOR6 |
| IOR7 |
| IOR8 |
| IOR9 |
| IOR10 |
| IOR11 |
| IOR12 |
| IOR13 |
| ] |
| add_pads: |
| [ |
| { |
| name: IO_CLK |
| type: InputStd |
| bank: VCC |
| connection: manual |
| desc: Extra clock input for FPGA target |
| } |
| { |
| name: IO_JSRST_N |
| type: InputStd |
| bank: VCC |
| connection: manual |
| desc: Dedicated JTAG system reset input |
| } |
| { |
| name: IO_USB_SENSE0 |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB signal for FPGA target |
| } |
| { |
| name: IO_USB_DNPULLUP0 |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB signal for FPGA target |
| } |
| { |
| name: IO_USB_DPPULLUP0 |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DP_TX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DN_TX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DP_RX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DN_RX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_D_RX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_OE_N |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_SENSE |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DPPULLUP |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| ] |
| } |
| pinmux: |
| { |
| special_signals: |
| [ |
| { |
| name: tap0 |
| pad: IOC0 |
| desc: TAP strap signal, maps to a stubbed-off MIO. |
| idx: 22 |
| } |
| { |
| name: tap1 |
| pad: IOB7 |
| desc: TAP strap signal, maps to MIO pad 16. |
| idx: 16 |
| } |
| { |
| name: dft0 |
| pad: IOC1 |
| desc: DFT strap signal, maps to a stubbed-off MIO. |
| idx: 23 |
| } |
| { |
| name: dft1 |
| pad: IOC12 |
| desc: DFT strap signal, maps to a stubbed-off MIO. |
| idx: 34 |
| } |
| { |
| name: tck |
| pad: SPI_DEV_CLK |
| desc: JTAG tck signal, overlaid on SPI_DEV. |
| idx: 58 |
| } |
| { |
| name: tms |
| pad: SPI_DEV_CS_L |
| desc: JTAG tms signal, overlaid on SPI_DEV. |
| idx: 59 |
| } |
| { |
| name: trst_n |
| pad: IOB9 |
| desc: JTAG trst_n signal, maps to MIO pad 18. |
| idx: 18 |
| } |
| { |
| name: tdi |
| pad: SPI_DEV_D0 |
| desc: JTAG tdi signal, overlaid on SPI_DEV. |
| idx: 51 |
| } |
| { |
| name: tdo |
| pad: SPI_DEV_D1 |
| desc: JTAG tdo signal, overlaid on SPI_DEV. |
| idx: 52 |
| } |
| ] |
| } |
| } |
| { |
| name: nexysvideo |
| pinout: |
| { |
| remove_pads: |
| [ |
| CC1 |
| CC2 |
| SPI_DEV_D2 |
| SPI_DEV_D3 |
| SPI_HOST_CLK |
| SPI_HOST_CS_L |
| SPI_HOST_D0 |
| SPI_HOST_D1 |
| SPI_HOST_D2 |
| SPI_HOST_D3 |
| FLASH_TEST_VOLT |
| OTP_EXT_VOLT |
| FLASH_TEST_MODE0 |
| FLASH_TEST_MODE1 |
| IOB10 |
| IOB11 |
| IOB12 |
| IOC0 |
| IOC1 |
| IOC12 |
| IOR0 |
| IOR1 |
| IOR2 |
| IOR3 |
| IOR4 |
| IOR5 |
| IOR6 |
| IOR7 |
| IOR8 |
| IOR9 |
| IOR10 |
| IOR11 |
| IOR12 |
| IOR13 |
| ] |
| add_pads: |
| [ |
| { |
| name: IO_CLK |
| type: InputStd |
| bank: VCC |
| connection: manual |
| desc: Extra clock input for FPGA target |
| } |
| { |
| name: IO_JSRST_N |
| type: InputStd |
| bank: VCC |
| connection: manual |
| desc: Dedicated JTAG system reset input |
| } |
| { |
| name: IO_USB_SENSE0 |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB signal for FPGA target |
| } |
| { |
| name: IO_USB_DNPULLUP0 |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB signal for FPGA target |
| } |
| { |
| name: IO_USB_DPPULLUP0 |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DP_TX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DN_TX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DP_RX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DN_RX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_D_RX |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_OE_N |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_SENSE |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| { |
| name: IO_UPHY_DPPULLUP |
| type: BidirStd |
| bank: VCC |
| connection: manual |
| desc: Manual USB UPHY signal for FPGA target |
| } |
| ] |
| } |
| pinmux: |
| { |
| special_signals: |
| [ |
| { |
| name: tap0 |
| pad: IOC0 |
| desc: TAP strap signal, maps to a stubbed-off MIO. |
| idx: 22 |
| } |
| { |
| name: tap1 |
| pad: IOB7 |
| desc: TAP strap signal, maps to MIO pad 16. |
| idx: 16 |
| } |
| { |
| name: dft0 |
| pad: IOC1 |
| desc: DFT strap signal, maps to a stubbed-off MIO. |
| idx: 23 |
| } |
| { |
| name: dft1 |
| pad: IOC12 |
| desc: DFT strap signal, maps to a stubbed-off MIO. |
| idx: 34 |
| } |
| { |
| name: tck |
| pad: SPI_DEV_CLK |
| desc: JTAG tck signal, overlaid on SPI_DEV. |
| idx: 58 |
| } |
| { |
| name: tms |
| pad: SPI_DEV_CS_L |
| desc: JTAG tms signal, overlaid on SPI_DEV. |
| idx: 59 |
| } |
| { |
| name: trst_n |
| pad: IOB9 |
| desc: JTAG trst_n signal, maps to MIO pad 18. |
| idx: 18 |
| } |
| { |
| name: tdi |
| pad: SPI_DEV_D0 |
| desc: JTAG tdi signal, overlaid on SPI_DEV. |
| idx: 51 |
| } |
| { |
| name: tdo |
| pad: SPI_DEV_D1 |
| desc: JTAG tdo signal, overlaid on SPI_DEV. |
| idx: 52 |
| } |
| ] |
| } |
| } |
| ] |
| exported_clks: |
| { |
| ast: |
| { |
| usbdev: |
| [ |
| io_div4_peri |
| aon_peri |
| usb_peri |
| ] |
| adc_ctrl_aon: |
| [ |
| io_div4_peri |
| aon_peri |
| ] |
| ast: |
| [ |
| io_div4_secure |
| ] |
| sensor_ctrl_aon: |
| [ |
| io_div4_secure |
| ] |
| entropy_src: |
| [ |
| main_secure |
| ] |
| edn0: |
| [ |
| main_secure |
| ] |
| } |
| } |
| wakeups: |
| [ |
| { |
| name: gsc_wk |
| width: "1" |
| module: sysrst_ctrl_aon |
| } |
| { |
| name: debug_cable_wakeup |
| width: "1" |
| module: adc_ctrl_aon |
| } |
| { |
| name: aon_wkup_req |
| width: "1" |
| module: pinmux_aon |
| } |
| { |
| name: usb_wkup_req |
| width: "1" |
| module: pinmux_aon |
| } |
| { |
| name: aon_timer_wkup_req |
| width: "1" |
| module: aon_timer_aon |
| } |
| ] |
| reset_requests: |
| [ |
| { |
| name: gsc_rst |
| width: "1" |
| module: sysrst_ctrl_aon |
| } |
| { |
| name: aon_timer_rst_req |
| width: "1" |
| module: aon_timer_aon |
| } |
| ] |
| interrupt_module: |
| [ |
| uart0 |
| uart1 |
| uart2 |
| uart3 |
| gpio |
| spi_device |
| spi_host0 |
| spi_host1 |
| i2c0 |
| i2c1 |
| i2c2 |
| pattgen |
| rv_timer |
| usbdev |
| otp_ctrl |
| alert_handler |
| pwrmgr_aon |
| sysrst_ctrl_aon |
| adc_ctrl_aon |
| aon_timer_aon |
| flash_ctrl |
| hmac |
| kmac |
| keymgr |
| csrng |
| entropy_src |
| edn0 |
| edn1 |
| otbn |
| ] |
| interrupt: |
| [ |
| { |
| name: uart0_tx_watermark |
| width: 1 |
| type: interrupt |
| module_name: uart0 |
| } |
| { |
| name: uart0_rx_watermark |
| width: 1 |
| type: interrupt |
| module_name: uart0 |
| } |
| { |
| name: uart0_tx_empty |
| width: 1 |
| type: interrupt |
| module_name: uart0 |
| } |
| { |
| name: uart0_rx_overflow |
| width: 1 |
| type: interrupt |
| module_name: uart0 |
| } |
| { |
| name: uart0_rx_frame_err |
| width: 1 |
| type: interrupt |
| module_name: uart0 |
| } |
| { |
| name: uart0_rx_break_err |
| width: 1 |
| type: interrupt |
| module_name: uart0 |
| } |
| { |
| name: uart0_rx_timeout |
| width: 1 |
| type: interrupt |
| module_name: uart0 |
| } |
| { |
| name: uart0_rx_parity_err |
| width: 1 |
| type: interrupt |
| module_name: uart0 |
| } |
| { |
| name: uart1_tx_watermark |
| width: 1 |
| type: interrupt |
| module_name: uart1 |
| } |
| { |
| name: uart1_rx_watermark |
| width: 1 |
| type: interrupt |
| module_name: uart1 |
| } |
| { |
| name: uart1_tx_empty |
| width: 1 |
| type: interrupt |
| module_name: uart1 |
| } |
| { |
| name: uart1_rx_overflow |
| width: 1 |
| type: interrupt |
| module_name: uart1 |
| } |
| { |
| name: uart1_rx_frame_err |
| width: 1 |
| type: interrupt |
| module_name: uart1 |
| } |
| { |
| name: uart1_rx_break_err |
| width: 1 |
| type: interrupt |
| module_name: uart1 |
| } |
| { |
| name: uart1_rx_timeout |
| width: 1 |
| type: interrupt |
| module_name: uart1 |
| } |
| { |
| name: uart1_rx_parity_err |
| width: 1 |
| type: interrupt |
| module_name: uart1 |
| } |
| { |
| name: uart2_tx_watermark |
| width: 1 |
| type: interrupt |
| module_name: uart2 |
| } |
| { |
| name: uart2_rx_watermark |
| width: 1 |
| type: interrupt |
| module_name: uart2 |
| } |
| { |
| name: uart2_tx_empty |
| width: 1 |
| type: interrupt |
| module_name: uart2 |
| } |
| { |
| name: uart2_rx_overflow |
| width: 1 |
| type: interrupt |
| module_name: uart2 |
| } |
| { |
| name: uart2_rx_frame_err |
| width: 1 |
| type: interrupt |
| module_name: uart2 |
| } |
| { |
| name: uart2_rx_break_err |
| width: 1 |
| type: interrupt |
| module_name: uart2 |
| } |
| { |
| name: uart2_rx_timeout |
| width: 1 |
| type: interrupt |
| module_name: uart2 |
| } |
| { |
| name: uart2_rx_parity_err |
| width: 1 |
| type: interrupt |
| module_name: uart2 |
| } |
| { |
| name: uart3_tx_watermark |
| width: 1 |
| type: interrupt |
| module_name: uart3 |
| } |
| { |
| name: uart3_rx_watermark |
| width: 1 |
| type: interrupt |
| module_name: uart3 |
| } |
| { |
| name: uart3_tx_empty |
| width: 1 |
| type: interrupt |
| module_name: uart3 |
| } |
| { |
| name: uart3_rx_overflow |
| width: 1 |
| type: interrupt |
| module_name: uart3 |
| } |
| { |
| name: uart3_rx_frame_err |
| width: 1 |
| type: interrupt |
| module_name: uart3 |
| } |
| { |
| name: uart3_rx_break_err |
| width: 1 |
| type: interrupt |
| module_name: uart3 |
| } |
| { |
| name: uart3_rx_timeout |
| width: 1 |
| type: interrupt |
| module_name: uart3 |
| } |
| { |
| name: uart3_rx_parity_err |
| width: 1 |
| type: interrupt |
| module_name: uart3 |
| } |
| { |
| name: gpio_gpio |
| width: 32 |
| type: interrupt |
| module_name: gpio |
| } |
| { |
| name: spi_device_rxf |
| width: 1 |
| type: interrupt |
| module_name: spi_device |
| } |
| { |
| name: spi_device_rxlvl |
| width: 1 |
| type: interrupt |
| module_name: spi_device |
| } |
| { |
| name: spi_device_txlvl |
| width: 1 |
| type: interrupt |
| module_name: spi_device |
| } |
| { |
| name: spi_device_rxerr |
| width: 1 |
| type: interrupt |
| module_name: spi_device |
| } |
| { |
| name: spi_device_rxoverflow |
| width: 1 |
| type: interrupt |
| module_name: spi_device |
| } |
| { |
| name: spi_device_txunderflow |
| width: 1 |
| type: interrupt |
| module_name: spi_device |
| } |
| { |
| name: spi_host0_error |
| width: 1 |
| type: interrupt |
| module_name: spi_host0 |
| } |
| { |
| name: spi_host0_spi_event |
| width: 1 |
| type: interrupt |
| module_name: spi_host0 |
| } |
| { |
| name: spi_host1_error |
| width: 1 |
| type: interrupt |
| module_name: spi_host1 |
| } |
| { |
| name: spi_host1_spi_event |
| width: 1 |
| type: interrupt |
| module_name: spi_host1 |
| } |
| { |
| name: i2c0_fmt_watermark |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_rx_watermark |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_fmt_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_rx_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_nak |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_scl_interference |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_sda_interference |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_stretch_timeout |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_sda_unstable |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_trans_complete |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_tx_empty |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_tx_nonempty |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_tx_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_acq_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_ack_stop |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c0_host_timeout |
| width: 1 |
| type: interrupt |
| module_name: i2c0 |
| } |
| { |
| name: i2c1_fmt_watermark |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_rx_watermark |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_fmt_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_rx_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_nak |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_scl_interference |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_sda_interference |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_stretch_timeout |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_sda_unstable |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_trans_complete |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_tx_empty |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_tx_nonempty |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_tx_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_acq_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_ack_stop |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c1_host_timeout |
| width: 1 |
| type: interrupt |
| module_name: i2c1 |
| } |
| { |
| name: i2c2_fmt_watermark |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_rx_watermark |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_fmt_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_rx_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_nak |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_scl_interference |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_sda_interference |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_stretch_timeout |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_sda_unstable |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_trans_complete |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_tx_empty |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_tx_nonempty |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_tx_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_acq_overflow |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_ack_stop |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: i2c2_host_timeout |
| width: 1 |
| type: interrupt |
| module_name: i2c2 |
| } |
| { |
| name: pattgen_done_ch0 |
| width: 1 |
| type: interrupt |
| module_name: pattgen |
| } |
| { |
| name: pattgen_done_ch1 |
| width: 1 |
| type: interrupt |
| module_name: pattgen |
| } |
| { |
| name: rv_timer_timer_expired_0_0 |
| width: 1 |
| type: interrupt |
| module_name: rv_timer |
| } |
| { |
| name: usbdev_pkt_received |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_pkt_sent |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_disconnected |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_host_lost |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_link_reset |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_link_suspend |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_link_resume |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_av_empty |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_rx_full |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_av_overflow |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_link_in_err |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_rx_crc_err |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_rx_pid_err |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_rx_bitstuff_err |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_frame |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_connected |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: usbdev_link_out_err |
| width: 1 |
| type: interrupt |
| module_name: usbdev |
| } |
| { |
| name: otp_ctrl_otp_operation_done |
| width: 1 |
| type: interrupt |
| module_name: otp_ctrl |
| } |
| { |
| name: otp_ctrl_otp_error |
| width: 1 |
| type: interrupt |
| module_name: otp_ctrl |
| } |
| { |
| name: alert_handler_classa |
| width: 1 |
| type: interrupt |
| module_name: alert_handler |
| } |
| { |
| name: alert_handler_classb |
| width: 1 |
| type: interrupt |
| module_name: alert_handler |
| } |
| { |
| name: alert_handler_classc |
| width: 1 |
| type: interrupt |
| module_name: alert_handler |
| } |
| { |
| name: alert_handler_classd |
| width: 1 |
| type: interrupt |
| module_name: alert_handler |
| } |
| { |
| name: pwrmgr_aon_wakeup |
| width: 1 |
| type: interrupt |
| module_name: pwrmgr_aon |
| } |
| { |
| name: sysrst_ctrl_aon_sysrst_ctrl |
| width: 1 |
| type: interrupt |
| module_name: sysrst_ctrl_aon |
| } |
| { |
| name: adc_ctrl_aon_debug_cable |
| width: 1 |
| type: interrupt |
| module_name: adc_ctrl_aon |
| } |
| { |
| name: aon_timer_aon_wkup_timer_expired |
| width: 1 |
| type: interrupt |
| module_name: aon_timer_aon |
| } |
| { |
| name: aon_timer_aon_wdog_timer_bark |
| width: 1 |
| type: interrupt |
| module_name: aon_timer_aon |
| } |
| { |
| name: flash_ctrl_prog_empty |
| width: 1 |
| type: interrupt |
| module_name: flash_ctrl |
| } |
| { |
| name: flash_ctrl_prog_lvl |
| width: 1 |
| type: interrupt |
| module_name: flash_ctrl |
| } |
| { |
| name: flash_ctrl_rd_full |
| width: 1 |
| type: interrupt |
| module_name: flash_ctrl |
| } |
| { |
| name: flash_ctrl_rd_lvl |
| width: 1 |
| type: interrupt |
| module_name: flash_ctrl |
| } |
| { |
| name: flash_ctrl_op_done |
| width: 1 |
| type: interrupt |
| module_name: flash_ctrl |
| } |
| { |
| name: flash_ctrl_err |
| width: 1 |
| type: interrupt |
| module_name: flash_ctrl |
| } |
| { |
| name: hmac_hmac_done |
| width: 1 |
| type: interrupt |
| module_name: hmac |
| } |
| { |
| name: hmac_fifo_empty |
| width: 1 |
| type: interrupt |
| module_name: hmac |
| } |
| { |
| name: hmac_hmac_err |
| width: 1 |
| type: interrupt |
| module_name: hmac |
| } |
| { |
| name: kmac_kmac_done |
| width: 1 |
| type: interrupt |
| module_name: kmac |
| } |
| { |
| name: kmac_fifo_empty |
| width: 1 |
| type: interrupt |
| module_name: kmac |
| } |
| { |
| name: kmac_kmac_err |
| width: 1 |
| type: interrupt |
| module_name: kmac |
| } |
| { |
| name: keymgr_op_done |
| width: 1 |
| type: interrupt |
| module_name: keymgr |
| } |
| { |
| name: csrng_cs_cmd_req_done |
| width: 1 |
| type: interrupt |
| module_name: csrng |
| } |
| { |
| name: csrng_cs_entropy_req |
| width: 1 |
| type: interrupt |
| module_name: csrng |
| } |
| { |
| name: csrng_cs_hw_inst_exc |
| width: 1 |
| type: interrupt |
| module_name: csrng |
| } |
| { |
| name: csrng_cs_fatal_err |
| width: 1 |
| type: interrupt |
| module_name: csrng |
| } |
| { |
| name: entropy_src_es_entropy_valid |
| width: 1 |
| type: interrupt |
| module_name: entropy_src |
| } |
| { |
| name: entropy_src_es_health_test_failed |
| width: 1 |
| type: interrupt |
| module_name: entropy_src |
| } |
| { |
| name: entropy_src_es_observe_fifo_ready |
| width: 1 |
| type: interrupt |
| module_name: entropy_src |
| } |
| { |
| name: entropy_src_es_fatal_err |
| width: 1 |
| type: interrupt |
| module_name: entropy_src |
| } |
| { |
| name: edn0_edn_cmd_req_done |
| width: 1 |
| type: interrupt |
| module_name: edn0 |
| } |
| { |
| name: edn0_edn_fatal_err |
| width: 1 |
| type: interrupt |
| module_name: edn0 |
| } |
| { |
| name: edn1_edn_cmd_req_done |
| width: 1 |
| type: interrupt |
| module_name: edn1 |
| } |
| { |
| name: edn1_edn_fatal_err |
| width: 1 |
| type: interrupt |
| module_name: edn1 |
| } |
| { |
| name: otbn_done |
| width: 1 |
| type: interrupt |
| module_name: otbn |
| } |
| ] |
| alert_module: |
| [ |
| uart0 |
| uart1 |
| uart2 |
| uart3 |
| gpio |
| spi_device |
| spi_host0 |
| spi_host1 |
| i2c0 |
| i2c1 |
| i2c2 |
| pattgen |
| rv_timer |
| usbdev |
| otp_ctrl |
| lc_ctrl |
| pwrmgr_aon |
| rstmgr_aon |
| clkmgr_aon |
| sysrst_ctrl_aon |
| adc_ctrl_aon |
| pwm_aon |
| pinmux_aon |
| aon_timer_aon |
| sensor_ctrl_aon |
| sram_ctrl_ret_aon |
| flash_ctrl |
| rv_dm |
| rv_plic |
| aes |
| hmac |
| kmac |
| keymgr |
| csrng |
| entropy_src |
| edn0 |
| edn1 |
| sram_ctrl_main |
| otbn |
| rom_ctrl |
| rv_core_ibex |
| ] |
| alert: |
| [ |
| { |
| name: uart0_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: uart0 |
| } |
| { |
| name: uart1_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: uart1 |
| } |
| { |
| name: uart2_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: uart2 |
| } |
| { |
| name: uart3_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: uart3 |
| } |
| { |
| name: gpio_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: gpio |
| } |
| { |
| name: spi_device_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: spi_device |
| } |
| { |
| name: spi_host0_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: spi_host0 |
| } |
| { |
| name: spi_host1_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: spi_host1 |
| } |
| { |
| name: i2c0_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: i2c0 |
| } |
| { |
| name: i2c1_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: i2c1 |
| } |
| { |
| name: i2c2_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: i2c2 |
| } |
| { |
| name: pattgen_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: pattgen |
| } |
| { |
| name: rv_timer_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: rv_timer |
| } |
| { |
| name: usbdev_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: usbdev |
| } |
| { |
| name: otp_ctrl_fatal_macro_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: otp_ctrl |
| } |
| { |
| name: otp_ctrl_fatal_check_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: otp_ctrl |
| } |
| { |
| name: otp_ctrl_fatal_bus_integ_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: otp_ctrl |
| } |
| { |
| name: lc_ctrl_fatal_prog_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: lc_ctrl |
| } |
| { |
| name: lc_ctrl_fatal_state_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: lc_ctrl |
| } |
| { |
| name: lc_ctrl_fatal_bus_integ_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: lc_ctrl |
| } |
| { |
| name: pwrmgr_aon_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: pwrmgr_aon |
| } |
| { |
| name: rstmgr_aon_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: rstmgr_aon |
| } |
| { |
| name: clkmgr_aon_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: clkmgr_aon |
| } |
| { |
| name: sysrst_ctrl_aon_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sysrst_ctrl_aon |
| } |
| { |
| name: adc_ctrl_aon_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: adc_ctrl_aon |
| } |
| { |
| name: pwm_aon_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: pwm_aon |
| } |
| { |
| name: pinmux_aon_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: pinmux_aon |
| } |
| { |
| name: aon_timer_aon_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: aon_timer_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_as |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_cg |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_gd |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_ts_hi |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_ts_lo |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_fla |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_otp |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_ot0 |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_ot1 |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_ot2 |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_ot3 |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_ot4 |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sensor_ctrl_aon_recov_ot5 |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sensor_ctrl_aon |
| } |
| { |
| name: sram_ctrl_ret_aon_fatal_intg_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sram_ctrl_ret_aon |
| } |
| { |
| name: sram_ctrl_ret_aon_fatal_parity_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sram_ctrl_ret_aon |
| } |
| { |
| name: flash_ctrl_recov_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: flash_ctrl |
| } |
| { |
| name: flash_ctrl_recov_mp_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: flash_ctrl |
| } |
| { |
| name: flash_ctrl_recov_ecc_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: flash_ctrl |
| } |
| { |
| name: flash_ctrl_fatal_intg_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: flash_ctrl |
| } |
| { |
| name: rv_dm_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: rv_dm |
| } |
| { |
| name: rv_plic_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: rv_plic |
| } |
| { |
| name: aes_recov_ctrl_update_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: aes |
| } |
| { |
| name: aes_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: aes |
| } |
| { |
| name: hmac_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: hmac |
| } |
| { |
| name: kmac_fatal_fault |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: kmac |
| } |
| { |
| name: keymgr_fatal_fault_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: keymgr |
| } |
| { |
| name: keymgr_recov_operation_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: keymgr |
| } |
| { |
| name: csrng_fatal_alert |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: csrng |
| } |
| { |
| name: entropy_src_recov_alert |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: entropy_src |
| } |
| { |
| name: entropy_src_fatal_alert |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: entropy_src |
| } |
| { |
| name: edn0_fatal_alert |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: edn0 |
| } |
| { |
| name: edn1_fatal_alert |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: edn1 |
| } |
| { |
| name: sram_ctrl_main_fatal_intg_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sram_ctrl_main |
| } |
| { |
| name: sram_ctrl_main_fatal_parity_error |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: sram_ctrl_main |
| } |
| { |
| name: otbn_fatal |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: otbn |
| } |
| { |
| name: otbn_recov |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: otbn |
| } |
| { |
| name: rom_ctrl_fatal |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: rom_ctrl |
| } |
| { |
| name: rv_core_ibex_fatal_sw_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: rv_core_ibex |
| } |
| { |
| name: rv_core_ibex_recov_sw_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: rv_core_ibex |
| } |
| { |
| name: rv_core_ibex_fatal_hw_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: rv_core_ibex |
| } |
| { |
| name: rv_core_ibex_recov_hw_err |
| width: 1 |
| type: alert |
| async: "1" |
| module_name: rv_core_ibex |
| } |
| ] |
| exported_rsts: |
| { |
| ast: |
| { |
| usbdev: |
| [ |
| sys_io_div4 |
| sys_aon |
| usb |
| ] |
| adc_ctrl_aon: |
| [ |
| sys_io_div4 |
| sys_aon |
| ] |
| ast: |
| [ |
| sys_io_div4 |
| ] |
| sensor_ctrl_aon: |
| [ |
| sys_io_div4 |
| ] |
| entropy_src: |
| [ |
| sys |
| ] |
| edn0: |
| [ |
| sys |
| ] |
| } |
| } |
| inter_signal: |
| { |
| signals: |
| [ |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart0 |
| default: "" |
| end_idx: -1 |
| top_signame: uart0_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart1 |
| default: "" |
| end_idx: -1 |
| top_signame: uart1_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart2 |
| default: "" |
| end_idx: -1 |
| top_signame: uart2_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: uart3 |
| default: "" |
| end_idx: -1 |
| top_signame: uart3_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: gpio |
| default: "" |
| end_idx: -1 |
| top_signame: gpio_tl |
| index: -1 |
| } |
| { |
| name: ram_cfg |
| struct: ram_2p_cfg |
| package: prim_ram_2p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| top_signame: ast_ram_2p_cfg |
| index: -1 |
| } |
| { |
| name: passthrough |
| struct: passthrough |
| package: spi_device_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| end_idx: -1 |
| top_signame: spi_device_passthrough |
| index: -1 |
| } |
| { |
| name: mbist_en |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: spi_device |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_device |
| default: "" |
| end_idx: -1 |
| top_signame: spi_device_tl |
| index: -1 |
| } |
| { |
| name: passthrough |
| struct: passthrough |
| package: spi_device_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host0 |
| default: "" |
| top_signame: spi_device_passthrough |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host0 |
| default: "" |
| end_idx: -1 |
| top_signame: spi_host0_tl |
| index: -1 |
| } |
| { |
| name: passthrough |
| struct: passthrough |
| package: spi_device_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host1 |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: spi_host1 |
| default: "" |
| end_idx: -1 |
| top_signame: spi_host1_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: i2c0 |
| default: "" |
| end_idx: -1 |
| top_signame: i2c0_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: i2c1 |
| default: "" |
| end_idx: -1 |
| top_signame: i2c1_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: i2c2 |
| default: "" |
| end_idx: -1 |
| top_signame: i2c2_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pattgen |
| default: "" |
| end_idx: -1 |
| top_signame: pattgen_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_timer |
| default: "" |
| end_idx: -1 |
| top_signame: rv_timer_tl |
| index: -1 |
| } |
| { |
| name: usb_ref_val |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_ref_val |
| index: -1 |
| } |
| { |
| name: usb_ref_pulse |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| external: true |
| top_signame: usbdev_usb_ref_pulse |
| index: -1 |
| } |
| { |
| name: usb_out_of_rst |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_out_of_rst |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_en |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_aon_wake_en |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_ack |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_aon_wake_ack |
| index: -1 |
| } |
| { |
| name: usb_suspend |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: usbdev_usb_suspend |
| index: -1 |
| } |
| { |
| name: usb_state_debug |
| struct: awk_state |
| package: usbdev_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| top_signame: pinmux_aon_usb_state_debug |
| index: -1 |
| } |
| { |
| name: ram_cfg |
| struct: ram_2p_cfg |
| package: prim_ram_2p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| top_signame: ast_ram_2p_cfg |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: usbdev |
| default: "" |
| end_idx: -1 |
| top_signame: usbdev_tl |
| index: -1 |
| } |
| { |
| name: otp_ast_pwr_seq |
| struct: otp_ast_req |
| package: otp_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| external: true |
| top_signame: otp_ctrl_otp_ast_pwr_seq |
| index: -1 |
| } |
| { |
| name: otp_ast_pwr_seq_h |
| struct: otp_ast_rsp |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| external: true |
| top_signame: otp_ctrl_otp_ast_pwr_seq_h |
| index: -1 |
| } |
| { |
| name: otp_alert |
| struct: ast_dif |
| package: ast_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| external: true |
| top_signame: otp_alert |
| index: -1 |
| } |
| { |
| name: edn |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| top_signame: edn0_edn |
| index: 1 |
| } |
| { |
| name: pwr_otp |
| struct: pwr_otp |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: pwrmgr_aon_pwr_otp |
| index: -1 |
| } |
| { |
| name: lc_otp_program |
| struct: lc_otp_program |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_otp_program |
| index: -1 |
| } |
| { |
| name: otp_lc_data |
| struct: otp_lc_data |
| package: otp_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: otp_ctrl_otp_lc_data |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_creator_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_creator_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_seed_hw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_seed_hw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_check_byp_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otp_ctrl |
| top_signame: lc_ctrl_lc_check_byp_en |
| index: -1 |
| } |
| { |
| name: otp_keymgr_key |
| struct: otp_keymgr_key |
| package: otp_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: otp_ctrl_otp_keymgr_key |
| index: -1 |
| } |
| { |
| name: flash_otp_key |
| struct: flash_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: flash_ctrl_otp |
| index: -1 |
| } |
| { |
| name: sram_otp_key |
| struct: sram_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 2 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: otp_ctrl_sram_otp_key |
| index: -1 |
| } |
| { |
| name: otbn_otp_key |
| struct: otbn_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| end_idx: -1 |
| top_signame: otp_ctrl_otbn_otp_key |
| index: -1 |
| } |
| { |
| name: otp_hw_cfg |
| struct: otp_hw_cfg |
| package: otp_ctrl_part_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otp_ctrl |
| top_signame: otp_ctrl_otp_hw_cfg |
| index: -1 |
| } |
| { |
| name: core_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: otp_ctrl_core_tl |
| index: -1 |
| } |
| { |
| name: prim_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: otp_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: otp_ctrl_prim_tl |
| index: -1 |
| } |
| { |
| name: jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: pinmux_aon_lc_jtag |
| index: -1 |
| } |
| { |
| name: esc_scrap_state0_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 1 |
| } |
| { |
| name: esc_scrap_state0_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 1 |
| } |
| { |
| name: esc_scrap_state1_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 2 |
| } |
| { |
| name: esc_scrap_state1_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 2 |
| } |
| { |
| name: pwr_lc |
| struct: pwr_lc |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| top_signame: pwrmgr_aon_pwr_lc |
| index: -1 |
| } |
| { |
| name: otp_lc_data |
| struct: otp_lc_data |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT |
| inst_name: lc_ctrl |
| top_signame: otp_ctrl_otp_lc_data |
| index: -1 |
| } |
| { |
| name: lc_otp_program |
| struct: lc_otp_program |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_signame: lc_ctrl_lc_otp_program |
| index: -1 |
| } |
| { |
| name: kmac_data |
| struct: app |
| package: kmac_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: kmac_app |
| index: 1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_nvm_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_nvm_debug_en |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: lc_cpu_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_cpu_en |
| index: -1 |
| } |
| { |
| name: lc_keymgr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_keymgr_en |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_clk_byp_req |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_clk_byp_ack |
| index: -1 |
| } |
| { |
| name: lc_flash_rma_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| top_signame: flash_ctrl_rma_req |
| index: -1 |
| } |
| { |
| name: lc_flash_rma_seed |
| struct: lc_flash_rma_seed |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: flash_ctrl_rma_seed |
| index: -1 |
| } |
| { |
| name: lc_flash_rma_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| top_signame: flash_ctrl_rma_ack |
| index: -1 |
| } |
| { |
| name: lc_check_byp_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_check_byp_en |
| index: -1 |
| } |
| { |
| name: lc_creator_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_creator_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_owner_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_owner_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_iso_part_sw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_wr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_iso_part_sw_wr_en |
| index: -1 |
| } |
| { |
| name: lc_seed_hw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_seed_hw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_keymgr_div |
| struct: lc_keymgr_div |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: lc_ctrl_lc_keymgr_div |
| index: -1 |
| } |
| { |
| name: otp_device_id |
| struct: otp_device_id |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: lc_ctrl |
| top_signame: lc_ctrl_otp_device_id |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: lc_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: lc_ctrl_tl |
| index: -1 |
| } |
| { |
| name: crashdump |
| struct: alert_crashdump |
| package: alert_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: alert_handler_crashdump |
| index: -1 |
| } |
| { |
| name: edn |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: alert_handler |
| default: "" |
| top_signame: edn0_edn |
| index: 4 |
| } |
| { |
| name: esc_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 4 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: alert_handler_esc_rx |
| index: -1 |
| } |
| { |
| name: esc_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 4 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: alert_handler_esc_tx |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: alert_handler |
| default: "" |
| end_idx: -1 |
| top_signame: alert_handler_tl |
| index: -1 |
| } |
| { |
| name: pwr_ast |
| struct: pwr_ast |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| external: true |
| top_signame: pwrmgr_ast |
| index: -1 |
| } |
| { |
| name: pwr_rst |
| struct: pwr_rst |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_rst |
| index: -1 |
| } |
| { |
| name: pwr_clk |
| struct: pwr_clk |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_clk |
| index: -1 |
| } |
| { |
| name: pwr_otp |
| struct: pwr_otp |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_otp |
| index: -1 |
| } |
| { |
| name: pwr_lc |
| struct: pwr_lc |
| package: pwrmgr_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_pwr_lc |
| index: -1 |
| } |
| { |
| name: pwr_flash |
| struct: pwr_flash |
| package: pwrmgr_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_pwr_flash |
| index: -1 |
| } |
| { |
| name: esc_rst_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 3 |
| } |
| { |
| name: esc_rst_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 3 |
| } |
| { |
| name: pwr_cpu |
| struct: pwr_cpu |
| package: pwrmgr_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: rv_core_ibex_pwrmgr |
| index: -1 |
| } |
| { |
| name: wakeups |
| struct: logic |
| type: uni |
| act: rcv |
| width: 5 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: pwrmgr_aon_wakeups |
| index: -1 |
| } |
| { |
| name: rstreqs |
| struct: logic |
| type: uni |
| act: rcv |
| width: 2 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: pwrmgr_aon_rstreqs |
| index: -1 |
| } |
| { |
| name: strap |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_strap |
| index: -1 |
| } |
| { |
| name: low_power |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_low_power |
| index: -1 |
| } |
| { |
| name: rom_ctrl |
| struct: pwrmgr_data |
| package: rom_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| top_signame: rom_ctrl_pwrmgr_data |
| index: -1 |
| } |
| { |
| name: fetch_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pwrmgr_aon_fetch_en |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pwrmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwrmgr_aon_tl |
| index: -1 |
| } |
| { |
| name: pwr |
| struct: pwr_rst |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| package: pwrmgr_pkg |
| top_signame: pwrmgr_aon_pwr_rst |
| index: -1 |
| } |
| { |
| name: resets |
| struct: rstmgr_out |
| package: rstmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: rstmgr_aon_resets |
| index: -1 |
| } |
| { |
| name: rst_cpu_n |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| package: "" |
| top_signame: rv_core_ibex_rst_cpu_n |
| index: -1 |
| } |
| { |
| name: ndmreset_req |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| package: "" |
| top_signame: rv_dm_ndmreset_req |
| index: -1 |
| } |
| { |
| name: alert_dump |
| struct: alert_crashdump |
| package: alert_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: alert_handler_crashdump |
| index: -1 |
| } |
| { |
| name: cpu_dump |
| struct: crash_dump |
| package: ibex_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| top_signame: rv_core_ibex_crash_dump |
| index: -1 |
| } |
| { |
| name: resets_ast |
| struct: rstmgr_ast_out |
| package: rstmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| external: true |
| top_signame: rsts_ast |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rstmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: rstmgr_aon_tl |
| index: -1 |
| } |
| { |
| name: clocks |
| struct: clkmgr_out |
| package: clkmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: clkmgr_aon_clocks |
| index: -1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: ast_clk_byp_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: ast_clk_byp_req |
| index: -1 |
| } |
| { |
| name: ast_clk_byp_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: ast_clk_byp_ack |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_clk_byp_req |
| index: -1 |
| } |
| { |
| name: lc_clk_byp_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| top_signame: lc_ctrl_lc_clk_byp_ack |
| index: -1 |
| } |
| { |
| name: jitter_en |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_main_jitter_en |
| index: -1 |
| } |
| { |
| name: clk_main |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_main |
| index: -1 |
| } |
| { |
| name: clk_io |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_io |
| index: -1 |
| } |
| { |
| name: clk_usb |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_usb |
| index: -1 |
| } |
| { |
| name: clk_aon |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: clk_aon |
| index: -1 |
| } |
| { |
| name: clocks_ast |
| struct: clkmgr_ast_out |
| package: clkmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| external: true |
| top_signame: clks_ast |
| index: -1 |
| } |
| { |
| name: pwr |
| struct: pwr_clk |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| package: pwrmgr_pkg |
| top_signame: pwrmgr_aon_pwr_clk |
| index: -1 |
| } |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: rcv |
| width: 5 |
| inst_name: clkmgr_aon |
| default: "" |
| package: "" |
| end_idx: 4 |
| top_type: partial-one-to-N |
| top_signame: clkmgr_aon_idle |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: clkmgr_aon |
| default: "" |
| end_idx: -1 |
| top_signame: clkmgr_aon_tl |
| index: -1 |
| } |
| { |
| name: gsc_wk |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sysrst_ctrl_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 0 |
| } |
| { |
| name: gsc_rst |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sysrst_ctrl_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_rstreqs |
| index: 0 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sysrst_ctrl_aon |
| default: "" |
| end_idx: -1 |
| top_signame: sysrst_ctrl_aon_tl |
| index: -1 |
| } |
| { |
| name: adc |
| struct: adc_ast |
| package: ast_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: adc_ctrl_aon |
| default: "" |
| external: true |
| top_signame: adc |
| index: -1 |
| } |
| { |
| name: debug_cable_wakeup |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: adc_ctrl_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: adc_ctrl_aon |
| default: "" |
| end_idx: -1 |
| top_signame: adc_ctrl_aon_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pwm_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pwm_aon_tl |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: pinmux_aon |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: lc_dft_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: pinmux_aon |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| } |
| { |
| name: lc_jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pinmux_aon_lc_jtag |
| index: -1 |
| } |
| { |
| name: rv_jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pinmux_aon_rv_jtag |
| index: -1 |
| } |
| { |
| name: dft_jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| top_signame: pinmux_aon_dft_jtag |
| index: -1 |
| } |
| { |
| name: dft_strap_test |
| struct: dft_strap_test_req |
| package: pinmux_pkg |
| type: uni |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: pinmux_aon |
| external: true |
| top_signame: dft_strap_test |
| index: -1 |
| } |
| { |
| name: dft_hold_tap_sel |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: pinmux_aon |
| package: "" |
| external: true |
| top_signame: dft_hold_tap_sel |
| index: -1 |
| } |
| { |
| name: sleep_en |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_low_power |
| index: -1 |
| } |
| { |
| name: strap_en |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_strap |
| index: -1 |
| } |
| { |
| name: aon_wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 2 |
| } |
| { |
| name: usb_wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: pinmux_aon |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 3 |
| } |
| { |
| name: usb_out_of_rst |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_out_of_rst |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_en |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_aon_wake_en |
| index: -1 |
| } |
| { |
| name: usb_aon_wake_ack |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_aon_wake_ack |
| index: -1 |
| } |
| { |
| name: usb_suspend |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| package: "" |
| top_signame: usbdev_usb_suspend |
| index: -1 |
| } |
| { |
| name: usb_state_debug |
| struct: awk_state |
| package: usbdev_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: pinmux_aon_usb_state_debug |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: pinmux_aon |
| default: "" |
| end_idx: -1 |
| top_signame: pinmux_aon_tl |
| index: -1 |
| } |
| { |
| name: aon_timer_wkup_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: aon_timer_aon |
| package: "" |
| top_signame: pwrmgr_aon_wakeups |
| index: 4 |
| } |
| { |
| name: aon_timer_rst_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| default: 1'b0 |
| inst_name: aon_timer_aon |
| package: "" |
| top_signame: pwrmgr_aon_rstreqs |
| index: 1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: aon_timer_aon |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: sleep_mode |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: aon_timer_aon |
| default: "" |
| package: "" |
| top_signame: pwrmgr_aon_low_power |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: aon_timer_aon |
| default: "" |
| end_idx: -1 |
| top_signame: aon_timer_aon_tl |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: ast |
| index: -1 |
| } |
| { |
| name: ast_alert |
| struct: ast_alert |
| package: ast_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| external: true |
| top_signame: sensor_ctrl_ast_alert |
| index: -1 |
| } |
| { |
| name: ast_status |
| struct: ast_status |
| package: ast_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| external: true |
| top_signame: sensor_ctrl_ast_status |
| index: -1 |
| } |
| { |
| name: ast_init_done |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: ast_init_done |
| index: -1 |
| } |
| { |
| name: ast2pinmux |
| struct: logic |
| type: uni |
| act: rcv |
| width: 9 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| package: "" |
| external: true |
| top_signame: ast2pinmux |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sensor_ctrl_aon |
| default: "" |
| end_idx: -1 |
| top_signame: sensor_ctrl_aon_tl |
| index: -1 |
| } |
| { |
| name: sram_otp_key |
| struct: sram_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_ret_aon |
| top_signame: otp_ctrl_sram_otp_key |
| index: 1 |
| } |
| { |
| name: sram_scr |
| struct: sram_scr |
| package: sram_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_ret_aon |
| end_idx: -1 |
| top_signame: sram_ctrl_ret_aon_sram_scr |
| index: -1 |
| } |
| { |
| name: sram_scr_init |
| struct: sram_scr_init |
| package: sram_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_ret_aon |
| end_idx: -1 |
| top_signame: sram_ctrl_ret_aon_sram_scr_init |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: sram_ctrl_ret_aon |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: sram_ctrl_ret_aon |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: otp_en_sram_ifetch |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_ret_aon |
| top_signame: sram_ctrl_ret_aon_otp_en_sram_ifetch |
| index: -1 |
| } |
| { |
| name: en_ifetch |
| struct: tl_instr_en |
| package: tlul_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sram_ctrl_ret_aon |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: sram_ctrl_ret_aon_en_ifetch |
| index: -1 |
| } |
| { |
| name: intg_error |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: sram_ctrl_ret_aon |
| default: "" |
| package: "" |
| top_signame: ram_ret_aon_intg_error |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sram_ctrl_ret_aon |
| default: "" |
| end_idx: -1 |
| top_signame: sram_ctrl_ret_aon_tl |
| index: -1 |
| } |
| { |
| name: flash |
| struct: flash |
| package: flash_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: flash_ctrl_flash |
| index: -1 |
| } |
| { |
| name: otp |
| struct: flash_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: flash_ctrl_otp |
| index: -1 |
| } |
| { |
| name: lc_creator_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_creator_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_owner_seed_sw_rw_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_owner_seed_sw_rw_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_iso_part_sw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_iso_part_sw_wr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_iso_part_sw_wr_en |
| index: -1 |
| } |
| { |
| name: lc_seed_hw_rd_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_seed_hw_rd_en |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: rma_req |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: flash_ctrl_rma_req |
| index: -1 |
| } |
| { |
| name: rma_ack |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: flash_ctrl_rma_ack |
| index: -1 |
| } |
| { |
| name: rma_seed |
| struct: lc_flash_rma_seed |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: flash_ctrl_rma_seed |
| index: -1 |
| } |
| { |
| name: pwrmgr |
| struct: pwr_flash |
| package: pwrmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| top_signame: pwrmgr_aon_pwr_flash |
| index: -1 |
| } |
| { |
| name: keymgr |
| struct: keymgr_flash |
| package: flash_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: flash_ctrl_keymgr |
| index: -1 |
| } |
| { |
| name: core_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: flash_ctrl_core_tl |
| index: -1 |
| } |
| { |
| name: prim_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: flash_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: flash_ctrl_prim_tl |
| index: -1 |
| } |
| { |
| name: jtag |
| struct: jtag |
| package: jtag_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| top_signame: pinmux_aon_rv_jtag |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: rv_dm |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: unavailable |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| default: 1'b0 |
| inst_name: rv_dm |
| index: -1 |
| } |
| { |
| name: ndmreset_req |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_dm_ndmreset_req |
| index: -1 |
| } |
| { |
| name: dmactive |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_dm |
| index: -1 |
| } |
| { |
| name: debug_req |
| struct: logic [rv_dm_reg_pkg::NrHarts-1:0] |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_dm_debug_req |
| index: -1 |
| } |
| { |
| name: sba_tl_h |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| top_signame: main_tl_rv_dm__sba |
| index: -1 |
| } |
| { |
| name: regs_tl_d |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| end_idx: -1 |
| top_signame: rv_dm_regs_tl_d |
| index: -1 |
| } |
| { |
| name: rom_tl_d |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_dm |
| default: "" |
| end_idx: -1 |
| top_signame: rv_dm_rom_tl_d |
| index: -1 |
| } |
| { |
| name: irq |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_plic |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_plic_irq |
| index: -1 |
| } |
| { |
| name: irq_id |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_plic |
| index: -1 |
| } |
| { |
| name: msip |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_plic |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_plic_msip |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_plic |
| default: "" |
| end_idx: -1 |
| top_signame: rv_plic_tl |
| index: -1 |
| } |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: aes |
| default: "" |
| package: "" |
| top_signame: clkmgr_aon_idle |
| index: 0 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: aes |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: edn |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: aes |
| default: "" |
| top_signame: edn0_edn |
| index: 5 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: aes |
| default: "" |
| end_idx: -1 |
| top_signame: aes_tl |
| index: -1 |
| } |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: hmac |
| default: "" |
| package: "" |
| top_signame: clkmgr_aon_idle |
| index: 1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: hmac |
| default: "" |
| end_idx: -1 |
| top_signame: hmac_tl |
| index: -1 |
| } |
| { |
| name: keymgr_key |
| struct: hw_key_req |
| package: keymgr_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: kmac |
| default: "" |
| top_signame: keymgr_kmac_key |
| index: -1 |
| } |
| { |
| name: app |
| struct: app |
| package: kmac_pkg |
| type: req_rsp |
| act: rsp |
| width: 3 |
| inst_name: kmac |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: kmac_app |
| index: -1 |
| } |
| { |
| name: entropy |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: kmac |
| default: "" |
| top_signame: edn0_edn |
| index: 3 |
| } |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: kmac |
| default: "" |
| package: "" |
| top_signame: clkmgr_aon_idle |
| index: 2 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: kmac |
| default: "" |
| end_idx: -1 |
| top_signame: kmac_tl |
| index: -1 |
| } |
| { |
| name: edn |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: edn0_edn |
| index: 0 |
| } |
| { |
| name: aes_key |
| struct: hw_key_req |
| package: keymgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: keymgr |
| index: -1 |
| } |
| { |
| name: hmac_key |
| struct: hw_key_req |
| package: keymgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: keymgr |
| index: -1 |
| } |
| { |
| name: kmac_key |
| struct: hw_key_req |
| package: keymgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: keymgr_kmac_key |
| index: -1 |
| } |
| { |
| name: otbn_key |
| struct: otbn_key_req |
| package: keymgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: keymgr |
| index: -1 |
| } |
| { |
| name: kmac_data |
| struct: app |
| package: kmac_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: kmac_app |
| index: 0 |
| } |
| { |
| name: otp_key |
| struct: otp_keymgr_key |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: otp_ctrl_otp_keymgr_key |
| index: -1 |
| } |
| { |
| name: otp_device_id |
| struct: otp_device_id |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: keymgr_otp_device_id |
| index: -1 |
| } |
| { |
| name: flash |
| struct: keymgr_flash |
| package: flash_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: flash_ctrl_keymgr |
| index: -1 |
| } |
| { |
| name: lc_keymgr_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::On |
| inst_name: keymgr |
| top_signame: lc_ctrl_lc_keymgr_en |
| index: -1 |
| } |
| { |
| name: lc_keymgr_div |
| struct: lc_keymgr_div |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: lc_ctrl_lc_keymgr_div |
| index: -1 |
| } |
| { |
| name: rom_digest |
| struct: keymgr_data |
| package: rom_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| top_signame: rom_ctrl_keymgr_data |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: keymgr |
| default: "" |
| end_idx: -1 |
| top_signame: keymgr_tl |
| index: -1 |
| } |
| { |
| name: csrng_cmd |
| struct: csrng |
| package: csrng_pkg |
| type: req_rsp |
| act: rsp |
| width: 2 |
| inst_name: csrng |
| default: "" |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: csrng_csrng_cmd |
| index: -1 |
| } |
| { |
| name: entropy_src_hw_if |
| struct: entropy_src_hw_if |
| package: entropy_src_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: csrng |
| default: "" |
| end_idx: -1 |
| top_signame: csrng_entropy_src_hw_if |
| index: -1 |
| } |
| { |
| name: cs_aes_halt |
| struct: cs_aes_halt |
| package: entropy_src_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: csrng |
| default: "" |
| end_idx: -1 |
| top_signame: csrng_cs_aes_halt |
| index: -1 |
| } |
| { |
| name: otp_en_csrng_sw_app_read |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: csrng |
| default: "" |
| top_signame: csrng_otp_en_csrng_sw_app_read |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: csrng |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: csrng |
| default: "" |
| end_idx: -1 |
| top_signame: csrng_tl |
| index: -1 |
| } |
| { |
| name: entropy_src_hw_if |
| struct: entropy_src_hw_if |
| package: entropy_src_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| top_signame: csrng_entropy_src_hw_if |
| index: -1 |
| } |
| { |
| name: cs_aes_halt |
| struct: cs_aes_halt |
| package: entropy_src_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| top_signame: csrng_cs_aes_halt |
| index: -1 |
| } |
| { |
| name: entropy_src_rng |
| struct: entropy_src_rng |
| package: entropy_src_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| external: true |
| top_signame: es_rng |
| index: -1 |
| } |
| { |
| name: entropy_src_xht |
| struct: entropy_src_xht |
| package: entropy_src_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: entropy_src |
| index: -1 |
| } |
| { |
| name: otp_en_entropy_src_fw_read |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| top_signame: entropy_src_otp_en_entropy_src_fw_read |
| index: -1 |
| } |
| { |
| name: otp_en_entropy_src_fw_over |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| top_signame: entropy_src_otp_en_entropy_src_fw_over |
| index: -1 |
| } |
| { |
| name: rng_fips |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| package: "" |
| external: true |
| top_signame: es_rng_fips |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: entropy_src |
| default: "" |
| end_idx: -1 |
| top_signame: entropy_src_tl |
| index: -1 |
| } |
| { |
| name: csrng_cmd |
| desc: EDN supports a signal CSRNG application interface. |
| struct: csrng |
| package: csrng_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: edn0 |
| default: "" |
| top_signame: csrng_csrng_cmd |
| index: 0 |
| } |
| { |
| name: edn |
| desc: |
| ''' |
| The collection of peripheral ports supported by edn. The width (4) |
| indicates the number of peripheral ports on a single instance. |
| Due to limitations in the parametrization of top-level interconnects |
| this value is not currently parameterizable. However, the number |
| of peripheral ports may change in a future revision. |
| ''' |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: rsp |
| width: 7 |
| default: "'0" |
| inst_name: edn0 |
| end_idx: -1 |
| top_type: one-to-N |
| top_signame: edn0_edn |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: edn0 |
| default: "" |
| end_idx: -1 |
| top_signame: edn0_tl |
| index: -1 |
| } |
| { |
| name: csrng_cmd |
| desc: EDN supports a signal CSRNG application interface. |
| struct: csrng |
| package: csrng_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: edn1 |
| default: "" |
| top_signame: csrng_csrng_cmd |
| index: 1 |
| } |
| { |
| name: edn |
| desc: |
| ''' |
| The collection of peripheral ports supported by edn. The width (4) |
| indicates the number of peripheral ports on a single instance. |
| Due to limitations in the parametrization of top-level interconnects |
| this value is not currently parameterizable. However, the number |
| of peripheral ports may change in a future revision. |
| ''' |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: rsp |
| width: 7 |
| default: "'0" |
| inst_name: edn1 |
| end_idx: 1 |
| top_type: partial-one-to-N |
| top_signame: edn1_edn |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: edn1 |
| default: "" |
| end_idx: -1 |
| top_signame: edn1_tl |
| index: -1 |
| } |
| { |
| name: sram_otp_key |
| struct: sram_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_main |
| top_signame: otp_ctrl_sram_otp_key |
| index: 0 |
| } |
| { |
| name: sram_scr |
| struct: sram_scr |
| package: sram_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_main |
| end_idx: -1 |
| top_signame: sram_ctrl_main_sram_scr |
| index: -1 |
| } |
| { |
| name: sram_scr_init |
| struct: sram_scr_init |
| package: sram_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_main |
| end_idx: -1 |
| top_signame: sram_ctrl_main_sram_scr_init |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: sram_ctrl_main |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: lc_hw_debug_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: sram_ctrl_main |
| top_signame: lc_ctrl_lc_hw_debug_en |
| index: -1 |
| } |
| { |
| name: otp_en_sram_ifetch |
| struct: otp_en |
| package: otp_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: "'0" |
| inst_name: sram_ctrl_main |
| top_signame: sram_ctrl_main_otp_en_sram_ifetch |
| index: -1 |
| } |
| { |
| name: en_ifetch |
| struct: tl_instr_en |
| package: tlul_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: sram_ctrl_main |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: sram_ctrl_main_en_ifetch |
| index: -1 |
| } |
| { |
| name: intg_error |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: sram_ctrl_main |
| default: "" |
| package: "" |
| top_signame: ram_main_intg_error |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: sram_ctrl_main |
| default: "" |
| end_idx: -1 |
| top_signame: sram_ctrl_main_tl |
| index: -1 |
| } |
| { |
| name: otbn_otp_key |
| struct: otbn_otp_key |
| package: otp_ctrl_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| default: "'0" |
| inst_name: otbn |
| top_signame: otp_ctrl_otbn_otp_key |
| index: -1 |
| } |
| { |
| name: edn_rnd |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: otbn |
| default: "" |
| top_signame: edn1_edn |
| index: 0 |
| } |
| { |
| name: edn_urnd |
| struct: edn |
| package: edn_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: otbn |
| default: "" |
| top_signame: edn0_edn |
| index: 6 |
| } |
| { |
| name: idle |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: otbn |
| default: "" |
| package: "" |
| top_signame: clkmgr_aon_idle |
| index: 3 |
| } |
| { |
| name: ram_cfg |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: otbn |
| default: "" |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| } |
| { |
| name: lc_escalate_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| default: lc_ctrl_pkg::Off |
| inst_name: otbn |
| top_signame: lc_ctrl_lc_escalate_en |
| index: -1 |
| } |
| { |
| name: tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: otbn |
| default: "" |
| end_idx: -1 |
| top_signame: otbn_tl |
| index: -1 |
| } |
| { |
| name: rom_cfg |
| struct: rom_cfg |
| package: prim_rom_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| top_signame: ast_rom_cfg |
| index: -1 |
| } |
| { |
| name: pwrmgr_data |
| struct: pwrmgr_data |
| package: rom_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rom_ctrl_pwrmgr_data |
| index: -1 |
| } |
| { |
| name: keymgr_data |
| struct: keymgr_data |
| package: rom_ctrl_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rom_ctrl_keymgr_data |
| index: -1 |
| } |
| { |
| name: kmac_data |
| struct: app |
| package: kmac_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| top_signame: kmac_app |
| index: 2 |
| } |
| { |
| name: regs_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: rom_ctrl_regs_tl |
| index: -1 |
| } |
| { |
| name: rom_tl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rom_ctrl |
| default: "" |
| end_idx: -1 |
| top_signame: rom_ctrl_rom_tl |
| index: -1 |
| } |
| { |
| name: rst_cpu_n |
| struct: logic |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_core_ibex_rst_cpu_n |
| index: -1 |
| } |
| { |
| name: ram_cfg |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| } |
| { |
| name: hart_id |
| struct: logic |
| type: uni |
| act: rcv |
| width: 32 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_core_ibex_hart_id |
| index: -1 |
| } |
| { |
| name: boot_addr |
| struct: logic |
| type: uni |
| act: rcv |
| width: 32 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_core_ibex_boot_addr |
| index: -1 |
| } |
| { |
| name: irq_software |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_plic_msip |
| index: -1 |
| } |
| { |
| name: irq_timer |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_core_ibex_irq_timer |
| index: -1 |
| } |
| { |
| name: irq_external |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_plic_irq |
| index: -1 |
| } |
| { |
| name: esc_tx |
| struct: esc_tx |
| package: prim_esc_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: alert_handler_esc_tx |
| index: 0 |
| } |
| { |
| name: esc_rx |
| struct: esc_rx |
| package: prim_esc_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: alert_handler_esc_rx |
| index: 0 |
| } |
| { |
| name: debug_req |
| struct: logic |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| package: "" |
| top_signame: rv_dm_debug_req |
| index: -1 |
| } |
| { |
| name: crash_dump |
| struct: crash_dump |
| package: ibex_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_core_ibex_crash_dump |
| index: -1 |
| } |
| { |
| name: lc_cpu_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: lc_ctrl_lc_cpu_en |
| index: -1 |
| } |
| { |
| name: pwrmgr_cpu_en |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: pwrmgr_aon_fetch_en |
| index: -1 |
| } |
| { |
| name: pwrmgr |
| struct: pwr_cpu |
| package: pwrmgr_pkg |
| type: uni |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: rv_core_ibex_pwrmgr |
| index: -1 |
| } |
| { |
| name: corei_tl_h |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: main_tl_rv_core_ibex__corei |
| index: -1 |
| } |
| { |
| name: cored_tl_h |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| top_signame: main_tl_rv_core_ibex__cored |
| index: -1 |
| } |
| { |
| name: cfg_tl_d |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: rv_core_ibex |
| default: "" |
| end_idx: -1 |
| top_signame: rv_core_ibex_cfg_tl_d |
| index: -1 |
| } |
| { |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| name: tl |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_signame: ram_main_tl |
| index: -1 |
| } |
| { |
| struct: sram_scr |
| package: sram_ctrl_pkg |
| type: req_rsp |
| name: sram_scr |
| act: rsp |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_main_sram_scr |
| index: -1 |
| } |
| { |
| struct: sram_scr_init |
| package: sram_ctrl_pkg |
| type: req_rsp |
| name: sram_scr_init |
| act: rsp |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_main_sram_scr_init |
| index: -1 |
| } |
| { |
| struct: tl_instr_en |
| package: tlul_pkg |
| type: uni |
| name: en_ifetch |
| act: rcv |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_main_en_ifetch |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| name: intg_error |
| act: req |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ram_main_intg_error |
| index: -1 |
| } |
| { |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| name: cfg |
| act: rcv |
| inst_name: ram_main |
| width: 1 |
| default: "" |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| } |
| { |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| name: tl |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_signame: ram_ret_aon_tl |
| index: -1 |
| } |
| { |
| struct: sram_scr |
| package: sram_ctrl_pkg |
| type: req_rsp |
| name: sram_scr |
| act: rsp |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_ret_aon_sram_scr |
| index: -1 |
| } |
| { |
| struct: sram_scr_init |
| package: sram_ctrl_pkg |
| type: req_rsp |
| name: sram_scr_init |
| act: rsp |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_ret_aon_sram_scr_init |
| index: -1 |
| } |
| { |
| struct: tl_instr_en |
| package: tlul_pkg |
| type: uni |
| name: en_ifetch |
| act: rcv |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| top_signame: sram_ctrl_ret_aon_en_ifetch |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| name: intg_error |
| act: req |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ram_ret_aon_intg_error |
| index: -1 |
| } |
| { |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| name: cfg |
| act: rcv |
| inst_name: ram_ret_aon |
| width: 1 |
| default: "" |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| } |
| { |
| struct: flash |
| type: req_rsp |
| name: flash_ctrl |
| act: rsp |
| inst_name: eflash |
| width: 1 |
| default: "" |
| package: flash_ctrl_pkg |
| top_signame: flash_ctrl_flash |
| index: -1 |
| } |
| { |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| name: tl |
| inst_name: eflash |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_signame: eflash_tl |
| index: -1 |
| } |
| { |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| name: lc_nvm_debug_en |
| inst_name: eflash |
| width: 1 |
| default: "" |
| top_signame: lc_ctrl_lc_nvm_debug_en |
| index: -1 |
| } |
| { |
| struct: lc_tx |
| package: lc_ctrl_pkg |
| type: uni |
| act: rcv |
| name: flash_bist_enable |
| inst_name: eflash |
| width: 1 |
| default: "" |
| external: true |
| top_signame: flash_bist_enable |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| act: rcv |
| name: flash_power_down_h |
| inst_name: eflash |
| width: 1 |
| default: "" |
| external: true |
| top_signame: flash_power_down_h |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| act: rcv |
| name: flash_power_ready_h |
| inst_name: eflash |
| width: 1 |
| default: "" |
| external: true |
| top_signame: flash_power_ready_h |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| width: "4" |
| type: uni |
| act: rcv |
| name: flash_test_mode_a |
| inst_name: eflash |
| index: -1 |
| } |
| { |
| struct: logic |
| package: "" |
| type: uni |
| act: rcv |
| name: flash_test_voltage_h |
| inst_name: eflash |
| index: -1 |
| } |
| { |
| struct: ast_dif |
| package: ast_pkg |
| type: uni |
| act: req |
| name: flash_alert |
| inst_name: eflash |
| width: 1 |
| default: "" |
| external: true |
| top_signame: flash_alert |
| index: -1 |
| } |
| { |
| name: tl_rv_core_ibex__corei |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: main |
| default: "" |
| end_idx: -1 |
| top_signame: main_tl_rv_core_ibex__corei |
| index: -1 |
| } |
| { |
| name: tl_rv_core_ibex__cored |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: main |
| default: "" |
| end_idx: -1 |
| top_signame: main_tl_rv_core_ibex__cored |
| index: -1 |
| } |
| { |
| name: tl_rv_dm__sba |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: main |
| default: "" |
| end_idx: -1 |
| top_signame: main_tl_rv_dm__sba |
| index: -1 |
| } |
| { |
| name: tl_rv_dm__regs |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rv_dm_regs_tl_d |
| index: -1 |
| } |
| { |
| name: tl_rv_dm__rom |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rv_dm_rom_tl_d |
| index: -1 |
| } |
| { |
| name: tl_rom_ctrl__rom |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rom_ctrl_rom_tl |
| index: -1 |
| } |
| { |
| name: tl_rom_ctrl__regs |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rom_ctrl_regs_tl |
| index: -1 |
| } |
| { |
| name: tl_ram_main |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: ram_main_tl |
| index: -1 |
| } |
| { |
| name: tl_eflash |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: eflash_tl |
| index: -1 |
| } |
| { |
| name: tl_peri |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| end_idx: -1 |
| top_signame: main_tl_peri |
| index: -1 |
| } |
| { |
| name: tl_flash_ctrl__core |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: flash_ctrl_core_tl |
| index: -1 |
| } |
| { |
| name: tl_flash_ctrl__prim |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: flash_ctrl_prim_tl |
| index: -1 |
| } |
| { |
| name: tl_hmac |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: hmac_tl |
| index: -1 |
| } |
| { |
| name: tl_kmac |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: kmac_tl |
| index: -1 |
| } |
| { |
| name: tl_aes |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: aes_tl |
| index: -1 |
| } |
| { |
| name: tl_entropy_src |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: entropy_src_tl |
| index: -1 |
| } |
| { |
| name: tl_csrng |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: csrng_tl |
| index: -1 |
| } |
| { |
| name: tl_edn0 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: edn0_tl |
| index: -1 |
| } |
| { |
| name: tl_edn1 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: edn1_tl |
| index: -1 |
| } |
| { |
| name: tl_rv_plic |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rv_plic_tl |
| index: -1 |
| } |
| { |
| name: tl_otbn |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: otbn_tl |
| index: -1 |
| } |
| { |
| name: tl_keymgr |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: keymgr_tl |
| index: -1 |
| } |
| { |
| name: tl_rv_core_ibex__cfg |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: rv_core_ibex_cfg_tl_d |
| index: -1 |
| } |
| { |
| name: tl_sram_ctrl_main |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: main |
| default: "" |
| top_signame: sram_ctrl_main_tl |
| index: -1 |
| } |
| { |
| name: tl_main |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: rsp |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: main_tl_peri |
| index: -1 |
| } |
| { |
| name: tl_uart0 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: uart0_tl |
| index: -1 |
| } |
| { |
| name: tl_uart1 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: uart1_tl |
| index: -1 |
| } |
| { |
| name: tl_uart2 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: uart2_tl |
| index: -1 |
| } |
| { |
| name: tl_uart3 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: uart3_tl |
| index: -1 |
| } |
| { |
| name: tl_i2c0 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: i2c0_tl |
| index: -1 |
| } |
| { |
| name: tl_i2c1 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: i2c1_tl |
| index: -1 |
| } |
| { |
| name: tl_i2c2 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: i2c2_tl |
| index: -1 |
| } |
| { |
| name: tl_pattgen |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: pattgen_tl |
| index: -1 |
| } |
| { |
| name: tl_pwm_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: pwm_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_gpio |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: gpio_tl |
| index: -1 |
| } |
| { |
| name: tl_spi_device |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: spi_device_tl |
| index: -1 |
| } |
| { |
| name: tl_spi_host0 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: spi_host0_tl |
| index: -1 |
| } |
| { |
| name: tl_spi_host1 |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: spi_host1_tl |
| index: -1 |
| } |
| { |
| name: tl_rv_timer |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: rv_timer_tl |
| index: -1 |
| } |
| { |
| name: tl_usbdev |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: usbdev_tl |
| index: -1 |
| } |
| { |
| name: tl_pwrmgr_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: pwrmgr_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_rstmgr_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: rstmgr_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_clkmgr_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: clkmgr_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_pinmux_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: pinmux_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_ram_ret_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: ram_ret_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_otp_ctrl__core |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: otp_ctrl_core_tl |
| index: -1 |
| } |
| { |
| name: tl_otp_ctrl__prim |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: otp_ctrl_prim_tl |
| index: -1 |
| } |
| { |
| name: tl_lc_ctrl |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: lc_ctrl_tl |
| index: -1 |
| } |
| { |
| name: tl_sensor_ctrl_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: sensor_ctrl_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_alert_handler |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: alert_handler_tl |
| index: -1 |
| } |
| { |
| name: tl_sram_ctrl_ret_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: sram_ctrl_ret_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_aon_timer_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: aon_timer_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_sysrst_ctrl_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: sysrst_ctrl_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_adc_ctrl_aon |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| top_signame: adc_ctrl_aon_tl |
| index: -1 |
| } |
| { |
| name: tl_ast |
| struct: tl |
| package: tlul_pkg |
| type: req_rsp |
| act: req |
| width: 1 |
| inst_name: peri |
| default: "" |
| external: true |
| top_signame: ast_tl |
| index: -1 |
| } |
| { |
| struct: edn |
| type: req_rsp |
| name: edn |
| act: rsp |
| package: edn_pkg |
| inst_name: ast |
| width: 1 |
| default: "" |
| top_signame: edn0_edn |
| index: 2 |
| external: true |
| } |
| { |
| struct: lc_tx |
| type: uni |
| name: lc_dft_en |
| act: req |
| package: lc_ctrl_pkg |
| inst_name: ast |
| width: 1 |
| default: "" |
| top_signame: lc_ctrl_lc_dft_en |
| index: -1 |
| external: true |
| } |
| { |
| struct: ram_1p_cfg |
| package: prim_ram_1p_pkg |
| type: uni |
| name: ram_1p_cfg |
| act: rcv |
| inst_name: ast |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ast_ram_1p_cfg |
| index: -1 |
| external: true |
| } |
| { |
| struct: ram_2p_cfg |
| package: prim_ram_2p_pkg |
| type: uni |
| name: ram_2p_cfg |
| act: rcv |
| inst_name: ast |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ast_ram_2p_cfg |
| index: -1 |
| external: true |
| } |
| { |
| struct: rom_cfg |
| package: prim_rom_pkg |
| type: uni |
| name: rom_cfg |
| act: rcv |
| inst_name: ast |
| width: 1 |
| default: "" |
| end_idx: -1 |
| top_type: broadcast |
| top_signame: ast_rom_cfg |
| index: -1 |
| external: true |
| } |
| ] |
| external: |
| [ |
| { |
| package: ast_pkg |
| struct: adc_ast_req |
| signame: adc_req_o |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: adc_req |
| } |
| { |
| package: ast_pkg |
| struct: adc_ast_rsp |
| signame: adc_rsp_i |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: adc_rsp |
| } |
| { |
| package: edn_pkg |
| struct: edn_req |
| signame: ast_edn_req_i |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: in |
| conn_type: true |
| index: 2 |
| netname: edn0_edn_req |
| } |
| { |
| package: edn_pkg |
| struct: edn_rsp |
| signame: ast_edn_rsp_o |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: out |
| conn_type: true |
| index: 2 |
| netname: edn0_edn_rsp |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: ast_lc_dft_en_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: true |
| index: -1 |
| netname: lc_ctrl_lc_dft_en |
| } |
| { |
| package: prim_ram_1p_pkg |
| struct: ram_1p_cfg |
| signame: ram_1p_cfg_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: true |
| index: -1 |
| netname: ast_ram_1p_cfg |
| } |
| { |
| package: prim_ram_2p_pkg |
| struct: ram_2p_cfg |
| signame: ram_2p_cfg_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: true |
| index: -1 |
| netname: ast_ram_2p_cfg |
| } |
| { |
| package: prim_rom_pkg |
| struct: rom_cfg |
| signame: rom_cfg_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: true |
| index: -1 |
| netname: ast_rom_cfg |
| } |
| { |
| package: "" |
| struct: logic |
| signame: clk_main_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: clk_main |
| } |
| { |
| package: "" |
| struct: logic |
| signame: clk_io_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: clk_io |
| } |
| { |
| package: "" |
| struct: logic |
| signame: clk_usb_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: clk_usb |
| } |
| { |
| package: "" |
| struct: logic |
| signame: clk_aon_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: clk_aon |
| } |
| { |
| package: "" |
| struct: logic |
| signame: clk_main_jitter_en_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: clk_main_jitter_en |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: ast_clk_byp_req_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: ast_clk_byp_req |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: ast_clk_byp_ack_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: ast_clk_byp_ack |
| } |
| { |
| package: ast_pkg |
| struct: ast_dif |
| signame: flash_alert_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: flash_alert |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: flash_bist_enable_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: flash_bist_enable |
| } |
| { |
| package: "" |
| struct: logic |
| signame: flash_power_down_h_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: flash_power_down_h |
| } |
| { |
| package: "" |
| struct: logic |
| signame: flash_power_ready_h_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: flash_power_ready_h |
| } |
| { |
| package: entropy_src_pkg |
| struct: entropy_src_rng_req |
| signame: es_rng_req_o |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: es_rng_req |
| } |
| { |
| package: entropy_src_pkg |
| struct: entropy_src_rng_rsp |
| signame: es_rng_rsp_i |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: es_rng_rsp |
| } |
| { |
| package: "" |
| struct: logic |
| signame: es_rng_fips_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: es_rng_fips |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: ast_tl_req_o |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: ast_tl_h2d |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: ast_tl_rsp_i |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: ast_tl_d2h |
| } |
| { |
| package: pinmux_pkg |
| struct: dft_strap_test_req |
| signame: dft_strap_test_o |
| width: 1 |
| type: uni |
| default: "'0" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: dft_strap_test |
| } |
| { |
| package: "" |
| struct: logic |
| signame: dft_hold_tap_sel_i |
| width: 1 |
| type: uni |
| default: "'0" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: dft_hold_tap_sel |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_ast_req |
| signame: pwrmgr_ast_req_o |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: pwrmgr_ast_req |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_ast_rsp |
| signame: pwrmgr_ast_rsp_i |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: pwrmgr_ast_rsp |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_ast_req |
| signame: otp_ctrl_otp_ast_pwr_seq_o |
| width: 1 |
| type: uni |
| default: "'0" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: otp_ctrl_otp_ast_pwr_seq |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_ast_rsp |
| signame: otp_ctrl_otp_ast_pwr_seq_h_i |
| width: 1 |
| type: uni |
| default: "'0" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: otp_ctrl_otp_ast_pwr_seq_h |
| } |
| { |
| package: ast_pkg |
| struct: ast_dif |
| signame: otp_alert_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: otp_alert |
| } |
| { |
| package: ast_pkg |
| struct: ast_alert_req |
| signame: sensor_ctrl_ast_alert_req_i |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: sensor_ctrl_ast_alert_req |
| } |
| { |
| package: ast_pkg |
| struct: ast_alert_rsp |
| signame: sensor_ctrl_ast_alert_rsp_o |
| width: 1 |
| type: req_rsp |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: sensor_ctrl_ast_alert_rsp |
| } |
| { |
| package: ast_pkg |
| struct: ast_status |
| signame: sensor_ctrl_ast_status_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: sensor_ctrl_ast_status |
| } |
| { |
| package: "" |
| struct: logic |
| signame: ast2pinmux_i |
| width: 9 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: ast2pinmux |
| } |
| { |
| package: "" |
| struct: logic |
| signame: ast_init_done_i |
| width: 1 |
| type: uni |
| default: "" |
| direction: in |
| conn_type: false |
| index: -1 |
| netname: ast_init_done |
| } |
| { |
| package: "" |
| struct: logic |
| signame: usbdev_usb_ref_val_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: usbdev_usb_ref_val |
| } |
| { |
| package: "" |
| struct: logic |
| signame: usbdev_usb_ref_pulse_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: usbdev_usb_ref_pulse |
| } |
| { |
| package: clkmgr_pkg |
| struct: clkmgr_ast_out |
| signame: clks_ast_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: clks_ast |
| } |
| { |
| package: rstmgr_pkg |
| struct: rstmgr_ast_out |
| signame: rsts_ast_o |
| width: 1 |
| type: uni |
| default: "" |
| direction: out |
| conn_type: false |
| index: -1 |
| netname: rsts_ast |
| } |
| ] |
| definitions: |
| [ |
| { |
| package: prim_ram_1p_pkg |
| struct: ram_1p_cfg |
| signame: ast_ram_1p_cfg |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: prim_ram_1p_pkg::RAM_1P_CFG_DEFAULT |
| } |
| { |
| package: prim_ram_2p_pkg |
| struct: ram_2p_cfg |
| signame: ast_ram_2p_cfg |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: prim_ram_2p_pkg::RAM_2P_CFG_DEFAULT |
| } |
| { |
| package: prim_rom_pkg |
| struct: rom_cfg |
| signame: ast_rom_cfg |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: prim_rom_pkg::ROM_CFG_DEFAULT |
| } |
| { |
| package: alert_pkg |
| struct: alert_crashdump |
| signame: alert_handler_crashdump |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: alert_pkg::ALERT_CRASHDUMP_DEFAULT |
| } |
| { |
| package: prim_esc_pkg |
| struct: esc_rx |
| signame: alert_handler_esc_rx |
| width: 4 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: prim_esc_pkg::ESC_RX_DEFAULT |
| } |
| { |
| package: prim_esc_pkg |
| struct: esc_tx |
| signame: alert_handler_esc_tx |
| width: 4 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: prim_esc_pkg::ESC_TX_DEFAULT |
| } |
| { |
| package: csrng_pkg |
| struct: csrng_req |
| signame: csrng_csrng_cmd_req |
| width: 2 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: csrng_pkg::CSRNG_REQ_DEFAULT |
| } |
| { |
| package: csrng_pkg |
| struct: csrng_rsp |
| signame: csrng_csrng_cmd_rsp |
| width: 2 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: entropy_src_pkg |
| struct: entropy_src_hw_if_req |
| signame: csrng_entropy_src_hw_if_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: entropy_src_pkg |
| struct: entropy_src_hw_if_rsp |
| signame: csrng_entropy_src_hw_if_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT |
| } |
| { |
| package: entropy_src_pkg |
| struct: cs_aes_halt_req |
| signame: csrng_cs_aes_halt_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: entropy_src_pkg::CS_AES_HALT_REQ_DEFAULT |
| } |
| { |
| package: entropy_src_pkg |
| struct: cs_aes_halt_rsp |
| signame: csrng_cs_aes_halt_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: flash_ctrl_pkg |
| struct: flash_req |
| signame: flash_ctrl_flash_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: flash_ctrl_pkg |
| struct: flash_rsp |
| signame: flash_ctrl_flash_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: flash_ctrl_pkg::FLASH_RSP_DEFAULT |
| } |
| { |
| package: flash_ctrl_pkg |
| struct: keymgr_flash |
| signame: flash_ctrl_keymgr |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: flash_ctrl_pkg::KEYMGR_FLASH_DEFAULT |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: flash_otp_key_req |
| signame: flash_ctrl_otp_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: flash_otp_key_rsp |
| signame: flash_ctrl_otp_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: flash_ctrl_rma_req |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: lc_ctrl_pkg::LC_TX_DEFAULT |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: flash_ctrl_rma_ack |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::LC_TX_DEFAULT |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_flash_rma_seed |
| signame: flash_ctrl_rma_seed |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: lc_ctrl_pkg::LC_FLASH_RMA_SEED_DEFAULT |
| } |
| { |
| package: sram_ctrl_pkg |
| struct: sram_scr_req |
| signame: sram_ctrl_main_sram_scr_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: sram_ctrl_pkg |
| struct: sram_scr_rsp |
| signame: sram_ctrl_main_sram_scr_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: "'0" |
| } |
| { |
| package: sram_ctrl_pkg |
| struct: sram_scr_init_req |
| signame: sram_ctrl_main_sram_scr_init_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: sram_ctrl_pkg |
| struct: sram_scr_init_rsp |
| signame: sram_ctrl_main_sram_scr_init_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: "'0" |
| } |
| { |
| package: sram_ctrl_pkg |
| struct: sram_scr_req |
| signame: sram_ctrl_ret_aon_sram_scr_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: sram_ctrl_pkg |
| struct: sram_scr_rsp |
| signame: sram_ctrl_ret_aon_sram_scr_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: "'0" |
| } |
| { |
| package: sram_ctrl_pkg |
| struct: sram_scr_init_req |
| signame: sram_ctrl_ret_aon_sram_scr_init_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: sram_ctrl_pkg |
| struct: sram_scr_init_rsp |
| signame: sram_ctrl_ret_aon_sram_scr_init_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: "'0" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_instr_en |
| signame: sram_ctrl_main_en_ifetch |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: tlul_pkg::TL_INSTR_EN_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_instr_en |
| signame: sram_ctrl_ret_aon_en_ifetch |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: tlul_pkg::TL_INSTR_EN_DEFAULT |
| } |
| { |
| package: "" |
| struct: logic |
| signame: ram_main_intg_error |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: ram_ret_aon_intg_error |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: sram_otp_key_req |
| signame: otp_ctrl_sram_otp_key_req |
| width: 2 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: "'0" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: sram_otp_key_rsp |
| signame: otp_ctrl_sram_otp_key_rsp |
| width: 2 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_flash |
| signame: pwrmgr_aon_pwr_flash |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: pwrmgr_pkg::PWR_FLASH_DEFAULT |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_rst_req |
| signame: pwrmgr_aon_pwr_rst_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_rst_rsp |
| signame: pwrmgr_aon_pwr_rst_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: pwrmgr_pkg::PWR_RST_RSP_DEFAULT |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_clk_req |
| signame: pwrmgr_aon_pwr_clk_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_clk_rsp |
| signame: pwrmgr_aon_pwr_clk_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: pwrmgr_pkg::PWR_CLK_RSP_DEFAULT |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_otp_req |
| signame: pwrmgr_aon_pwr_otp_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_otp_rsp |
| signame: pwrmgr_aon_pwr_otp_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: pwrmgr_pkg::PWR_OTP_RSP_DEFAULT |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_lc_req |
| signame: pwrmgr_aon_pwr_lc_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_lc_rsp |
| signame: pwrmgr_aon_pwr_lc_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: pwrmgr_pkg::PWR_LC_RSP_DEFAULT |
| } |
| { |
| package: "" |
| struct: logic |
| signame: pwrmgr_aon_strap |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: pwrmgr_aon_low_power |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: pwrmgr_aon_fetch_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::LC_TX_DEFAULT |
| } |
| { |
| package: rom_ctrl_pkg |
| struct: pwrmgr_data |
| signame: rom_ctrl_pwrmgr_data |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: rom_ctrl_pkg::PWRMGR_DATA_DEFAULT |
| } |
| { |
| package: rom_ctrl_pkg |
| struct: keymgr_data |
| signame: rom_ctrl_keymgr_data |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: rom_ctrl_pkg::KEYMGR_DATA_DEFAULT |
| } |
| { |
| package: "" |
| struct: logic |
| signame: usbdev_usb_out_of_rst |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: usbdev_usb_aon_wake_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: usbdev_usb_aon_wake_ack |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: usbdev_usb_suspend |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: usbdev_pkg |
| struct: awk_state |
| signame: pinmux_aon_usb_state_debug |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: usbdev_pkg::AWK_STATE_DEFAULT |
| } |
| { |
| package: edn_pkg |
| struct: edn_req |
| signame: edn0_edn_req |
| width: 7 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: "'0" |
| } |
| { |
| package: edn_pkg |
| struct: edn_rsp |
| signame: edn0_edn_rsp |
| width: 7 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: edn_pkg |
| struct: edn_req |
| signame: edn1_edn_req |
| width: 7 |
| type: req_rsp |
| end_idx: 1 |
| act: rsp |
| suffix: req |
| default: "'0" |
| } |
| { |
| package: edn_pkg |
| struct: edn_rsp |
| signame: edn1_edn_rsp |
| width: 7 |
| type: req_rsp |
| end_idx: 1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otbn_otp_key_req |
| signame: otp_ctrl_otbn_otp_key_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: "'0" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otbn_otp_key_rsp |
| signame: otp_ctrl_otbn_otp_key_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_keymgr_key |
| signame: otp_ctrl_otp_keymgr_key |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: keymgr_pkg |
| struct: hw_key_req |
| signame: keymgr_kmac_key |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: keymgr_pkg::HW_KEY_REQ_DEFAULT |
| } |
| { |
| package: kmac_pkg |
| struct: app_req |
| signame: kmac_app_req |
| width: 3 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: kmac_pkg::APP_REQ_DEFAULT |
| } |
| { |
| package: kmac_pkg |
| struct: app_rsp |
| signame: kmac_app_rsp |
| width: 3 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: clkmgr_aon_idle |
| width: 5 |
| type: uni |
| end_idx: 4 |
| act: rcv |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: jtag_pkg |
| struct: jtag_req |
| signame: pinmux_aon_lc_jtag_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: jtag_pkg |
| struct: jtag_rsp |
| signame: pinmux_aon_lc_jtag_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: jtag_pkg::JTAG_RSP_DEFAULT |
| } |
| { |
| package: jtag_pkg |
| struct: jtag_req |
| signame: pinmux_aon_rv_jtag_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: jtag_pkg |
| struct: jtag_rsp |
| signame: pinmux_aon_rv_jtag_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: jtag_pkg::JTAG_RSP_DEFAULT |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_lc_data |
| signame: otp_ctrl_otp_lc_data |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: lc_otp_program_req |
| signame: lc_ctrl_lc_otp_program_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: lc_otp_program_rsp |
| signame: lc_ctrl_lc_otp_program_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: "'0" |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_keymgr_div |
| signame: lc_ctrl_lc_keymgr_div |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_dft_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_nvm_debug_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_hw_debug_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_cpu_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_keymgr_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_escalate_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_check_byp_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_clk_byp_req |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_clk_byp_ack |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_creator_seed_sw_rw_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_owner_seed_sw_rw_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_iso_part_sw_rd_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_iso_part_sw_wr_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: lc_ctrl_pkg |
| struct: lc_tx |
| signame: lc_ctrl_lc_seed_hw_rd_en |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: lc_ctrl_pkg::Off |
| } |
| { |
| package: "" |
| struct: logic |
| signame: rv_plic_msip |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: rv_plic_irq |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic [rv_dm_reg_pkg::NrHarts-1:0] |
| signame: rv_dm_debug_req |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: rv_core_ibex_rst_cpu_n |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: ibex_pkg |
| struct: crash_dump |
| signame: rv_core_ibex_crash_dump |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: ibex_pkg::CRASH_DUMP_DEFAULT |
| } |
| { |
| package: pwrmgr_pkg |
| struct: pwr_cpu |
| signame: rv_core_ibex_pwrmgr |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: pwrmgr_pkg::PWR_CPU_DEFAULT |
| } |
| { |
| package: spi_device_pkg |
| struct: passthrough_req |
| signame: spi_device_passthrough_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: spi_device_pkg |
| struct: passthrough_rsp |
| signame: spi_device_passthrough_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: spi_device_pkg::PASSTHROUGH_RSP_DEFAULT |
| } |
| { |
| package: "" |
| struct: logic |
| signame: rv_dm_ndmreset_req |
| width: 1 |
| type: uni |
| end_idx: -1 |
| act: req |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: pwrmgr_aon_wakeups |
| width: 5 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: pwrmgr_aon_rstreqs |
| width: 2 |
| type: uni |
| end_idx: -1 |
| act: rcv |
| suffix: "" |
| default: "'0" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: main_tl_rv_core_ibex__corei_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: main_tl_rv_core_ibex__corei_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: main_tl_rv_core_ibex__cored_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: main_tl_rv_core_ibex__cored_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: main_tl_rv_dm__sba_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: main_tl_rv_dm__sba_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: rv_dm_regs_tl_d_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: rv_dm_regs_tl_d_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: rv_dm_rom_tl_d_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: rv_dm_rom_tl_d_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: rom_ctrl_rom_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: rom_ctrl_rom_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: rom_ctrl_regs_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: rom_ctrl_regs_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: ram_main_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: ram_main_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: eflash_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: eflash_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: main_tl_peri_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: req |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: main_tl_peri_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: req |
| suffix: rsp |
| default: tlul_pkg::TL_D2H_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: flash_ctrl_core_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: flash_ctrl_core_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: flash_ctrl_prim_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: flash_ctrl_prim_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: hmac_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: hmac_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: kmac_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: kmac_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: aes_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: aes_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: entropy_src_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: entropy_src_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: csrng_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: csrng_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: edn0_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: edn0_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: edn1_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: edn1_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: rv_plic_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: rv_plic_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: otbn_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: otbn_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: keymgr_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: keymgr_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: rv_core_ibex_cfg_tl_d_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: rv_core_ibex_cfg_tl_d_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: sram_ctrl_main_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: sram_ctrl_main_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: uart0_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: uart0_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: uart1_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: uart1_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: uart2_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: uart2_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: uart3_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: uart3_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: i2c0_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: i2c0_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: i2c1_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: i2c1_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: i2c2_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: i2c2_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: pattgen_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: pattgen_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: pwm_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: pwm_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: gpio_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: gpio_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: spi_device_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: spi_device_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: spi_host0_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: spi_host0_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: spi_host1_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: spi_host1_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: rv_timer_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: rv_timer_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: usbdev_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: usbdev_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: pwrmgr_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: pwrmgr_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: rstmgr_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: rstmgr_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: clkmgr_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: clkmgr_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: pinmux_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: pinmux_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: ram_ret_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: ram_ret_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: otp_ctrl_core_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: otp_ctrl_core_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: otp_ctrl_prim_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: otp_ctrl_prim_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: lc_ctrl_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: lc_ctrl_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: sensor_ctrl_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: sensor_ctrl_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: alert_handler_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: alert_handler_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: sram_ctrl_ret_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: sram_ctrl_ret_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: aon_timer_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: aon_timer_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: sysrst_ctrl_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: sysrst_ctrl_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: tlul_pkg |
| struct: tl_h2d |
| signame: adc_ctrl_aon_tl_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: req |
| default: tlul_pkg::TL_H2D_DEFAULT |
| } |
| { |
| package: tlul_pkg |
| struct: tl_d2h |
| signame: adc_ctrl_aon_tl_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| act: rsp |
| suffix: rsp |
| default: "" |
| } |
| { |
| package: rstmgr_pkg |
| struct: rstmgr_out |
| signame: rstmgr_aon_resets |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: clkmgr_pkg |
| struct: clkmgr_out |
| signame: clkmgr_aon_clocks |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: rv_core_ibex_irq_timer |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: rv_core_ibex_hart_id |
| width: 32 |
| type: uni |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: "" |
| struct: logic |
| signame: rv_core_ibex_boot_addr |
| width: 32 |
| type: uni |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: jtag_pkg |
| struct: jtag_req |
| signame: pinmux_aon_dft_jtag_req |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: jtag_pkg |
| struct: jtag_rsp |
| signame: pinmux_aon_dft_jtag_rsp |
| width: 1 |
| type: req_rsp |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: otp_ctrl_part_pkg |
| struct: otp_hw_cfg |
| signame: otp_ctrl_otp_hw_cfg |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "'0" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_en |
| signame: csrng_otp_en_csrng_sw_app_read |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_en |
| signame: entropy_src_otp_en_entropy_src_fw_read |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_en |
| signame: entropy_src_otp_en_entropy_src_fw_over |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_device_id |
| signame: lc_ctrl_otp_device_id |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "'0" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_device_id |
| signame: keymgr_otp_device_id |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_en |
| signame: sram_ctrl_main_otp_en_sram_ifetch |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "'0" |
| } |
| { |
| package: otp_ctrl_pkg |
| struct: otp_en |
| signame: sram_ctrl_ret_aon_otp_en_sram_ifetch |
| width: 1 |
| type: uni |
| end_idx: -1 |
| default: "'0" |
| } |
| ] |
| } |
| } |
