[fpga] add option to stub out otbn
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/otbn/data/otbn.hjson b/hw/ip/otbn/data/otbn.hjson
index ac5f7a1..9637400 100644
--- a/hw/ip/otbn/data/otbn.hjson
+++ b/hw/ip/otbn/data/otbn.hjson
@@ -14,6 +14,13 @@
{ protocol: "tlul", direction: "device" }
],
param_list: [
+ { name: "Stub",
+ type: "bit",
+ default: "0",
+ desc: "Stub out the core of Otbn logic"
+ local: "false",
+ expose: "true"
+ },
{ name: "RegFile",
type: "otbn_pkg::regfile_e",
default: "otbn_pkg::RegFileFF",
diff --git a/hw/ip/otbn/rtl/otbn.sv b/hw/ip/otbn/rtl/otbn.sv
index 7aba7fd..9bd7723 100644
--- a/hw/ip/otbn/rtl/otbn.sv
+++ b/hw/ip/otbn/rtl/otbn.sv
@@ -12,6 +12,7 @@
import otbn_pkg::*;
import otbn_reg_pkg::*;
#(
+ parameter bit Stub = 1'b0,
parameter regfile_e RegFile = RegFileFF,
parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
@@ -50,6 +51,15 @@
import prim_util_pkg::vbits;
+ logic rst_n;
+
+ // hold module in reset permanently when stubbing
+ if (Stub) begin : gen_stub_otbn
+ assign rst_n = 1'b0;
+ end else begin : gen_real_otbn
+ assign rst_n = rst_ni;
+ end
+
// The OTBN_*_SIZE parameters are auto-generated by regtool and come from the
// bus window sizes; they are given in bytes and must be powers of two.
localparam int ImemSizeByte = int'(otbn_reg_pkg::OTBN_IMEM_SIZE);
@@ -95,7 +105,7 @@
.Width(1)
) u_intr_hw_done (
.clk_i,
- .rst_ni,
+ .rst_ni (rst_n),
.event_intr_i (done),
.reg2hw_intr_enable_q_i (reg2hw.intr_enable.q),
.reg2hw_intr_test_q_i (reg2hw.intr_test.q),
@@ -155,7 +165,7 @@
.DataBitsPerMask (39)
) u_imem (
.clk_i,
- .rst_ni,
+ .rst_ni (rst_n),
.req_i (imem_req),
.write_i (imem_write),
.addr_i (imem_index),
@@ -185,7 +195,7 @@
.EnableDataIntgPt (1)
) u_tlul_adapter_sram_imem (
.clk_i,
- .rst_ni,
+ .rst_ni (rst_n ),
.tl_i (tl_win_h2d[TlWinImem] ),
.tl_o (tl_win_d2h[TlWinImem] ),
.en_ifetch_i (tlul_pkg::InstrDis ),
@@ -295,7 +305,7 @@
.DataBitsPerMask (39)
) u_dmem (
.clk_i,
- .rst_ni,
+ .rst_ni (rst_n),
.req_i (dmem_req),
.write_i (dmem_write),
.addr_i (dmem_index),
@@ -324,7 +334,7 @@
.EnableDataIntgPt (1)
) u_tlul_adapter_sram_dmem (
.clk_i,
- .rst_ni,
+ .rst_ni (rst_n ),
.tl_i (tl_win_h2d[TlWinDmem] ),
.tl_o (tl_win_d2h[TlWinDmem] ),
.en_ifetch_i (tlul_pkg::InstrDis ),
@@ -374,7 +384,7 @@
otbn_reg_top u_reg (
.clk_i,
- .rst_ni,
+ .rst_ni (rst_n),
.tl_i,
.tl_o,
.tl_win_o (tl_win_h2d),
@@ -461,7 +471,7 @@
.IsFatal(i == AlertFatal)
) u_prim_alert_sender (
.clk_i,
- .rst_ni,
+ .rst_ni ( rst_n ),
.alert_test_i ( alert_test[i] ),
.alert_req_i ( alerts[i] ),
.alert_ack_o ( ),
@@ -486,7 +496,7 @@
.OutWidth(EdnDataWidth)
) u_prim_edn_rnd_req (
.clk_i,
- .rst_ni,
+ .rst_ni ( rst_n ),
.req_i ( edn_rnd_req ),
.ack_o ( edn_rnd_ack ),
.data_o ( edn_rnd_data ),
@@ -501,7 +511,7 @@
.OutWidth(EdnDataWidth)
) u_prim_edn_urnd_req (
.clk_i,
- .rst_ni,
+ .rst_ni ( rst_n ),
.req_i ( edn_urnd_req ),
.ack_o ( edn_urnd_ack ),
.data_o ( edn_urnd_data ),
@@ -515,8 +525,8 @@
// OTBN Core =================================================================
- always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) begin
+ always_ff @(posedge clk_i or negedge rst_n) begin
+ if (!rst_n) begin
busy_q <= 1'b0;
end else begin
busy_q <= busy_d;
@@ -564,7 +574,7 @@
.DesignScope("")
) u_otbn_core_model (
.clk_i,
- .rst_ni,
+ .rst_ni (rst_n),
.start_i (start_model),
.done_o (done_model),
@@ -589,7 +599,7 @@
.RndCnstUrndChunkLfsrPerm(RndCnstUrndChunkLfsrPerm)
) u_otbn_core (
.clk_i,
- .rst_ni,
+ .rst_ni (rst_n),
.start_i (start_rtl),
.done_o (done_rtl),
@@ -631,7 +641,7 @@
.RndCnstUrndChunkLfsrPerm(RndCnstUrndChunkLfsrPerm)
) u_otbn_core (
.clk_i,
- .rst_ni,
+ .rst_ni (rst_n),
.start_i (start),
.done_o (done),
@@ -680,6 +690,7 @@
assign unused_rdata_core_integrity[i] = &{dmem_rdata_core[i*39 + 32 +: 7]};
end
+
// LFSR ======================================================================
// TODO: Potentially insert local LFSR, or use output from RNG distribution
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 15bda2e..8e186e9 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -4948,6 +4948,14 @@
param_list:
[
{
+ name: Stub
+ desc: Stub out the core of Otbn logic
+ type: bit
+ default: "0"
+ expose: "true"
+ name_top: OtbnStub
+ }
+ {
name: RegFile
desc: Selection of the register file implementation. See otbn_pkg.sv.
type: otbn_pkg::regfile_e
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
index 15682f0..251a96a 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
@@ -717,6 +717,7 @@
.SecAesSkipPRNGReseeding(1'b0),
.CsrngSBoxImpl(aes_pkg::SBoxImplLut),
.OtbnRegFile(otbn_pkg::RegFileFPGA),
+ .OtbnStub(1'b1),
.OtpCtrlMemInitFile(OtpCtrlMemInitFile),
.RomCtrlBootRomInitFile(BootRomInitFile),
.IbexRegFile(ibex_pkg::RegFileFPGA),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 003498f..51b8e47 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -23,6 +23,7 @@
parameter int KmacReuseShare = 0,
parameter aes_pkg::sbox_impl_e CsrngSBoxImpl = aes_pkg::SBoxImplCanright,
parameter bit SramCtrlMainInstrExec = 1,
+ parameter bit OtbnStub = 0,
parameter otbn_pkg::regfile_e OtbnRegFile = otbn_pkg::RegFileFF,
parameter RomCtrlBootRomInitFile = "",
parameter bit RomCtrlSkipCheck = 1,
@@ -2251,6 +2252,7 @@
otbn #(
.AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:28]),
+ .Stub(OtbnStub),
.RegFile(OtbnRegFile),
.RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed),
.RndCnstUrndChunkLfsrPerm(RndCnstOtbnUrndChunkLfsrPerm)
diff --git a/test/systemtest/config.py b/test/systemtest/config.py
index 8c53555..33fcd85 100644
--- a/test/systemtest/config.py
+++ b/test/systemtest/config.py
@@ -25,6 +25,7 @@
"name": "dif_otbn_smoketest_rtl",
"binary_name": "dif_otbn_smoketest",
"verilator_extra_args": ['+OTBN_USE_MODEL=0'],
+ "targets": ["sim_verilator"],
},
{
"name": "dif_otbn_smoketest_model",
@@ -34,14 +35,14 @@
},
# The OTBN end-to-end tests can be run in simulation, but take a long time
# there. Run them on FPGAs only for faster test results.
- {
- "name": "otbn_rsa_test",
- "targets": ["fpga_nexysvideo"],
- },
- {
- "name": "otbn_ecdsa_p256_test",
- "targets": ["fpga_nexysvideo"],
- },
+ #{
+ # "name": "otbn_rsa_test",
+ # "targets": ["fpga_nexysvideo"],
+ #},
+ #{
+ # "name": "otbn_ecdsa_p256_test",
+ # "targets": ["fpga_nexysvideo"],
+ #},
{
"name": "dif_aes_smoketest",
},
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index 5dc9f5e..f647099 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -1113,6 +1113,7 @@
.SecAesSkipPRNGReseeding(1'b0),
.CsrngSBoxImpl(aes_pkg::SBoxImplLut),
.OtbnRegFile(otbn_pkg::RegFileFPGA),
+ .OtbnStub(1'b1),
.OtpCtrlMemInitFile(OtpCtrlMemInitFile),
.RomCtrlBootRomInitFile(BootRomInitFile),
% endif
