| commit | 6357816adf481cc795647b02ecd0e14c8ca25290 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Apr 22 10:53:46 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Thu Apr 22 12:31:13 2021 +0100 |
| tree | b2cac5d4b255d4c521d0395c6ce0fff1281a0585 | |
| parent | b41d0c84b95c68240229e304e731137fc6a6dc0d [diff] |
[reggen,dv] Split some long lines in generated UVM code In order to get a proper "longlines" check in CI, it would be nice to drop the current Verible configuration from 150 characters down to 100, to match AscentLint. Since we use that for DV code as well as RTL, we there are a few other places that need tidying up. This patch avoids the long lines in the generated UVM code, such as chip_ral_pkg.sv. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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