[dv] Configure dvsim to run tests with mask ROM This commit: 1. Adds configuration options to the dvsim test running environment that can be used to select whether a chip-level test (run out of flash) is launched with the test ROM or mask ROM. 2. Renames the dvsim run mode for all chip-level tests run with the rest ROM has been from `sw_test_mode` --> `sw_test_mode_test_rom`. 3. Checks-in the Cargo.lock file for the ROM_EXT image signer tool (since it is a complete binary), in order to enable reproducible builds, which is necessary to run this tool on internet-isolated simulation infrastructure. Signed-off-by: Timothy Trippel <ttrippel@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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