[clkmgr] d2s relate fixes - Add missing mubi/lc synchronizers. - Convert jitter_en / hi_speed_sel to direct mubi outputs to ast. - Synchronize step_down_ack - Add regwen to jitter_en - Keep step_down_req in mubi form all the way through synchronizer. However keep prim_div input as single bit since it is already synchronous. Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/clkmgr/data/clkmgr.hjson.tpl b/hw/ip/clkmgr/data/clkmgr.hjson.tpl index bf29d2e..6949d7f 100644 --- a/hw/ip/clkmgr/data/clkmgr.hjson.tpl +++ b/hw/ip/clkmgr/data/clkmgr.hjson.tpl
@@ -103,11 +103,11 @@ package: "prim_mubi_pkg", }, - { struct: "logic", + { struct: "mubi4", type: "uni", name: "hi_speed_sel", act: "req", - package: "", + package: "prim_mubi_pkg", }, { struct: "lc_tx", @@ -124,11 +124,11 @@ package: "lc_ctrl_pkg", }, - { struct: "logic", + { struct: "mubi4", type: "uni", name: "jitter_en", act: "req", - package: "" + package: "prim_mubi_pkg" }, // Exported clocks @@ -232,11 +232,11 @@ }, { bits: "7:4", - name: "LOW_SPEED_SEL", + name: "HI_SPEED_SEL", mubi: true, desc: ''' - A value of kMultiBitBool4True selects low speed external clocks. - All other values selects nominal speed clocks. + A value of kMultiBitBool4True selects nominal speed external clocks. + All other values selects low speed clocks. Note this field only has an effect when the !!EXTCLK_CTRL.SEL field is set to kMultiBitBool4True. @@ -246,6 +246,22 @@ ] }, + { name: "JITTER_REGWEN", + desc: "Jitter write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, the value of !!JITTER_ENALBE can be changed. When 0, writes have no + effect. + ''' + }, + ] + }, + { name: "JITTER_ENABLE", desc: ''' Enable jittery clock
diff --git a/hw/ip/clkmgr/data/clkmgr.sv.tpl b/hw/ip/clkmgr/data/clkmgr.sv.tpl index b8effc7..bfd6561 100644 --- a/hw/ip/clkmgr/data/clkmgr.sv.tpl +++ b/hw/ip/clkmgr/data/clkmgr.sv.tpl
@@ -66,10 +66,10 @@ input mubi4_t io_clk_byp_ack_i, output mubi4_t all_clk_byp_req_o, input mubi4_t all_clk_byp_ack_i, - output logic hi_speed_sel_o, + output mubi4_t hi_speed_sel_o, // jittery enable - output logic jitter_en_o, + output mubi4_t jitter_en_o, // clock gated indications going to alert handlers output clkmgr_cg_en_t cg_en_o, @@ -84,6 +84,7 @@ import prim_mubi_pkg::MuBi4False; import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::mubi4_test_true_strict; import prim_mubi_pkg::mubi4_test_true_loose; import prim_mubi_pkg::mubi4_test_false_loose; @@ -91,7 +92,7 @@ // Divided clocks //////////////////////////////////////////////////// - logic step_down_req; + mubi4_t step_down_req; logic [${len(clocks.derived_srcs)-1}:0] step_down_acks; % for src_name in clocks.derived_srcs: @@ -99,14 +100,17 @@ % endfor % for src_name in clocks.all_derived_srcs(): - logic ${src_name}_step_down_req; - prim_flop_2sync #( - .Width(1) + mubi4_t ${src_name}_step_down_req; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(1), + .StabilityCheck(1), + .ResetValue(MuBi4False) ) u_${src_name}_step_down_req_sync ( .clk_i(clk_${src_name}_i), .rst_ni(rst_${src_name}_ni), - .d_i(step_down_req), - .q_o(${src_name}_step_down_req) + .mubi_i(step_down_req), + .mubi_o(${src_name}_step_down_req) ); % endfor @@ -129,9 +133,9 @@ ) u_no_scan_${src.name}_div ( .clk_i(clk_${src.src.name}_i), .rst_ni(rst_${src.src.name}_ni), - .step_down_req_i(${src.src.name}_step_down_req), + .step_down_req_i(mubi4_test_true_strict(${src.src.name}_step_down_req)), .step_down_ack_o(step_down_acks[${loop.index}]), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(${src.name}_div_scanmode[0])), + .test_en_i(mubi4_test_true_strict(${src.name}_div_scanmode[0])), .clk_o(clk_${src.name}_i) ); % endfor @@ -209,8 +213,6 @@ // Clock bypass request //////////////////////////////////////////////////// - mubi4_t low_speed_sel; - assign low_speed_sel = mubi4_t'(reg2hw.extclk_ctrl.low_speed_sel.q); clkmgr_byp #( .NumDivClks(${len(clocks.derived_srcs)}) ) u_clkmgr_byp ( @@ -220,7 +222,6 @@ .lc_clk_byp_req_i, .lc_clk_byp_ack_o, .byp_req_i(mubi4_t'(reg2hw.extclk_ctrl.sel.q)), - .low_speed_sel_i(low_speed_sel), .all_clk_byp_req_o, .all_clk_byp_ack_i, .io_clk_byp_req_o, @@ -231,16 +232,6 @@ .step_down_req_o(step_down_req) ); - // the external consumer of this signal requires the opposite polarity - prim_flop #( - .ResetValue(1'b1) - ) u_high_speed_sel ( - .clk_i, - .rst_ni, - .d_i(mubi4_test_false_loose(low_speed_sel)), - .q_o(hi_speed_sel_o) - ); - //////////////////////////////////////////////////// // Feed through clocks // Feed through clocks do not actually need to be in clkmgr, as they are @@ -433,7 +424,7 @@ ) u_${k}_cg ( .clk_i(clk_${v.src.name}_root), .en_i(${k}_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(${k}_scanmode[0])), + .test_en_i(mubi4_test_true_strict(${k}_scanmode[0])), .clk_o(clocks_o.${k}) ); @@ -501,7 +492,7 @@ ) u_${clk}_cg ( .clk_i(clk_${sig.src.name}_root), .en_i(${clk}_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(${clk}_scanmode[0])), + .test_en_i(mubi4_test_true_strict(${clk}_scanmode[0])), .clk_o(clocks_o.${clk}) ); @@ -524,7 +515,10 @@ % endfor // SEC_CM: JITTER.CONFIG.MUBI - assign jitter_en_o = mubi4_test_true_loose(mubi4_t'(reg2hw.jitter_enable.q)); + assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q); + + + assign hi_speed_sel_o = mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q); //////////////////////////////////////////////////// // Exported clocks
diff --git a/hw/ip/clkmgr/dv/env/clkmgr_if.sv b/hw/ip/clkmgr/dv/env/clkmgr_if.sv index dfe3ff0..ed0d4ce 100644 --- a/hw/ip/clkmgr/dv/env/clkmgr_if.sv +++ b/hw/ip/clkmgr/dv/env/clkmgr_if.sv
@@ -43,7 +43,7 @@ prim_mubi_pkg::mubi4_t all_clk_byp_req; prim_mubi_pkg::mubi4_t all_clk_byp_ack; - logic jitter_en_o; + prim_mubi_pkg::mubi4_t jitter_en_o; clkmgr_pkg::clkmgr_out_t clocks_o; // Internal DUT signals. @@ -81,8 +81,7 @@ prim_mubi_pkg::mubi4_t extclk_ctrl_csr_step_down; always_comb begin - extclk_ctrl_csr_step_down = prim_mubi_pkg::mubi4_t'( - `CLKMGR_HIER.reg2hw.extclk_ctrl.low_speed_sel.q); + extclk_ctrl_csr_step_down = ~`CLKMGR_HIER.hi_speed_sel_o; end prim_mubi_pkg::mubi4_t jitter_enable_csr;
diff --git a/hw/ip/clkmgr/dv/env/clkmgr_scoreboard.sv b/hw/ip/clkmgr/dv/env/clkmgr_scoreboard.sv index 9463e2b..0efa02a 100644 --- a/hw/ip/clkmgr/dv/env/clkmgr_scoreboard.sv +++ b/hw/ip/clkmgr/dv/env/clkmgr_scoreboard.sv
@@ -103,8 +103,8 @@ if (cfg.clk_rst_vif.rst_n) begin @cfg.clkmgr_vif.jitter_enable_csr begin cfg.clk_rst_vif.wait_clks(2); - `DV_CHECK_EQ(cfg.clkmgr_vif.jitter_en_o, prim_mubi_pkg::mubi4_test_true_loose( - cfg.clkmgr_vif.jitter_enable_csr), "Mismatching jitter enable output") + `DV_CHECK_EQ(cfg.clkmgr_vif.jitter_en_o, cfg.clkmgr_vif.jitter_enable_csr, + "Mismatching jitter enable output") end end end @@ -113,8 +113,8 @@ if (cfg.clk_rst_vif.rst_n) begin @cfg.clkmgr_vif.jitter_en_o begin cfg.clk_rst_vif.wait_clks(2); - `DV_CHECK_EQ(cfg.clkmgr_vif.jitter_en_o, prim_mubi_pkg::mubi4_test_true_loose( - cfg.clkmgr_vif.jitter_enable_csr), "Mismatching jitter enable output") + `DV_CHECK_EQ(cfg.clkmgr_vif.jitter_en_o, cfg.clkmgr_vif.jitter_enable_csr, + "Mismatching jitter enable output") end end end
diff --git a/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv b/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv index 9ec441e..f142d0a 100644 --- a/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv +++ b/hw/ip/clkmgr/dv/sva/clkmgr_bind.sv
@@ -112,7 +112,7 @@ .lc_step_down_ack(io_clk_byp_ack_i == prim_mubi_pkg::MuBi4True), .sw_step_down_ctrl(lc_hw_debug_en_i == lc_ctrl_pkg::On && reg2hw.extclk_ctrl.sel.q == prim_mubi_pkg::MuBi4True && - reg2hw.extclk_ctrl.low_speed_sel.q == prim_mubi_pkg::MuBi4True), + reg2hw.extclk_ctrl.hi_speed_sel.q == prim_mubi_pkg::MuBi4False), .sw_step_down_ack(all_clk_byp_ack_i == prim_mubi_pkg::MuBi4True), .sw_step_up_ack(all_clk_byp_ack_i == prim_mubi_pkg::MuBi4False), .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True) @@ -129,7 +129,7 @@ .lc_step_down_ack(io_clk_byp_ack_i == prim_mubi_pkg::MuBi4True), .sw_step_down_ctrl(lc_hw_debug_en_i == lc_ctrl_pkg::On && reg2hw.extclk_ctrl.sel.q == prim_mubi_pkg::MuBi4True && - reg2hw.extclk_ctrl.low_speed_sel.q == prim_mubi_pkg::MuBi4True), + reg2hw.extclk_ctrl.hi_speed_sel.q == prim_mubi_pkg::MuBi4False), .sw_step_down_ack(all_clk_byp_ack_i == prim_mubi_pkg::MuBi4True), .sw_step_up_ack(all_clk_byp_ack_i == prim_mubi_pkg::MuBi4False), .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True)
diff --git a/hw/ip/clkmgr/rtl/clkmgr_byp.sv b/hw/ip/clkmgr/rtl/clkmgr_byp.sv index c1f9c11..55bdb91 100644 --- a/hw/ip/clkmgr/rtl/clkmgr_byp.sv +++ b/hw/ip/clkmgr/rtl/clkmgr_byp.sv
@@ -19,7 +19,6 @@ output lc_tx_t lc_clk_byp_ack_o, // interaction with software input mubi4_t byp_req_i, - input mubi4_t low_speed_sel_i, // interaction with ast output mubi4_t all_clk_byp_req_o, input mubi4_t all_clk_byp_ack_i, @@ -27,7 +26,7 @@ input mubi4_t io_clk_byp_ack_i, // interaction with dividers input [NumDivClks-1:0] step_down_acks_i, - output logic step_down_req_o + output mubi4_t step_down_req_o ); import prim_mubi_pkg::MuBi4Width; @@ -38,9 +37,52 @@ import prim_mubi_pkg::mubi4_test_false_strict; import prim_mubi_pkg::mubi4_test_true_strict; + // synchornize incoming lc signals + lc_tx_t en; + prim_lc_sync #( + .NumCopies(1), + .AsyncOn(1), + .ResetValueIsOn(0) + ) u_en_sync ( + .clk_i, + .rst_ni, + .lc_en_i(en_i), + .lc_en_o(en) + ); + + typedef enum logic [1:0] { + LcClkBypReqIoReq, + LcClkBypReqLcAck, + LcClkBypReqLast + } lc_clk_byp_req_e; + + lc_tx_t [LcClkBypReqLast-1:0] lc_clk_byp_req; + prim_lc_sync #( + .NumCopies(int'(LcClkBypReqLast)), + .AsyncOn(1), + .ResetValueIsOn(0) + ) u_lc_byp_req ( + .clk_i, + .rst_ni, + .lc_en_i(lc_clk_byp_req_i), + .lc_en_o(lc_clk_byp_req) + ); + + // synchronize step down acks + logic [NumDivClks-1:0] step_down_acks_sync; + prim_flop #( + .Width(NumDivClks), + .ResetValue(0) + ) u_step_down_acks_sync ( + .clk_i, + .rst_ni, + .d_i(step_down_acks_i), + .q_o(step_down_acks_sync) + ); + // life cycle handling mubi4_t io_clk_byp_req_d; - assign io_clk_byp_req_d = (lc_clk_byp_req_i == lc_ctrl_pkg::On) ? + assign io_clk_byp_req_d = (lc_clk_byp_req[LcClkBypReqIoReq] == lc_ctrl_pkg::On) ? MuBi4True : MuBi4False; @@ -58,18 +100,19 @@ prim_lc_sender u_send ( .clk_i, .rst_ni, - .lc_en_i((&step_down_acks_i) ? lc_clk_byp_req_i : lc_ctrl_pkg::Off), + .lc_en_i(&step_down_acks_sync ? lc_clk_byp_req[LcClkBypReqLcAck] : lc_ctrl_pkg::Off), .lc_en_o(lc_clk_byp_ack_o) ); // software switch request handling mubi4_t dft_en; - assign dft_en = (en_i == lc_ctrl_pkg::On) ? MuBi4True : MuBi4False; + assign dft_en = (en == lc_ctrl_pkg::On) ? MuBi4True : MuBi4False; mubi4_t all_clk_byp_req_d; assign all_clk_byp_req_d = mubi4_and_hi(byp_req_i, dft_en); prim_mubi4_sender #( + .AsyncOn(1), .ResetValue(MuBi4False), .EnSecBuf(1) ) u_all_byp_req ( @@ -127,15 +170,17 @@ end // when in external clock state, allow low speed select to directly control // clock divider. - assign sw_step_down_req = mubi4_and_hi(sw_step_down_en, low_speed_sel_i); + + // TODO + // This will be updated to a different signaling, see #10890 + assign sw_step_down_req = sw_step_down_en; // combine requests always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - step_down_req_o <= '0; + step_down_req_o <= MuBi4False; end else begin - step_down_req_o <= - mubi4_test_true_strict(mubi4_or_hi(lc_step_down_req, sw_step_down_req)); + step_down_req_o <= mubi4_or_hi(lc_step_down_req, sw_step_down_req); end end
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 43c5cad..a0fe369 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -3171,13 +3171,13 @@ } { name: hi_speed_sel - struct: logic + struct: mubi4 + package: prim_mubi_pkg type: uni act: req width: 1 inst_name: clkmgr_aon default: "" - package: "" external: true top_signame: hi_speed_sel conn_type: false @@ -3209,13 +3209,13 @@ } { name: jitter_en - struct: logic + struct: mubi4 + package: prim_mubi_pkg type: uni act: req width: 1 inst_name: clkmgr_aon default: "" - package: "" external: true top_signame: clk_main_jitter_en conn_type: false @@ -16070,13 +16070,13 @@ } { name: hi_speed_sel - struct: logic + struct: mubi4 + package: prim_mubi_pkg type: uni act: req width: 1 inst_name: clkmgr_aon default: "" - package: "" external: true top_signame: hi_speed_sel conn_type: false @@ -16108,13 +16108,13 @@ } { name: jitter_en - struct: logic + struct: mubi4 + package: prim_mubi_pkg type: uni act: req width: 1 inst_name: clkmgr_aon default: "" - package: "" external: true top_signame: clk_main_jitter_en conn_type: false @@ -19261,8 +19261,8 @@ netname: ast_rom_cfg } { - package: "" - struct: logic + package: prim_mubi_pkg + struct: mubi4 signame: clk_main_jitter_en_o width: 1 type: uni @@ -19321,8 +19321,8 @@ netname: all_clk_byp_ack } { - package: "" - struct: logic + package: prim_mubi_pkg + struct: mubi4 signame: hi_speed_sel_o width: 1 type: uni
diff --git a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson index 42d169b..e50447c 100644 --- a/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson +++ b/hw/top_earlgrey/ip/clkmgr/data/autogen/clkmgr.hjson
@@ -109,11 +109,11 @@ package: "prim_mubi_pkg", }, - { struct: "logic", + { struct: "mubi4", type: "uni", name: "hi_speed_sel", act: "req", - package: "", + package: "prim_mubi_pkg", }, { struct: "lc_tx", @@ -130,11 +130,11 @@ package: "lc_ctrl_pkg", }, - { struct: "logic", + { struct: "mubi4", type: "uni", name: "jitter_en", act: "req", - package: "" + package: "prim_mubi_pkg" }, // Exported clocks @@ -230,11 +230,11 @@ }, { bits: "7:4", - name: "LOW_SPEED_SEL", + name: "HI_SPEED_SEL", mubi: true, desc: ''' - A value of kMultiBitBool4True selects low speed external clocks. - All other values selects nominal speed clocks. + A value of kMultiBitBool4True selects nominal speed external clocks. + All other values selects low speed clocks. Note this field only has an effect when the !!EXTCLK_CTRL.SEL field is set to kMultiBitBool4True. @@ -244,6 +244,22 @@ ] }, + { name: "JITTER_REGWEN", + desc: "Jitter write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, the value of !!JITTER_ENALBE can be changed. When 0, writes have no + effect. + ''' + }, + ] + }, + { name: "JITTER_ENABLE", desc: ''' Enable jittery clock
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv index a1e078b..cf8f7cc 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -75,10 +75,10 @@ input mubi4_t io_clk_byp_ack_i, output mubi4_t all_clk_byp_req_o, input mubi4_t all_clk_byp_ack_i, - output logic hi_speed_sel_o, + output mubi4_t hi_speed_sel_o, // jittery enable - output logic jitter_en_o, + output mubi4_t jitter_en_o, // clock gated indications going to alert handlers output clkmgr_cg_en_t cg_en_o, @@ -90,6 +90,7 @@ import prim_mubi_pkg::MuBi4False; import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::mubi4_test_true_strict; import prim_mubi_pkg::mubi4_test_true_loose; import prim_mubi_pkg::mubi4_test_false_loose; @@ -97,20 +98,23 @@ // Divided clocks //////////////////////////////////////////////////// - logic step_down_req; + mubi4_t step_down_req; logic [1:0] step_down_acks; logic clk_io_div2_i; logic clk_io_div4_i; - logic io_step_down_req; - prim_flop_2sync #( - .Width(1) + mubi4_t io_step_down_req; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(1), + .StabilityCheck(1), + .ResetValue(MuBi4False) ) u_io_step_down_req_sync ( .clk_i(clk_io_i), .rst_ni(rst_io_ni), - .d_i(step_down_req), - .q_o(io_step_down_req) + .mubi_i(step_down_req), + .mubi_o(io_step_down_req) ); @@ -131,9 +135,9 @@ ) u_no_scan_io_div2_div ( .clk_i(clk_io_i), .rst_ni(rst_io_ni), - .step_down_req_i(io_step_down_req), + .step_down_req_i(mubi4_test_true_strict(io_step_down_req)), .step_down_ack_o(step_down_acks[0]), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(io_div2_div_scanmode[0])), + .test_en_i(mubi4_test_true_strict(io_div2_div_scanmode[0])), .clk_o(clk_io_div2_i) ); @@ -154,9 +158,9 @@ ) u_no_scan_io_div4_div ( .clk_i(clk_io_i), .rst_ni(rst_io_ni), - .step_down_req_i(io_step_down_req), + .step_down_req_i(mubi4_test_true_strict(io_step_down_req)), .step_down_ack_o(step_down_acks[1]), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(io_div4_div_scanmode[0])), + .test_en_i(mubi4_test_true_strict(io_div4_div_scanmode[0])), .clk_o(clk_io_div4_i) ); @@ -249,8 +253,6 @@ // Clock bypass request //////////////////////////////////////////////////// - mubi4_t low_speed_sel; - assign low_speed_sel = mubi4_t'(reg2hw.extclk_ctrl.low_speed_sel.q); clkmgr_byp #( .NumDivClks(2) ) u_clkmgr_byp ( @@ -260,7 +262,6 @@ .lc_clk_byp_req_i, .lc_clk_byp_ack_o, .byp_req_i(mubi4_t'(reg2hw.extclk_ctrl.sel.q)), - .low_speed_sel_i(low_speed_sel), .all_clk_byp_req_o, .all_clk_byp_ack_i, .io_clk_byp_req_o, @@ -271,16 +272,6 @@ .step_down_req_o(step_down_req) ); - // the external consumer of this signal requires the opposite polarity - prim_flop #( - .ResetValue(1'b1) - ) u_high_speed_sel ( - .clk_i, - .rst_ni, - .d_i(mubi4_test_false_loose(low_speed_sel)), - .q_o(hi_speed_sel_o) - ); - //////////////////////////////////////////////////// // Feed through clocks // Feed through clocks do not actually need to be in clkmgr, as they are @@ -926,7 +917,7 @@ ) u_clk_io_div4_peri_cg ( .clk_i(clk_io_div4_root), .en_i(clk_io_div4_peri_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_io_div4_peri_scanmode[0])), + .test_en_i(mubi4_test_true_strict(clk_io_div4_peri_scanmode[0])), .clk_o(clocks_o.clk_io_div4_peri) ); @@ -968,7 +959,7 @@ ) u_clk_io_div2_peri_cg ( .clk_i(clk_io_div2_root), .en_i(clk_io_div2_peri_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_io_div2_peri_scanmode[0])), + .test_en_i(mubi4_test_true_strict(clk_io_div2_peri_scanmode[0])), .clk_o(clocks_o.clk_io_div2_peri) ); @@ -1010,7 +1001,7 @@ ) u_clk_usb_peri_cg ( .clk_i(clk_usb_root), .en_i(clk_usb_peri_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_usb_peri_scanmode[0])), + .test_en_i(mubi4_test_true_strict(clk_usb_peri_scanmode[0])), .clk_o(clocks_o.clk_usb_peri) ); @@ -1052,7 +1043,7 @@ ) u_clk_io_peri_cg ( .clk_i(clk_io_root), .en_i(clk_io_peri_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_io_peri_scanmode[0])), + .test_en_i(mubi4_test_true_strict(clk_io_peri_scanmode[0])), .clk_o(clocks_o.clk_io_peri) ); @@ -1120,7 +1111,7 @@ ) u_clk_main_aes_cg ( .clk_i(clk_main_root), .en_i(clk_main_aes_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_main_aes_scanmode[0])), + .test_en_i(mubi4_test_true_strict(clk_main_aes_scanmode[0])), .clk_o(clocks_o.clk_main_aes) ); @@ -1170,7 +1161,7 @@ ) u_clk_main_hmac_cg ( .clk_i(clk_main_root), .en_i(clk_main_hmac_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_main_hmac_scanmode[0])), + .test_en_i(mubi4_test_true_strict(clk_main_hmac_scanmode[0])), .clk_o(clocks_o.clk_main_hmac) ); @@ -1220,7 +1211,7 @@ ) u_clk_main_kmac_cg ( .clk_i(clk_main_root), .en_i(clk_main_kmac_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_main_kmac_scanmode[0])), + .test_en_i(mubi4_test_true_strict(clk_main_kmac_scanmode[0])), .clk_o(clocks_o.clk_main_kmac) ); @@ -1270,7 +1261,7 @@ ) u_clk_main_otbn_cg ( .clk_i(clk_main_root), .en_i(clk_main_otbn_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_main_otbn_scanmode[0])), + .test_en_i(mubi4_test_true_strict(clk_main_otbn_scanmode[0])), .clk_o(clocks_o.clk_main_otbn) ); @@ -1320,7 +1311,7 @@ ) u_clk_io_div4_otbn_cg ( .clk_i(clk_io_div4_root), .en_i(clk_io_div4_otbn_combined_en), - .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(clk_io_div4_otbn_scanmode[0])), + .test_en_i(mubi4_test_true_strict(clk_io_div4_otbn_scanmode[0])), .clk_o(clocks_o.clk_io_div4_otbn) ); @@ -1348,7 +1339,10 @@ assign hw2reg.clk_hints_status.clk_io_div4_otbn_val.d = clk_io_div4_otbn_en; // SEC_CM: JITTER.CONFIG.MUBI - assign jitter_en_o = mubi4_test_true_loose(mubi4_t'(reg2hw.jitter_enable.q)); + assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q); + + + assign hi_speed_sel_o = mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q); //////////////////////////////////////////////////// // Exported clocks
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv index 6a545d6..73bdfcb 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_pkg.sv
@@ -36,7 +36,7 @@ } sel; struct packed { logic [3:0] q; - } low_speed_sel; + } hi_speed_sel; } clkmgr_reg2hw_extclk_ctrl_reg_t; typedef struct packed { @@ -326,18 +326,19 @@ parameter logic [BlockAw-1:0] CLKMGR_ALERT_TEST_OFFSET = 6'h 0; parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET = 6'h 4; parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_OFFSET = 6'h 8; - parameter logic [BlockAw-1:0] CLKMGR_JITTER_ENABLE_OFFSET = 6'h c; - parameter logic [BlockAw-1:0] CLKMGR_CLK_ENABLES_OFFSET = 6'h 10; - parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_OFFSET = 6'h 14; - parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_STATUS_OFFSET = 6'h 18; - parameter logic [BlockAw-1:0] CLKMGR_MEASURE_CTRL_REGWEN_OFFSET = 6'h 1c; - parameter logic [BlockAw-1:0] CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET = 6'h 20; - parameter logic [BlockAw-1:0] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET = 6'h 24; - parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET = 6'h 28; - parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET = 6'h 2c; - parameter logic [BlockAw-1:0] CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET = 6'h 30; - parameter logic [BlockAw-1:0] CLKMGR_RECOV_ERR_CODE_OFFSET = 6'h 34; - parameter logic [BlockAw-1:0] CLKMGR_FATAL_ERR_CODE_OFFSET = 6'h 38; + parameter logic [BlockAw-1:0] CLKMGR_JITTER_REGWEN_OFFSET = 6'h c; + parameter logic [BlockAw-1:0] CLKMGR_JITTER_ENABLE_OFFSET = 6'h 10; + parameter logic [BlockAw-1:0] CLKMGR_CLK_ENABLES_OFFSET = 6'h 14; + parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_OFFSET = 6'h 18; + parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_STATUS_OFFSET = 6'h 1c; + parameter logic [BlockAw-1:0] CLKMGR_MEASURE_CTRL_REGWEN_OFFSET = 6'h 20; + parameter logic [BlockAw-1:0] CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET = 6'h 24; + parameter logic [BlockAw-1:0] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET = 6'h 28; + parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET = 6'h 2c; + parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET = 6'h 30; + parameter logic [BlockAw-1:0] CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET = 6'h 34; + parameter logic [BlockAw-1:0] CLKMGR_RECOV_ERR_CODE_OFFSET = 6'h 38; + parameter logic [BlockAw-1:0] CLKMGR_FATAL_ERR_CODE_OFFSET = 6'h 3c; // Reset values for hwext registers and their fields parameter logic [1:0] CLKMGR_ALERT_TEST_RESVAL = 2'h 0; @@ -349,6 +350,7 @@ CLKMGR_ALERT_TEST, CLKMGR_EXTCLK_CTRL_REGWEN, CLKMGR_EXTCLK_CTRL, + CLKMGR_JITTER_REGWEN, CLKMGR_JITTER_ENABLE, CLKMGR_CLK_ENABLES, CLKMGR_CLK_HINTS, @@ -364,22 +366,23 @@ } clkmgr_id_e; // Register width information to check illegal writes - parameter logic [3:0] CLKMGR_PERMIT [15] = '{ + parameter logic [3:0] CLKMGR_PERMIT [16] = '{ 4'b 0001, // index[ 0] CLKMGR_ALERT_TEST 4'b 0001, // index[ 1] CLKMGR_EXTCLK_CTRL_REGWEN 4'b 0001, // index[ 2] CLKMGR_EXTCLK_CTRL - 4'b 0001, // index[ 3] CLKMGR_JITTER_ENABLE - 4'b 0001, // index[ 4] CLKMGR_CLK_ENABLES - 4'b 0001, // index[ 5] CLKMGR_CLK_HINTS - 4'b 0001, // index[ 6] CLKMGR_CLK_HINTS_STATUS - 4'b 0001, // index[ 7] CLKMGR_MEASURE_CTRL_REGWEN - 4'b 0111, // index[ 8] CLKMGR_IO_MEAS_CTRL_SHADOWED - 4'b 0111, // index[ 9] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED - 4'b 0111, // index[10] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED - 4'b 0111, // index[11] CLKMGR_MAIN_MEAS_CTRL_SHADOWED - 4'b 0111, // index[12] CLKMGR_USB_MEAS_CTRL_SHADOWED - 4'b 0011, // index[13] CLKMGR_RECOV_ERR_CODE - 4'b 0001 // index[14] CLKMGR_FATAL_ERR_CODE + 4'b 0001, // index[ 3] CLKMGR_JITTER_REGWEN + 4'b 0001, // index[ 4] CLKMGR_JITTER_ENABLE + 4'b 0001, // index[ 5] CLKMGR_CLK_ENABLES + 4'b 0001, // index[ 6] CLKMGR_CLK_HINTS + 4'b 0001, // index[ 7] CLKMGR_CLK_HINTS_STATUS + 4'b 0001, // index[ 8] CLKMGR_MEASURE_CTRL_REGWEN + 4'b 0111, // index[ 9] CLKMGR_IO_MEAS_CTRL_SHADOWED + 4'b 0111, // index[10] CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED + 4'b 0111, // index[11] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED + 4'b 0111, // index[12] CLKMGR_MAIN_MEAS_CTRL_SHADOWED + 4'b 0111, // index[13] CLKMGR_USB_MEAS_CTRL_SHADOWED + 4'b 0011, // index[14] CLKMGR_RECOV_ERR_CODE + 4'b 0001 // index[15] CLKMGR_FATAL_ERR_CODE }; endpackage
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv index 9f3a7f3..fe228d7 100644 --- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv +++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
@@ -188,8 +188,11 @@ logic extclk_ctrl_we; logic [3:0] extclk_ctrl_sel_qs; logic [3:0] extclk_ctrl_sel_wd; - logic [3:0] extclk_ctrl_low_speed_sel_qs; - logic [3:0] extclk_ctrl_low_speed_sel_wd; + logic [3:0] extclk_ctrl_hi_speed_sel_qs; + logic [3:0] extclk_ctrl_hi_speed_sel_wd; + logic jitter_regwen_we; + logic jitter_regwen_qs; + logic jitter_regwen_wd; logic jitter_enable_we; logic [3:0] jitter_enable_qs; logic [3:0] jitter_enable_wd; @@ -574,18 +577,18 @@ .qs (extclk_ctrl_sel_qs) ); - // F[low_speed_sel]: 7:4 + // F[hi_speed_sel]: 7:4 prim_subreg #( .DW (4), .SwAccess(prim_subreg_pkg::SwAccessRW), .RESVAL (4'h5) - ) u_extclk_ctrl_low_speed_sel ( + ) u_extclk_ctrl_hi_speed_sel ( .clk_i (clk_i), .rst_ni (rst_ni), // from register interface .we (extclk_ctrl_we & extclk_ctrl_regwen_qs), - .wd (extclk_ctrl_low_speed_sel_wd), + .wd (extclk_ctrl_hi_speed_sel_wd), // from internal hardware .de (1'b0), @@ -593,10 +596,36 @@ // to internal hardware .qe (), - .q (reg2hw.extclk_ctrl.low_speed_sel.q), + .q (reg2hw.extclk_ctrl.hi_speed_sel.q), // to register interface (read) - .qs (extclk_ctrl_low_speed_sel_qs) + .qs (extclk_ctrl_hi_speed_sel_qs) + ); + + + // R[jitter_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1) + ) u_jitter_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (jitter_regwen_we), + .wd (jitter_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (jitter_regwen_qs) ); @@ -2418,24 +2447,25 @@ - logic [14:0] addr_hit; + logic [15:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == CLKMGR_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET); addr_hit[ 2] = (reg_addr == CLKMGR_EXTCLK_CTRL_OFFSET); - addr_hit[ 3] = (reg_addr == CLKMGR_JITTER_ENABLE_OFFSET); - addr_hit[ 4] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET); - addr_hit[ 5] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET); - addr_hit[ 6] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET); - addr_hit[ 7] = (reg_addr == CLKMGR_MEASURE_CTRL_REGWEN_OFFSET); - addr_hit[ 8] = (reg_addr == CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[ 9] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[10] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[11] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[12] = (reg_addr == CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET); - addr_hit[13] = (reg_addr == CLKMGR_RECOV_ERR_CODE_OFFSET); - addr_hit[14] = (reg_addr == CLKMGR_FATAL_ERR_CODE_OFFSET); + addr_hit[ 3] = (reg_addr == CLKMGR_JITTER_REGWEN_OFFSET); + addr_hit[ 4] = (reg_addr == CLKMGR_JITTER_ENABLE_OFFSET); + addr_hit[ 5] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET); + addr_hit[ 6] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET); + addr_hit[ 7] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET); + addr_hit[ 8] = (reg_addr == CLKMGR_MEASURE_CTRL_REGWEN_OFFSET); + addr_hit[ 9] = (reg_addr == CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[10] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[11] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[12] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[13] = (reg_addr == CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[14] = (reg_addr == CLKMGR_RECOV_ERR_CODE_OFFSET); + addr_hit[15] = (reg_addr == CLKMGR_FATAL_ERR_CODE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -2457,7 +2487,8 @@ (addr_hit[11] & (|(CLKMGR_PERMIT[11] & ~reg_be))) | (addr_hit[12] & (|(CLKMGR_PERMIT[12] & ~reg_be))) | (addr_hit[13] & (|(CLKMGR_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(CLKMGR_PERMIT[14] & ~reg_be))))); + (addr_hit[14] & (|(CLKMGR_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(CLKMGR_PERMIT[15] & ~reg_be))))); end assign alert_test_we = addr_hit[0] & reg_we & !reg_error; @@ -2471,11 +2502,14 @@ assign extclk_ctrl_sel_wd = reg_wdata[3:0]; - assign extclk_ctrl_low_speed_sel_wd = reg_wdata[7:4]; - assign jitter_enable_we = addr_hit[3] & reg_we & !reg_error; + assign extclk_ctrl_hi_speed_sel_wd = reg_wdata[7:4]; + assign jitter_regwen_we = addr_hit[3] & reg_we & !reg_error; + + assign jitter_regwen_wd = reg_wdata[0]; + assign jitter_enable_we = addr_hit[4] & reg_we & !reg_error; assign jitter_enable_wd = reg_wdata[3:0]; - assign clk_enables_we = addr_hit[4] & reg_we & !reg_error; + assign clk_enables_we = addr_hit[5] & reg_we & !reg_error; assign clk_enables_clk_io_div4_peri_en_wd = reg_wdata[0]; @@ -2484,7 +2518,7 @@ assign clk_enables_clk_usb_peri_en_wd = reg_wdata[2]; assign clk_enables_clk_io_peri_en_wd = reg_wdata[3]; - assign clk_hints_we = addr_hit[5] & reg_we & !reg_error; + assign clk_hints_we = addr_hit[6] & reg_we & !reg_error; assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0]; @@ -2495,35 +2529,35 @@ assign clk_hints_clk_io_div4_otbn_hint_wd = reg_wdata[3]; assign clk_hints_clk_main_otbn_hint_wd = reg_wdata[4]; - assign measure_ctrl_regwen_we = addr_hit[7] & reg_we & !reg_error; + assign measure_ctrl_regwen_we = addr_hit[8] & reg_we & !reg_error; assign measure_ctrl_regwen_wd = reg_wdata[0]; - assign io_meas_ctrl_shadowed_re = addr_hit[8] & reg_re & !reg_error; - assign io_meas_ctrl_shadowed_we = addr_hit[8] & reg_we & !reg_error; + assign io_meas_ctrl_shadowed_re = addr_hit[9] & reg_re & !reg_error; + assign io_meas_ctrl_shadowed_we = addr_hit[9] & reg_we & !reg_error; - assign io_div2_meas_ctrl_shadowed_re = addr_hit[9] & reg_re & !reg_error; - assign io_div2_meas_ctrl_shadowed_we = addr_hit[9] & reg_we & !reg_error; + assign io_div2_meas_ctrl_shadowed_re = addr_hit[10] & reg_re & !reg_error; + assign io_div2_meas_ctrl_shadowed_we = addr_hit[10] & reg_we & !reg_error; - assign io_div4_meas_ctrl_shadowed_re = addr_hit[10] & reg_re & !reg_error; - assign io_div4_meas_ctrl_shadowed_we = addr_hit[10] & reg_we & !reg_error; + assign io_div4_meas_ctrl_shadowed_re = addr_hit[11] & reg_re & !reg_error; + assign io_div4_meas_ctrl_shadowed_we = addr_hit[11] & reg_we & !reg_error; - assign main_meas_ctrl_shadowed_re = addr_hit[11] & reg_re & !reg_error; - assign main_meas_ctrl_shadowed_we = addr_hit[11] & reg_we & !reg_error; + assign main_meas_ctrl_shadowed_re = addr_hit[12] & reg_re & !reg_error; + assign main_meas_ctrl_shadowed_we = addr_hit[12] & reg_we & !reg_error; - assign usb_meas_ctrl_shadowed_re = addr_hit[12] & reg_re & !reg_error; - assign usb_meas_ctrl_shadowed_we = addr_hit[12] & reg_we & !reg_error; + assign usb_meas_ctrl_shadowed_re = addr_hit[13] & reg_re & !reg_error; + assign usb_meas_ctrl_shadowed_we = addr_hit[13] & reg_we & !reg_error; - assign recov_err_code_we = addr_hit[13] & reg_we & !reg_error; + assign recov_err_code_we = addr_hit[14] & reg_we & !reg_error; assign recov_err_code_io_measure_err_wd = reg_wdata[0]; @@ -2570,21 +2604,25 @@ addr_hit[2]: begin reg_rdata_next[3:0] = extclk_ctrl_sel_qs; - reg_rdata_next[7:4] = extclk_ctrl_low_speed_sel_qs; + reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs; end addr_hit[3]: begin - reg_rdata_next[3:0] = jitter_enable_qs; + reg_rdata_next[0] = jitter_regwen_qs; end addr_hit[4]: begin + reg_rdata_next[3:0] = jitter_enable_qs; + end + + addr_hit[5]: begin reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs; reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs; reg_rdata_next[2] = clk_enables_clk_usb_peri_en_qs; reg_rdata_next[3] = clk_enables_clk_io_peri_en_qs; end - addr_hit[5]: begin + addr_hit[6]: begin reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs; reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs; reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs; @@ -2592,7 +2630,7 @@ reg_rdata_next[4] = clk_hints_clk_main_otbn_hint_qs; end - addr_hit[6]: begin + addr_hit[7]: begin reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs; reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs; reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs; @@ -2600,26 +2638,26 @@ reg_rdata_next[4] = clk_hints_status_clk_main_otbn_val_qs; end - addr_hit[7]: begin + addr_hit[8]: begin reg_rdata_next[0] = measure_ctrl_regwen_qs; end - addr_hit[8]: begin + addr_hit[9]: begin reg_rdata_next = DW'(io_meas_ctrl_shadowed_qs); end - addr_hit[9]: begin + addr_hit[10]: begin reg_rdata_next = DW'(io_div2_meas_ctrl_shadowed_qs); end - addr_hit[10]: begin + addr_hit[11]: begin reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs); end - addr_hit[11]: begin + addr_hit[12]: begin reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs); end - addr_hit[12]: begin + addr_hit[13]: begin reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs); end - addr_hit[13]: begin + addr_hit[14]: begin reg_rdata_next[0] = recov_err_code_io_measure_err_qs; reg_rdata_next[1] = recov_err_code_io_div2_measure_err_qs; reg_rdata_next[2] = recov_err_code_io_div4_measure_err_qs; @@ -2637,7 +2675,7 @@ reg_rdata_next[14] = recov_err_code_usb_update_err_qs; end - addr_hit[14]: begin + addr_hit[15]: begin reg_rdata_next[0] = fatal_err_code_reg_intg_qs; reg_rdata_next[1] = fatal_err_code_io_storage_err_qs; reg_rdata_next[2] = fatal_err_code_io_div2_storage_err_qs; @@ -2681,19 +2719,19 @@ always_comb begin reg_busy_sel = '0; unique case (1'b1) - addr_hit[8]: begin + addr_hit[9]: begin reg_busy_sel = io_meas_ctrl_shadowed_busy; end - addr_hit[9]: begin + addr_hit[10]: begin reg_busy_sel = io_div2_meas_ctrl_shadowed_busy; end - addr_hit[10]: begin + addr_hit[11]: begin reg_busy_sel = io_div4_meas_ctrl_shadowed_busy; end - addr_hit[11]: begin + addr_hit[12]: begin reg_busy_sel = main_meas_ctrl_shadowed_busy; end - addr_hit[12]: begin + addr_hit[13]: begin reg_busy_sel = usb_meas_ctrl_shadowed_busy; end default: begin
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index e96b42b..e912796 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -738,7 +738,7 @@ prim_mubi_pkg::mubi4_t io_clk_byp_ack; prim_mubi_pkg::mubi4_t all_clk_byp_req; prim_mubi_pkg::mubi4_t all_clk_byp_ack; - logic hi_speed_sel; + prim_mubi_pkg::mubi4_t hi_speed_sel; // DFT connections logic scan_en; @@ -750,7 +750,7 @@ logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast; // Jitter enable - logic jen; + prim_mubi_pkg::mubi4_t jen; // reset domain connections import rstmgr_pkg::PowerDomains;
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv index e4de760..865fad0 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
@@ -692,7 +692,7 @@ prim_mubi_pkg::mubi4_t io_clk_byp_ack; prim_mubi_pkg::mubi4_t all_clk_byp_req; prim_mubi_pkg::mubi4_t all_clk_byp_ack; - logic hi_speed_sel; + prim_mubi_pkg::mubi4_t hi_speed_sel; // DFT connections logic scan_en; @@ -704,7 +704,7 @@ logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast; // Jitter enable - logic jen; + prim_mubi_pkg::mubi4_t jen; // reset domain connections import rstmgr_pkg::PowerDomains;
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv index 628c973..46d7deb 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
@@ -711,7 +711,7 @@ prim_mubi_pkg::mubi4_t io_clk_byp_ack; prim_mubi_pkg::mubi4_t all_clk_byp_req; prim_mubi_pkg::mubi4_t all_clk_byp_ack; - logic hi_speed_sel; + prim_mubi_pkg::mubi4_t hi_speed_sel; // DFT connections logic scan_en; @@ -723,7 +723,7 @@ logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast; // Jitter enable - logic jen; + prim_mubi_pkg::mubi4_t jen; // reset domain connections import rstmgr_pkg::PowerDomains;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 58a33fc..28f3790 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -126,12 +126,12 @@ input prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg_i, input prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg_i, input prim_rom_pkg::rom_cfg_t rom_cfg_i, - output logic clk_main_jitter_en_o, + output prim_mubi_pkg::mubi4_t clk_main_jitter_en_o, output prim_mubi_pkg::mubi4_t io_clk_byp_req_o, input prim_mubi_pkg::mubi4_t io_clk_byp_ack_i, output prim_mubi_pkg::mubi4_t all_clk_byp_req_o, input prim_mubi_pkg::mubi4_t all_clk_byp_ack_i, - output logic hi_speed_sel_o, + output prim_mubi_pkg::mubi4_t hi_speed_sel_o, output ast_pkg::ast_dif_t flash_alert_o, input prim_mubi_pkg::mubi4_t flash_bist_enable_i, input logic flash_power_down_h_i,
diff --git a/sw/device/lib/dif/dif_clkmgr.c b/sw/device/lib/dif/dif_clkmgr.c index e01b3aa..30c88ac 100644 --- a/sw/device/lib/dif/dif_clkmgr.c +++ b/sw/device/lib/dif/dif_clkmgr.c
@@ -160,8 +160,8 @@ extclk_ctrl_reg = bitfield_field32_write( extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_SEL_FIELD, kMultiBitBool4True); extclk_ctrl_reg = bitfield_field32_write( - extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_LOW_SPEED_SEL_FIELD, - is_low_speed ? kMultiBitBool4True : kMultiBitBool4False); + extclk_ctrl_reg, CLKMGR_EXTCLK_CTRL_HI_SPEED_SEL_FIELD, + is_low_speed ? kMultiBitBool4False : kMultiBitBool4True); mmio_region_write32(clkmgr->base_addr, CLKMGR_EXTCLK_CTRL_REG_OFFSET, extclk_ctrl_reg); return kDifOk;
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl index e568e0a..b6afe87 100644 --- a/util/topgen/templates/chiplevel.sv.tpl +++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -634,7 +634,7 @@ prim_mubi_pkg::mubi4_t io_clk_byp_ack; prim_mubi_pkg::mubi4_t all_clk_byp_req; prim_mubi_pkg::mubi4_t all_clk_byp_ack; - logic hi_speed_sel; + prim_mubi_pkg::mubi4_t hi_speed_sel; // DFT connections logic scan_en; @@ -646,7 +646,7 @@ logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast; // Jitter enable - logic jen; + prim_mubi_pkg::mubi4_t jen; // reset domain connections import rstmgr_pkg::PowerDomains;