| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| { |
| // Name of the sim cfg - typically same as the name of the DUT. |
| name: chip |
| |
| // Top level dut name (sv module). |
| dut: chip_earlgrey_asic |
| |
| // Top level testbench name (sv module). |
| tb: tb |
| |
| // Default simulator used to sign off. |
| tool: vcs |
| |
| // Fusesoc core file used for building the file list. |
| fusesoc_core: lowrisc:dv:chip_sim:0.1 |
| |
| // Testplan hjson file, excluding the connectivity tests. |
| testplan: "{proj_root}/hw/top_earlgrey/data/chip_testplan.hjson:-conn" |
| |
| // RAL spec - used to generate the RAL model. |
| ral_spec: "{proj_root}/hw/top_earlgrey/data/top_earlgrey.hjson" |
| |
| // Add additional tops for simulation. |
| sim_tops: ["clkmgr_bind", |
| "pwrmgr_bind", |
| "rstmgr_bind", |
| "sec_cm_prim_onehot_check_bind", |
| "top_earlgrey_error_injection_ifs_bind", |
| "top_earlgrey_bind", |
| "xbar_main_bind", |
| "xbar_peri_bind"] |
| |
| // Import additional common sim cfg files. |
| import_cfgs: [// Project wide common sim cfg file |
| "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", |
| // Common CIP test lists |
| "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", |
| // TODO #5484, comment these 2 lines out because spi host memory is dummy |
| // "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", |
| // xbar tests |
| "{proj_root}/hw/ip/tlul/generic_dv/xbar_tests.hjson", |
| // Config files to get the correct flags for otbn_memutil and otbn_tracer |
| "{proj_root}/hw/dv/verilator/memutil_dpi_scrambled_opts.hjson", |
| "{proj_root}/hw/ip/otbn/dv/memutil/otbn_memutil_sim_opts.hjson", |
| "{proj_root}/hw/ip/otbn/dv/tracer/otbn_tracer_sim_opts.hjson", |
| "{proj_root}/hw/top_earlgrey/dv/chip_smoketests.hjson", |
| "{proj_root}/hw/top_earlgrey/dv/chip_rom_tests.hjson", |
| ] |
| |
| // Override existing project defaults to supply chip-specific values. |
| overrides: [ |
| // Chip level design is markedly different from our Comportable IPs (and so |
| // is our coverage goals). The coverage goals also differ between 'default' |
| // and the 'cover_reg_top' (used by common tests) builds. We override the |
| // variables below to swap the coverage cfg files used for the Comportable |
| // IPs with chip-specific ones. See `doc/ug/dv_methodology.md` for more |
| // details. |
| |
| // Used by all chip level functional test. Collects coverage on the IO |
| // boundary of all pre-verified IPs and full coverage on non-pre-verified |
| // IPs. See `hw/dv/tools/dvsim/common_sim_cfg.hjson` for the default value. |
| { |
| name: default_vcs_cov_cfg_file |
| value: "-cm_hier {proj_root}/hw/top_earlgrey/dv/cov/chip_cover.cfg+{proj_root}/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg" |
| } |
| // Used by 'cover_reg_top' only builds - we only cover the *_reg_top of |
| // the non-pre-verified modules at the chip level. See |
| // `hw/dv/tools/dvsim/common_sim_cfg.hjson` for the default value. |
| { |
| name: cover_reg_top_vcs_cov_cfg_file |
| value: "-cm_hier {proj_root}/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg+{proj_root}/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg" |
| } |
| { |
| name: xbar_build_mode_vcs_cov_cfg_file |
| value: "-cm_hier {proj_root}/hw/top_earlgrey/dv/cov/chip_cover_reg_top.cfg+{proj_root}/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg" |
| } |
| // Used by the UNR flow. |
| { |
| name: vcs_unr_cfg_file |
| value: "{proj_root}/hw/top_earlgrey/dv/cov/unr.cfg" |
| } |
| |
| // This defaults to 'ip' in `hw/data/common_project_cfg.hjson`. |
| { |
| name: design_level |
| value: "top" |
| } |
| // The jtag agent requires the data and bytenable widths to be increased. |
| { |
| name: tl_dw |
| value: 64 |
| } |
| { |
| name: tl_dbw |
| value: 8 |
| } |
| ] |
| |
| // exclusion files |
| vcs_cov_excl_files: ["{proj_root}/hw/top_earlgrey/dv/cov/conn_ast_mem_cfg.el"] |
| |
| // Default iterations for all tests - each test entry can override this. |
| reseed: 3 |
| |
| // Uncomment if using manufacturer tests / test hooks that live somewhere else |
| // on your system, outside of $REPO_TOP. See |
| // sw/device/tests/closed_source/README.md for more details. |
| // exports: [ |
| // {MANUFACTURER_HOOKS_DIR: "/path/to/manufacturer_hooks_dir"} |
| // ] |
| |
| // Default UVM test and seq class name. |
| uvm_test: chip_base_test |
| uvm_test_seq: chip_sw_base_vseq |
| sw_build_device: sim_dv |
| |
| // Add a default build option to indicate it is a top-level DV testbench. |
| build_opts: ["+define+TOP_LEVEL_DV"] |
| |
| // Add build modes. |
| build_modes: [ |
| { |
| name: en_ibex_tracer |
| build_opts: ["+define+RVFI=1"] |
| } |
| // Sim mode that enables build randomization. See the `build_seed` mode |
| // defined in `hw/dv/tools/dvsim/common_modes.hjson` for more details. |
| { |
| name: build_seed |
| pre_build_cmds: [ |
| // TODO: find where in run phase we are using this pkg. It fails during ibex TLUL integrity |
| // check. |
| // '''cd {proj_root} && ./util/topgen.py -t {ral_spec} \ |
| // -o hw/top_earlgrey --rnd_cnst_seed {seed} |
| // ''', |
| "cd {proj_root} && ./util/design/gen-otp-mmap.py --seed {seed}", |
| // Use eval_cmd to save build_seed in a file and reuse that file during run phase. |
| // Create the build directory first because eval_cmd runs before actual build phase command |
| // execution. |
| '''{eval_cmd} mkdir -p {build_dir}; echo {seed} > {build_seed_file_path}; \ |
| echo "echo create file {build_seed_file_path}" |
| ''' |
| ] |
| is_sim_mode: 1 |
| } |
| // Sim mode that enables faster simulation for test development. |
| // DO NOT USE FOR NIGHTLY |
| { |
| name: fast_sim |
| build_opts: ["+define+DISABLE_ROM_INTEGRITY_CHECK"] |
| } |
| ] |
| |
| // Add options needed to compile against otbn_memutil, otbn_tracer, and |
| // memutil_dpi_scrambled. |
| en_build_modes: ["{tool}_otbn_memutil_build_opts", |
| "{tool}_otbn_tracer_build_opts", |
| "{tool}_memutil_dpi_scrambled_build_opts"] |
| |
| // Setup for generating OTP images. |
| gen_otp_images_cfg_dir: "{proj_root}/hw/ip/otp_ctrl/data" |
| gen_otp_images_cmd: "{proj_root}/util/design/gen-otp-img.py" |
| gen_otp_images_cmd_opts: ["--quiet", |
| "--img-seed {seed}", |
| // Only provide `--otp-seed` argument if the file to store build_seed |
| // is found. Set this option at the end of the list to avoid `eval_cmd` |
| // take other options as eval_cmd. |
| '''{eval_cmd} file=`echo {build_seed_file_path}`; \ |
| if [ -f $file ]; then \ |
| while read line; do \ |
| echo "--otp-seed $line"; \ |
| done < $file; \ |
| fi '''] |
| // Add run modes. |
| run_modes: [ |
| // Generates OTP images with different LC states with cannonical values, |
| // pseudo-randomized with the same test seed. |
| { |
| name: gen_otp_images_mode |
| pre_run_cmds: [ |
| '''{gen_otp_images_cmd} \ |
| --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_raw.hjson \ |
| --out {run_dir}/otp_ctrl_img_raw.vmem \ |
| {gen_otp_images_cmd_opts} |
| ''', |
| '''{gen_otp_images_cmd} \ |
| --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_dev.hjson \ |
| --out {run_dir}/otp_ctrl_img_dev.vmem \ |
| {gen_otp_images_cmd_opts} |
| ''', |
| '''{gen_otp_images_cmd} \ |
| --img-cfg {gen_otp_images_cfg_dir}/otp_ctrl_img_rma.hjson \ |
| --out {run_dir}/otp_ctrl_img_rma.vmem \ |
| {gen_otp_images_cmd_opts} |
| ''', |
| ] |
| } |
| { |
| name: sw_test_mode_common |
| run_opts: ["+sw_build_device={sw_build_device}", |
| // Format SW image names (which are Bazel labels concatenated with an index |
| // and/or flags, see below) into output file names separated by commas to feed into |
| // +sw_images plusarg. For example, if the input list of SW images is |
| // ["//sw/device/tests/sim_dv:uart_tx_rx_test:1", |
| // "//sw/device/lib/testing/test_rom:test_rom:0"], then the output of this eval_cmd |
| // will be: "uart_tx_rx_test:1,test_rom:0". |
| '''+sw_images={eval_cmd} \ |
| reformatted_sw_images=; \ |
| for image in {sw_images}; do \ |
| reformatted_sw_images="$reformatted_sw_images `echo $image | cut -d: -f2-`"; \ |
| done; \ |
| echo $reformatted_sw_images | sed -E 's/\s+/,/g' '''] |
| en_run_modes: ["gen_otp_images_mode"] |
| } |
| { |
| name: sw_test_mode_test_rom |
| sw_images: ["//sw/device/lib/testing/test_rom:test_rom:0"] |
| en_run_modes: ["sw_test_mode_common"] |
| } |
| { |
| name: sw_test_mode_rom |
| sw_images: ["//sw/device/silicon_creator/rom:rom:0"] |
| en_run_modes: ["sw_test_mode_common"] |
| } |
| { |
| name: stub_cpu_mode |
| en_run_modes: ["gen_otp_images_mode"] |
| run_opts: ["+stub_cpu=1"] |
| } |
| { |
| // Append stub cpu mode to csr_tests_mode, run with 20 reseeds. |
| name: csr_tests_mode |
| en_run_modes: ["stub_cpu_mode"] |
| } |
| { |
| // Append stub cpu mode to mem_tests_mode, run with 20 reseeds. |
| name: mem_tests_mode |
| en_run_modes: ["stub_cpu_mode"] |
| reseed: 20 |
| } |
| { |
| name: strap_tests_mode |
| en_run_modes: ["sw_test_mode_common"] |
| // The tests using this mode only require the ROM init check to succeed. |
| // The example_test_from_rom test is sufficient. |
| sw_images: ["//sw/device/tests:example_test_from_rom:0:test_in_rom"] |
| run_opts: ["+create_jtag_riscv_map=1"] |
| reseed: 5 |
| } |
| { |
| name: xbar_run_mode |
| en_run_modes: ["gen_otp_images_mode"] |
| run_opts: ["+xbar_mode=1"] |
| reseed: 100 |
| } |
| ] |
| |
| // List of test specifications. |
| // |
| // If you are adding a test that has been generated from a Bazel |
| // `opentitan_functest` macro, you can specify the test using its Bazel label |
| // followed by an index separated with a ':', which is used by the testbench |
| // to know what type of image is it: |
| // - 0 for Boot ROM, |
| // - 1 for SW test (loaded in flash), |
| // - 2 for OTBN test, |
| // This allows an arbitrary number of SW images to be supplied to the TB. |
| // |
| // For example, if the Bazel label for a test is: |
| // `//sw/device/tests:example_test_from_flash`, then you would specify this as |
| // `//sw/device/tests:example_test_from_flash:1`. |
| // |
| // To calculate the value of `+sw_test_timeout_ns` run dvsim by: |
| // $ util/dvsim/dvsim.py hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson \ |
| // -i TEST_NAME --fixed-seed=1 |
| // Run this a few times and take the worst case runtime, then increase this |
| // value by 20% and use the relationship that 5 minutes of runtime is roughly |
| // 4 milliseconds of timeout. |
| tests: [ |
| { |
| // Reused from hw/dv/tools/dvsim/tests/csr_tests.hjson. |
| name: "chip_csr_bit_bash" |
| // Don't test over 512 randomly picked CSRs at a time. |
| run_opts: ["+test_timeout_ns=120_000_000", "+num_test_csrs=400"] |
| run_timeout_mins: 120 |
| } |
| { |
| // Reused from hw/dv/tools/dvsim/tests/csr_tests.hjson. |
| name: "chip_csr_aliasing" |
| run_timeout_mins: 180 |
| } |
| { |
| name: chip_sw_example_flash |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:example_test_from_flash:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_example_rom |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:example_test_from_rom:0:test_in_rom"] |
| en_run_modes: ["sw_test_mode_common"] |
| } |
| { |
| name: chip_sw_example_manufacturer |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["@manufacturer_test_hooks//:example_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_clkmgr_escalation_reset |
| uvm_test_seq: chip_sw_clkmgr_escalation_reset_vseq |
| sw_images: ["//sw/device/tests/sim_dv:clkmgr_escalation_reset_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+bypass_alert_ready_to_end_check=1"] |
| } |
| { |
| name: chip_sw_all_escalation_resets |
| uvm_test_seq: chip_sw_all_escalation_resets_vseq |
| sw_images: ["//sw/device/tests/sim_dv:all_escalation_resets_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+bypass_alert_ready_to_end_check=1"] |
| reseed: 60 |
| } |
| { |
| name: chip_sw_sleep_pwm_pulses |
| uvm_test_seq: chip_sw_pwm_pulses_vseq |
| sw_images: ["//sw/device/tests:sleep_pwm_pulses_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_uart_tx_rx |
| uvm_test_seq: chip_sw_uart_tx_rx_vseq |
| sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+uart_idx=0", "+calibrate_usb_clk=1"] |
| reseed: 5 |
| } |
| { |
| name: chip_sw_uart_tx_rx_idx1 |
| uvm_test_seq: chip_sw_uart_tx_rx_vseq |
| sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+uart_idx=1", "+calibrate_usb_clk=1"] |
| reseed: 5 |
| } |
| { |
| name: chip_sw_uart_tx_rx_idx2 |
| uvm_test_seq: chip_sw_uart_tx_rx_vseq |
| sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+uart_idx=2", "+calibrate_usb_clk=1"] |
| reseed: 5 |
| } |
| { |
| name: chip_sw_uart_tx_rx_idx3 |
| uvm_test_seq: chip_sw_uart_tx_rx_vseq |
| sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+uart_idx=3", "+calibrate_usb_clk=1"] |
| reseed: 5 |
| } |
| { |
| name: chip_sw_uart_tx_rx_bootstrap |
| uvm_test_seq: chip_sw_uart_tx_rx_vseq |
| sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+use_spi_load_bootstrap=1", "+calibrate_usb_clk=1"] |
| } |
| { |
| name: chip_sw_uart_rand_baudrate |
| uvm_test_seq: chip_sw_uart_rand_baudrate_vseq |
| sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=80_000_000", "+calibrate_usb_clk=1"] |
| reseed: 20 |
| } |
| { |
| name: chip_sw_uart_tx_rx_alt_clk_freq |
| uvm_test_seq: chip_sw_uart_rand_baudrate_vseq |
| sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=80_000_000", |
| "+ext_clk_type=ExtClkHighSpeed", "+use_extclk=1", "+calibrate_usb_clk=1"] |
| reseed: 5 |
| } |
| { |
| name: chip_sw_uart_tx_rx_alt_clk_freq_low_speed |
| uvm_test_seq: chip_sw_uart_rand_baudrate_vseq |
| sw_images: ["//sw/device/tests/sim_dv:uart_tx_rx_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=80_000_000", "+calibrate_usb_clk=1", |
| "+ext_clk_type=ExtClkLowSpeed", "+use_extclk=1", "+extclk_low_speed_sel=1"] |
| reseed: 5 |
| } |
| { |
| name: chip_sw_spi_device_tx_rx |
| uvm_test_seq: chip_sw_spi_tx_rx_vseq |
| sw_images: ["//sw/device/tests/sim_dv:spi_tx_rx_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_gpio |
| uvm_test_seq: chip_sw_gpio_vseq |
| sw_images: ["//sw/device/tests/sim_dv:gpio_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_flash_ctrl_ops |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:flash_ctrl_ops_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=14_000_000"] |
| } |
| { |
| name: chip_sw_flash_ctrl_ops_jitter_en |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:flash_ctrl_ops_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=14_000_000", "+en_jitter=1"] |
| } |
| { |
| name: chip_sw_flash_ctrl_lc_rw_en |
| uvm_test_seq: chip_sw_flash_ctrl_lc_rw_en_vseq |
| sw_images: ["//sw/device/tests/sim_dv:flash_ctrl_lc_rw_en_test:1"] |
| run_opts: ["+bypass_alert_ready_to_end_check=1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_flash_ctrl_access |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:flash_ctrl_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_flash_ctrl_access_jitter_en |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:flash_ctrl_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+en_jitter=1"] |
| } |
| { |
| name: chip_sw_flash_ctrl_idle_low_power |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:flash_ctrl_idle_low_power_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_flash_init |
| uvm_test_seq: chip_sw_flash_init_vseq |
| sw_images: ["//sw/device/tests/sim_dv:flash_init_test:0:test_in_rom"] |
| en_run_modes: ["sw_test_mode_common"] |
| run_opts: ["+sw_test_timeout_ns=25_000_000"] |
| } |
| { |
| name: chip_sw_flash_rma_unlocked |
| uvm_test_seq: chip_sw_flash_rma_unlocked_vseq |
| sw_images: ["//sw/device/tests/sim_dv:flash_rma_unlocked_test:0:test_in_rom"] |
| en_run_modes: ["sw_test_mode_common"] |
| run_opts: ["+flash_program_latency=5", "+sw_test_timeout_ns=150_000_000"] |
| run_timeout_mins: 200 |
| } |
| { |
| name: chip_sw_flash_ctrl_clock_freqs |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:flash_ctrl_clock_freqs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_lc_ctrl_otp_hw_cfg |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:lc_ctrl_otp_hw_cfg_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| // Set higher reseed value to reach all kmac_data to lc_ctrl toggle coverage. |
| name: chip_sw_lc_ctrl_transition |
| uvm_test_seq: chip_sw_lc_ctrl_transition_vseq |
| sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_transition_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| reseed: 15 |
| } |
| { |
| name: chip_sw_lc_ctrl_kmac_reset |
| uvm_test_seq: chip_sw_lc_ctrl_kmac_reset_vseq |
| sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_kmac_reset_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_lc_walkthrough_dev |
| uvm_test_seq: chip_sw_lc_walkthrough_vseq |
| sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+flash_program_latency=5", |
| "+use_otp_image=LcStRaw", "+dest_dec_state=DecLcStDev", |
| // The test takes long time because it will transit to RMA state |
| "+sw_test_timeout_ns=200_000_000"] |
| run_timeout_mins: 240 |
| } |
| { |
| name: chip_sw_lc_walkthrough_prod |
| uvm_test_seq: chip_sw_lc_walkthrough_vseq |
| sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+flash_program_latency=5", |
| "+use_otp_image=LcStRaw", "+dest_dec_state=DecLcStProd", |
| // The test takes long time because it will transit to RMA state |
| "+sw_test_timeout_ns=200_000_000"] |
| run_timeout_mins: 240 |
| } |
| { |
| name: chip_sw_lc_walkthrough_prodend |
| uvm_test_seq: chip_sw_lc_walkthrough_vseq |
| sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+flash_program_latency=5", |
| "+use_otp_image=LcStRaw", "+dest_dec_state=DecLcStProdEnd"] |
| } |
| { |
| name: chip_sw_lc_walkthrough_rma |
| uvm_test_seq: chip_sw_lc_walkthrough_vseq |
| sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+use_otp_image=LcStRaw", "+dest_dec_state=DecLcStRma", |
| "+flash_program_latency=5", |
| // The test takes long time because it will transit to RMA state |
| "+sw_test_timeout_ns=200_000_000"] |
| run_timeout_mins: 240 |
| } |
| { |
| name: chip_sw_lc_walkthrough_testunlocks |
| uvm_test_seq: chip_sw_lc_walkthrough_testunlocks_vseq |
| sw_images: ["//sw/device/tests/sim_dv:lc_walkthrough_testunlocks_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+use_otp_image=LcStRaw", "+dest_dec_state=DecLcStTestUnlock7"] |
| } |
| { |
| name: chip_sw_rstmgr_sw_req |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:rstmgr_sw_req_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_rstmgr_sw_rst |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:rstmgr_sw_rst_ctrl_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_rstmgr_alert_info |
| uvm_test_seq: chip_sw_rstmgr_alert_info_vseq |
| sw_images: ["//sw/device/tests:rstmgr_alert_info_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000", "+en_scb_tl_err_chk=0"] |
| } |
| { |
| name: chip_sw_rstmgr_cpu_info |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:rstmgr_cpu_info_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_pwrmgr_full_aon_reset |
| uvm_test_seq: chip_sw_full_aon_reset_vseq |
| sw_images: ["//sw/device/tests:rstmgr_smoketest:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_pwrmgr_main_power_glitch_reset |
| uvm_test_seq: chip_sw_main_power_glitch_vseq |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_main_power_glitch_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+bypass_alert_ready_to_end_check=1"] |
| } |
| { |
| name: chip_sw_pwrmgr_sysrst_ctrl_reset |
| uvm_test_seq: chip_sw_sysrst_ctrl_vseq |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_sysrst_ctrl_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_pwrmgr_random_sleep_all_reset_reqs |
| uvm_test_seq: chip_sw_random_sleep_all_reset_vseq |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_random_sleep_all_reset_reqs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=50_000_000"] |
| run_timeout_mins: 120 |
| } |
| { |
| name: chip_sw_pwrmgr_deep_sleep_all_reset_reqs |
| uvm_test_seq: chip_sw_deep_sleep_all_reset_vseq |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_deep_sleep_all_reset_reqs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=50_000_000"] |
| run_timeout_mins: 120 |
| } |
| { |
| name: chip_sw_pwrmgr_normal_sleep_all_reset_reqs |
| uvm_test_seq: chip_sw_deep_sleep_all_reset_vseq |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_normal_sleep_all_reset_reqs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_timeout_mins: 120 |
| } |
| { |
| name: chip_sw_pwrmgr_sleep_power_glitch_reset |
| uvm_test_seq: chip_sw_main_power_glitch_vseq |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_sleep_power_glitch_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+bypass_alert_ready_to_end_check=1"] |
| } |
| { |
| name: chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
| uvm_test_seq: chip_sw_deep_power_glitch_vseq |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_deep_sleep_power_glitch_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+bypass_alert_ready_to_end_check=1"] |
| } |
| { |
| name: chip_sw_pwrmgr_sleep_disabled |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:pwrmgr_sleep_disabled_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_rv_timer_irq |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:rv_timer_smoketest:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_sysrst_ctrl_inputs |
| uvm_test_seq: chip_sw_sysrst_ctrl_inputs_vseq |
| sw_images: ["//sw/device/tests/sim_dv:sysrst_ctrl_inputs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_sysrst_ctrl_reset |
| uvm_test_seq: chip_sw_sysrst_ctrl_reset_vseq |
| sw_images: ["//sw/device/tests/sim_dv:sysrst_ctrl_reset_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=36_000_000"] |
| } |
| { |
| name: chip_sw_sysrst_ctrl_outputs |
| uvm_test_seq: chip_sw_sysrst_ctrl_outputs_vseq |
| sw_images: ["//sw/device/tests/sim_dv:sysrst_ctrl_outputs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_aon_timer_irq |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:aon_timer_irq_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_sw_aon_timer_sleep_wdog_sleep_pause |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:aon_timer_sleep_wdog_sleep_pause_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_sw_aon_timer_wdog_bite_reset |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:aon_timer_wdog_bite_reset_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_sw_pwrmgr_wdog_reset |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:pwrmgr_wdog_reset_reqs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_sw_aon_timer_wdog_lc_escalate |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:aon_timer_wdog_lc_escalate_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_sw_adc_ctrl_sleep_debug_cable_wakeup |
| uvm_test_seq: chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq |
| sw_images: ["//sw/device/tests/sim_dv:adc_ctrl_sleep_debug_cable_wakeup_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_sw_otbn_randomness |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:otbn_randomness_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000","+rng_srate_value=30"] |
| } |
| { |
| name: chip_sw_otbn_ecdsa_op_irq |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=28_000_000", "+rng_srate_value=30"] |
| run_timeout_mins: 300 |
| } |
| { |
| name: chip_sw_otbn_ecdsa_op_irq_jitter_en |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:otbn_ecdsa_op_irq_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=33_000_000", "+rng_srate_value=30", "+en_jitter=1"] |
| run_timeout_mins: 300 |
| } |
| { |
| name: chip_sw_otbn_mem_scramble |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:otbn_mem_scramble_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=15_000_000", "+en_scb_tl_err_chk=0", |
| "+bypass_alert_ready_to_end_check=1"] |
| } |
| { |
| name: chip_sw_rv_core_ibex_rnd |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["sw/device/tests:rv_core_ibex_rnd_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| // Timeout based on a 10min dvsim runtime. |
| run_opts: ["+sw_test_timeout_ns=10_000_000"] |
| } |
| { |
| name: chip_sw_rv_core_ibex_nmi_irq |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["sw/device/tests:rv_core_ibex_nmi_irq_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=10_000_000"] |
| } |
| { |
| name: chip_sw_aes_enc |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:aes_smoketest:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=22_000_000"] |
| } |
| { |
| name: chip_sw_aes_enc_jitter_en |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:aes_smoketest:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=26_000_000", "+en_jitter=1"] |
| } |
| { |
| name: chip_sw_aes_idle |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:aes_idle_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=25_000_000"] |
| } |
| { |
| name: chip_sw_aes_sideload |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:aes_sideload_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=35000000"] |
| } |
| { |
| name: chip_sw_alert_test |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests/autogen:alert_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_alert_handler_escalation |
| uvm_test_seq: chip_sw_alert_handler_escalation_vseq |
| sw_images: ["//sw/device/tests/sim_dv:alert_handler_escalation_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+en_scb=0", "+sw_test_timeout_ns=5000000", "+bypass_alert_ready_to_end_check=1"] |
| } |
| { |
| name: chip_sw_alert_handler_ping_timeout |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:alert_handler_ping_timeout_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+en_scb=0"] |
| } |
| { |
| name: chip_sw_alert_handler_entropy |
| uvm_test_seq: chip_sw_alert_handler_entropy_vseq |
| sw_images: ["//sw/device/tests/sim_dv:alert_handler_entropy_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| // Disable scoreboard to avoid incorrect alert prediction from the alert_monitor. Due to the |
| // cross-domain alert senders and receivers, the monitor from the chip level did not support |
| // processing alerts accurately from both ends. |
| run_opts: ["+en_scb=0", "+bypass_alert_ready_to_end_check=1"] |
| } |
| { |
| name: chip_sw_aes_entropy |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:aes_entropy_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=15_000_000"] |
| } |
| { |
| name: chip_sw_entropy_src_fuse_en_fw_read_test |
| uvm_test_seq: chip_sw_entropy_src_fuse_vseq |
| sw_images: ["//sw/device/tests/sim_dv:entropy_src_fuse_en_fw_read_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18000000"] |
| } |
| { |
| name: chip_sw_entropy_src_kat_test |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:entropy_src_kat_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_sw_csrng_kat_test |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:csrng_kat_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_sw_csrng_fuse_en_sw_app_read_test |
| uvm_test_seq: chip_sw_entropy_src_fuse_vseq |
| sw_images: ["//sw/device/tests/sim_dv:csrng_fuse_en_sw_app_read:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=15_000_000"] |
| } |
| { |
| name: chip_sw_entropy_src_ast_rng_req |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:entropy_src_ast_rng_req_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=15_000_000"] |
| } |
| { |
| name: chip_sw_edn_entropy_reqs |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:entropy_src_edn_reqs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=15000000", "+rng_srate_value_min=15", |
| "+rng_srate_value_max=30"] |
| } |
| { |
| name: chip_sw_hmac_enc |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:hmac_enc_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_hmac_enc_jitter_en |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:hmac_enc_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+en_jitter=1"] |
| } |
| { |
| name: chip_sw_hmac_enc_idle |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:hmac_enc_idle_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_keymgr_key_derivation |
| uvm_test_seq: chip_sw_keymgr_key_derivation_vseq |
| sw_images: ["//sw/device/tests/sim_dv:keymgr_key_derivation_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=20_000_000"] |
| } |
| { |
| name: chip_sw_keymgr_key_derivation_prod |
| uvm_test_seq: chip_sw_keymgr_key_derivation_vseq |
| sw_images: ["//sw/device/tests/sim_dv:keymgr_key_derivation_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+lc_at_prod=1", "+sw_test_timeout_ns=20_000_000"] |
| } |
| { |
| name: chip_sw_keymgr_key_derivation_jitter_en |
| uvm_test_seq: chip_sw_keymgr_key_derivation_vseq |
| sw_images: ["//sw/device/tests/sim_dv:keymgr_key_derivation_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=20_000_000", "+en_jitter=1"] |
| } |
| { |
| name: chip_sw_keymgr_sideload_kmac |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests/sim_dv:keymgr_sideload_kmac_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=20_000_000"] |
| } |
| { |
| name: chip_sw_keymgr_sideload_otbn |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests/sim_dv:keymgr_sideload_otbn_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=20_000_000"] |
| } |
| { |
| name: chip_sw_kmac_mode_cshake |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:kmac_mode_cshake_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_kmac_mode_kmac |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:kmac_mode_kmac_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_kmac_mode_kmac_jitter_en |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:kmac_mode_kmac_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+en_jitter=1"] |
| } |
| { |
| name: chip_sw_kmac_app_rom |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:kmac_app_rom_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_kmac_idle |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:kmac_idle_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_rom_ctrl_integrity_check |
| uvm_test_seq: chip_sw_rom_ctrl_integrity_check_vseq |
| sw_images: ["//sw/device/tests/sim_dv:rom_ctrl_integrity_check_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_sram_ctrl_ret_scrambled_access |
| uvm_test_seq: chip_sw_sram_ctrl_scrambled_access_vseq |
| sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_ret_scrambled_access_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+mem_sel=ret"] |
| } |
| { |
| name: chip_sw_sram_ctrl_main_scrambled_access |
| uvm_test_seq: chip_sw_sram_ctrl_scrambled_access_vseq |
| sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_main_scrambled_access_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+mem_sel=main", |
| "+sw_test_timeout_ns=12_000_000", "+en_scb_tl_err_chk=0"] |
| } |
| { |
| name: chip_sw_sram_ctrl_main_scrambled_access_jitter_en |
| uvm_test_seq: chip_sw_sram_ctrl_scrambled_access_vseq |
| sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_main_scrambled_access_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+mem_sel=main", |
| "+sw_test_timeout_ns=12_000_000", |
| "+en_jitter=1", "+en_scb_tl_err_chk=0"] |
| } |
| { |
| name: chip_sw_sram_ctrl_execution_main |
| uvm_test_seq: chip_sw_sram_ctrl_execution_main_vseq |
| sw_images: ["//sw/device/tests/sim_dv:sram_ctrl_execution_test_main:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_sleep_sram_ret_contents |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:sram_ctrl_sleep_sram_ret_contents_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=20_000_000"] |
| } |
| { |
| name: chip_sw_sensor_ctrl_alert |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:sensor_ctrl_alert_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=40_000_000"] |
| } |
| { |
| name: chip_sw_sensor_ctrl_status |
| uvm_test_seq: chip_sw_sensor_ctrl_status_intr_vseq |
| sw_images: ["//sw/device/tests/sim_dv:sensor_ctrl_status_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=40_000_000"] |
| } |
| { |
| name: chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:sensor_ctrl_wakeup_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=8_000_000"] |
| } |
| { |
| name: chip_sw_coremark |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/benchmarks/coremark/coremark_top_earlgrey:1:external"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+en_uart_logger=1", |
| "+sw_test_timeout_ns=22_000_000"] |
| } |
| { |
| name: chip_sw_pwrmgr_b2b_sleep_reset_req |
| uvm_test_seq: chip_sw_repeat_reset_wkup_vseq |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_b2b_sleep_reset_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=35_000_000"] |
| } |
| // The test below is from tl_access_tests.hjson, but we don't need to include tl_intg_err, |
| // which is also in tl_access_tests.hjson, as TLUL integrity is generated by design and we |
| // include this block in the data path when we stub CPU to verify TL access |
| // So copy chip_tl_errors here and append the stub_cpu_mode run mode. |
| { |
| name: chip_tl_errors |
| build_mode: "cover_reg_top" |
| uvm_test_seq: "{name}_common_vseq" |
| run_opts: ["+run_tl_errors"] |
| en_run_modes: ["stub_cpu_mode"] |
| reseed: 20 |
| } |
| { |
| name: chip_prim_tl_access |
| build_mode: "cover_reg_top" |
| uvm_test_seq: "chip_prim_tl_access_vseq" |
| en_run_modes: ["stub_cpu_mode"] |
| run_opts: ["+en_scb=0", "+en_scb_tl_err_chk=0"] |
| } |
| { |
| name: chip_plic_all_irqs |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests/autogen:plic_all_irqs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_plic_sw_irq |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:plic_sw_irq_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_clkmgr_off_peri |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:clkmgr_off_peri_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=30_000_000"] |
| } |
| { |
| name: chip_sw_clkmgr_off_aes_trans |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:clkmgr_off_aes_trans_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_clkmgr_off_hmac_trans |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:clkmgr_off_hmac_trans_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_clkmgr_off_kmac_trans |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:clkmgr_off_kmac_trans_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_clkmgr_off_otbn_trans |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:clkmgr_off_otbn_trans_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_clkmgr_external_clk_src_for_lc |
| uvm_test_seq: chip_sw_lc_ctrl_transition_vseq |
| sw_images: ["//sw/device/tests/sim_dv:clkmgr_external_clk_src_for_lc_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+ext_clk_type=ExtClkLowSpeed", "+calibrate_usb_clk=1"] |
| } |
| { |
| name: chip_sw_clkmgr_external_clk_src_for_sw_fast |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:clkmgr_external_clk_src_for_sw_fast_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+ext_clk_type=ExtClkHighSpeed", "+calibrate_usb_clk=1"] |
| } |
| { |
| name: chip_sw_clkmgr_external_clk_src_for_sw_slow |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:clkmgr_external_clk_src_for_sw_slow_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+ext_clk_type=ExtClkLowSpeed", "+calibrate_usb_clk=1"] |
| } |
| { |
| name: chip_sw_clkmgr_reset_frequency |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["sw/device/tests:clkmgr_reset_frequency_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+calibrate_usb_clk=1"] |
| } |
| { |
| name: chip_sw_clkmgr_jitter |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["//sw/device/tests:clkmgr_jitter_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| } |
| { |
| name: chip_sw_clkmgr_sleep_frequency |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["sw/device/tests:clkmgr_sleep_frequency_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+calibrate_usb_clk=1"] |
| } |
| { |
| name: chip_jtag_csr_rw |
| uvm_test_seq: "chip_jtag_csr_rw_vseq" |
| en_run_modes: ["stub_cpu_mode"] |
| run_opts: ["+en_scb=0", "+csr_rw", "+create_jtag_riscv_map=1"] |
| } |
| { |
| name: chip_jtag_mem_access |
| uvm_test_seq: "chip_jtag_mem_vseq" |
| en_run_modes: ["stub_cpu_mode"] |
| run_opts: ["+create_jtag_riscv_map=1"] |
| } |
| { |
| name: chip_sw_ast_clk_outputs |
| uvm_test_seq: chip_sw_ast_clk_outputs_vseq |
| sw_images: ["//sw/device/tests:ast_clk_outs_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+calibrate_usb_clk=1"] |
| } |
| { |
| name: chip_sw_lc_ctrl_program_error |
| uvm_test_seq: chip_sw_lc_ctrl_program_error_vseq |
| sw_images: ["sw/device/tests/sim_dv:lc_ctrl_program_error:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+en_scb=0", "+bypass_alert_ready_to_end_check=1"] |
| } |
| { |
| name: chip_sw_pwrmgr_normal_sleep_all_wake_ups |
| uvm_test_seq: "chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq" |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_normal_sleep_all_wake_ups:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_sw_pwrmgr_deep_sleep_all_wake_ups |
| uvm_test_seq: "chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq" |
| sw_images: ["//sw/device/tests/sim_dv:pwrmgr_deep_sleep_all_wake_ups:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+sw_test_timeout_ns=18_000_000"] |
| } |
| { |
| name: chip_rv_dm_ndm_reset_req |
| uvm_test_seq: "chip_rv_dm_ndm_reset_vseq" |
| sw_images: ["//sw/device/tests/sim_dv:rv_dm_ndm_reset_req:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+en_scb_tl_err_chk=0", "+use_jtag_dmi=1"] |
| } |
| { |
| name: chip_tap_straps_dev |
| uvm_test_seq: chip_tap_straps_vseq |
| en_run_modes: ["strap_tests_mode"] |
| run_opts: ["+use_otp_image=LcStDev"] |
| run_timeout_mins: 120 |
| } |
| { |
| name: chip_tap_straps_rma |
| uvm_test_seq: chip_tap_straps_vseq |
| en_run_modes: ["strap_tests_mode"] |
| run_timeout_mins: 120 |
| } |
| { |
| name: chip_tap_straps_prod |
| uvm_test_seq: chip_tap_straps_vseq |
| en_run_modes: ["strap_tests_mode"] |
| run_opts: ["+lc_at_prod=1"] |
| run_timeout_mins: 120 |
| } |
| { |
| name: chip_sw_rv_core_ibex_address_translation |
| uvm_test_seq: chip_sw_base_vseq |
| sw_images: ["sw/device/tests:rv_core_ibex_address_translation_test:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| // Timeout based on a ~7 minute dvsim runtime. |
| run_opts: ["+sw_test_timeout_ns=7_000_000"] |
| } |
| { |
| name: chip_sw_usb_ast_clk_calib |
| uvm_test_seq: "chip_sw_usb_ast_clk_calib_vseq" |
| sw_images: ["//sw/device/tests/sim_dv:ast_usb_clk_calib:1"] |
| en_run_modes: ["sw_test_mode_test_rom"] |
| run_opts: ["+usb_max_drift=1", "+usb_fast_sof=1"] |
| reseed: 1 |
| } |
| ] |
| |
| // List of regressions. |
| regressions: [ |
| { |
| name: smoke |
| tests: ["xbar_chip_smoke", |
| "chip_sw_uart_tx_rx", |
| "chip_plic_all_irqs", |
| "chip_sw_example_flash", |
| "chip_sw_example_rom", |
| "chip_sw_example_manufacturer"] |
| // TODO: add this test after enabling HW verification: "rom_e2e_bootup_success"] |
| } |
| { |
| name: jitter |
| tests: ["chip_sw_clkmgr_jitter", |
| "chip_sw_flash_ctrl_ops_jitter_en", |
| "chip_sw_flash_ctrl_access_jitter_en", |
| "chip_sw_otbn_ecdsa_op_irq_jitter_en", |
| "chip_sw_aes_enc_jitter_en", |
| "chip_sw_hmac_enc_jitter_en", |
| "chip_sw_keymgr_key_derivation_jitter_en", |
| "chip_sw_kmac_mode_kmac_jitter_en", |
| "chip_sw_sram_ctrl_main_scrambled_access_jitter_en" |
| ] |
| } |
| { |
| name: xcelium_ci |
| tests: ["chip_plic_all_irqs"] |
| reseed: 1 |
| } |
| ] |
| } |
