[otbn] Fix read/write enables in tracer

* `insn_valid` must be factored in with the read enable for the bignum
  register file as it uses the raw decoder signal.
* `rf_base_wr_commit` must be combined with the write enable for the
  base register file to determine if the write occurred.

Signed-off-by: Greg Chadwick <gac@lowrisc.org>

hw/ip/otbn/dv/tracer/rtl/otbn_trace_if.sv

diff --git a/hw/ip/otbn/dv/tracer/rtl/otbn_trace_if.sv b/hw/ip/otbn/dv/tracer/rtl/otbn_trace_if.sv
index 7887c2c..ba5ed44 100644
--- a/hw/ip/otbn/dv/tracer/rtl/otbn_trace_if.sv
+++ b/hw/ip/otbn/dv/tracer/rtl/otbn_trace_if.sv
@@ -40,6 +40,7 @@
   input logic rf_base_rd_en_a,
   input logic rf_base_rd_en_b,
   input logic rf_base_wr_en,
+  input logic rf_base_wr_commit,
 
   input logic [31:0] rf_base_rd_data_a,
   input logic [31:0] rf_base_rd_data_b,
@@ -74,13 +75,27 @@
 
   localparam int DmemSubWordAddrWidth = prim_util_pkg::vbits(WLEN/8);
 
+  // `insn_stall` isn't a signal that exists in the design so needs creating here. To keep things
+  // consistent `insn_X` signals are provided here that are simply assigned to `otbn_core` signals.
+  // To prevent the tracer needing to deal with differing Imem sizes the address is padded out to
+  // 32-bits.
+  logic        insn_valid;
+  logic [31:0] insn_addr;
+  logic [31:0] insn_data;
+  logic        insn_stall;
+
+  assign insn_valid = insn_fetch_resp_valid;
+  assign insn_addr  = {{(32-ImemAddrWidth){1'b0}}, insn_fetch_resp_addr};
+  assign insn_data  = insn_fetch_resp_data;
+  assign insn_stall = u_otbn_core.u_otbn_controller.state_d == OtbnStateStall;
+
   logic rf_ren_a_bignum;
   logic rf_ren_b_bignum;
 
   // Read enables for bignum are only inside the decoder with the current design, so bring them out
   // here for access by the tracer.
-  assign rf_ren_a_bignum = u_otbn_decoder.rf_ren_a_bignum;
-  assign rf_ren_b_bignum = u_otbn_decoder.rf_ren_b_bignum;
+  assign rf_ren_a_bignum = u_otbn_decoder.rf_ren_a_bignum & insn_valid;
+  assign rf_ren_b_bignum = u_otbn_decoder.rf_ren_b_bignum & insn_valid;
 
   // The bignum register file is capable of half register writes. To avoid the tracer having to deal
   // with this, slightly modified rf_bignum_wr_en and rf_bignum_wr_data signals are provided here.
@@ -106,20 +121,6 @@
       rf_bignum_wr_old_data[(WLEN/2)*i +: WLEN/2];
   end
 
-  // `insn_stall` isn't a signal that exists in the design so needs creating here. To keep things
-  // consistent `insn_X` signals are provided here that are simply assigned to `otbn_core` signals.
-  // To prevent the tracer needing to deal with differing Imem sizes the address is padded out to
-  // 32-bits.
-  logic        insn_valid;
-  logic [31:0] insn_addr;
-  logic [31:0] insn_data;
-  logic        insn_stall;
-
-  assign insn_valid = insn_fetch_resp_valid;
-  assign insn_addr  = {{(32-ImemAddrWidth){1'b0}}, insn_fetch_resp_addr};
-  assign insn_data  = insn_fetch_resp_data;
-  assign insn_stall = u_otbn_core.u_otbn_controller.state_d == OtbnStateStall;
-
   // Take Dmem interface and present it as two seperate read and write sets of signals. To ease
   // tracer implementation a small tracker tracks reads so the whole transaction (address + data
   // together) is presented in a single cycle.

hw/ip/otbn/dv/tracer/rtl/otbn_tracer.sv

diff --git a/hw/ip/otbn/dv/tracer/rtl/otbn_tracer.sv b/hw/ip/otbn/dv/tracer/rtl/otbn_tracer.sv
index a148ce6..094dbaf 100644
--- a/hw/ip/otbn/dv/tracer/rtl/otbn_tracer.sv
+++ b/hw/ip/otbn/dv/tracer/rtl/otbn_tracer.sv
@@ -114,7 +114,8 @@
                                             otbn_trace.rf_base_rd_data_b));
     end
 
-    if (otbn_trace.rf_base_wr_en && otbn_trace.rf_base_wr_addr != 0) begin
+    if (otbn_trace.rf_base_wr_en && otbn_trace.rf_base_wr_commit &&
+        otbn_trace.rf_base_wr_addr != '0) begin
       output_trace(RegWritePrefix, $sformatf("x%02d: 0x%08x", otbn_trace.rf_base_wr_addr,
                                              otbn_trace.rf_base_wr_data));
     end