[fpga] Correct port type for clock and reset, add proper buffers
This commit changes the port type of the clock and reset from `inout` to
`input`. In addition, a proper input buffer is added for the reset and
the input buffer for the clock is switched from IBUF to IBUFG as
recommend by Xilinx (clock capable input buffer).
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/top_earlgrey/rtl/clkgen_xil7series.sv b/hw/top_earlgrey/rtl/clkgen_xil7series.sv
index 905968d..2822a62 100644
--- a/hw/top_earlgrey/rtl/clkgen_xil7series.sv
+++ b/hw/top_earlgrey/rtl/clkgen_xil7series.sv
@@ -8,12 +8,14 @@
) (
input IO_CLK,
input IO_RST_N,
+ input jtag_srst_n,
output clk_main,
output clk_48MHz,
output rst_n
);
logic locked_pll;
logic io_clk_buf;
+ logic io_rst_buf_n;
logic clk_10_buf;
logic clk_10_unbuf;
logic clk_fb_buf;
@@ -21,12 +23,18 @@
logic clk_48_buf;
logic clk_48_unbuf;
- // input buffer
- IBUF io_clk_ibuf (
+ // input clock buffer
+ IBUFG io_clk_ibufg (
.I (IO_CLK),
.O (io_clk_buf)
);
+ // input reset buffer
+ IBUF io_rst_ibuf (
+ .I (IO_RST_N),
+ .O (io_rst_buf_n)
+ );
+
PLLE2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
@@ -97,5 +105,5 @@
assign clk_48MHz = clk_48_buf;
// reset
- assign rst_n = locked_pll & IO_RST_N;
+ assign rst_n = locked_pll & io_rst_buf_n & jtag_srst_n;
endmodule
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
index 2f579ab..962d9f1 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_artys7.sv
@@ -8,8 +8,8 @@
parameter BootRomInitFile = "boot_rom_fpga_artys7.32.vmem"
) (
// Clock and Reset
- inout IO_CLK,
- inout IO_RST_N,
+ input IO_CLK,
+ input IO_RST_N,
// JTAG interface -- not hooked up at the moment
// inout IO_DPS0, // IO_JTCK, IO_SDCK
// inout IO_DPS3, // IO_JTMS, IO_SDCSB
@@ -157,6 +157,7 @@
) clkgen (
.IO_CLK,
.IO_RST_N,
+ .jtag_srst_n,
.clk_main(clk_main),
.clk_48MHz(clk_usb_48mhz),
.rst_n(rst_n)
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
index 2d98040..c3c4ebc 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
@@ -8,8 +8,8 @@
parameter BootRomInitFile = "boot_rom_fpga_nexysvideo.32.vmem"
) (
// Clock and Reset
- inout IO_CLK,
- inout IO_RST_N,
+ input IO_CLK,
+ input IO_RST_N,
// JTAG interface
inout IO_DPS0, // IO_JTCK, IO_SDCK
inout IO_DPS3, // IO_JTMS, IO_SDCSB
@@ -199,7 +199,8 @@
.AddClkBuf(0)
) clkgen (
.IO_CLK,
- .IO_RST_N(IO_RST_N & jtag_srst_n),
+ .IO_RST_N,
+ .jtag_srst_n,
.clk_main(clk_main),
.clk_48MHz(clk_usb_48mhz),
.rst_n(rst_n)
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
index 78c282c..5f1a022 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -8,8 +8,8 @@
parameter BootRomInitFile = "boot_rom_fpga_nexysvideo.32.vmem"
) (
// Clock and Reset
- inout IO_CLK,
- inout IO_RST_N,
+ input IO_CLK,
+ input IO_RST_N,
// JTAG interface
inout IO_DPS0, // IO_JTCK, IO_SDCK
inout IO_DPS3, // IO_JTMS, IO_SDCSB
@@ -195,7 +195,8 @@
.AddClkBuf(0)
) clkgen (
.IO_CLK,
- .IO_RST_N(IO_RST_N & jtag_srst_n),
+ .IO_RST_N,
+ .jtag_srst_n,
.clk_main(clk_main),
.clk_48MHz(clk_usb_48mhz),
.rst_n(rst_n)
