| commit | 7169f9567e765ce267323c95ef7de33f0b1c52e4 | [log] [tgz] |
|---|---|---|
| author | Pirmin Vogel <vogelpi@lowrisc.org> | Fri Oct 02 10:43:07 2020 +0200 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Mon Oct 05 10:56:24 2020 +0200 |
| tree | 16d1fefcb6d73c454fb62665b0c4cf3ddc8fc870 | |
| parent | 8520647a7e1df72c97c22a20450030bcbf099aa3 [diff] |
[fpga] Correct port type for clock and reset, add proper buffers This commit changes the port type of the clock and reset from `inout` to `input`. In addition, a proper input buffer is added for the reset and the input buffer for the clock is switched from IBUF to IBUFG as recommend by Xilinx (clock capable input buffer). Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
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