[alert_handler] Add full list of countermeasures in prep for D2S

Signed-off-by: Michael Schaffner <msf@opentitan.org>

hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl

diff --git a/hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl b/hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl
index 5f63549..7cb163f 100644
--- a/hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl
+++ b/hw/ip_templates/alert_handler/data/alert_handler.hjson.tpl
@@ -227,7 +227,53 @@
     { name: "BUS.INTEGRITY",
       desc: "End-to-end bus integrity scheme."
     }
+    { name: "CONFIG.SHADOW",
+      desc: "Important CSRs are shadowed."
+    }
+    { name: "ALERT.INTERSIG.DIFF",
+      desc: "Differentially encoded alert channels."
+    }
+    { name: "LPG.INTERSIG.MUBI",
+      desc: "LPG signals are encoded with MUBI types."
+    }
+    { name: "ESC.INTERSIG.DIFF",
+      desc: "Differentially encoded escalation channels."
+    }
+    { name: "ALERT_RX.INTERSIG.BKGN_CHK",
+      desc: "Periodic background checks on alert channels (ping mechanism)."
+    }
+    { name: "ESC_TX.INTERSIG.BKGN_CHK",
+      desc: "Periodic background checks on escalation channels (ping mechanism)."
+    }
+    { name: "ESC_RX.INTERSIG.BKGN_CHK",
+      desc: "Escalation receivers can detect absence of periodic ping requests."
+    }
+    { name: "ESC_TIMER.FSM.SPARSE",
+      desc: "Escalation timer FSMs are sparsely encoded."
+    }
+    { name: "PING_TIMER.FSM.SPARSE",
+      desc: "Ping timer FSM is sparsely encoded."
+    }
+    { name: "ESC_TIMER.FSM.LOCAL_ESC",
+      desc: "Escalation timer FSMs move into an invalid state upon local escalation."
+    }
+    { name: "PING_TIMER.FSM.LOCAL_ESC",
+      desc: "Ping timer FSM moves into an invalid state upon local escalation."
+    }
+    { name: "ACCU.CTR.REDUN",
+      desc: "Accumulator counters are redundant."
+    }
+    { name: "ESC_TIMER.CTR.REDUN",
+      desc: "Escalation timer counters are redundant."
+    }
+    { name: "PING_TIMER.CTR.REDUN",
+      desc: "Ping timer counters are redundant."
+    }
+    { name: "PING_TIMER.LFSR.REDUN",
+      desc: "Ping timer LFSR is redundant."
+    }
   ]
+
 ##############################################################################
 # interrupt registers for the classes
   interrupt_list: [

hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson

diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
index 309d2c4..f02f31e 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
@@ -327,7 +327,53 @@
     { name: "BUS.INTEGRITY",
       desc: "End-to-end bus integrity scheme."
     }
+    { name: "CONFIG.SHADOW",
+      desc: "Important CSRs are shadowed."
+    }
+    { name: "ALERT.INTERSIG.DIFF",
+      desc: "Differentially encoded alert channels."
+    }
+    { name: "LPG.INTERSIG.MUBI",
+      desc: "LPG signals are encoded with MUBI types."
+    }
+    { name: "ESC.INTERSIG.DIFF",
+      desc: "Differentially encoded escalation channels."
+    }
+    { name: "ALERT_RX.INTERSIG.BKGN_CHK",
+      desc: "Periodic background checks on alert channels (ping mechanism)."
+    }
+    { name: "ESC_TX.INTERSIG.BKGN_CHK",
+      desc: "Periodic background checks on escalation channels (ping mechanism)."
+    }
+    { name: "ESC_RX.INTERSIG.BKGN_CHK",
+      desc: "Escalation receivers can detect absence of periodic ping requests."
+    }
+    { name: "ESC_TIMER.FSM.SPARSE",
+      desc: "Escalation timer FSMs are sparsely encoded."
+    }
+    { name: "PING_TIMER.FSM.SPARSE",
+      desc: "Ping timer FSM is sparsely encoded."
+    }
+    { name: "ESC_TIMER.FSM.LOCAL_ESC",
+      desc: "Escalation timer FSMs move into an invalid state upon local escalation."
+    }
+    { name: "PING_TIMER.FSM.LOCAL_ESC",
+      desc: "Ping timer FSM moves into an invalid state upon local escalation."
+    }
+    { name: "ACCU.CTR.REDUN",
+      desc: "Accumulator counters are redundant."
+    }
+    { name: "ESC_TIMER.CTR.REDUN",
+      desc: "Escalation timer counters are redundant."
+    }
+    { name: "PING_TIMER.CTR.REDUN",
+      desc: "Ping timer counters are redundant."
+    }
+    { name: "PING_TIMER.LFSR.REDUN",
+      desc: "Ping timer LFSR is redundant."
+    }
   ]
+
 # interrupt registers for the classes
   interrupt_list: [
     { name: "classa",