[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/aes/rtl/aes_reg_top.sv b/hw/ip/aes/rtl/aes_reg_top.sv
index 105dc3d..e9bc512 100644
--- a/hw/ip/aes/rtl/aes_reg_top.sv
+++ b/hw/ip/aes/rtl/aes_reg_top.sv
@@ -17,6 +17,9 @@
output aes_reg_pkg::aes_reg2hw_t reg2hw, // Write
input aes_reg_pkg::aes_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv b/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv
index 3440bb6..6af994e 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_reg_top.sv
@@ -17,6 +17,9 @@
output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write
input alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv b/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
index d6a69b4..291968b 100644
--- a/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
+++ b/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
@@ -17,6 +17,9 @@
output aon_timer_reg_pkg::aon_timer_reg2hw_t reg2hw, // Write
input aon_timer_reg_pkg::aon_timer_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv b/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv
index 0a7a808..24aa924 100644
--- a/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv
+++ b/hw/ip/clkmgr/rtl/clkmgr_reg_top.sv
@@ -17,6 +17,9 @@
output clkmgr_reg_pkg::clkmgr_reg2hw_t reg2hw, // Write
input clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/csrng/rtl/csrng_reg_top.sv b/hw/ip/csrng/rtl/csrng_reg_top.sv
index 6c7be33..b3e29d8 100644
--- a/hw/ip/csrng/rtl/csrng_reg_top.sv
+++ b/hw/ip/csrng/rtl/csrng_reg_top.sv
@@ -17,6 +17,9 @@
output csrng_reg_pkg::csrng_reg2hw_t reg2hw, // Write
input csrng_reg_pkg::csrng_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/edn/rtl/edn_reg_top.sv b/hw/ip/edn/rtl/edn_reg_top.sv
index 5abd4b6..0fef80b 100644
--- a/hw/ip/edn/rtl/edn_reg_top.sv
+++ b/hw/ip/edn/rtl/edn_reg_top.sv
@@ -17,6 +17,9 @@
output edn_reg_pkg::edn_reg2hw_t reg2hw, // Write
input edn_reg_pkg::edn_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
index 1b5fabe..021fa74 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
@@ -17,6 +17,9 @@
output entropy_src_reg_pkg::entropy_src_reg2hw_t reg2hw, // Write
input entropy_src_reg_pkg::entropy_src_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index fffad7d..30bc0e3 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -90,6 +90,7 @@
.reg2hw,
.hw2reg,
+ .intg_err_o (),
.devmode_i (1'b1)
);
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
index cdc8494..1721ee4 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
@@ -22,6 +22,9 @@
output flash_ctrl_reg_pkg::flash_ctrl_reg2hw_t reg2hw, // Write
input flash_ctrl_reg_pkg::flash_ctrl_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -49,15 +52,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -113,7 +127,7 @@
if (tl_i.a_address[AW-1:0] >= 384 && tl_i.a_address[AW-1:0] < 468) begin
reg_steer = 2;
end
- if (chk_err) begin
+ if (intg_err) begin
reg_steer = 3;
end
end
@@ -138,7 +152,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/gpio/rtl/gpio_reg_top.sv b/hw/ip/gpio/rtl/gpio_reg_top.sv
index 6b2132e..aa7fc90 100644
--- a/hw/ip/gpio/rtl/gpio_reg_top.sv
+++ b/hw/ip/gpio/rtl/gpio_reg_top.sv
@@ -17,6 +17,9 @@
output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write
input gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/hmac/rtl/hmac_reg_top.sv b/hw/ip/hmac/rtl/hmac_reg_top.sv
index 59a4c61..90c9227 100644
--- a/hw/ip/hmac/rtl/hmac_reg_top.sv
+++ b/hw/ip/hmac/rtl/hmac_reg_top.sv
@@ -22,6 +22,9 @@
output hmac_reg_pkg::hmac_reg2hw_t reg2hw, // Write
input hmac_reg_pkg::hmac_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -49,15 +52,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -104,7 +118,7 @@
// Exceed or meet the address range. Removed the comparison of limit addr 'h 1000
reg_steer = 0;
end
- if (chk_err) begin
+ if (intg_err) begin
reg_steer = 1;
end
end
@@ -129,7 +143,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/i2c/rtl/i2c_reg_top.sv b/hw/ip/i2c/rtl/i2c_reg_top.sv
index 0e93571..9df5f51 100644
--- a/hw/ip/i2c/rtl/i2c_reg_top.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_top.sv
@@ -17,6 +17,9 @@
output i2c_reg_pkg::i2c_reg2hw_t reg2hw, // Write
input i2c_reg_pkg::i2c_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/keymgr/rtl/keymgr_reg_top.sv b/hw/ip/keymgr/rtl/keymgr_reg_top.sv
index 32dd3af..39ecc16 100644
--- a/hw/ip/keymgr/rtl/keymgr_reg_top.sv
+++ b/hw/ip/keymgr/rtl/keymgr_reg_top.sv
@@ -17,6 +17,9 @@
output keymgr_reg_pkg::keymgr_reg2hw_t reg2hw, // Write
input keymgr_reg_pkg::keymgr_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/kmac/rtl/kmac_reg_top.sv b/hw/ip/kmac/rtl/kmac_reg_top.sv
index 07ada7b..a0a46b6 100644
--- a/hw/ip/kmac/rtl/kmac_reg_top.sv
+++ b/hw/ip/kmac/rtl/kmac_reg_top.sv
@@ -22,6 +22,9 @@
output kmac_reg_pkg::kmac_reg2hw_t reg2hw, // Write
input kmac_reg_pkg::kmac_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -49,15 +52,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -109,7 +123,7 @@
// Exceed or meet the address range. Removed the comparison of limit addr 'h 1000
reg_steer = 1;
end
- if (chk_err) begin
+ if (intg_err) begin
reg_steer = 2;
end
end
@@ -134,7 +148,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv
index 5213464..ffc5ca8 100644
--- a/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv
+++ b/hw/ip/lc_ctrl/rtl/lc_ctrl_reg_top.sv
@@ -17,6 +17,9 @@
output lc_ctrl_reg_pkg::lc_ctrl_reg2hw_t reg2hw, // Write
input lc_ctrl_reg_pkg::lc_ctrl_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/nmi_gen/rtl/nmi_gen_reg_top.sv b/hw/ip/nmi_gen/rtl/nmi_gen_reg_top.sv
index ce2ff7e..fbfe218 100644
--- a/hw/ip/nmi_gen/rtl/nmi_gen_reg_top.sv
+++ b/hw/ip/nmi_gen/rtl/nmi_gen_reg_top.sv
@@ -17,6 +17,9 @@
output nmi_gen_reg_pkg::nmi_gen_reg2hw_t reg2hw, // Write
input nmi_gen_reg_pkg::nmi_gen_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/otbn/rtl/otbn_reg_top.sv b/hw/ip/otbn/rtl/otbn_reg_top.sv
index 75aed01..0323486 100644
--- a/hw/ip/otbn/rtl/otbn_reg_top.sv
+++ b/hw/ip/otbn/rtl/otbn_reg_top.sv
@@ -22,6 +22,9 @@
output otbn_reg_pkg::otbn_reg2hw_t reg2hw, // Write
input otbn_reg_pkg::otbn_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -49,15 +52,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -108,7 +122,7 @@
if (tl_i.a_address[AW-1:0] >= 32768 && tl_i.a_address[AW-1:0] < 36864) begin
reg_steer = 1;
end
- if (chk_err) begin
+ if (intg_err) begin
reg_steer = 2;
end
end
@@ -133,7 +147,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
index e0b6cfd..c6fe56a 100644
--- a/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
+++ b/hw/ip/otp_ctrl/rtl/otp_ctrl_reg_top.sv
@@ -22,6 +22,9 @@
output otp_ctrl_reg_pkg::otp_ctrl_reg2hw_t reg2hw, // Write
input otp_ctrl_reg_pkg::otp_ctrl_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -49,15 +52,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -108,7 +122,7 @@
if (tl_i.a_address[AW-1:0] >= 8192 && tl_i.a_address[AW-1:0] < 8256) begin
reg_steer = 1;
end
- if (chk_err) begin
+ if (intg_err) begin
reg_steer = 2;
end
end
@@ -133,7 +147,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/pattgen/rtl/pattgen_reg_top.sv b/hw/ip/pattgen/rtl/pattgen_reg_top.sv
index 854a38c..029d946 100644
--- a/hw/ip/pattgen/rtl/pattgen_reg_top.sv
+++ b/hw/ip/pattgen/rtl/pattgen_reg_top.sv
@@ -17,6 +17,9 @@
output pattgen_reg_pkg::pattgen_reg2hw_t reg2hw, // Write
input pattgen_reg_pkg::pattgen_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/pinmux/rtl/pinmux_reg_top.sv b/hw/ip/pinmux/rtl/pinmux_reg_top.sv
index 76a55de..7a30d6c 100644
--- a/hw/ip/pinmux/rtl/pinmux_reg_top.sv
+++ b/hw/ip/pinmux/rtl/pinmux_reg_top.sv
@@ -17,6 +17,9 @@
output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write
input pinmux_reg_pkg::pinmux_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv b/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv
index 81eaffb..d30e73f 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv
@@ -17,6 +17,9 @@
output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write
input pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv b/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv
index cbcfab1..2ad0e84 100644
--- a/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv
+++ b/hw/ip/rstmgr/rtl/rstmgr_reg_top.sv
@@ -17,6 +17,9 @@
output rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw, // Write
input rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
index c4df42a..ef4be0a 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_reg_top.sv
@@ -17,6 +17,9 @@
output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write
input rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv b/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
index c9a3845..4a76ba7 100644
--- a/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
+++ b/hw/ip/rv_timer/rtl/rv_timer_reg_top.sv
@@ -17,6 +17,9 @@
output rv_timer_reg_pkg::rv_timer_reg2hw_t reg2hw, // Write
input rv_timer_reg_pkg::rv_timer_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_top.sv b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
index 649b117..2758c15 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_top.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
@@ -22,6 +22,9 @@
output spi_device_reg_pkg::spi_device_reg2hw_t reg2hw, // Write
input spi_device_reg_pkg::spi_device_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -49,15 +52,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -104,7 +118,7 @@
// Exceed or meet the address range. Removed the comparison of limit addr 'h 2000
reg_steer = 0;
end
- if (chk_err) begin
+ if (intg_err) begin
reg_steer = 1;
end
end
@@ -129,7 +143,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/spi_host/rtl/spi_host_reg_top.sv b/hw/ip/spi_host/rtl/spi_host_reg_top.sv
index ca700ba..960ee32 100644
--- a/hw/ip/spi_host/rtl/spi_host_reg_top.sv
+++ b/hw/ip/spi_host/rtl/spi_host_reg_top.sv
@@ -22,6 +22,9 @@
output spi_host_reg_pkg::spi_host_reg2hw_t reg2hw, // Write
input spi_host_reg_pkg::spi_host_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -49,15 +52,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -103,7 +117,7 @@
if (tl_i.a_address[AW-1:0] >= 28 && tl_i.a_address[AW-1:0] < 32) begin
reg_steer = 0;
end
- if (chk_err) begin
+ if (intg_err) begin
reg_steer = 1;
end
end
@@ -128,7 +142,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_top.sv b/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_top.sv
index 6576a3d..fd2cae0 100644
--- a/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_top.sv
+++ b/hw/ip/sram_ctrl/rtl/sram_ctrl_reg_top.sv
@@ -17,6 +17,9 @@
output sram_ctrl_reg_pkg::sram_ctrl_reg2hw_t reg2hw, // Write
input sram_ctrl_reg_pkg::sram_ctrl_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/trial1/rtl/trial1_reg_top.sv b/hw/ip/trial1/rtl/trial1_reg_top.sv
index c11182b..54d02eb 100644
--- a/hw/ip/trial1/rtl/trial1_reg_top.sv
+++ b/hw/ip/trial1/rtl/trial1_reg_top.sv
@@ -17,6 +17,9 @@
output trial1_reg_pkg::trial1_reg2hw_t reg2hw, // Write
input trial1_reg_pkg::trial1_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/uart/rtl/uart_reg_top.sv b/hw/ip/uart/rtl/uart_reg_top.sv
index 9b70d4a..128fb33 100644
--- a/hw/ip/uart/rtl/uart_reg_top.sv
+++ b/hw/ip/uart/rtl/uart_reg_top.sv
@@ -17,6 +17,9 @@
output uart_reg_pkg::uart_reg2hw_t reg2hw, // Write
input uart_reg_pkg::uart_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/usbdev/rtl/usbdev_reg_top.sv b/hw/ip/usbdev/rtl/usbdev_reg_top.sv
index 201b467..b752c6d 100644
--- a/hw/ip/usbdev/rtl/usbdev_reg_top.sv
+++ b/hw/ip/usbdev/rtl/usbdev_reg_top.sv
@@ -22,6 +22,9 @@
output usbdev_reg_pkg::usbdev_reg2hw_t reg2hw, // Write
input usbdev_reg_pkg::usbdev_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -49,15 +52,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -104,7 +118,7 @@
// Exceed or meet the address range. Removed the comparison of limit addr 'h 1000
reg_steer = 0;
end
- if (chk_err) begin
+ if (intg_err) begin
reg_steer = 1;
end
end
@@ -129,7 +143,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/ip/usbuart/rtl/usbuart_reg_top.sv b/hw/ip/usbuart/rtl/usbuart_reg_top.sv
index 59081d9..66de953 100644
--- a/hw/ip/usbuart/rtl/usbuart_reg_top.sv
+++ b/hw/ip/usbuart/rtl/usbuart_reg_top.sv
@@ -17,6 +17,9 @@
output usbuart_reg_pkg::usbuart_reg2hw_t reg2hw, // Write
input usbuart_reg_pkg::usbuart_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index fb7f2e6..a730c07 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -17,6 +17,9 @@
output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write
input alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv b/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
index 6e28915..fa0d29d 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_reg_top.sv
@@ -47,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -83,8 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
-
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index 540e888..4f98a06 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -76,6 +76,7 @@
.tl_o,
.reg2hw,
.hw2reg,
+ .intg_err_o(),
.devmode_i(1'b1)
);
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
index 1ad0576..11bc0fe 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_reg_top.sv
@@ -17,6 +17,9 @@
output clkmgr_reg_pkg::clkmgr_reg2hw_t reg2hw, // Write
input clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index 3180d53..1764e98 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -96,6 +96,7 @@
.reg2hw,
.hw2reg,
+ .intg_err_o (),
.devmode_i (1'b1)
);
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
index cdc8494..1721ee4 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
@@ -22,6 +22,9 @@
output flash_ctrl_reg_pkg::flash_ctrl_reg2hw_t reg2hw, // Write
input flash_ctrl_reg_pkg::flash_ctrl_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -49,15 +52,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -113,7 +127,7 @@
if (tl_i.a_address[AW-1:0] >= 384 && tl_i.a_address[AW-1:0] < 468) begin
reg_steer = 2;
end
- if (chk_err) begin
+ if (intg_err) begin
reg_steer = 3;
end
end
@@ -138,7 +152,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
index 7146bb2..6f3b368 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -17,6 +17,9 @@
output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write
input pinmux_reg_pkg::pinmux_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv
index 51e1060..76afb70 100644
--- a/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv
+++ b/hw/top_earlgrey/ip/pwrmgr/rtl/autogen/pwrmgr_reg_top.sv
@@ -17,6 +17,9 @@
output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write
input pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
index 6b0771b..629d336 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -113,6 +113,7 @@
.tl_o,
.reg2hw,
.hw2reg,
+ .intg_err_o(),
.devmode_i(1'b1)
);
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
index dc8cf10..407c03d 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
@@ -17,6 +17,9 @@
output rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw, // Write
input rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
index 5298394..0d15c40 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
@@ -363,6 +363,7 @@
.reg2hw,
.hw2reg,
+ .intg_err_o (),
.devmode_i (1'b1)
);
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
index 64eac70..0c29fc7 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
@@ -17,6 +17,9 @@
output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write
input rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
index 5fe64cb..bfb4bf2 100644
--- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
+++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
@@ -17,6 +17,9 @@
output sensor_ctrl_reg_pkg::sensor_ctrl_reg2hw_t reg2hw, // Write
input sensor_ctrl_reg_pkg::sensor_ctrl_hw2reg_t hw2reg, // Read
+ // Integrity check errors
+ output logic intg_err_o,
+
// Config
input devmode_i // If 1, explicit error return for unmapped register access
);
@@ -44,15 +47,26 @@
tlul_pkg::tl_d2h_t tl_reg_d2h;
// incoming payload check
- logic chk_err;
- tlul_payload_chk u_chk (
+ logic intg_err;
+ tlul_cmd_intg_chk u_chk (
.tl_i,
- .err_o(chk_err)
+ // connect this to intg_err later when all DV / hosts are hooked up
+ .err_o()
);
+ assign intg_err = 1'b0;
- // outgoing payload generation
+ // Once integrity error is detected, it does not let go until reset.
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intg_err_o <= '0;
+ end else if (intg_err) begin
+ intg_err_o <= 1'b1;
+ end
+ end
+
+ // outgoing integrity generation
tlul_pkg::tl_d2h_t tl_o_pre;
- tlul_gen_payload_chk u_gen_chk (
+ tlul_rsp_intg_gen u_rsp_intg_gen (
.tl_i(tl_o_pre),
.tl_o
);
@@ -80,7 +94,7 @@
);
assign reg_rdata = reg_rdata_next ;
- assign reg_error = (devmode_i & addrmiss) | wr_err | chk_err;
+ assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
