[flash_ctrl] Add tlul configuration interface to prim_flash Signed-off-by: Timothy Chen <timothytim@google.com> [flash_ctrl / prim] connect fake 'tlul configuration' bus Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl index 5023911..e36577b 100644 --- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl +++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson.tpl
@@ -876,6 +876,7 @@ ''' }, }, + { window: { name: "rd_fifo", items: "1", @@ -890,5 +891,20 @@ ''' }, }, + + { window: { + name: "prim_flash_cfg", + items: "21", + validbits: "32", + byte-write: "true", + unusual: "false" + swaccess: "rw", + desc: ''' + Configuration window for prim_flash. + + This window contains proprietary registers that is not exposed in open-source. + ''' + }, + }, ] }
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl index 56c684d..be116cc 100644 --- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl +++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
@@ -59,9 +59,10 @@ flash_ctrl_reg2hw_t reg2hw; flash_ctrl_hw2reg_t hw2reg; - tlul_pkg::tl_h2d_t tl_fifo_h2d [2]; - tlul_pkg::tl_d2h_t tl_fifo_d2h [2]; + tlul_pkg::tl_h2d_t tl_win_h2d [3]; + tlul_pkg::tl_d2h_t tl_win_d2h [3]; + assign tl_win_d2h[2] = flash_i.tl_flash_p2c; // Register module flash_ctrl_reg_top u_reg ( .clk_i, @@ -70,8 +71,8 @@ .tl_i, .tl_o, - .tl_win_o (tl_fifo_h2d), - .tl_win_i (tl_fifo_d2h), + .tl_win_o (tl_win_h2d), + .tl_win_i (tl_win_d2h), .reg2hw, .hw2reg, @@ -421,8 +422,8 @@ ) u_to_prog_fifo ( .clk_i, .rst_ni, - .tl_i (tl_fifo_h2d[0]), - .tl_o (tl_fifo_d2h[0]), + .tl_i (tl_win_h2d[0]), + .tl_o (tl_win_d2h[0]), .req_o (sw_wvalid), .gnt_i (sw_wready), .we_o (sw_wen), @@ -502,8 +503,8 @@ ) u_to_rd_fifo ( .clk_i, .rst_ni, - .tl_i (tl_fifo_h2d[1]), - .tl_o (tl_fifo_d2h[1]), + .tl_i (tl_win_h2d[1]), + .tl_o (tl_win_d2h[1]), .req_o (rd_fifo_ren), .gnt_i (rd_fifo_rvalid), .we_o (), @@ -754,6 +755,7 @@ assign flash_o.region_cfgs = region_cfgs; assign flash_o.addr_key = addr_key; assign flash_o.data_key = data_key; + assign flash_o.tl_flash_c2p = tl_win_h2d[2]; assign flash_rd_err = flash_i.rd_err; assign flash_rd_data = flash_i.rd_data; assign flash_phy_busy = flash_i.init_busy;
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl_pkg.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl_pkg.sv.tpl index edf6b30..0a6c69e 100644 --- a/hw/ip/flash_ctrl/data/flash_ctrl_pkg.sv.tpl +++ b/hw/ip/flash_ctrl/data/flash_ctrl_pkg.sv.tpl
@@ -298,6 +298,7 @@ logic [KeyWidth-1:0] addr_key; logic [KeyWidth-1:0] data_key; logic rd_buf_en; + tlul_pkg::tl_h2d_t tl_flash_c2p; } flash_req_t; // default value of flash_req_t (for dangling ports) @@ -320,7 +321,8 @@ region_cfgs: '0, addr_key: RndCnstAddrKeyDefault, data_key: RndCnstDataKeyDefault, - rd_buf_en: 1'b0 + rd_buf_en: 1'b0, + tl_flash_c2p: '0 }; // memory to flash controller @@ -333,6 +335,7 @@ logic [BusWidth-1:0] rd_data; logic init_busy; logic erase_suspend_done; + tlul_pkg::tl_d2h_t tl_flash_p2c; } flash_rsp_t; // default value of flash_rsp_t (for dangling ports) @@ -344,7 +347,8 @@ rd_err: '0, rd_data: '0, init_busy: 1'b0, - erase_suspend_done: 1'b1 + erase_suspend_done: 1'b1, + tl_flash_p2c: '0 }; // RMA entries
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv index 935be6c..8ab878e 100644 --- a/hw/ip/flash_ctrl/rtl/flash_phy.sv +++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv
@@ -243,11 +243,11 @@ ) u_flash ( .clk_i, .rst_ni, + .tl_i(flash_ctrl_i.tl_flash_c2p), + .tl_o(flash_ctrl_o.tl_flash_p2c), .flash_req_i(prim_flash_req), .flash_rsp_o(prim_flash_rsp), .prog_type_avail_o(prog_type_avail), - // initialize whenever power is ready - .init_i(1'b1), .init_busy_o(init_busy), .tck_i(tck_i & (lc_dft_en[FlashLcTckSel] == lc_ctrl_pkg::On)), .tdi_i(tdi_i & (lc_dft_en[FlashLcTdiSel] == lc_ctrl_pkg::On)),
diff --git a/hw/ip/prim/prim_secded.core b/hw/ip/prim/prim_secded.core index 73aeda7..abcad6c 100644 --- a/hw/ip/prim/prim_secded.core +++ b/hw/ip/prim/prim_secded.core
@@ -14,6 +14,8 @@ - rtl/prim_secded_28_22_enc.sv - rtl/prim_secded_39_32_dec.sv - rtl/prim_secded_39_32_enc.sv + - rtl/prim_secded_72_64_dec.sv + - rtl/prim_secded_72_64_enc.sv - rtl/prim_secded_hamming_72_64_dec.sv - rtl/prim_secded_hamming_72_64_enc.sv file_type: systemVerilogSource
diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/prim_generic/prim_generic_flash.core index b37299f..5dbbeab 100644 --- a/hw/ip/prim_generic/prim_generic_flash.core +++ b/hw/ip/prim_generic/prim_generic_flash.core
@@ -8,6 +8,7 @@ filesets: files_rtl: depend: + - lowrisc:ip:tlul - lowrisc:prim:ram_1p - lowrisc:ip:flash_ctrl_pkg files:
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash.sv b/hw/ip/prim_generic/rtl/prim_generic_flash.sv index ee5c65c..d626f5a 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flash.sv +++ b/hw/ip/prim_generic/rtl/prim_generic_flash.sv
@@ -18,10 +18,11 @@ ) ( input clk_i, input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, input flash_phy_pkg::flash_phy_prim_flash_req_t [NumBanks-1:0] flash_req_i, output flash_phy_pkg::flash_phy_prim_flash_rsp_t [NumBanks-1:0] flash_rsp_o, output logic [flash_phy_pkg::ProgTypes-1:0] prog_type_avail_o, - input init_i, output init_busy_o, input tck_i, input tdi_i, @@ -35,6 +36,13 @@ input flash_test_voltage_h_i ); + localparam int CfgRegs = 21; + localparam int CfgAddrWidth = $clog2(CfgRegs); + + // convert this into a tlul write later + logic init; + assign init = 1'b1; + logic [NumBanks-1:0] init_busy; assign init_busy_o = |init_busy; @@ -73,7 +81,7 @@ .ack_o(flash_rsp_o[bank].ack), .done_o(flash_rsp_o[bank].done), .rd_data_o(flash_rsp_o[bank].rdata), - .init_i, + .init_i(init), .init_busy_o(init_busy[bank]), .erase_suspend_done_o(flash_rsp_o[bank].erase_suspend_done), .flash_power_ready_h_i, @@ -98,4 +106,55 @@ assign unused_tms = tms_i; assign tdo_o = '0; + // fake memory used to emulate configuration + logic cfg_req; + logic cfg_we; + logic [CfgAddrWidth-1:0] cfg_addr; + logic [31:0] cfg_wdata; + logic cfg_rvalid; + logic [31:0] cfg_rdata; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cfg_rvalid <= 1'b0; + end else begin + cfg_rvalid <= cfg_req & !cfg_we; + end + end + + tlul_adapter_sram #( + .SramAw(CfgAddrWidth), + .SramDw(32), + .Outstanding(2), + .ErrOnWrite(1) + ) u_cfg ( + .clk_i, + .rst_ni, + .tl_i, + .tl_o, + .req_o(cfg_req), + .gnt_i(1'b1), + .we_o(cfg_we), + .addr_o(cfg_addr), + .wdata_o(cfg_wdata), + .wmask_o(), + .rdata_i(cfg_rdata), + .rvalid_i(cfg_rvalid), + .rerror_i('0) + ); + + prim_ram_1p #( + .Width(32), + .Depth(CfgRegs) + ) u_cfg_ram ( + .clk_i, + .req_i(cfg_req), + .write_i(cfg_we), + .addr_i(cfg_addr), + .wdata_i(cfg_wdata), + .wmask_i({32{1'b1}}), + .rdata_o(cfg_rdata) + ); + + endmodule // prim_generic_flash