| commit | 6c9375fa5c9c7fea7b00c304d068897c2456610d | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Mon May 02 11:24:59 2022 -0700 |
| committer | Eli Kim <github@elikim.dev> | Mon May 02 14:30:51 2022 -0700 |
| tree | 00bcc81693541bda7a6015d5be619f4c4d84c090 | |
| parent | 0fce98b7ef3c5c182431803697f798ae875b5290 [diff] |
[spi_device] Define a buffer address width Previous design defined `threshold` as `[BufferAw:0]`. It is syntatically correct but confuses contextually. It reduces readability. In this commit, `SramBufferAw` is defined. It is the required bit width of a Read Buffer size in bytes rather than the entries in DPSRAM. This commit does not alter the width of the threshold. It stays 10 bits as a Read Buffer size is 1kB. Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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