hw/top_earlgrey/dv/chip_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: chip

  // Top level dut name (sv module).
  dut: top_earlgrey

  // Top level testbench name (sv module).
  tb: tb

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:chip_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/top_earlgrey/data/chip_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/top_earlgrey/data/top_earlgrey.hjson"

  // Add additional tops for simulation.
  sim_tops: ["-top xbar_main_bind",
             "-top xbar_peri_bind"]

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/data/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/data/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/data/tests/mem_tests.hjson",
                "{proj_root}/hw/dv/data/tests/tl_access_tests.hjson"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 1

  // Default UVM test and seq class name.
  uvm_test: chip_base_test
  uvm_test_seq: chip_base_vseq

  // Additional option to RAL generation for top level.
  gen_ral_pkg_opts: ["--top"]

  // Add run modes.
  run_modes: [
    {
      name: stub_cpu
      run_opts: ["+stub_cpu=1"]
    }

    {
      // Append stub cpu mode to csr_tests_mode
      name: csr_tests_mode
      en_run_modes: ["stub_cpu"]
    }

    {
      // Append stub cpu mode to mem_tests_mode
      name: mem_tests_mode
      en_run_modes: ["stub_cpu"]
    }
  ]

  // List of test specifications.
  tests: [
    {
      name: chip_sanity
      uvm_test_seq: chip_sanity_vseq
    }
  ]
}