[dv/hmac] hmac wr_ptr needs to wait when fifo full

When fifo is full, hmac needs to wait until d_valid is asserted.
Add more display for debugging
Wait 1ps before checking fifo full
hmac fifo updates to depth 17

hw/ip/hmac/dv/env/hmac_env_pkg.sv

diff --git a/hw/ip/hmac/dv/env/hmac_env_pkg.sv b/hw/ip/hmac/dv/env/hmac_env_pkg.sv
index b4c1cdb..327880d 100644
--- a/hw/ip/hmac/dv/env/hmac_env_pkg.sv
+++ b/hw/ip/hmac/dv/env/hmac_env_pkg.sv
@@ -21,7 +21,7 @@
   // local parameters and types
   // csr and mem total size for IP
   parameter uint   HMAC_ADDR_MAP_SIZE        = 4096;
-  parameter uint32 HMAC_MSG_FIFO_DEPTH       = 16;
+  parameter uint32 HMAC_MSG_FIFO_DEPTH       = 17;
   parameter uint32 HMAC_MSG_FIFO_DEPTH_BYTES = HMAC_MSG_FIFO_DEPTH * 4;
   parameter uint32 HMAC_MSG_FIFO_SIZE        = 2048;
   parameter uint32 HMAC_MSG_FIFO_BASE        = 32'h800;

hw/ip/hmac/dv/env/hmac_scoreboard.sv

diff --git a/hw/ip/hmac/dv/env/hmac_scoreboard.sv b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
index df30f57..1ed6054 100644
--- a/hw/ip/hmac/dv/env/hmac_scoreboard.sv
+++ b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
@@ -11,6 +11,7 @@
   bit               sha_en;
   bit [7:0]         msg_q[$];
   bit               hmac_start, hmac_process;
+  bit               fifo_full;
   int               hmac_wr_cnt;
   int               hmac_rd_cnt;
 
@@ -199,15 +200,26 @@
 
   virtual task incr_wr_and_check_fifo_full();
     if (sha_en) begin
+      // if fifo full, tlul will not write next data until d_valid is asserted
+      if (fifo_full) begin
+        wait (cfg.tlul_assert_vif.d2h.d_valid == 1);
+        fifo_full = 0;
+      end
       @(negedge cfg.clk_rst_vif.clk);
       hmac_wr_cnt++;
+      `uvm_info(`gfn, $sformatf("increase wr cnt %0d", hmac_wr_cnt), UVM_HIGH)
     end
   endtask
 
   virtual task hmac_process_fifo_full();
     forever @(hmac_wr_cnt, hmac_rd_cnt) begin
+      // when hmac_wr_cnt and hmac_rd_cnt update at the same time, wait 1ps to guarantee
+      // get both update
+      #1ps;
       if ((hmac_wr_cnt - hmac_rd_cnt) == HMAC_MSG_FIFO_DEPTH) begin
         void'(ral.intr_state.fifo_full.predict(1));
+        `uvm_info(`gfn, "predict interrupt fifo full is set", UVM_HIGH)
+        fifo_full = 1;
       end
     end
   endtask
@@ -258,6 +270,7 @@
               #1; // delay 1 ns to make sure did not sample right at negedge clk
               cfg.clk_rst_vif.wait_n_clks(1);
               hmac_rd_cnt++;
+              `uvm_info(`gfn, $sformatf("increase rd cnt %0d", hmac_rd_cnt), UVM_HIGH)
               if (hmac_rd_cnt % 16 == 0) cfg.clk_rst_vif.wait_n_clks(HMAC_MSG_PROCESS_CYCLES);
             end
             begin : reset_hmac_fifo_rd