[rv_dm] Make the RV_DM a comportable module

This makes the RV_DM a comportable IP module.
To this end, an Hjson description is created, leveraging the recently
added topgen feature that allows for multiple TL-UL interfaces per
comportable IP.

This patch also modifies some of the interface signals to be compatible
with the intersignal mechanism in topgen, and it adds the alert
integrity alerts.

Signed-off-by: Michael Schaffner <msf@opentitan.org>

hw/top_earlgrey/data/top_earlgrey.hjson

diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index e7bfe6a..97692a4 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -246,17 +246,6 @@
         },
       ],
     }
-    { name: "rv_dm",
-      type: "rv_dm",
-      inter_signal_list: [
-        { struct:  "jtag",
-          type:    "req_rsp",
-          name:    "jtag",
-          act:     "rsp",
-          package: "jtag_pkg",
-        },
-      ]
-    }
   ]
 
   // `module` defines the peripherals.
@@ -545,6 +534,14 @@
       base_addrs: {core: "0x41000000", prim: "0x41008000"}
       attr: "templated",
     },
+    { name: "rv_dm",
+      type: "rv_dm",
+      clock_srcs: {clk_i: "main"},
+      clock_group: "infra",
+      reset_connections: {rst_ni: "lc"},
+      // Note that this module also contains a bus host.
+      base_addrs: {rom: "0x00010000", regs: "0x41200000"}
+    },
     { name: "rv_plic",
       type: "rv_plic",
       clock_srcs: {clk_i: "main"},
@@ -976,7 +973,8 @@
       'lc_ctrl.lc_hw_debug_en'     : ['sram_ctrl_main.lc_hw_debug_en',
                                       'sram_ctrl_ret_aon.lc_hw_debug_en',
                                       'pinmux_aon.lc_hw_debug_en',
-                                      'csrng.lc_hw_debug_en'],
+                                      'csrng.lc_hw_debug_en',
+                                      'rv_dm.lc_hw_debug_en'],
       'lc_ctrl.lc_cpu_en'          : ['rv_core_ibex.lc_cpu_en'],
       'lc_ctrl.lc_keymgr_en'       : ['keymgr.lc_keymgr_en'],
       'lc_ctrl.lc_escalate_en'     : ['aes.lc_escalate_en',
@@ -999,6 +997,7 @@
       'lc_ctrl.lc_seed_hw_rd_en'           : ['otp_ctrl.lc_seed_hw_rd_en',
                                               'flash_ctrl.lc_seed_hw_rd_en'],
 
+
       // rv core ibex peripheral connections
       'rv_core_ibex.fatal_intg_event' : ['rv_core_ibex_peri.fatal_intg_event'],
       'rv_core_ibex.fatal_core_event' : ['rv_core_ibex_peri.fatal_core_event'],
@@ -1008,17 +1007,24 @@
 
       // spi passthrough connection
       'spi_device.passthrough'     : ['spi_host0.passthrough']
+
+      // Debug module reset request to reset manager
+      'rv_dm.ndmreset_req' : ['rstmgr_aon.ndmreset_req']
     }
 
     // top is to connect to top net/struct.
     // It defines the signal in the top and connect from the module,
     // use of the signal is up to top template
     'top': [
-        'rstmgr_aon.resets', 'rstmgr_aon.cpu', 'pwrmgr_aon.pwr_cpu', 'clkmgr_aon.clocks',
-        'pwrmgr_aon.fetch_en',
+        'rstmgr_aon.resets', 'rstmgr_aon.rst_cpu_n',
+        'pwrmgr_aon.pwr_cpu', 'pwrmgr_aon.fetch_en',
+        'clkmgr_aon.clocks',
+
+        // Debug request from debug module to CPU
+        'rv_dm.debug_req',
 
         // Xbars
-        'main.tl_corei', 'main.tl_cored', 'main.tl_dm_sba', 'main.tl_debug_mem',
+        'main.tl_corei', 'main.tl_cored',
 
         // Pinmux JTAG signals for the tool-inserted DFT TAP
         'pinmux_aon.dft_jtag',
@@ -1073,8 +1079,6 @@
     },
   },
 
-  debug_mem_base_addr: "0x1A110000",
-
   // Crossbars: having a top level crossbar
   // This version assumes all crossbars are instantiated at the top.
   // Assume xbar.hjson is located in the same directory of top.hjson