[rv_dm] Make the RV_DM a comportable module This makes the RV_DM a comportable IP module. To this end, an Hjson description is created, leveraging the recently added topgen feature that allows for multiple TL-UL interfaces per comportable IP. This patch also modifies some of the interface signals to be compatible with the intersignal mechanism in topgen, and it adds the alert integrity alerts. Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/Makefile b/hw/Makefile index 91a1474..452c819 100644 --- a/hw/Makefile +++ b/hw/Makefile
@@ -34,6 +34,7 @@ rom_ctrl \ rstmgr \ rv_core_ibex_peri \ + rv_dm \ rv_plic \ rv_timer \ sensor_ctrl \
diff --git a/hw/ip/rstmgr/data/rstmgr.hjson.tpl b/hw/ip/rstmgr/data/rstmgr.hjson.tpl index e9cdbde..b3dc5ab 100644 --- a/hw/ip/rstmgr/data/rstmgr.hjson.tpl +++ b/hw/ip/rstmgr/data/rstmgr.hjson.tpl
@@ -76,11 +76,15 @@ package: "rstmgr_pkg", // Origin package (only needs for the req) }, - { struct: "rstmgr_cpu", + { struct: "logic", type: "uni", - name: "cpu", + name: "rst_cpu_n", act: "rcv", - package: "rstmgr_pkg", // Origin package (only needs for the req) + }, + { struct: "logic", + type: "uni", + name: "ndmreset_req", + act: "rcv", }, { struct: "alert_crashdump",
diff --git a/hw/ip/rstmgr/data/rstmgr.sv.tpl b/hw/ip/rstmgr/data/rstmgr.sv.tpl index 7bd8baa..4c347c5 100644 --- a/hw/ip/rstmgr/data/rstmgr.sv.tpl +++ b/hw/ip/rstmgr/data/rstmgr.sv.tpl
@@ -33,7 +33,8 @@ output pwrmgr_pkg::pwr_rst_rsp_t pwr_o, // cpu related inputs - input rstmgr_cpu_t cpu_i, + input logic rst_cpu_n_i, + input logic ndmreset_req_i, // Interface to alert handler input alert_pkg::alert_crashdump_t alert_dump_i, @@ -150,7 +151,7 @@ ) u_sync ( .clk_i, .rst_ni(local_rst_n), - .d_i(cpu_i.ndmreset_req), + .d_i(ndmreset_req_i), .q_o(ndmreset_req_q) ); @@ -312,7 +313,7 @@ ) u_cpu_reset_synced ( .clk_i, .rst_ni(local_rst_n), - .d_i(cpu_i.rst_cpu_n), + .d_i(rst_cpu_n_i), .q_o(rst_cpu_nq) );
diff --git a/hw/ip/rstmgr/rtl/rstmgr_pkg.sv b/hw/ip/rstmgr/rtl/rstmgr_pkg.sv index 8e4cc4c..430a187 100644 --- a/hw/ip/rstmgr/rtl/rstmgr_pkg.sv +++ b/hw/ip/rstmgr/rtl/rstmgr_pkg.sv
@@ -49,12 +49,6 @@ logic [PowerDomains-1:0] rst_usb_n; } rstmgr_out_t; - // cpu reset requests and status - typedef struct packed { - logic rst_cpu_n; - logic ndmreset_req; - } rstmgr_cpu_t; - // exported resets typedef struct packed { logic [PowerDomains-1:0] rst_ast_usbdev_sys_io_div4_n;
diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv index 527396e..4e1a207 100644 --- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv +++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -38,6 +38,8 @@ // Clock domain for escalation receiver input logic clk_esc_i, input logic rst_esc_ni, + // Reset feedback to rstmgr + output logic rst_cpu_n_o, input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i, @@ -160,6 +162,9 @@ assign fatal_core_event_o = alert_major ? EventOn : EventOff; assign recov_core_event_o = alert_minor ? EventOn : EventOff; + // Reset feedback to clkmgr + assign rst_cpu_n_o = rst_ni; + // Escalation receiver that converts differential // protocol into single ended signal. logic esc_irq_nm;
diff --git a/hw/ip/rv_dm/data/rv_dm.hjson b/hw/ip/rv_dm/data/rv_dm.hjson new file mode 100644 index 0000000..a11f5d9 --- /dev/null +++ b/hw/ip/rv_dm/data/rv_dm.hjson
@@ -0,0 +1,91 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "rv_dm", + clocking: [ + {clock: "clk_i", reset: "rst_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "host", name: "sba" } + { protocol: "tlul", direction: "device", name: "regs" } + { protocol: "tlul", direction: "device", name: "rom" } + ], + scan: "true", // Enable `scanmode_i` port + scan_reset: "true", // Enable `scan_rst_ni` port + param_list: [ + { name: "NrHarts", + type: "int", + default: "1", + desc: "Number of hardware threads in the system." + local: "true" + }, + { name: "IdcodeValue", + type: "logic [31:0]", + default: "32'h 0000_0001", + desc: "RISC-V debug module JTAG ID code." + local: "false", + expose: "true" + }, + ] + interrupt_list: [ + ], + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + inter_signal_list: [ + { struct: "jtag", + type: "req_rsp", + name: "jtag", + act: "rsp", + package: "jtag_pkg", + }, + { struct: "lc_tx" + type: "uni" + name: "lc_hw_debug_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + }, + // TBD: should we connect this to the clock manager? + { struct: "logic" + type: "uni" + name: "unavailable" + act: "rcv" + default: "1'b0" + }, + { struct: "logic" + type: "uni" + name: "ndmreset_req" + act: "req" + }, + { struct: "logic" + type: "uni" + name: "dmactive" + act: "req" + }, + { struct: "logic [rv_dm_reg_pkg::NrHarts-1:0]" + type: "uni" + name: "debug_req" + act: "req" + }, + ] + regwidth: "32", + registers: { + regs:[ + ] + rom: [ + // ROM size (given as `items` below) must be a power of two. + { window: { + name: "ROM" + items: "1024" // 4 KiB + swaccess: "ro", + desc: '''Access window into the debug ROM.''' + } + } + ] + } +}
diff --git a/hw/ip/rv_dm/rtl/rv_dm.sv b/hw/ip/rv_dm/rtl/rv_dm.sv index dcc3de7..7186d9f 100644 --- a/hw/ip/rv_dm/rtl/rv_dm.sv +++ b/hw/ip/rv_dm/rtl/rv_dm.sv
@@ -12,32 +12,42 @@ `include "prim_assert.sv" -module rv_dm #( - parameter int NrHarts = 1, - parameter logic [31:0] IdcodeValue = 32'h 0000_0001 +module rv_dm + import rv_dm_reg_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter logic [31:0] IdcodeValue = 32'h 0000_0001 ) ( input logic clk_i, // clock input logic rst_ni, // asynchronous reset active low, connect PoR - // here, not the system reset - input lc_ctrl_pkg::lc_tx_t hw_debug_en_i, + // here, not the system reset + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, input lc_ctrl_pkg::lc_tx_t scanmode_i, input scan_rst_ni, - output logic ndmreset_o, // non-debug module reset + output logic ndmreset_req_o, // non-debug module reset output logic dmactive_o, // debug module is active output logic [NrHarts-1:0] debug_req_o, // async debug request input logic [NrHarts-1:0] unavailable_i, // communicate whether the hart is unavailable - // (e.g.: power down) + // (e.g.: power down) + + // bus device for comportable CSR access + input tlul_pkg::tl_h2d_t regs_tl_d_i, + output tlul_pkg::tl_d2h_t regs_tl_d_o, // bus device with debug memory, for an execution based technique - input tlul_pkg::tl_h2d_t tl_d_i, - output tlul_pkg::tl_d2h_t tl_d_o, + input tlul_pkg::tl_h2d_t rom_tl_d_i, + output tlul_pkg::tl_d2h_t rom_tl_d_o, // bus host, for system bus accesses - output tlul_pkg::tl_h2d_t tl_h_o, - input tlul_pkg::tl_d2h_t tl_h_i, + output tlul_pkg::tl_h2d_t sba_tl_h_o, + input tlul_pkg::tl_d2h_t sba_tl_h_i, - input jtag_pkg::jtag_req_t jtag_req_i, - output jtag_pkg::jtag_rsp_t jtag_rsp_o + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + input jtag_pkg::jtag_req_t jtag_i, + output jtag_pkg::jtag_rsp_t jtag_o ); `ASSERT_INIT(paramCheckNrHarts, NrHarts > 0) @@ -47,6 +57,59 @@ // all harts have contiguous IDs localparam logic [NrHarts-1:0] SelectableHarts = {NrHarts{1'b1}}; + // CSR Nodes + tlul_pkg::tl_h2d_t rom_tl_win_h2d; + tlul_pkg::tl_d2h_t rom_tl_win_d2h; + rv_dm_reg_pkg::rv_dm_regs_reg2hw_t regs_reg2hw; + logic regs_intg_error, rom_intg_error; + + rv_dm_regs_reg_top u_reg_regs ( + .clk_i, + .rst_ni, + .tl_i (regs_tl_d_i ), + .tl_o (regs_tl_d_o ), + .reg2hw (regs_reg2hw ), + .intg_err_o(regs_intg_error), + .devmode_i (1'b1 ) + ); + + rv_dm_rom_reg_top u_reg_rom ( + .clk_i, + .rst_ni, + .tl_i (rom_tl_d_i ), + .tl_o (rom_tl_d_o ), + .tl_win_o (rom_tl_win_h2d), + .tl_win_i (rom_tl_win_d2h), + .intg_err_o(rom_intg_error), + .devmode_i (1'b1 ) + ); + + // Alerts + logic [NumAlerts-1:0] alert_test, alerts; + + assign alerts[0] = regs_intg_error | rom_intg_error; + + assign alert_test = { + regs_reg2hw.alert_test.q & + regs_reg2hw.alert_test.qe + }; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[0] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + // Debug CSRs dm::hartinfo_t [NrHarts-1:0] hartinfo; logic [NrHarts-1:0] halted; @@ -121,7 +184,7 @@ .dmi_resp_valid_o ( dmi_rsp_valid ), .dmi_resp_ready_i ( dmi_rsp_ready ), .dmi_resp_o ( dmi_rsp ), - .ndmreset_o ( ndmreset_o ), + .ndmreset_o ( ndmreset_req_o ), .dmactive_o ( dmactive_o ), .hartsel_o ( hartsel ), .hartinfo_i ( hartinfo ), @@ -214,8 +277,8 @@ .rdata_o (host_r_rdata), .err_o (host_r_err), .intg_err_o (), - .tl_o (tl_h_o), - .tl_i (tl_h_i) + .tl_o (sba_tl_h_o), + .tl_i (sba_tl_h_i) ); // DBG doesn't handle error responses so raise assertion if we see one @@ -288,7 +351,7 @@ prim_clock_mux2 #( .NoFpgaBufG(1'b1) ) u_prim_clock_mux2 ( - .clk0_i(jtag_req_i.tck), + .clk0_i(jtag_i.tck), .clk1_i(clk_i), .sel_i (testmode), .clk_o (tck_muxed) @@ -297,7 +360,7 @@ prim_clock_mux2 #( .NoFpgaBufG(1'b1) ) u_prim_rst_n_mux2 ( - .clk0_i(jtag_req_i.trst_n), + .clk0_i(jtag_i.trst_n), .clk1_i(scan_rst_ni), .sel_i (testmode), .clk_o (trst_n_muxed) @@ -322,28 +385,28 @@ //JTAG .tck_i (tck_muxed), - .tms_i (jtag_req_i.tms), + .tms_i (jtag_i.tms), .trst_ni (trst_n_muxed), - .td_i (jtag_req_i.tdi), - .td_o (jtag_rsp_o.tdo), - .tdo_oe_o (jtag_rsp_o.tdo_oe) + .td_i (jtag_i.tdi), + .td_o (jtag_o.tdo), + .tdo_oe_o (jtag_o.tdo_oe) ); `endif tlul_pkg::tl_instr_en_e en_ifetch; - lc_ctrl_pkg::lc_tx_t [0:0] hw_debug_en; + lc_ctrl_pkg::lc_tx_t [0:0] lc_hw_debug_en; prim_lc_sync #( .NumCopies(1) ) u_lc_en_sync ( .clk_i, .rst_ni, - .lc_en_i(hw_debug_en_i), - .lc_en_o(hw_debug_en) + .lc_en_i(lc_hw_debug_en_i), + .lc_en_o(lc_hw_debug_en) ); - assign en_ifetch = (hw_debug_en == lc_ctrl_pkg::On) ? tlul_pkg::InstrEn : tlul_pkg::InstrDis; + assign en_ifetch = (lc_hw_debug_en == lc_ctrl_pkg::On) ? tlul_pkg::InstrEn : tlul_pkg::InstrDis; tlul_adapter_sram #( .SramAw(AddressWidthWords), .SramDw(BusWidth), @@ -366,8 +429,8 @@ .rvalid_i (rvalid), .rerror_i (2'b00), - .tl_o (tl_d_o), - .tl_i (tl_d_i) + .tl_o (rom_tl_win_d2h), + .tl_i (rom_tl_win_h2d) ); always_ff @(posedge clk_i or negedge rst_ni) begin @@ -378,18 +441,21 @@ end end - `ASSERT_KNOWN(TlDODValidKnown_A, tl_d_o.d_valid) - `ASSERT_KNOWN(TlDOAReadyKnown_A, tl_d_o.a_ready) + `ASSERT_KNOWN(TlRegsDValidKnown_A, regs_tl_d_o.d_valid) + `ASSERT_KNOWN(TlRegsAReadyKnown_A, regs_tl_d_o.a_ready) - `ASSERT_KNOWN(TlHOAValidKnown_A, tl_h_o.a_valid) - `ASSERT_KNOWN(TlHODReadyKnown_A, tl_h_o.d_ready) + `ASSERT_KNOWN(TlRomDValidKnown_A, rom_tl_d_o.d_valid) + `ASSERT_KNOWN(TlRomAReadyKnown_A, rom_tl_d_o.a_ready) - `ASSERT_KNOWN(NdmresetOKnown_A, ndmreset_o) + `ASSERT_KNOWN(TlSbaAValidKnown_A, sba_tl_h_o.a_valid) + `ASSERT_KNOWN(TlSbaDReadyKnown_A, sba_tl_h_o.d_ready) + + `ASSERT_KNOWN(NdmresetOKnown_A, ndmreset_req_o) `ASSERT_KNOWN(DmactiveOKnown_A, dmactive_o) `ASSERT_KNOWN(DebugReqOKnown_A, debug_req_o) // JTAG TDO is driven by an inverted TCK in dmi_jtag_tap.sv - `ASSERT_KNOWN(JtagRspOTdoKnown_A, jtag_rsp_o.tdo, !jtag_req_i.tck, !jtag_req_i.trst_n) - `ASSERT_KNOWN(JtagRspOTdoOeKnown_A, jtag_rsp_o.tdo_oe, !jtag_req_i.tck, !jtag_req_i.trst_n) + `ASSERT_KNOWN(JtagRspOTdoKnown_A, jtag_o.tdo, !jtag_i.tck, !jtag_i.trst_n) + `ASSERT_KNOWN(JtagRspOTdoOeKnown_A, jtag_o.tdo_oe, !jtag_i.tck, !jtag_i.trst_n) endmodule
diff --git a/hw/ip/rv_dm/rtl/rv_dm_reg_pkg.sv b/hw/ip/rv_dm/rtl/rv_dm_reg_pkg.sv new file mode 100644 index 0000000..ef263f8 --- /dev/null +++ b/hw/ip/rv_dm/rtl/rv_dm_reg_pkg.sv
@@ -0,0 +1,53 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package rv_dm_reg_pkg; + + // Param list + parameter int NrHarts = 1; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int RegsAw = 2; + parameter int RomAw = 12; + + /////////////////////////////////////////////// + // Typedefs for registers for regs interface // + /////////////////////////////////////////////// + + typedef struct packed { + logic q; + logic qe; + } rv_dm_reg2hw_alert_test_reg_t; + + // Register -> HW type for regs interface + typedef struct packed { + rv_dm_reg2hw_alert_test_reg_t alert_test; // [1:0] + } rv_dm_regs_reg2hw_t; + + // Register offsets for regs interface + parameter logic [RegsAw-1:0] RV_DM_ALERT_TEST_OFFSET = 2'h 0; + + // Reset values for hwext registers and their fields for regs interface + parameter logic [0:0] RV_DM_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] RV_DM_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + + // Register index for regs interface + typedef enum int { + RV_DM_ALERT_TEST + } rv_dm_regs_id_e; + + // Register width information to check illegal writes for regs interface + parameter logic [3:0] RV_DM_REGS_PERMIT [1] = '{ + 4'b 0001 // index[0] RV_DM_ALERT_TEST + }; + + // Window parameters for rom interface + parameter logic [RomAw-1:0] RV_DM_ROM_OFFSET = 12'h 0; + parameter int unsigned RV_DM_ROM_SIZE = 'h 1000; + +endpackage +
diff --git a/hw/ip/rv_dm/rtl/rv_dm_regs_reg_top.sv b/hw/ip/rv_dm/rtl/rv_dm_regs_reg_top.sv new file mode 100644 index 0000000..0f99a74 --- /dev/null +++ b/hw/ip/rv_dm/rtl/rv_dm_regs_reg_top.sv
@@ -0,0 +1,180 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module rv_dm_regs_reg_top ( + input clk_i, + input rst_ni, + + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output rv_dm_reg_pkg::rv_dm_regs_reg2hw_t reg2hw, // Write + + // Integrity check errors + output logic intg_err_o, + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import rv_dm_reg_pkg::* ; + + localparam int AW = 2; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i, + .err_o(intg_err) + ); + + logic intg_err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + intg_err_q <= '0; + end else if (intg_err) begin + intg_err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = intg_err_q | intg_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i, + .rst_ni, + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; + + // Define SW related signals + // Format: <reg>_<field>_{wd|we|qs} + // or <reg>_{wd|we|qs} if field == 1 or 0 + logic alert_test_we; + logic alert_test_wd; + + // Register instances + // R[alert_test]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (reg2hw.alert_test.qe), + .q (reg2hw.alert_test.q), + .qs () + ); + + + + + logic [0:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[0] = (reg_addr == RV_DM_ALERT_TEST_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[0] & (|(RV_DM_REGS_PERMIT[0] & ~reg_be))))); + end + assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = '0; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we) + `ASSERT_PULSE(rePulse, reg_re) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule
diff --git a/hw/ip/rv_dm/rtl/rv_dm_rom_reg_top.sv b/hw/ip/rv_dm/rtl/rv_dm_rom_reg_top.sv new file mode 100644 index 0000000..68b2083 --- /dev/null +++ b/hw/ip/rv_dm/rtl/rv_dm_rom_reg_top.sv
@@ -0,0 +1,69 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module rv_dm_rom_reg_top ( + input clk_i, + input rst_ni, + + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Output port for window + output tlul_pkg::tl_h2d_t tl_win_o, + input tlul_pkg::tl_d2h_t tl_win_i, + + // To HW + + // Integrity check errors + output logic intg_err_o, + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import rv_dm_reg_pkg::* ; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i, + .err_o(intg_err) + ); + + logic intg_err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + intg_err_q <= '0; + end else if (intg_err) begin + intg_err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = intg_err_q | intg_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o + ); + + assign tl_win_o = tl_i; + assign tl_o_pre = tl_win_i; + + // Unused signal tieoff + // devmode_i is not used if there are no registers + logic unused_devmode; + assign unused_devmode = ^devmode_i; +endmodule
diff --git a/hw/ip/rv_dm/rv_dm.core b/hw/ip/rv_dm/rv_dm.core index 345536c..7e9c5ca 100644 --- a/hw/ip/rv_dm/rv_dm.core +++ b/hw/ip/rv_dm/rv_dm.core
@@ -17,6 +17,9 @@ - pulp-platform:riscv-dbg:0.1 - lowrisc:prim:lc_sync files: + - rtl/rv_dm_reg_pkg.sv + - rtl/rv_dm_regs_reg_top.sv + - rtl/rv_dm_rom_reg_top.sv - rtl/rv_dm.sv file_type: systemVerilogSource
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 24ae176..662f4b9 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -552,25 +552,6 @@ } ] } - { - name: rv_dm - type: rv_dm - inter_signal_list: - [ - { - struct: jtag - type: req_rsp - name: jtag - act: rsp - package: jtag_pkg - inst_name: rv_dm - width: 1 - default: "" - top_signame: pinmux_aon_rv_jtag - index: -1 - } - ] - } ] module: [ @@ -2448,15 +2429,27 @@ index: -1 } { - name: cpu - struct: rstmgr_cpu - package: rstmgr_pkg + name: rst_cpu_n + struct: logic type: uni act: rcv width: 1 inst_name: rstmgr_aon default: "" - top_signame: rstmgr_aon_cpu + package: "" + top_signame: rstmgr_aon_rst_cpu_n + index: -1 + } + { + name: ndmreset_req + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + default: "" + package: "" + top_signame: rv_dm_ndmreset_req index: -1 } { @@ -3844,6 +3837,150 @@ ] } { + name: rv_dm + type: rv_dm + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel] + } + base_addrs: + { + rom: 0x00010000 + regs: 0x41200000 + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + domain: "0" + param_list: + [ + { + name: IdcodeValue + desc: RISC-V debug module JTAG ID code. + type: logic [31:0] + default: 32'h 0000_0001 + expose: "true" + name_top: RvDmIdcodeValue + } + ] + inter_signal_list: + [ + { + name: jtag + struct: jtag + package: jtag_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + top_signame: pinmux_aon_rv_jtag + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: unavailable + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_dm + index: -1 + } + { + name: ndmreset_req + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_dm + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_dm_ndmreset_req + index: -1 + } + { + name: dmactive + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_dm + index: -1 + } + { + name: debug_req + struct: logic [rv_dm_reg_pkg::NrHarts-1:0] + type: uni + act: req + width: 1 + inst_name: rv_dm + default: "" + package: "" + top_signame: rv_dm_debug_req + index: -1 + } + { + name: sba_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_dm + default: "" + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: regs_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: rom_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_rom_tl_d + index: -1 + } + ] + } + { name: rv_plic type: rv_plic clock_srcs: @@ -6243,6 +6380,7 @@ sram_ctrl_ret_aon.lc_hw_debug_en pinmux_aon.lc_hw_debug_en csrng.lc_hw_debug_en + rv_dm.lc_hw_debug_en ] lc_ctrl.lc_cpu_en: [ @@ -6319,6 +6457,10 @@ [ spi_host0.passthrough ] + rv_dm.ndmreset_req: + [ + rstmgr_aon.ndmreset_req + ] pwrmgr_aon.wakeups: [ sysrst_ctrl_aon.gsc_wk @@ -6332,6 +6474,18 @@ sysrst_ctrl_aon.gsc_rst aon_timer_aon.aon_timer_rst_req ] + main.tl_rv_dm__sba: + [ + rv_dm.sba_tl_h + ] + rv_dm.regs_tl_d: + [ + main.tl_rv_dm__regs + ] + rv_dm.rom_tl_d: + [ + main.tl_rv_dm__rom + ] rom_ctrl.rom_tl: [ main.tl_rom_ctrl__rom @@ -6524,14 +6678,13 @@ top: [ rstmgr_aon.resets - rstmgr_aon.cpu + rstmgr_aon.rst_cpu_n pwrmgr_aon.pwr_cpu - clkmgr_aon.clocks pwrmgr_aon.fetch_en + clkmgr_aon.clocks + rv_dm.debug_req main.tl_corei main.tl_cored - main.tl_dm_sba - main.tl_debug_mem pinmux_aon.dft_jtag otp_ctrl.otp_hw_cfg csrng.otp_en_csrng_sw_app_read @@ -6607,7 +6760,7 @@ corei: [ rom_ctrl.rom - debug_mem + rv_dm.rom ram_main eflash ] @@ -6615,7 +6768,8 @@ [ rom_ctrl.rom rom_ctrl.regs - debug_mem + rv_dm.rom + rv_dm.regs ram_main eflash peri @@ -6634,10 +6788,11 @@ sram_ctrl_main rv_core_ibex_peri ] - dm_sba: + rv_dm.sba: [ rom_ctrl.rom rom_ctrl.regs + rv_dm.regs ram_main eflash peri @@ -6682,14 +6837,50 @@ pipeline_byp: "true" } { - name: dm_sba + name: rv_dm.sba type: host clock: clk_main_i reset: rst_main_ni pipeline_byp: "false" xbar: false stub: false + inst_type: "" + pipeline: "true" + } + { + name: rv_dm.regs + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline_byp: "false" inst_type: rv_dm + addr_range: + [ + { + base_addr: 0x41200000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: "true" + } + { + name: rv_dm.rom + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline_byp: "false" + inst_type: rv_dm + addr_range: + [ + { + base_addr: 0x10000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false pipeline: "true" } { @@ -6729,24 +6920,6 @@ pipeline_byp: "true" } { - name: debug_mem - type: device - clock: clk_main_i - reset: rst_main_ni - pipeline_byp: "false" - inst_type: rv_dm - addr_range: - [ - { - base_addr: 0x1A110000 - size_byte: 0x1000 - } - ] - xbar: false - stub: false - pipeline: "true" - } - { name: ram_main type: device clock: clk_main_i @@ -7081,7 +7254,7 @@ index: -1 } { - name: tl_dm_sba + name: tl_rv_dm__sba struct: tl package: tlul_pkg type: req_rsp @@ -7089,7 +7262,32 @@ width: 1 inst_name: main default: "" - top_signame: main_tl_dm_sba + end_idx: -1 + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: tl_rv_dm__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: tl_rv_dm__rom + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_dm_rom_tl_d index: -1 } { @@ -7117,18 +7315,6 @@ index: -1 } { - name: tl_debug_mem - struct: tl - package: tlul_pkg - type: req_rsp - act: req - width: 1 - inst_name: main - default: "" - top_signame: main_tl_debug_mem - index: -1 - } - { name: tl_ram_main struct: tl package: tlul_pkg @@ -11884,6 +12070,7 @@ sensor_ctrl_aon sram_ctrl_ret_aon flash_ctrl + rv_dm rv_plic aes hmac @@ -12223,6 +12410,13 @@ module_name: flash_ctrl } { + name: rv_dm_fatal_fault + width: 1 + type: alert + async: "1" + module_name: rv_dm + } + { name: rv_plic_fatal_fault width: 1 type: alert @@ -13680,15 +13874,27 @@ index: -1 } { - name: cpu - struct: rstmgr_cpu - package: rstmgr_pkg + name: rst_cpu_n + struct: logic type: uni act: rcv width: 1 inst_name: rstmgr_aon default: "" - top_signame: rstmgr_aon_cpu + package: "" + top_signame: rstmgr_aon_rst_cpu_n + index: -1 + } + { + name: ndmreset_req + struct: logic + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + default: "" + package: "" + top_signame: rv_dm_ndmreset_req index: -1 } { @@ -14673,6 +14879,113 @@ index: -1 } { + name: jtag + struct: jtag + package: jtag_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + top_signame: pinmux_aon_rv_jtag + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: rv_dm + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: unavailable + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: rv_dm + index: -1 + } + { + name: ndmreset_req + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_dm + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: rv_dm_ndmreset_req + index: -1 + } + { + name: dmactive + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_dm + index: -1 + } + { + name: debug_req + struct: logic [rv_dm_reg_pkg::NrHarts-1:0] + type: uni + act: req + width: 1 + inst_name: rv_dm + default: "" + package: "" + top_signame: rv_dm_debug_req + index: -1 + } + { + name: sba_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: rv_dm + default: "" + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: regs_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: rom_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_dm + default: "" + end_idx: -1 + top_signame: rv_dm_rom_tl_d + index: -1 + } + { name: tl struct: tl package: tlul_pkg @@ -15859,7 +16172,7 @@ index: -1 } { - name: tl_dm_sba + name: tl_rv_dm__sba struct: tl package: tlul_pkg type: req_rsp @@ -15867,7 +16180,32 @@ width: 1 inst_name: main default: "" - top_signame: main_tl_dm_sba + end_idx: -1 + top_signame: main_tl_rv_dm__sba + index: -1 + } + { + name: tl_rv_dm__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: tl_rv_dm__rom + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: main + default: "" + top_signame: rv_dm_rom_tl_d index: -1 } { @@ -15895,18 +16233,6 @@ index: -1 } { - name: tl_debug_mem - struct: tl - package: tlul_pkg - type: req_rsp - act: req - width: 1 - inst_name: main - default: "" - top_signame: main_tl_debug_mem - index: -1 - } - { name: tl_ram_main struct: tl package: tlul_pkg @@ -16601,18 +16927,6 @@ index: -1 } { - struct: jtag - type: req_rsp - name: jtag - act: rsp - package: jtag_pkg - inst_name: rv_dm - width: 1 - default: "" - top_signame: pinmux_aon_rv_jtag - index: -1 - } - { struct: edn type: req_rsp name: edn @@ -18195,6 +18509,17 @@ { package: "" struct: logic + signame: rv_dm_ndmreset_req + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic signame: pwrmgr_aon_wakeups width: 5 type: uni @@ -18217,6 +18542,72 @@ { package: tlul_pkg struct: tl_h2d + signame: main_tl_rv_dm__sba_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_rv_dm__sba_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rv_dm_regs_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rv_dm_regs_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rv_dm_rom_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rv_dm_rom_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d signame: rom_ctrl_rom_tl_req width: 1 type: req_rsp @@ -19258,9 +19649,9 @@ default: "" } { - package: rstmgr_pkg - struct: rstmgr_cpu - signame: rstmgr_aon_cpu + package: "" + struct: logic + signame: rstmgr_aon_rst_cpu_n width: 1 type: uni end_idx: -1 @@ -19276,6 +19667,15 @@ default: "" } { + package: lc_ctrl_pkg + struct: lc_tx + signame: pwrmgr_aon_fetch_en + width: 1 + type: uni + end_idx: -1 + default: "" + } + { package: clkmgr_pkg struct: clkmgr_out signame: clkmgr_aon_clocks @@ -19285,9 +19685,9 @@ default: "" } { - package: lc_ctrl_pkg - struct: lc_tx - signame: pwrmgr_aon_fetch_en + package: "" + struct: logic [rv_dm_reg_pkg::NrHarts-1:0] + signame: rv_dm_debug_req width: 1 type: uni end_idx: -1 @@ -19330,42 +19730,6 @@ default: "" } { - package: tlul_pkg - struct: tl_h2d - signame: main_tl_dm_sba_req - width: 1 - type: req_rsp - end_idx: -1 - default: "" - } - { - package: tlul_pkg - struct: tl_d2h - signame: main_tl_dm_sba_rsp - width: 1 - type: req_rsp - end_idx: -1 - default: "" - } - { - package: tlul_pkg - struct: tl_h2d - signame: main_tl_debug_mem_req - width: 1 - type: req_rsp - end_idx: -1 - default: "" - } - { - package: tlul_pkg - struct: tl_d2h - signame: main_tl_debug_mem_rsp - width: 1 - type: req_rsp - end_idx: -1 - default: "" - } - { package: jtag_pkg struct: jtag_req signame: pinmux_aon_dft_jtag_req
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index e7bfe6a..97692a4 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -246,17 +246,6 @@ }, ], } - { name: "rv_dm", - type: "rv_dm", - inter_signal_list: [ - { struct: "jtag", - type: "req_rsp", - name: "jtag", - act: "rsp", - package: "jtag_pkg", - }, - ] - } ] // `module` defines the peripherals. @@ -545,6 +534,14 @@ base_addrs: {core: "0x41000000", prim: "0x41008000"} attr: "templated", }, + { name: "rv_dm", + type: "rv_dm", + clock_srcs: {clk_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + // Note that this module also contains a bus host. + base_addrs: {rom: "0x00010000", regs: "0x41200000"} + }, { name: "rv_plic", type: "rv_plic", clock_srcs: {clk_i: "main"}, @@ -976,7 +973,8 @@ 'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en', 'sram_ctrl_ret_aon.lc_hw_debug_en', 'pinmux_aon.lc_hw_debug_en', - 'csrng.lc_hw_debug_en'], + 'csrng.lc_hw_debug_en', + 'rv_dm.lc_hw_debug_en'], 'lc_ctrl.lc_cpu_en' : ['rv_core_ibex.lc_cpu_en'], 'lc_ctrl.lc_keymgr_en' : ['keymgr.lc_keymgr_en'], 'lc_ctrl.lc_escalate_en' : ['aes.lc_escalate_en', @@ -999,6 +997,7 @@ 'lc_ctrl.lc_seed_hw_rd_en' : ['otp_ctrl.lc_seed_hw_rd_en', 'flash_ctrl.lc_seed_hw_rd_en'], + // rv core ibex peripheral connections 'rv_core_ibex.fatal_intg_event' : ['rv_core_ibex_peri.fatal_intg_event'], 'rv_core_ibex.fatal_core_event' : ['rv_core_ibex_peri.fatal_core_event'], @@ -1008,17 +1007,24 @@ // spi passthrough connection 'spi_device.passthrough' : ['spi_host0.passthrough'] + + // Debug module reset request to reset manager + 'rv_dm.ndmreset_req' : ['rstmgr_aon.ndmreset_req'] } // top is to connect to top net/struct. // It defines the signal in the top and connect from the module, // use of the signal is up to top template 'top': [ - 'rstmgr_aon.resets', 'rstmgr_aon.cpu', 'pwrmgr_aon.pwr_cpu', 'clkmgr_aon.clocks', - 'pwrmgr_aon.fetch_en', + 'rstmgr_aon.resets', 'rstmgr_aon.rst_cpu_n', + 'pwrmgr_aon.pwr_cpu', 'pwrmgr_aon.fetch_en', + 'clkmgr_aon.clocks', + + // Debug request from debug module to CPU + 'rv_dm.debug_req', // Xbars - 'main.tl_corei', 'main.tl_cored', 'main.tl_dm_sba', 'main.tl_debug_mem', + 'main.tl_corei', 'main.tl_cored', // Pinmux JTAG signals for the tool-inserted DFT TAP 'pinmux_aon.dft_jtag', @@ -1073,8 +1079,6 @@ }, }, - debug_mem_base_addr: "0x1A110000", - // Crossbars: having a top level crossbar // This version assumes all crossbars are instantiated at the top. // Assume xbar.hjson is located in the same directory of top.hjson
diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson index 70a1415..fbb047c 100644 --- a/hw/top_earlgrey/data/xbar_main.hjson +++ b/hw/top_earlgrey/data/xbar_main.hjson
@@ -23,12 +23,23 @@ pipeline: "false" }, - { name: "dm_sba", // DM - type: "host", - clock: "clk_main_i", - reset: "rst_main_ni", + { name: "rv_dm.sba", + type: "host", + clock: "clk_main_i", + reset: "rst_main_ni", pipeline_byp: "false" - + }, + { name: "rv_dm.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline_byp: "false" + }, + { name: "rv_dm.rom", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline_byp: "false" }, { name: "rom_ctrl.rom", type: "device", @@ -42,12 +53,6 @@ reset: "rst_main_ni", pipeline: "false", }, - { name: "debug_mem", - type: "device", - clock: "clk_main_i", - reset: "rst_main_ni", - pipeline_byp: "false" - }, { name: "ram_main", type: "device", clock: "clk_main_i", @@ -153,19 +158,19 @@ }, ], connections: { - corei: ["rom_ctrl.rom", "debug_mem", "ram_main", "eflash"], + corei: ["rom_ctrl.rom", "rv_dm.rom", "ram_main", "eflash"], cored: [ - "rom_ctrl.rom", "rom_ctrl.regs", "debug_mem", "ram_main", - "eflash", "peri", "flash_ctrl.core", "flash_ctrl.prim", + "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.rom", "rv_dm.regs", + "ram_main", "eflash", "peri", "flash_ctrl.core", "flash_ctrl.prim", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main", "rv_core_ibex_peri" ], - dm_sba: [ - "rom_ctrl.rom", "rom_ctrl.regs", "ram_main", "eflash", "peri", - "flash_ctrl.core", "flash_ctrl.prim", "aes", "entropy_src", - "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr", - "kmac", "sram_ctrl_main", "rv_core_ibex_peri" + rv_dm.sba: [ + "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.regs", "ram_main", + "eflash", "peri", "flash_ctrl.core", "flash_ctrl.prim", "aes", + "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", + "otbn", "keymgr", "kmac", "sram_ctrl_main", "rv_core_ibex_peri" ], }, }
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv index 48adc0f..f67d95e 100644 --- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -50,24 +50,25 @@ assign alert_if[43].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1]; assign alert_if[44].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2]; assign alert_if[45].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3]; -assign alert_if[46].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; -assign alert_if[47].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; -assign alert_if[48].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; -assign alert_if[49].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; -assign alert_if[50].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; -assign alert_if[51].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0]; -assign alert_if[52].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1]; -assign alert_if[53].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; -assign alert_if[54].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; -assign alert_if[55].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1]; -assign alert_if[56].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; -assign alert_if[57].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; -assign alert_if[58].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; -assign alert_if[59].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1]; -assign alert_if[60].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; -assign alert_if[61].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; -assign alert_if[62].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0]; -assign alert_if[63].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[0]; -assign alert_if[64].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[1]; -assign alert_if[65].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[2]; -assign alert_if[66].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[3]; +assign alert_if[46].alert_tx = `CHIP_HIER.u_rv_dm.alert_tx_o[0]; +assign alert_if[47].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; +assign alert_if[48].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; +assign alert_if[49].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; +assign alert_if[50].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; +assign alert_if[51].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; +assign alert_if[52].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0]; +assign alert_if[53].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1]; +assign alert_if[54].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; +assign alert_if[55].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; +assign alert_if[56].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1]; +assign alert_if[57].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; +assign alert_if[58].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; +assign alert_if[59].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; +assign alert_if[60].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1]; +assign alert_if[61].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; +assign alert_if[62].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[63].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0]; +assign alert_if[64].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[0]; +assign alert_if[65].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[1]; +assign alert_if[66].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[2]; +assign alert_if[67].alert_tx = `CHIP_HIER.u_rv_core_ibex_peri.alert_tx_o[3];
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index 6952375..52a1dc9 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -31,11 +31,12 @@ tl_if corei_tl_if(clk_main, rst_n); tl_if cored_tl_if(clk_main, rst_n); -tl_if dm_sba_tl_if(clk_main, rst_n); +tl_if rv_dm__sba_tl_if(clk_main, rst_n); +tl_if rv_dm__regs_tl_if(clk_main, rst_n); +tl_if rv_dm__rom_tl_if(clk_main, rst_n); tl_if rom_ctrl__rom_tl_if(clk_main, rst_n); tl_if rom_ctrl__regs_tl_if(clk_main, rst_n); -tl_if debug_mem_tl_if(clk_main, rst_n); tl_if ram_main_tl_if(clk_main, rst_n); tl_if eflash_tl_if(clk_main, rst_n); tl_if flash_ctrl__core_tl_if(clk_main, rst_n); @@ -108,10 +109,11 @@ `DRIVE_CHIP_TL_HOST_IF(corei, rv_core_ibex, tl_i) `DRIVE_CHIP_TL_HOST_IF(cored, rv_core_ibex, tl_d) - `DRIVE_CHIP_TL_HOST_IF(dm_sba, dm_top, tl_h) + `DRIVE_CHIP_TL_HOST_IF(rv_dm__sba, rv_dm, sba_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(rv_dm__regs, rv_dm, regs_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(rv_dm__rom, rv_dm, rom_tl_d) `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl__rom, rom_ctrl, rom_tl) `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl__regs, rom_ctrl, regs_tl) - `DRIVE_CHIP_TL_DEVICE_IF(debug_mem, dm_top, tl_d) `DRIVE_CHIP_TL_DEVICE_IF(ram_main, tl_adapter_ram_main, tl) `DRIVE_CHIP_TL_DEVICE_IF(eflash, tl_adapter_eflash, tl) `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__core, flash_ctrl, core_tl)
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index 2e39a02..4f89e46 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -7,15 +7,18 @@ // List of Xbar device memory map tl_device_t xbar_devices[$] = '{ + '{"rv_dm__regs", '{ + '{32'h41200000, 32'h41200fff} + }}, + '{"rv_dm__rom", '{ + '{32'h00010000, 32'h00010fff} + }}, '{"rom_ctrl__rom", '{ '{32'h00008000, 32'h0000bfff} }}, '{"rom_ctrl__regs", '{ '{32'h411e0000, 32'h411e0fff} }}, - '{"debug_mem", '{ - '{32'h1a110000, 32'h1a110fff} - }}, '{"ram_main", '{ '{32'h10000000, 32'h1001ffff} }}, @@ -155,15 +158,16 @@ // List of Xbar hosts tl_host_t xbar_hosts[$] = '{ '{"corei", 0, '{ - "rom_ctrl.rom", - "debug_mem", + "rom_ctrl__rom", + "rv_dm__rom", "ram_main", "eflash"}} , '{"cored", 1, '{ - "rom_ctrl.rom", - "rom_ctrl.regs", - "debug_mem", + "rom_ctrl__rom", + "rom_ctrl__regs", + "rv_dm__rom", + "rv_dm__regs", "ram_main", "eflash", "uart0", @@ -195,8 +199,8 @@ "adc_ctrl_aon", "sysrst_ctrl_aon", "pwm_aon", - "flash_ctrl.core", - "flash_ctrl.prim", + "flash_ctrl__core", + "flash_ctrl__prim", "aes", "entropy_src", "csrng", @@ -210,9 +214,10 @@ "sram_ctrl_main", "rv_core_ibex_peri"}} , - '{"dm_sba", 2, '{ - "rom_ctrl.rom", - "rom_ctrl.regs", + '{"rv_dm__sba", 2, '{ + "rom_ctrl__rom", + "rom_ctrl__regs", + "rv_dm__regs", "ram_main", "eflash", "uart0", @@ -244,8 +249,8 @@ "adc_ctrl_aon", "sysrst_ctrl_aon", "pwm_aon", - "flash_ctrl.core", - "flash_ctrl.prim", + "flash_ctrl__core", + "flash_ctrl__prim", "aes", "entropy_src", "csrng",
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv index be4ec50..6b997d6 100644 --- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -51,6 +51,7 @@ "flash_ctrl_recov_mp_err", "flash_ctrl_recov_ecc_err", "flash_ctrl_fatal_intg_err", + "rv_dm_fatal_fault", "rv_plic_fatal_fault", "aes_recov_ctrl_update_err", "aes_fatal_fault", @@ -74,4 +75,4 @@ "rv_core_ibex_peri_recov_hw_err" }; -parameter uint NUM_ALERTS = 67; +parameter uint NUM_ALERTS = 68;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson index aed413c..a604303 100644 --- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson +++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -48,7 +48,7 @@ { name: "NAlerts", desc: "Number of alert channels.", type: "int", - default: "67", + default: "68", local: "true" }, { name: "EscCntDw", @@ -69,7 +69,7 @@ defines whether the protocol is synchronous (0) or asynchronous (1). ''' type: "logic [NAlerts-1:0]", - default: "67'h7ffffffffffffffff", + default: "68'hfffffffffffffffff", local: "true" }, { name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv index 40231dc..ee9529e 100644 --- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv +++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@ package alert_handler_reg_pkg; // Param list - parameter int NAlerts = 67; + parameter int NAlerts = 68; parameter int EscCntDw = 32; parameter int AccuCntDw = 16; - parameter logic [NAlerts-1:0] AsyncOn = 67'h7ffffffffffffffff; + parameter logic [NAlerts-1:0] AsyncOn = 68'hfffffffffffffffff; parameter int N_CLASSES = 4; parameter int N_ESC_SEV = 4; parameter int N_PHASES = 4; @@ -464,15 +464,15 @@ // Register -> HW type typedef struct packed { - alert_handler_reg2hw_intr_state_reg_t intr_state; // [1155:1152] - alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1151:1148] - alert_handler_reg2hw_intr_test_reg_t intr_test; // [1147:1140] - alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1139:1124] - alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1123:1123] - alert_handler_reg2hw_alert_regwen_mreg_t [66:0] alert_regwen; // [1122:1056] - alert_handler_reg2hw_alert_en_mreg_t [66:0] alert_en; // [1055:989] - alert_handler_reg2hw_alert_class_mreg_t [66:0] alert_class; // [988:855] - alert_handler_reg2hw_alert_cause_mreg_t [66:0] alert_cause; // [854:788] + alert_handler_reg2hw_intr_state_reg_t intr_state; // [1160:1157] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1156:1153] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [1152:1145] + alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1144:1129] + alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [1128:1128] + alert_handler_reg2hw_alert_regwen_mreg_t [67:0] alert_regwen; // [1127:1060] + alert_handler_reg2hw_alert_en_mreg_t [67:0] alert_en; // [1059:992] + alert_handler_reg2hw_alert_class_mreg_t [67:0] alert_class; // [991:856] + alert_handler_reg2hw_alert_cause_mreg_t [67:0] alert_cause; // [855:788] alert_handler_reg2hw_loc_alert_en_mreg_t [4:0] loc_alert_en; // [787:783] alert_handler_reg2hw_loc_alert_class_mreg_t [4:0] loc_alert_class; // [782:773] alert_handler_reg2hw_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [772:768] @@ -512,8 +512,8 @@ // HW -> register type typedef struct packed { - alert_handler_hw2reg_intr_state_reg_t intr_state; // [363:356] - alert_handler_hw2reg_alert_cause_mreg_t [66:0] alert_cause; // [355:222] + alert_handler_hw2reg_intr_state_reg_t intr_state; // [365:358] + alert_handler_hw2reg_alert_cause_mreg_t [67:0] alert_cause; // [357:222] alert_handler_hw2reg_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [221:212] alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] @@ -607,279 +607,283 @@ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_65_OFFSET = 11'h 11c; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_66_OFFSET = 11'h 120; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 11'h 124; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 11'h 128; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 11'h 12c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 11'h 130; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 11'h 134; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 11'h 138; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 11'h 13c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 11'h 140; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 11'h 144; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 11'h 148; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 11'h 14c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 11'h 150; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 11'h 154; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 11'h 158; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 11'h 15c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 11'h 160; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 11'h 164; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 11'h 168; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 11'h 16c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 11'h 170; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 11'h 174; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 11'h 178; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 11'h 17c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 11'h 180; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 11'h 184; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 11'h 188; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 11'h 18c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 11'h 190; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 11'h 194; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 11'h 198; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 11'h 19c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 11'h 1a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 11'h 1a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 11'h 1a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 11'h 1ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 11'h 1b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 11'h 1b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 11'h 1b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 11'h 1bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 11'h 1c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 11'h 1c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 11'h 1c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 11'h 1cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_43_OFFSET = 11'h 1d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_44_OFFSET = 11'h 1d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_45_OFFSET = 11'h 1d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_46_OFFSET = 11'h 1dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_47_OFFSET = 11'h 1e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_48_OFFSET = 11'h 1e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_49_OFFSET = 11'h 1e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_50_OFFSET = 11'h 1ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_51_OFFSET = 11'h 1f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_52_OFFSET = 11'h 1f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_53_OFFSET = 11'h 1f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_54_OFFSET = 11'h 1fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_55_OFFSET = 11'h 200; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_56_OFFSET = 11'h 204; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_57_OFFSET = 11'h 208; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_58_OFFSET = 11'h 20c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_59_OFFSET = 11'h 210; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_60_OFFSET = 11'h 214; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_61_OFFSET = 11'h 218; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_62_OFFSET = 11'h 21c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_63_OFFSET = 11'h 220; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_64_OFFSET = 11'h 224; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_65_OFFSET = 11'h 228; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_66_OFFSET = 11'h 22c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 11'h 230; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 11'h 234; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 11'h 238; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 11'h 23c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 11'h 240; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 11'h 244; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 11'h 248; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 11'h 24c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 11'h 250; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 11'h 254; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 11'h 258; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 11'h 25c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 11'h 260; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 11'h 264; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 11'h 268; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 11'h 26c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 11'h 270; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 11'h 274; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 11'h 278; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 11'h 27c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 11'h 280; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 11'h 284; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 11'h 288; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 11'h 28c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 11'h 290; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 11'h 294; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 11'h 298; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 11'h 29c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 11'h 2a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 11'h 2a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 11'h 2a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 11'h 2ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 11'h 2b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 11'h 2b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 11'h 2b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 11'h 2bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 11'h 2c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 11'h 2c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 11'h 2c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 11'h 2cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 11'h 2d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 11'h 2d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 11'h 2d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_43_OFFSET = 11'h 2dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_44_OFFSET = 11'h 2e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_45_OFFSET = 11'h 2e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_46_OFFSET = 11'h 2e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_47_OFFSET = 11'h 2ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_48_OFFSET = 11'h 2f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_49_OFFSET = 11'h 2f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_50_OFFSET = 11'h 2f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_51_OFFSET = 11'h 2fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_52_OFFSET = 11'h 300; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_53_OFFSET = 11'h 304; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_54_OFFSET = 11'h 308; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_55_OFFSET = 11'h 30c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_56_OFFSET = 11'h 310; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_57_OFFSET = 11'h 314; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_58_OFFSET = 11'h 318; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_59_OFFSET = 11'h 31c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_60_OFFSET = 11'h 320; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_61_OFFSET = 11'h 324; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_62_OFFSET = 11'h 328; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_63_OFFSET = 11'h 32c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_64_OFFSET = 11'h 330; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_65_OFFSET = 11'h 334; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_66_OFFSET = 11'h 338; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 33c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 340; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 344; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 348; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 34c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 350; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 354; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 358; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 35c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 360; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 364; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 368; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 36c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 370; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 374; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 378; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 37c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 380; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 384; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 388; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 38c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 390; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 394; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 398; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 39c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 3a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 3a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 3a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 3ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 3b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 3b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 3f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 3f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 3fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 400; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 404; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 408; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 40c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 410; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 414; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 418; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 41c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 420; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 424; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 428; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 42c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 430; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 434; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 438; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 43c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 440; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_66_OFFSET = 11'h 444; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 448; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 44c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 450; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 454; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 458; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 11'h 45c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 11'h 460; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 11'h 464; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 11'h 468; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 11'h 46c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 11'h 470; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 11'h 474; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 11'h 478; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 11'h 47c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 11'h 480; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 484; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 488; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 48c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 490; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 494; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 498; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 11'h 49c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 11'h 4a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 11'h 4ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 11'h 4b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 11'h 4b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 11'h 4b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 11'h 4bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 11'h 4c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 11'h 4d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 11'h 4d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 11'h 4e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 11'h 4e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 11'h 4e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 11'h 4ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 11'h 4f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 11'h 4f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 500; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 11'h 504; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 508; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 11'h 50c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 510; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 11'h 514; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 11'h 518; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 11'h 51c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 11'h 520; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 11'h 524; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 11'h 528; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 52c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 530; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 534; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 11'h 538; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 53c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 11'h 540; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 544; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 11'h 548; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 11'h 54c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 11'h 550; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 11'h 554; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 11'h 558; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 11'h 55c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 560; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_67_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_41_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_42_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_43_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_44_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_45_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_46_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_47_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_48_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_49_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_50_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_51_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_52_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_53_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_54_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_55_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_56_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_57_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_58_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_59_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_60_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_61_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_62_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_63_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_64_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_65_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_66_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_67_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_41_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_42_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_43_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_44_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_45_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_46_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_47_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_48_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_49_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_50_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_51_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_52_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_53_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_54_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_55_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_56_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_57_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_58_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_59_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_60_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_61_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_62_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_63_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_64_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_65_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_66_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_67_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_66_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_67_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 574; // Reset values for hwext registers and their fields parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; @@ -975,6 +979,7 @@ ALERT_HANDLER_ALERT_REGWEN_64, ALERT_HANDLER_ALERT_REGWEN_65, ALERT_HANDLER_ALERT_REGWEN_66, + ALERT_HANDLER_ALERT_REGWEN_67, ALERT_HANDLER_ALERT_EN_0, ALERT_HANDLER_ALERT_EN_1, ALERT_HANDLER_ALERT_EN_2, @@ -1042,6 +1047,7 @@ ALERT_HANDLER_ALERT_EN_64, ALERT_HANDLER_ALERT_EN_65, ALERT_HANDLER_ALERT_EN_66, + ALERT_HANDLER_ALERT_EN_67, ALERT_HANDLER_ALERT_CLASS_0, ALERT_HANDLER_ALERT_CLASS_1, ALERT_HANDLER_ALERT_CLASS_2, @@ -1109,6 +1115,7 @@ ALERT_HANDLER_ALERT_CLASS_64, ALERT_HANDLER_ALERT_CLASS_65, ALERT_HANDLER_ALERT_CLASS_66, + ALERT_HANDLER_ALERT_CLASS_67, ALERT_HANDLER_ALERT_CAUSE_0, ALERT_HANDLER_ALERT_CAUSE_1, ALERT_HANDLER_ALERT_CAUSE_2, @@ -1176,6 +1183,7 @@ ALERT_HANDLER_ALERT_CAUSE_64, ALERT_HANDLER_ALERT_CAUSE_65, ALERT_HANDLER_ALERT_CAUSE_66, + ALERT_HANDLER_ALERT_CAUSE_67, ALERT_HANDLER_LOC_ALERT_REGWEN_0, ALERT_HANDLER_LOC_ALERT_REGWEN_1, ALERT_HANDLER_LOC_ALERT_REGWEN_2, @@ -1251,7 +1259,7 @@ } alert_handler_id_e; // Register width information to check illegal writes - parameter logic [3:0] ALERT_HANDLER_PERMIT [346] = '{ + parameter logic [3:0] ALERT_HANDLER_PERMIT [350] = '{ 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST @@ -1325,279 +1333,283 @@ 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_REGWEN_65 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_REGWEN_66 - 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_0 - 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_1 - 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_2 - 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_3 - 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_4 - 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_5 - 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_6 - 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_7 - 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_8 - 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_9 - 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_10 - 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_11 - 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_12 - 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_13 - 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_14 - 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_15 - 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_16 - 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_17 - 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_18 - 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_19 - 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_20 - 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_21 - 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_22 - 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_23 - 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_24 - 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_25 - 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_26 - 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_27 - 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_28 - 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_29 - 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_30 - 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_31 - 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_32 - 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_33 - 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_34 - 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_35 - 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_36 - 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_37 - 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_38 - 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_39 - 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_40 - 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_41 - 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_42 - 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_43 - 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_44 - 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_45 - 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_46 - 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_47 - 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_48 - 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_49 - 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_50 - 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_51 - 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_52 - 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_53 - 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_54 - 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_55 - 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_56 - 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_57 - 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_58 - 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_59 - 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_60 - 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_61 - 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_62 - 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_63 - 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_64 - 4'b 0001, // index[138] ALERT_HANDLER_ALERT_EN_65 - 4'b 0001, // index[139] ALERT_HANDLER_ALERT_EN_66 - 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_0 - 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_1 - 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_2 - 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_3 - 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_4 - 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_5 - 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_6 - 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_7 - 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_8 - 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_9 - 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_10 - 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_11 - 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_12 - 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_13 - 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_14 - 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_15 - 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_16 - 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_17 - 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_18 - 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_19 - 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_20 - 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_21 - 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_22 - 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_23 - 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_24 - 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_25 - 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_26 - 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_27 - 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_28 - 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_29 - 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_30 - 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_31 - 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_32 - 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_33 - 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_34 - 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_35 - 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_36 - 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_37 - 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_38 - 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_39 - 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_40 - 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_41 - 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_42 - 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_43 - 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_44 - 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_45 - 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_46 - 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_47 - 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_48 - 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_49 - 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_50 - 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_51 - 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_52 - 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_53 - 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_54 - 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_55 - 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_56 - 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_57 - 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_58 - 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_59 - 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_60 - 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CLASS_61 - 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CLASS_62 - 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CLASS_63 - 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CLASS_64 - 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CLASS_65 - 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CLASS_66 - 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_0 - 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_1 - 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_2 - 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_3 - 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_4 - 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_5 - 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_6 - 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_7 - 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_8 - 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_9 - 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_10 - 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_11 - 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_12 - 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_13 - 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_14 - 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_15 - 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_16 - 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_17 - 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_18 - 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_19 - 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_20 - 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_21 - 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_22 - 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_23 - 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_24 - 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_25 - 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_26 - 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_27 - 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_28 - 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_29 - 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_30 - 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_31 - 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_32 - 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_33 - 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_34 - 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_35 - 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_36 - 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_37 - 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_38 - 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_39 - 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_40 - 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_41 - 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_42 - 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_43 - 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_44 - 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_45 - 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_46 - 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_47 - 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_48 - 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_49 - 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_50 - 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_51 - 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_52 - 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_53 - 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_54 - 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_55 - 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_56 - 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_57 - 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_58 - 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CAUSE_59 - 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CAUSE_60 - 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CAUSE_61 - 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CAUSE_62 - 4'b 0001, // index[270] ALERT_HANDLER_ALERT_CAUSE_63 - 4'b 0001, // index[271] ALERT_HANDLER_ALERT_CAUSE_64 - 4'b 0001, // index[272] ALERT_HANDLER_ALERT_CAUSE_65 - 4'b 0001, // index[273] ALERT_HANDLER_ALERT_CAUSE_66 - 4'b 0001, // index[274] ALERT_HANDLER_LOC_ALERT_REGWEN_0 - 4'b 0001, // index[275] ALERT_HANDLER_LOC_ALERT_REGWEN_1 - 4'b 0001, // index[276] ALERT_HANDLER_LOC_ALERT_REGWEN_2 - 4'b 0001, // index[277] ALERT_HANDLER_LOC_ALERT_REGWEN_3 - 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_REGWEN_4 - 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_EN_0 - 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_EN_1 - 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_EN_2 - 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_EN_3 - 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_EN_4 - 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_CLASS_0 - 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_CLASS_1 - 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_CLASS_2 - 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_CLASS_3 - 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CLASS_4 - 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CAUSE_0 - 4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_CAUSE_1 - 4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_CAUSE_2 - 4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_CAUSE_3 - 4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_CAUSE_4 - 4'b 0001, // index[294] ALERT_HANDLER_CLASSA_REGWEN - 4'b 0011, // index[295] ALERT_HANDLER_CLASSA_CTRL - 4'b 0001, // index[296] ALERT_HANDLER_CLASSA_CLR_REGWEN - 4'b 0001, // index[297] ALERT_HANDLER_CLASSA_CLR - 4'b 0011, // index[298] ALERT_HANDLER_CLASSA_ACCUM_CNT - 4'b 0011, // index[299] ALERT_HANDLER_CLASSA_ACCUM_THRESH - 4'b 1111, // index[300] ALERT_HANDLER_CLASSA_TIMEOUT_CYC - 4'b 1111, // index[301] ALERT_HANDLER_CLASSA_PHASE0_CYC - 4'b 1111, // index[302] ALERT_HANDLER_CLASSA_PHASE1_CYC - 4'b 1111, // index[303] ALERT_HANDLER_CLASSA_PHASE2_CYC - 4'b 1111, // index[304] ALERT_HANDLER_CLASSA_PHASE3_CYC - 4'b 1111, // index[305] ALERT_HANDLER_CLASSA_ESC_CNT - 4'b 0001, // index[306] ALERT_HANDLER_CLASSA_STATE - 4'b 0001, // index[307] ALERT_HANDLER_CLASSB_REGWEN - 4'b 0011, // index[308] ALERT_HANDLER_CLASSB_CTRL - 4'b 0001, // index[309] ALERT_HANDLER_CLASSB_CLR_REGWEN - 4'b 0001, // index[310] ALERT_HANDLER_CLASSB_CLR - 4'b 0011, // index[311] ALERT_HANDLER_CLASSB_ACCUM_CNT - 4'b 0011, // index[312] ALERT_HANDLER_CLASSB_ACCUM_THRESH - 4'b 1111, // index[313] ALERT_HANDLER_CLASSB_TIMEOUT_CYC - 4'b 1111, // index[314] ALERT_HANDLER_CLASSB_PHASE0_CYC - 4'b 1111, // index[315] ALERT_HANDLER_CLASSB_PHASE1_CYC - 4'b 1111, // index[316] ALERT_HANDLER_CLASSB_PHASE2_CYC - 4'b 1111, // index[317] ALERT_HANDLER_CLASSB_PHASE3_CYC - 4'b 1111, // index[318] ALERT_HANDLER_CLASSB_ESC_CNT - 4'b 0001, // index[319] ALERT_HANDLER_CLASSB_STATE - 4'b 0001, // index[320] ALERT_HANDLER_CLASSC_REGWEN - 4'b 0011, // index[321] ALERT_HANDLER_CLASSC_CTRL - 4'b 0001, // index[322] ALERT_HANDLER_CLASSC_CLR_REGWEN - 4'b 0001, // index[323] ALERT_HANDLER_CLASSC_CLR - 4'b 0011, // index[324] ALERT_HANDLER_CLASSC_ACCUM_CNT - 4'b 0011, // index[325] ALERT_HANDLER_CLASSC_ACCUM_THRESH - 4'b 1111, // index[326] ALERT_HANDLER_CLASSC_TIMEOUT_CYC - 4'b 1111, // index[327] ALERT_HANDLER_CLASSC_PHASE0_CYC - 4'b 1111, // index[328] ALERT_HANDLER_CLASSC_PHASE1_CYC - 4'b 1111, // index[329] ALERT_HANDLER_CLASSC_PHASE2_CYC - 4'b 1111, // index[330] ALERT_HANDLER_CLASSC_PHASE3_CYC - 4'b 1111, // index[331] ALERT_HANDLER_CLASSC_ESC_CNT - 4'b 0001, // index[332] ALERT_HANDLER_CLASSC_STATE - 4'b 0001, // index[333] ALERT_HANDLER_CLASSD_REGWEN - 4'b 0011, // index[334] ALERT_HANDLER_CLASSD_CTRL - 4'b 0001, // index[335] ALERT_HANDLER_CLASSD_CLR_REGWEN - 4'b 0001, // index[336] ALERT_HANDLER_CLASSD_CLR - 4'b 0011, // index[337] ALERT_HANDLER_CLASSD_ACCUM_CNT - 4'b 0011, // index[338] ALERT_HANDLER_CLASSD_ACCUM_THRESH - 4'b 1111, // index[339] ALERT_HANDLER_CLASSD_TIMEOUT_CYC - 4'b 1111, // index[340] ALERT_HANDLER_CLASSD_PHASE0_CYC - 4'b 1111, // index[341] ALERT_HANDLER_CLASSD_PHASE1_CYC - 4'b 1111, // index[342] ALERT_HANDLER_CLASSD_PHASE2_CYC - 4'b 1111, // index[343] ALERT_HANDLER_CLASSD_PHASE3_CYC - 4'b 1111, // index[344] ALERT_HANDLER_CLASSD_ESC_CNT - 4'b 0001 // index[345] ALERT_HANDLER_CLASSD_STATE + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_REGWEN_67 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_0 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_1 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_2 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_3 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_4 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_5 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_6 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_7 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_8 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_9 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_10 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_11 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_12 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_13 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_14 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_15 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_16 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_17 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_18 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_19 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_20 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_21 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_22 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_23 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_24 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_25 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_26 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_27 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_28 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_29 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_30 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_31 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_32 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_33 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_34 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_35 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_36 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_37 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_38 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_39 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_40 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_41 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_42 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_43 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_44 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_45 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_46 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_47 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_48 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_49 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_50 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_51 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_52 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_53 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_54 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_55 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_56 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_57 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_58 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_59 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_60 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_61 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_62 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_63 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_EN_64 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_EN_65 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_EN_66 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_EN_67 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_0 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_1 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_2 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_3 + 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_4 + 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_5 + 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_6 + 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_7 + 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_8 + 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_9 + 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_10 + 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_11 + 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_12 + 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_13 + 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_14 + 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_15 + 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_16 + 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_17 + 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_18 + 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_19 + 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_20 + 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_21 + 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_22 + 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_23 + 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_24 + 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_25 + 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_26 + 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_27 + 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_28 + 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_29 + 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_30 + 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_31 + 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_32 + 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_33 + 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_34 + 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_35 + 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_36 + 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_37 + 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_38 + 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_39 + 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_40 + 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CLASS_41 + 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CLASS_42 + 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CLASS_43 + 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CLASS_44 + 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CLASS_45 + 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CLASS_46 + 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CLASS_47 + 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CLASS_48 + 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CLASS_49 + 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CLASS_50 + 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CLASS_51 + 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CLASS_52 + 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CLASS_53 + 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CLASS_54 + 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CLASS_55 + 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CLASS_56 + 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CLASS_57 + 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CLASS_58 + 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CLASS_59 + 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CLASS_60 + 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CLASS_61 + 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CLASS_62 + 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CLASS_63 + 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CLASS_64 + 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CLASS_65 + 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CLASS_66 + 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CLASS_67 + 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CAUSE_35 + 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CAUSE_36 + 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CAUSE_37 + 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CAUSE_38 + 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CAUSE_39 + 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CAUSE_40 + 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CAUSE_41 + 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CAUSE_42 + 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CAUSE_43 + 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CAUSE_44 + 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CAUSE_45 + 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CAUSE_46 + 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CAUSE_47 + 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CAUSE_48 + 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CAUSE_49 + 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CAUSE_50 + 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CAUSE_51 + 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CAUSE_52 + 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CAUSE_53 + 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CAUSE_54 + 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CAUSE_55 + 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CAUSE_56 + 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CAUSE_57 + 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CAUSE_58 + 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CAUSE_59 + 4'b 0001, // index[270] ALERT_HANDLER_ALERT_CAUSE_60 + 4'b 0001, // index[271] ALERT_HANDLER_ALERT_CAUSE_61 + 4'b 0001, // index[272] ALERT_HANDLER_ALERT_CAUSE_62 + 4'b 0001, // index[273] ALERT_HANDLER_ALERT_CAUSE_63 + 4'b 0001, // index[274] ALERT_HANDLER_ALERT_CAUSE_64 + 4'b 0001, // index[275] ALERT_HANDLER_ALERT_CAUSE_65 + 4'b 0001, // index[276] ALERT_HANDLER_ALERT_CAUSE_66 + 4'b 0001, // index[277] ALERT_HANDLER_ALERT_CAUSE_67 + 4'b 0001, // index[278] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[279] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[280] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[281] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[282] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[283] ALERT_HANDLER_LOC_ALERT_EN_0 + 4'b 0001, // index[284] ALERT_HANDLER_LOC_ALERT_EN_1 + 4'b 0001, // index[285] ALERT_HANDLER_LOC_ALERT_EN_2 + 4'b 0001, // index[286] ALERT_HANDLER_LOC_ALERT_EN_3 + 4'b 0001, // index[287] ALERT_HANDLER_LOC_ALERT_EN_4 + 4'b 0001, // index[288] ALERT_HANDLER_LOC_ALERT_CLASS_0 + 4'b 0001, // index[289] ALERT_HANDLER_LOC_ALERT_CLASS_1 + 4'b 0001, // index[290] ALERT_HANDLER_LOC_ALERT_CLASS_2 + 4'b 0001, // index[291] ALERT_HANDLER_LOC_ALERT_CLASS_3 + 4'b 0001, // index[292] ALERT_HANDLER_LOC_ALERT_CLASS_4 + 4'b 0001, // index[293] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[294] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[295] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[296] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[297] ALERT_HANDLER_LOC_ALERT_CAUSE_4 + 4'b 0001, // index[298] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[299] ALERT_HANDLER_CLASSA_CTRL + 4'b 0001, // index[300] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[301] ALERT_HANDLER_CLASSA_CLR + 4'b 0011, // index[302] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[303] ALERT_HANDLER_CLASSA_ACCUM_THRESH + 4'b 1111, // index[304] ALERT_HANDLER_CLASSA_TIMEOUT_CYC + 4'b 1111, // index[305] ALERT_HANDLER_CLASSA_PHASE0_CYC + 4'b 1111, // index[306] ALERT_HANDLER_CLASSA_PHASE1_CYC + 4'b 1111, // index[307] ALERT_HANDLER_CLASSA_PHASE2_CYC + 4'b 1111, // index[308] ALERT_HANDLER_CLASSA_PHASE3_CYC + 4'b 1111, // index[309] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[310] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[311] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[312] ALERT_HANDLER_CLASSB_CTRL + 4'b 0001, // index[313] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[314] ALERT_HANDLER_CLASSB_CLR + 4'b 0011, // index[315] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[316] ALERT_HANDLER_CLASSB_ACCUM_THRESH + 4'b 1111, // index[317] ALERT_HANDLER_CLASSB_TIMEOUT_CYC + 4'b 1111, // index[318] ALERT_HANDLER_CLASSB_PHASE0_CYC + 4'b 1111, // index[319] ALERT_HANDLER_CLASSB_PHASE1_CYC + 4'b 1111, // index[320] ALERT_HANDLER_CLASSB_PHASE2_CYC + 4'b 1111, // index[321] ALERT_HANDLER_CLASSB_PHASE3_CYC + 4'b 1111, // index[322] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[323] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[324] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[325] ALERT_HANDLER_CLASSC_CTRL + 4'b 0001, // index[326] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[327] ALERT_HANDLER_CLASSC_CLR + 4'b 0011, // index[328] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[329] ALERT_HANDLER_CLASSC_ACCUM_THRESH + 4'b 1111, // index[330] ALERT_HANDLER_CLASSC_TIMEOUT_CYC + 4'b 1111, // index[331] ALERT_HANDLER_CLASSC_PHASE0_CYC + 4'b 1111, // index[332] ALERT_HANDLER_CLASSC_PHASE1_CYC + 4'b 1111, // index[333] ALERT_HANDLER_CLASSC_PHASE2_CYC + 4'b 1111, // index[334] ALERT_HANDLER_CLASSC_PHASE3_CYC + 4'b 1111, // index[335] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[336] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[337] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[338] ALERT_HANDLER_CLASSD_CTRL + 4'b 0001, // index[339] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[340] ALERT_HANDLER_CLASSD_CLR + 4'b 0011, // index[341] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[342] ALERT_HANDLER_CLASSD_ACCUM_THRESH + 4'b 1111, // index[343] ALERT_HANDLER_CLASSD_TIMEOUT_CYC + 4'b 1111, // index[344] ALERT_HANDLER_CLASSD_PHASE0_CYC + 4'b 1111, // index[345] ALERT_HANDLER_CLASSD_PHASE1_CYC + 4'b 1111, // index[346] ALERT_HANDLER_CLASSD_PHASE2_CYC + 4'b 1111, // index[347] ALERT_HANDLER_CLASSD_PHASE3_CYC + 4'b 1111, // index[348] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[349] ALERT_HANDLER_CLASSD_STATE }; endpackage
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv index 084c881..494e0d9 100644 --- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv +++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -337,6 +337,9 @@ logic alert_regwen_66_we; logic alert_regwen_66_qs; logic alert_regwen_66_wd; + logic alert_regwen_67_we; + logic alert_regwen_67_qs; + logic alert_regwen_67_wd; logic alert_en_0_we; logic alert_en_0_qs; logic alert_en_0_wd; @@ -538,6 +541,9 @@ logic alert_en_66_we; logic alert_en_66_qs; logic alert_en_66_wd; + logic alert_en_67_we; + logic alert_en_67_qs; + logic alert_en_67_wd; logic alert_class_0_we; logic [1:0] alert_class_0_qs; logic [1:0] alert_class_0_wd; @@ -739,6 +745,9 @@ logic alert_class_66_we; logic [1:0] alert_class_66_qs; logic [1:0] alert_class_66_wd; + logic alert_class_67_we; + logic [1:0] alert_class_67_qs; + logic [1:0] alert_class_67_wd; logic alert_cause_0_we; logic alert_cause_0_qs; logic alert_cause_0_wd; @@ -940,6 +949,9 @@ logic alert_cause_66_we; logic alert_cause_66_qs; logic alert_cause_66_wd; + logic alert_cause_67_we; + logic alert_cause_67_qs; + logic alert_cause_67_wd; logic loc_alert_regwen_0_we; logic loc_alert_regwen_0_qs; logic loc_alert_regwen_0_wd; @@ -3379,6 +3391,33 @@ .qs (alert_regwen_66_qs) ); + // Subregister 67 of Multireg alert_regwen + // R[alert_regwen_67]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_alert_regwen_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_67_we), + .wd (alert_regwen_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[67].q), + + // to register interface (read) + .qs (alert_regwen_67_qs) + ); + // Subregister 0 of Multireg alert_en @@ -5190,6 +5229,33 @@ .qs (alert_en_66_qs) ); + // Subregister 67 of Multireg alert_en + // R[alert_en_67]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_en_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_en_67_we & alert_regwen_67_qs), + .wd (alert_en_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en[67].q), + + // to register interface (read) + .qs (alert_en_67_qs) + ); + // Subregister 0 of Multireg alert_class @@ -7001,6 +7067,33 @@ .qs (alert_class_66_qs) ); + // Subregister 67 of Multireg alert_class + // R[alert_class_67]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_alert_class_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_class_67_we & alert_regwen_67_qs), + .wd (alert_class_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class[67].q), + + // to register interface (read) + .qs (alert_class_67_qs) + ); + // Subregister 0 of Multireg alert_cause @@ -8812,6 +8905,33 @@ .qs (alert_cause_66_qs) ); + // Subregister 67 of Multireg alert_cause + // R[alert_cause_67]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_cause_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_67_we), + .wd (alert_cause_67_wd), + + // from internal hardware + .de (hw2reg.alert_cause[67].de), + .d (hw2reg.alert_cause[67].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[67].q), + + // to register interface (read) + .qs (alert_cause_67_qs) + ); + // Subregister 0 of Multireg loc_alert_regwen @@ -11575,7 +11695,7 @@ - logic [345:0] addr_hit; + logic [349:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET); @@ -11651,279 +11771,283 @@ addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET); addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_65_OFFSET); addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_66_OFFSET); - addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET); - addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET); - addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET); - addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET); - addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET); - addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET); - addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET); - addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET); - addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET); - addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET); - addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET); - addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET); - addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET); - addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET); - addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET); - addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET); - addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET); - addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET); - addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET); - addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET); - addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET); - addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET); - addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET); - addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET); - addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET); - addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET); - addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET); - addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET); - addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET); - addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET); - addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET); - addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET); - addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET); - addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET); - addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET); - addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET); - addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET); - addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET); - addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET); - addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET); - addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET); - addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET); - addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET); - addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_43_OFFSET); - addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_44_OFFSET); - addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_45_OFFSET); - addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_46_OFFSET); - addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_47_OFFSET); - addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_48_OFFSET); - addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_49_OFFSET); - addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_50_OFFSET); - addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_51_OFFSET); - addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_52_OFFSET); - addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_53_OFFSET); - addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_54_OFFSET); - addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_55_OFFSET); - addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_56_OFFSET); - addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_57_OFFSET); - addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_58_OFFSET); - addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_59_OFFSET); - addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_60_OFFSET); - addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_61_OFFSET); - addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_62_OFFSET); - addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_63_OFFSET); - addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_64_OFFSET); - addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_EN_65_OFFSET); - addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_EN_66_OFFSET); - addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET); - addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET); - addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET); - addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET); - addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET); - addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET); - addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET); - addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET); - addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET); - addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET); - addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET); - addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET); - addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET); - addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET); - addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET); - addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET); - addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET); - addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET); - addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET); - addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET); - addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET); - addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET); - addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET); - addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET); - addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET); - addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET); - addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET); - addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET); - addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET); - addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET); - addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET); - addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET); - addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET); - addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET); - addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET); - addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET); - addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET); - addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET); - addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET); - addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET); - addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET); - addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET); - addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET); - addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_43_OFFSET); - addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_44_OFFSET); - addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_45_OFFSET); - addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_46_OFFSET); - addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_47_OFFSET); - addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_48_OFFSET); - addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_49_OFFSET); - addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_50_OFFSET); - addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_51_OFFSET); - addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_52_OFFSET); - addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_53_OFFSET); - addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_54_OFFSET); - addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_55_OFFSET); - addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_56_OFFSET); - addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_57_OFFSET); - addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_58_OFFSET); - addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_59_OFFSET); - addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_60_OFFSET); - addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_61_OFFSET); - addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_62_OFFSET); - addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_63_OFFSET); - addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_64_OFFSET); - addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_65_OFFSET); - addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_66_OFFSET); - addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); - addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); - addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); - addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); - addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); - addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); - addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); - addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); - addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); - addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); - addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); - addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); - addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); - addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); - addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); - addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); - addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); - addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); - addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); - addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); - addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); - addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); - addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); - addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); - addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); - addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); - addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); - addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); - addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); - addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); - addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); - addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); - addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); - addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); - addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); - addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); - addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); - addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); - addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); - addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); - addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); - addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); - addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); - addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); - addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); - addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); - addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); - addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); - addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); - addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); - addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); - addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); - addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); - addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); - addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); - addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); - addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); - addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); - addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); - addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); - addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); - addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); - addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); - addr_hit[270] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); - addr_hit[271] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); - addr_hit[272] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET); - addr_hit[273] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_66_OFFSET); - addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); - addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); - addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); - addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); - addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); - addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET); - addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET); - addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET); - addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET); - addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET); - addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET); - addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET); - addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET); - addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET); - addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET); - addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); - addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); - addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); - addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); - addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); - addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); - addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET); - addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); - addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET); - addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); - addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET); - addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET); - addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET); - addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET); - addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET); - addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET); - addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); - addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); - addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); - addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET); - addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); - addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET); - addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); - addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET); - addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET); - addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET); - addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET); - addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET); - addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET); - addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); - addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); - addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); - addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET); - addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); - addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET); - addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); - addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET); - addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET); - addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET); - addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET); - addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET); - addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET); - addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); - addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); - addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); - addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET); - addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); - addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET); - addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); - addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET); - addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET); - addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET); - addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET); - addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET); - addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET); - addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); - addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); + addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_67_OFFSET); + addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET); + addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET); + addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET); + addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET); + addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET); + addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET); + addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET); + addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET); + addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET); + addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET); + addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET); + addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET); + addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET); + addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET); + addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET); + addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET); + addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET); + addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET); + addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET); + addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET); + addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET); + addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET); + addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET); + addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET); + addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET); + addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET); + addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET); + addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET); + addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET); + addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET); + addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET); + addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET); + addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET); + addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET); + addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET); + addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET); + addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET); + addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET); + addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET); + addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET); + addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET); + addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_41_OFFSET); + addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_42_OFFSET); + addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_43_OFFSET); + addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_44_OFFSET); + addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_45_OFFSET); + addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_46_OFFSET); + addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_47_OFFSET); + addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_48_OFFSET); + addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_49_OFFSET); + addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_50_OFFSET); + addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_51_OFFSET); + addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_52_OFFSET); + addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_53_OFFSET); + addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_54_OFFSET); + addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_55_OFFSET); + addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_56_OFFSET); + addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_57_OFFSET); + addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_58_OFFSET); + addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_59_OFFSET); + addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_60_OFFSET); + addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_61_OFFSET); + addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_62_OFFSET); + addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_63_OFFSET); + addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_EN_64_OFFSET); + addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_EN_65_OFFSET); + addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_EN_66_OFFSET); + addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_EN_67_OFFSET); + addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET); + addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET); + addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET); + addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET); + addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET); + addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET); + addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET); + addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET); + addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET); + addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET); + addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET); + addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET); + addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET); + addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET); + addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET); + addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET); + addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET); + addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET); + addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET); + addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET); + addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET); + addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET); + addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET); + addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET); + addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET); + addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET); + addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET); + addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET); + addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET); + addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET); + addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET); + addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET); + addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET); + addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET); + addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET); + addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET); + addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET); + addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET); + addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET); + addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET); + addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET); + addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_41_OFFSET); + addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_42_OFFSET); + addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_43_OFFSET); + addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_44_OFFSET); + addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_45_OFFSET); + addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_46_OFFSET); + addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_47_OFFSET); + addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_48_OFFSET); + addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_49_OFFSET); + addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_50_OFFSET); + addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_51_OFFSET); + addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_52_OFFSET); + addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_53_OFFSET); + addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_54_OFFSET); + addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_55_OFFSET); + addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_56_OFFSET); + addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_57_OFFSET); + addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_58_OFFSET); + addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_59_OFFSET); + addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_60_OFFSET); + addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_61_OFFSET); + addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_62_OFFSET); + addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_63_OFFSET); + addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_64_OFFSET); + addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_65_OFFSET); + addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_66_OFFSET); + addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_67_OFFSET); + addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); + addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); + addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); + addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); + addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); + addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); + addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); + addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); + addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); + addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); + addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); + addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); + addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); + addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); + addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); + addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); + addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); + addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); + addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); + addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); + addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); + addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); + addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); + addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); + addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); + addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); + addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); + addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); + addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); + addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); + addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); + addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); + addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); + addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); + addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); + addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); + addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); + addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); + addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); + addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); + addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); + addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); + addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); + addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); + addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); + addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); + addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); + addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); + addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); + addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); + addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); + addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); + addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); + addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); + addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); + addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); + addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); + addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); + addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); + addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); + addr_hit[270] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); + addr_hit[271] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); + addr_hit[272] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); + addr_hit[273] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); + addr_hit[274] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); + addr_hit[275] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET); + addr_hit[276] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_66_OFFSET); + addr_hit[277] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_67_OFFSET); + addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); + addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); + addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); + addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); + addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); + addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET); + addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET); + addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET); + addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET); + addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET); + addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET); + addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET); + addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET); + addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET); + addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET); + addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); + addr_hit[294] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); + addr_hit[295] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); + addr_hit[296] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); + addr_hit[297] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); + addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); + addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET); + addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); + addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET); + addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); + addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET); + addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET); + addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET); + addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET); + addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET); + addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET); + addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); + addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); + addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); + addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET); + addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); + addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET); + addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); + addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET); + addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET); + addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET); + addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET); + addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET); + addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET); + addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); + addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); + addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); + addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET); + addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); + addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET); + addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); + addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET); + addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET); + addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET); + addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET); + addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET); + addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET); + addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); + addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); + addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); + addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET); + addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); + addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET); + addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); + addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET); + addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET); + addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET); + addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET); + addr_hit[346] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET); + addr_hit[347] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET); + addr_hit[348] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); + addr_hit[349] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -12276,7 +12400,11 @@ (addr_hit[342] & (|(ALERT_HANDLER_PERMIT[342] & ~reg_be))) | (addr_hit[343] & (|(ALERT_HANDLER_PERMIT[343] & ~reg_be))) | (addr_hit[344] & (|(ALERT_HANDLER_PERMIT[344] & ~reg_be))) | - (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))))); + (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))) | + (addr_hit[346] & (|(ALERT_HANDLER_PERMIT[346] & ~reg_be))) | + (addr_hit[347] & (|(ALERT_HANDLER_PERMIT[347] & ~reg_be))) | + (addr_hit[348] & (|(ALERT_HANDLER_PERMIT[348] & ~reg_be))) | + (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be))))); end assign intr_state_we = addr_hit[0] & reg_we & !reg_error; @@ -12515,673 +12643,685 @@ assign alert_regwen_66_we = addr_hit[72] & reg_we & !reg_error; assign alert_regwen_66_wd = reg_wdata[0]; - assign alert_en_0_we = addr_hit[73] & reg_we & !reg_error; + assign alert_regwen_67_we = addr_hit[73] & reg_we & !reg_error; + + assign alert_regwen_67_wd = reg_wdata[0]; + assign alert_en_0_we = addr_hit[74] & reg_we & !reg_error; assign alert_en_0_wd = reg_wdata[0]; - assign alert_en_1_we = addr_hit[74] & reg_we & !reg_error; + assign alert_en_1_we = addr_hit[75] & reg_we & !reg_error; assign alert_en_1_wd = reg_wdata[0]; - assign alert_en_2_we = addr_hit[75] & reg_we & !reg_error; + assign alert_en_2_we = addr_hit[76] & reg_we & !reg_error; assign alert_en_2_wd = reg_wdata[0]; - assign alert_en_3_we = addr_hit[76] & reg_we & !reg_error; + assign alert_en_3_we = addr_hit[77] & reg_we & !reg_error; assign alert_en_3_wd = reg_wdata[0]; - assign alert_en_4_we = addr_hit[77] & reg_we & !reg_error; + assign alert_en_4_we = addr_hit[78] & reg_we & !reg_error; assign alert_en_4_wd = reg_wdata[0]; - assign alert_en_5_we = addr_hit[78] & reg_we & !reg_error; + assign alert_en_5_we = addr_hit[79] & reg_we & !reg_error; assign alert_en_5_wd = reg_wdata[0]; - assign alert_en_6_we = addr_hit[79] & reg_we & !reg_error; + assign alert_en_6_we = addr_hit[80] & reg_we & !reg_error; assign alert_en_6_wd = reg_wdata[0]; - assign alert_en_7_we = addr_hit[80] & reg_we & !reg_error; + assign alert_en_7_we = addr_hit[81] & reg_we & !reg_error; assign alert_en_7_wd = reg_wdata[0]; - assign alert_en_8_we = addr_hit[81] & reg_we & !reg_error; + assign alert_en_8_we = addr_hit[82] & reg_we & !reg_error; assign alert_en_8_wd = reg_wdata[0]; - assign alert_en_9_we = addr_hit[82] & reg_we & !reg_error; + assign alert_en_9_we = addr_hit[83] & reg_we & !reg_error; assign alert_en_9_wd = reg_wdata[0]; - assign alert_en_10_we = addr_hit[83] & reg_we & !reg_error; + assign alert_en_10_we = addr_hit[84] & reg_we & !reg_error; assign alert_en_10_wd = reg_wdata[0]; - assign alert_en_11_we = addr_hit[84] & reg_we & !reg_error; + assign alert_en_11_we = addr_hit[85] & reg_we & !reg_error; assign alert_en_11_wd = reg_wdata[0]; - assign alert_en_12_we = addr_hit[85] & reg_we & !reg_error; + assign alert_en_12_we = addr_hit[86] & reg_we & !reg_error; assign alert_en_12_wd = reg_wdata[0]; - assign alert_en_13_we = addr_hit[86] & reg_we & !reg_error; + assign alert_en_13_we = addr_hit[87] & reg_we & !reg_error; assign alert_en_13_wd = reg_wdata[0]; - assign alert_en_14_we = addr_hit[87] & reg_we & !reg_error; + assign alert_en_14_we = addr_hit[88] & reg_we & !reg_error; assign alert_en_14_wd = reg_wdata[0]; - assign alert_en_15_we = addr_hit[88] & reg_we & !reg_error; + assign alert_en_15_we = addr_hit[89] & reg_we & !reg_error; assign alert_en_15_wd = reg_wdata[0]; - assign alert_en_16_we = addr_hit[89] & reg_we & !reg_error; + assign alert_en_16_we = addr_hit[90] & reg_we & !reg_error; assign alert_en_16_wd = reg_wdata[0]; - assign alert_en_17_we = addr_hit[90] & reg_we & !reg_error; + assign alert_en_17_we = addr_hit[91] & reg_we & !reg_error; assign alert_en_17_wd = reg_wdata[0]; - assign alert_en_18_we = addr_hit[91] & reg_we & !reg_error; + assign alert_en_18_we = addr_hit[92] & reg_we & !reg_error; assign alert_en_18_wd = reg_wdata[0]; - assign alert_en_19_we = addr_hit[92] & reg_we & !reg_error; + assign alert_en_19_we = addr_hit[93] & reg_we & !reg_error; assign alert_en_19_wd = reg_wdata[0]; - assign alert_en_20_we = addr_hit[93] & reg_we & !reg_error; + assign alert_en_20_we = addr_hit[94] & reg_we & !reg_error; assign alert_en_20_wd = reg_wdata[0]; - assign alert_en_21_we = addr_hit[94] & reg_we & !reg_error; + assign alert_en_21_we = addr_hit[95] & reg_we & !reg_error; assign alert_en_21_wd = reg_wdata[0]; - assign alert_en_22_we = addr_hit[95] & reg_we & !reg_error; + assign alert_en_22_we = addr_hit[96] & reg_we & !reg_error; assign alert_en_22_wd = reg_wdata[0]; - assign alert_en_23_we = addr_hit[96] & reg_we & !reg_error; + assign alert_en_23_we = addr_hit[97] & reg_we & !reg_error; assign alert_en_23_wd = reg_wdata[0]; - assign alert_en_24_we = addr_hit[97] & reg_we & !reg_error; + assign alert_en_24_we = addr_hit[98] & reg_we & !reg_error; assign alert_en_24_wd = reg_wdata[0]; - assign alert_en_25_we = addr_hit[98] & reg_we & !reg_error; + assign alert_en_25_we = addr_hit[99] & reg_we & !reg_error; assign alert_en_25_wd = reg_wdata[0]; - assign alert_en_26_we = addr_hit[99] & reg_we & !reg_error; + assign alert_en_26_we = addr_hit[100] & reg_we & !reg_error; assign alert_en_26_wd = reg_wdata[0]; - assign alert_en_27_we = addr_hit[100] & reg_we & !reg_error; + assign alert_en_27_we = addr_hit[101] & reg_we & !reg_error; assign alert_en_27_wd = reg_wdata[0]; - assign alert_en_28_we = addr_hit[101] & reg_we & !reg_error; + assign alert_en_28_we = addr_hit[102] & reg_we & !reg_error; assign alert_en_28_wd = reg_wdata[0]; - assign alert_en_29_we = addr_hit[102] & reg_we & !reg_error; + assign alert_en_29_we = addr_hit[103] & reg_we & !reg_error; assign alert_en_29_wd = reg_wdata[0]; - assign alert_en_30_we = addr_hit[103] & reg_we & !reg_error; + assign alert_en_30_we = addr_hit[104] & reg_we & !reg_error; assign alert_en_30_wd = reg_wdata[0]; - assign alert_en_31_we = addr_hit[104] & reg_we & !reg_error; + assign alert_en_31_we = addr_hit[105] & reg_we & !reg_error; assign alert_en_31_wd = reg_wdata[0]; - assign alert_en_32_we = addr_hit[105] & reg_we & !reg_error; + assign alert_en_32_we = addr_hit[106] & reg_we & !reg_error; assign alert_en_32_wd = reg_wdata[0]; - assign alert_en_33_we = addr_hit[106] & reg_we & !reg_error; + assign alert_en_33_we = addr_hit[107] & reg_we & !reg_error; assign alert_en_33_wd = reg_wdata[0]; - assign alert_en_34_we = addr_hit[107] & reg_we & !reg_error; + assign alert_en_34_we = addr_hit[108] & reg_we & !reg_error; assign alert_en_34_wd = reg_wdata[0]; - assign alert_en_35_we = addr_hit[108] & reg_we & !reg_error; + assign alert_en_35_we = addr_hit[109] & reg_we & !reg_error; assign alert_en_35_wd = reg_wdata[0]; - assign alert_en_36_we = addr_hit[109] & reg_we & !reg_error; + assign alert_en_36_we = addr_hit[110] & reg_we & !reg_error; assign alert_en_36_wd = reg_wdata[0]; - assign alert_en_37_we = addr_hit[110] & reg_we & !reg_error; + assign alert_en_37_we = addr_hit[111] & reg_we & !reg_error; assign alert_en_37_wd = reg_wdata[0]; - assign alert_en_38_we = addr_hit[111] & reg_we & !reg_error; + assign alert_en_38_we = addr_hit[112] & reg_we & !reg_error; assign alert_en_38_wd = reg_wdata[0]; - assign alert_en_39_we = addr_hit[112] & reg_we & !reg_error; + assign alert_en_39_we = addr_hit[113] & reg_we & !reg_error; assign alert_en_39_wd = reg_wdata[0]; - assign alert_en_40_we = addr_hit[113] & reg_we & !reg_error; + assign alert_en_40_we = addr_hit[114] & reg_we & !reg_error; assign alert_en_40_wd = reg_wdata[0]; - assign alert_en_41_we = addr_hit[114] & reg_we & !reg_error; + assign alert_en_41_we = addr_hit[115] & reg_we & !reg_error; assign alert_en_41_wd = reg_wdata[0]; - assign alert_en_42_we = addr_hit[115] & reg_we & !reg_error; + assign alert_en_42_we = addr_hit[116] & reg_we & !reg_error; assign alert_en_42_wd = reg_wdata[0]; - assign alert_en_43_we = addr_hit[116] & reg_we & !reg_error; + assign alert_en_43_we = addr_hit[117] & reg_we & !reg_error; assign alert_en_43_wd = reg_wdata[0]; - assign alert_en_44_we = addr_hit[117] & reg_we & !reg_error; + assign alert_en_44_we = addr_hit[118] & reg_we & !reg_error; assign alert_en_44_wd = reg_wdata[0]; - assign alert_en_45_we = addr_hit[118] & reg_we & !reg_error; + assign alert_en_45_we = addr_hit[119] & reg_we & !reg_error; assign alert_en_45_wd = reg_wdata[0]; - assign alert_en_46_we = addr_hit[119] & reg_we & !reg_error; + assign alert_en_46_we = addr_hit[120] & reg_we & !reg_error; assign alert_en_46_wd = reg_wdata[0]; - assign alert_en_47_we = addr_hit[120] & reg_we & !reg_error; + assign alert_en_47_we = addr_hit[121] & reg_we & !reg_error; assign alert_en_47_wd = reg_wdata[0]; - assign alert_en_48_we = addr_hit[121] & reg_we & !reg_error; + assign alert_en_48_we = addr_hit[122] & reg_we & !reg_error; assign alert_en_48_wd = reg_wdata[0]; - assign alert_en_49_we = addr_hit[122] & reg_we & !reg_error; + assign alert_en_49_we = addr_hit[123] & reg_we & !reg_error; assign alert_en_49_wd = reg_wdata[0]; - assign alert_en_50_we = addr_hit[123] & reg_we & !reg_error; + assign alert_en_50_we = addr_hit[124] & reg_we & !reg_error; assign alert_en_50_wd = reg_wdata[0]; - assign alert_en_51_we = addr_hit[124] & reg_we & !reg_error; + assign alert_en_51_we = addr_hit[125] & reg_we & !reg_error; assign alert_en_51_wd = reg_wdata[0]; - assign alert_en_52_we = addr_hit[125] & reg_we & !reg_error; + assign alert_en_52_we = addr_hit[126] & reg_we & !reg_error; assign alert_en_52_wd = reg_wdata[0]; - assign alert_en_53_we = addr_hit[126] & reg_we & !reg_error; + assign alert_en_53_we = addr_hit[127] & reg_we & !reg_error; assign alert_en_53_wd = reg_wdata[0]; - assign alert_en_54_we = addr_hit[127] & reg_we & !reg_error; + assign alert_en_54_we = addr_hit[128] & reg_we & !reg_error; assign alert_en_54_wd = reg_wdata[0]; - assign alert_en_55_we = addr_hit[128] & reg_we & !reg_error; + assign alert_en_55_we = addr_hit[129] & reg_we & !reg_error; assign alert_en_55_wd = reg_wdata[0]; - assign alert_en_56_we = addr_hit[129] & reg_we & !reg_error; + assign alert_en_56_we = addr_hit[130] & reg_we & !reg_error; assign alert_en_56_wd = reg_wdata[0]; - assign alert_en_57_we = addr_hit[130] & reg_we & !reg_error; + assign alert_en_57_we = addr_hit[131] & reg_we & !reg_error; assign alert_en_57_wd = reg_wdata[0]; - assign alert_en_58_we = addr_hit[131] & reg_we & !reg_error; + assign alert_en_58_we = addr_hit[132] & reg_we & !reg_error; assign alert_en_58_wd = reg_wdata[0]; - assign alert_en_59_we = addr_hit[132] & reg_we & !reg_error; + assign alert_en_59_we = addr_hit[133] & reg_we & !reg_error; assign alert_en_59_wd = reg_wdata[0]; - assign alert_en_60_we = addr_hit[133] & reg_we & !reg_error; + assign alert_en_60_we = addr_hit[134] & reg_we & !reg_error; assign alert_en_60_wd = reg_wdata[0]; - assign alert_en_61_we = addr_hit[134] & reg_we & !reg_error; + assign alert_en_61_we = addr_hit[135] & reg_we & !reg_error; assign alert_en_61_wd = reg_wdata[0]; - assign alert_en_62_we = addr_hit[135] & reg_we & !reg_error; + assign alert_en_62_we = addr_hit[136] & reg_we & !reg_error; assign alert_en_62_wd = reg_wdata[0]; - assign alert_en_63_we = addr_hit[136] & reg_we & !reg_error; + assign alert_en_63_we = addr_hit[137] & reg_we & !reg_error; assign alert_en_63_wd = reg_wdata[0]; - assign alert_en_64_we = addr_hit[137] & reg_we & !reg_error; + assign alert_en_64_we = addr_hit[138] & reg_we & !reg_error; assign alert_en_64_wd = reg_wdata[0]; - assign alert_en_65_we = addr_hit[138] & reg_we & !reg_error; + assign alert_en_65_we = addr_hit[139] & reg_we & !reg_error; assign alert_en_65_wd = reg_wdata[0]; - assign alert_en_66_we = addr_hit[139] & reg_we & !reg_error; + assign alert_en_66_we = addr_hit[140] & reg_we & !reg_error; assign alert_en_66_wd = reg_wdata[0]; - assign alert_class_0_we = addr_hit[140] & reg_we & !reg_error; + assign alert_en_67_we = addr_hit[141] & reg_we & !reg_error; + + assign alert_en_67_wd = reg_wdata[0]; + assign alert_class_0_we = addr_hit[142] & reg_we & !reg_error; assign alert_class_0_wd = reg_wdata[1:0]; - assign alert_class_1_we = addr_hit[141] & reg_we & !reg_error; + assign alert_class_1_we = addr_hit[143] & reg_we & !reg_error; assign alert_class_1_wd = reg_wdata[1:0]; - assign alert_class_2_we = addr_hit[142] & reg_we & !reg_error; + assign alert_class_2_we = addr_hit[144] & reg_we & !reg_error; assign alert_class_2_wd = reg_wdata[1:0]; - assign alert_class_3_we = addr_hit[143] & reg_we & !reg_error; + assign alert_class_3_we = addr_hit[145] & reg_we & !reg_error; assign alert_class_3_wd = reg_wdata[1:0]; - assign alert_class_4_we = addr_hit[144] & reg_we & !reg_error; + assign alert_class_4_we = addr_hit[146] & reg_we & !reg_error; assign alert_class_4_wd = reg_wdata[1:0]; - assign alert_class_5_we = addr_hit[145] & reg_we & !reg_error; + assign alert_class_5_we = addr_hit[147] & reg_we & !reg_error; assign alert_class_5_wd = reg_wdata[1:0]; - assign alert_class_6_we = addr_hit[146] & reg_we & !reg_error; + assign alert_class_6_we = addr_hit[148] & reg_we & !reg_error; assign alert_class_6_wd = reg_wdata[1:0]; - assign alert_class_7_we = addr_hit[147] & reg_we & !reg_error; + assign alert_class_7_we = addr_hit[149] & reg_we & !reg_error; assign alert_class_7_wd = reg_wdata[1:0]; - assign alert_class_8_we = addr_hit[148] & reg_we & !reg_error; + assign alert_class_8_we = addr_hit[150] & reg_we & !reg_error; assign alert_class_8_wd = reg_wdata[1:0]; - assign alert_class_9_we = addr_hit[149] & reg_we & !reg_error; + assign alert_class_9_we = addr_hit[151] & reg_we & !reg_error; assign alert_class_9_wd = reg_wdata[1:0]; - assign alert_class_10_we = addr_hit[150] & reg_we & !reg_error; + assign alert_class_10_we = addr_hit[152] & reg_we & !reg_error; assign alert_class_10_wd = reg_wdata[1:0]; - assign alert_class_11_we = addr_hit[151] & reg_we & !reg_error; + assign alert_class_11_we = addr_hit[153] & reg_we & !reg_error; assign alert_class_11_wd = reg_wdata[1:0]; - assign alert_class_12_we = addr_hit[152] & reg_we & !reg_error; + assign alert_class_12_we = addr_hit[154] & reg_we & !reg_error; assign alert_class_12_wd = reg_wdata[1:0]; - assign alert_class_13_we = addr_hit[153] & reg_we & !reg_error; + assign alert_class_13_we = addr_hit[155] & reg_we & !reg_error; assign alert_class_13_wd = reg_wdata[1:0]; - assign alert_class_14_we = addr_hit[154] & reg_we & !reg_error; + assign alert_class_14_we = addr_hit[156] & reg_we & !reg_error; assign alert_class_14_wd = reg_wdata[1:0]; - assign alert_class_15_we = addr_hit[155] & reg_we & !reg_error; + assign alert_class_15_we = addr_hit[157] & reg_we & !reg_error; assign alert_class_15_wd = reg_wdata[1:0]; - assign alert_class_16_we = addr_hit[156] & reg_we & !reg_error; + assign alert_class_16_we = addr_hit[158] & reg_we & !reg_error; assign alert_class_16_wd = reg_wdata[1:0]; - assign alert_class_17_we = addr_hit[157] & reg_we & !reg_error; + assign alert_class_17_we = addr_hit[159] & reg_we & !reg_error; assign alert_class_17_wd = reg_wdata[1:0]; - assign alert_class_18_we = addr_hit[158] & reg_we & !reg_error; + assign alert_class_18_we = addr_hit[160] & reg_we & !reg_error; assign alert_class_18_wd = reg_wdata[1:0]; - assign alert_class_19_we = addr_hit[159] & reg_we & !reg_error; + assign alert_class_19_we = addr_hit[161] & reg_we & !reg_error; assign alert_class_19_wd = reg_wdata[1:0]; - assign alert_class_20_we = addr_hit[160] & reg_we & !reg_error; + assign alert_class_20_we = addr_hit[162] & reg_we & !reg_error; assign alert_class_20_wd = reg_wdata[1:0]; - assign alert_class_21_we = addr_hit[161] & reg_we & !reg_error; + assign alert_class_21_we = addr_hit[163] & reg_we & !reg_error; assign alert_class_21_wd = reg_wdata[1:0]; - assign alert_class_22_we = addr_hit[162] & reg_we & !reg_error; + assign alert_class_22_we = addr_hit[164] & reg_we & !reg_error; assign alert_class_22_wd = reg_wdata[1:0]; - assign alert_class_23_we = addr_hit[163] & reg_we & !reg_error; + assign alert_class_23_we = addr_hit[165] & reg_we & !reg_error; assign alert_class_23_wd = reg_wdata[1:0]; - assign alert_class_24_we = addr_hit[164] & reg_we & !reg_error; + assign alert_class_24_we = addr_hit[166] & reg_we & !reg_error; assign alert_class_24_wd = reg_wdata[1:0]; - assign alert_class_25_we = addr_hit[165] & reg_we & !reg_error; + assign alert_class_25_we = addr_hit[167] & reg_we & !reg_error; assign alert_class_25_wd = reg_wdata[1:0]; - assign alert_class_26_we = addr_hit[166] & reg_we & !reg_error; + assign alert_class_26_we = addr_hit[168] & reg_we & !reg_error; assign alert_class_26_wd = reg_wdata[1:0]; - assign alert_class_27_we = addr_hit[167] & reg_we & !reg_error; + assign alert_class_27_we = addr_hit[169] & reg_we & !reg_error; assign alert_class_27_wd = reg_wdata[1:0]; - assign alert_class_28_we = addr_hit[168] & reg_we & !reg_error; + assign alert_class_28_we = addr_hit[170] & reg_we & !reg_error; assign alert_class_28_wd = reg_wdata[1:0]; - assign alert_class_29_we = addr_hit[169] & reg_we & !reg_error; + assign alert_class_29_we = addr_hit[171] & reg_we & !reg_error; assign alert_class_29_wd = reg_wdata[1:0]; - assign alert_class_30_we = addr_hit[170] & reg_we & !reg_error; + assign alert_class_30_we = addr_hit[172] & reg_we & !reg_error; assign alert_class_30_wd = reg_wdata[1:0]; - assign alert_class_31_we = addr_hit[171] & reg_we & !reg_error; + assign alert_class_31_we = addr_hit[173] & reg_we & !reg_error; assign alert_class_31_wd = reg_wdata[1:0]; - assign alert_class_32_we = addr_hit[172] & reg_we & !reg_error; + assign alert_class_32_we = addr_hit[174] & reg_we & !reg_error; assign alert_class_32_wd = reg_wdata[1:0]; - assign alert_class_33_we = addr_hit[173] & reg_we & !reg_error; + assign alert_class_33_we = addr_hit[175] & reg_we & !reg_error; assign alert_class_33_wd = reg_wdata[1:0]; - assign alert_class_34_we = addr_hit[174] & reg_we & !reg_error; + assign alert_class_34_we = addr_hit[176] & reg_we & !reg_error; assign alert_class_34_wd = reg_wdata[1:0]; - assign alert_class_35_we = addr_hit[175] & reg_we & !reg_error; + assign alert_class_35_we = addr_hit[177] & reg_we & !reg_error; assign alert_class_35_wd = reg_wdata[1:0]; - assign alert_class_36_we = addr_hit[176] & reg_we & !reg_error; + assign alert_class_36_we = addr_hit[178] & reg_we & !reg_error; assign alert_class_36_wd = reg_wdata[1:0]; - assign alert_class_37_we = addr_hit[177] & reg_we & !reg_error; + assign alert_class_37_we = addr_hit[179] & reg_we & !reg_error; assign alert_class_37_wd = reg_wdata[1:0]; - assign alert_class_38_we = addr_hit[178] & reg_we & !reg_error; + assign alert_class_38_we = addr_hit[180] & reg_we & !reg_error; assign alert_class_38_wd = reg_wdata[1:0]; - assign alert_class_39_we = addr_hit[179] & reg_we & !reg_error; + assign alert_class_39_we = addr_hit[181] & reg_we & !reg_error; assign alert_class_39_wd = reg_wdata[1:0]; - assign alert_class_40_we = addr_hit[180] & reg_we & !reg_error; + assign alert_class_40_we = addr_hit[182] & reg_we & !reg_error; assign alert_class_40_wd = reg_wdata[1:0]; - assign alert_class_41_we = addr_hit[181] & reg_we & !reg_error; + assign alert_class_41_we = addr_hit[183] & reg_we & !reg_error; assign alert_class_41_wd = reg_wdata[1:0]; - assign alert_class_42_we = addr_hit[182] & reg_we & !reg_error; + assign alert_class_42_we = addr_hit[184] & reg_we & !reg_error; assign alert_class_42_wd = reg_wdata[1:0]; - assign alert_class_43_we = addr_hit[183] & reg_we & !reg_error; + assign alert_class_43_we = addr_hit[185] & reg_we & !reg_error; assign alert_class_43_wd = reg_wdata[1:0]; - assign alert_class_44_we = addr_hit[184] & reg_we & !reg_error; + assign alert_class_44_we = addr_hit[186] & reg_we & !reg_error; assign alert_class_44_wd = reg_wdata[1:0]; - assign alert_class_45_we = addr_hit[185] & reg_we & !reg_error; + assign alert_class_45_we = addr_hit[187] & reg_we & !reg_error; assign alert_class_45_wd = reg_wdata[1:0]; - assign alert_class_46_we = addr_hit[186] & reg_we & !reg_error; + assign alert_class_46_we = addr_hit[188] & reg_we & !reg_error; assign alert_class_46_wd = reg_wdata[1:0]; - assign alert_class_47_we = addr_hit[187] & reg_we & !reg_error; + assign alert_class_47_we = addr_hit[189] & reg_we & !reg_error; assign alert_class_47_wd = reg_wdata[1:0]; - assign alert_class_48_we = addr_hit[188] & reg_we & !reg_error; + assign alert_class_48_we = addr_hit[190] & reg_we & !reg_error; assign alert_class_48_wd = reg_wdata[1:0]; - assign alert_class_49_we = addr_hit[189] & reg_we & !reg_error; + assign alert_class_49_we = addr_hit[191] & reg_we & !reg_error; assign alert_class_49_wd = reg_wdata[1:0]; - assign alert_class_50_we = addr_hit[190] & reg_we & !reg_error; + assign alert_class_50_we = addr_hit[192] & reg_we & !reg_error; assign alert_class_50_wd = reg_wdata[1:0]; - assign alert_class_51_we = addr_hit[191] & reg_we & !reg_error; + assign alert_class_51_we = addr_hit[193] & reg_we & !reg_error; assign alert_class_51_wd = reg_wdata[1:0]; - assign alert_class_52_we = addr_hit[192] & reg_we & !reg_error; + assign alert_class_52_we = addr_hit[194] & reg_we & !reg_error; assign alert_class_52_wd = reg_wdata[1:0]; - assign alert_class_53_we = addr_hit[193] & reg_we & !reg_error; + assign alert_class_53_we = addr_hit[195] & reg_we & !reg_error; assign alert_class_53_wd = reg_wdata[1:0]; - assign alert_class_54_we = addr_hit[194] & reg_we & !reg_error; + assign alert_class_54_we = addr_hit[196] & reg_we & !reg_error; assign alert_class_54_wd = reg_wdata[1:0]; - assign alert_class_55_we = addr_hit[195] & reg_we & !reg_error; + assign alert_class_55_we = addr_hit[197] & reg_we & !reg_error; assign alert_class_55_wd = reg_wdata[1:0]; - assign alert_class_56_we = addr_hit[196] & reg_we & !reg_error; + assign alert_class_56_we = addr_hit[198] & reg_we & !reg_error; assign alert_class_56_wd = reg_wdata[1:0]; - assign alert_class_57_we = addr_hit[197] & reg_we & !reg_error; + assign alert_class_57_we = addr_hit[199] & reg_we & !reg_error; assign alert_class_57_wd = reg_wdata[1:0]; - assign alert_class_58_we = addr_hit[198] & reg_we & !reg_error; + assign alert_class_58_we = addr_hit[200] & reg_we & !reg_error; assign alert_class_58_wd = reg_wdata[1:0]; - assign alert_class_59_we = addr_hit[199] & reg_we & !reg_error; + assign alert_class_59_we = addr_hit[201] & reg_we & !reg_error; assign alert_class_59_wd = reg_wdata[1:0]; - assign alert_class_60_we = addr_hit[200] & reg_we & !reg_error; + assign alert_class_60_we = addr_hit[202] & reg_we & !reg_error; assign alert_class_60_wd = reg_wdata[1:0]; - assign alert_class_61_we = addr_hit[201] & reg_we & !reg_error; + assign alert_class_61_we = addr_hit[203] & reg_we & !reg_error; assign alert_class_61_wd = reg_wdata[1:0]; - assign alert_class_62_we = addr_hit[202] & reg_we & !reg_error; + assign alert_class_62_we = addr_hit[204] & reg_we & !reg_error; assign alert_class_62_wd = reg_wdata[1:0]; - assign alert_class_63_we = addr_hit[203] & reg_we & !reg_error; + assign alert_class_63_we = addr_hit[205] & reg_we & !reg_error; assign alert_class_63_wd = reg_wdata[1:0]; - assign alert_class_64_we = addr_hit[204] & reg_we & !reg_error; + assign alert_class_64_we = addr_hit[206] & reg_we & !reg_error; assign alert_class_64_wd = reg_wdata[1:0]; - assign alert_class_65_we = addr_hit[205] & reg_we & !reg_error; + assign alert_class_65_we = addr_hit[207] & reg_we & !reg_error; assign alert_class_65_wd = reg_wdata[1:0]; - assign alert_class_66_we = addr_hit[206] & reg_we & !reg_error; + assign alert_class_66_we = addr_hit[208] & reg_we & !reg_error; assign alert_class_66_wd = reg_wdata[1:0]; - assign alert_cause_0_we = addr_hit[207] & reg_we & !reg_error; + assign alert_class_67_we = addr_hit[209] & reg_we & !reg_error; + + assign alert_class_67_wd = reg_wdata[1:0]; + assign alert_cause_0_we = addr_hit[210] & reg_we & !reg_error; assign alert_cause_0_wd = reg_wdata[0]; - assign alert_cause_1_we = addr_hit[208] & reg_we & !reg_error; + assign alert_cause_1_we = addr_hit[211] & reg_we & !reg_error; assign alert_cause_1_wd = reg_wdata[0]; - assign alert_cause_2_we = addr_hit[209] & reg_we & !reg_error; + assign alert_cause_2_we = addr_hit[212] & reg_we & !reg_error; assign alert_cause_2_wd = reg_wdata[0]; - assign alert_cause_3_we = addr_hit[210] & reg_we & !reg_error; + assign alert_cause_3_we = addr_hit[213] & reg_we & !reg_error; assign alert_cause_3_wd = reg_wdata[0]; - assign alert_cause_4_we = addr_hit[211] & reg_we & !reg_error; + assign alert_cause_4_we = addr_hit[214] & reg_we & !reg_error; assign alert_cause_4_wd = reg_wdata[0]; - assign alert_cause_5_we = addr_hit[212] & reg_we & !reg_error; + assign alert_cause_5_we = addr_hit[215] & reg_we & !reg_error; assign alert_cause_5_wd = reg_wdata[0]; - assign alert_cause_6_we = addr_hit[213] & reg_we & !reg_error; + assign alert_cause_6_we = addr_hit[216] & reg_we & !reg_error; assign alert_cause_6_wd = reg_wdata[0]; - assign alert_cause_7_we = addr_hit[214] & reg_we & !reg_error; + assign alert_cause_7_we = addr_hit[217] & reg_we & !reg_error; assign alert_cause_7_wd = reg_wdata[0]; - assign alert_cause_8_we = addr_hit[215] & reg_we & !reg_error; + assign alert_cause_8_we = addr_hit[218] & reg_we & !reg_error; assign alert_cause_8_wd = reg_wdata[0]; - assign alert_cause_9_we = addr_hit[216] & reg_we & !reg_error; + assign alert_cause_9_we = addr_hit[219] & reg_we & !reg_error; assign alert_cause_9_wd = reg_wdata[0]; - assign alert_cause_10_we = addr_hit[217] & reg_we & !reg_error; + assign alert_cause_10_we = addr_hit[220] & reg_we & !reg_error; assign alert_cause_10_wd = reg_wdata[0]; - assign alert_cause_11_we = addr_hit[218] & reg_we & !reg_error; + assign alert_cause_11_we = addr_hit[221] & reg_we & !reg_error; assign alert_cause_11_wd = reg_wdata[0]; - assign alert_cause_12_we = addr_hit[219] & reg_we & !reg_error; + assign alert_cause_12_we = addr_hit[222] & reg_we & !reg_error; assign alert_cause_12_wd = reg_wdata[0]; - assign alert_cause_13_we = addr_hit[220] & reg_we & !reg_error; + assign alert_cause_13_we = addr_hit[223] & reg_we & !reg_error; assign alert_cause_13_wd = reg_wdata[0]; - assign alert_cause_14_we = addr_hit[221] & reg_we & !reg_error; + assign alert_cause_14_we = addr_hit[224] & reg_we & !reg_error; assign alert_cause_14_wd = reg_wdata[0]; - assign alert_cause_15_we = addr_hit[222] & reg_we & !reg_error; + assign alert_cause_15_we = addr_hit[225] & reg_we & !reg_error; assign alert_cause_15_wd = reg_wdata[0]; - assign alert_cause_16_we = addr_hit[223] & reg_we & !reg_error; + assign alert_cause_16_we = addr_hit[226] & reg_we & !reg_error; assign alert_cause_16_wd = reg_wdata[0]; - assign alert_cause_17_we = addr_hit[224] & reg_we & !reg_error; + assign alert_cause_17_we = addr_hit[227] & reg_we & !reg_error; assign alert_cause_17_wd = reg_wdata[0]; - assign alert_cause_18_we = addr_hit[225] & reg_we & !reg_error; + assign alert_cause_18_we = addr_hit[228] & reg_we & !reg_error; assign alert_cause_18_wd = reg_wdata[0]; - assign alert_cause_19_we = addr_hit[226] & reg_we & !reg_error; + assign alert_cause_19_we = addr_hit[229] & reg_we & !reg_error; assign alert_cause_19_wd = reg_wdata[0]; - assign alert_cause_20_we = addr_hit[227] & reg_we & !reg_error; + assign alert_cause_20_we = addr_hit[230] & reg_we & !reg_error; assign alert_cause_20_wd = reg_wdata[0]; - assign alert_cause_21_we = addr_hit[228] & reg_we & !reg_error; + assign alert_cause_21_we = addr_hit[231] & reg_we & !reg_error; assign alert_cause_21_wd = reg_wdata[0]; - assign alert_cause_22_we = addr_hit[229] & reg_we & !reg_error; + assign alert_cause_22_we = addr_hit[232] & reg_we & !reg_error; assign alert_cause_22_wd = reg_wdata[0]; - assign alert_cause_23_we = addr_hit[230] & reg_we & !reg_error; + assign alert_cause_23_we = addr_hit[233] & reg_we & !reg_error; assign alert_cause_23_wd = reg_wdata[0]; - assign alert_cause_24_we = addr_hit[231] & reg_we & !reg_error; + assign alert_cause_24_we = addr_hit[234] & reg_we & !reg_error; assign alert_cause_24_wd = reg_wdata[0]; - assign alert_cause_25_we = addr_hit[232] & reg_we & !reg_error; + assign alert_cause_25_we = addr_hit[235] & reg_we & !reg_error; assign alert_cause_25_wd = reg_wdata[0]; - assign alert_cause_26_we = addr_hit[233] & reg_we & !reg_error; + assign alert_cause_26_we = addr_hit[236] & reg_we & !reg_error; assign alert_cause_26_wd = reg_wdata[0]; - assign alert_cause_27_we = addr_hit[234] & reg_we & !reg_error; + assign alert_cause_27_we = addr_hit[237] & reg_we & !reg_error; assign alert_cause_27_wd = reg_wdata[0]; - assign alert_cause_28_we = addr_hit[235] & reg_we & !reg_error; + assign alert_cause_28_we = addr_hit[238] & reg_we & !reg_error; assign alert_cause_28_wd = reg_wdata[0]; - assign alert_cause_29_we = addr_hit[236] & reg_we & !reg_error; + assign alert_cause_29_we = addr_hit[239] & reg_we & !reg_error; assign alert_cause_29_wd = reg_wdata[0]; - assign alert_cause_30_we = addr_hit[237] & reg_we & !reg_error; + assign alert_cause_30_we = addr_hit[240] & reg_we & !reg_error; assign alert_cause_30_wd = reg_wdata[0]; - assign alert_cause_31_we = addr_hit[238] & reg_we & !reg_error; + assign alert_cause_31_we = addr_hit[241] & reg_we & !reg_error; assign alert_cause_31_wd = reg_wdata[0]; - assign alert_cause_32_we = addr_hit[239] & reg_we & !reg_error; + assign alert_cause_32_we = addr_hit[242] & reg_we & !reg_error; assign alert_cause_32_wd = reg_wdata[0]; - assign alert_cause_33_we = addr_hit[240] & reg_we & !reg_error; + assign alert_cause_33_we = addr_hit[243] & reg_we & !reg_error; assign alert_cause_33_wd = reg_wdata[0]; - assign alert_cause_34_we = addr_hit[241] & reg_we & !reg_error; + assign alert_cause_34_we = addr_hit[244] & reg_we & !reg_error; assign alert_cause_34_wd = reg_wdata[0]; - assign alert_cause_35_we = addr_hit[242] & reg_we & !reg_error; + assign alert_cause_35_we = addr_hit[245] & reg_we & !reg_error; assign alert_cause_35_wd = reg_wdata[0]; - assign alert_cause_36_we = addr_hit[243] & reg_we & !reg_error; + assign alert_cause_36_we = addr_hit[246] & reg_we & !reg_error; assign alert_cause_36_wd = reg_wdata[0]; - assign alert_cause_37_we = addr_hit[244] & reg_we & !reg_error; + assign alert_cause_37_we = addr_hit[247] & reg_we & !reg_error; assign alert_cause_37_wd = reg_wdata[0]; - assign alert_cause_38_we = addr_hit[245] & reg_we & !reg_error; + assign alert_cause_38_we = addr_hit[248] & reg_we & !reg_error; assign alert_cause_38_wd = reg_wdata[0]; - assign alert_cause_39_we = addr_hit[246] & reg_we & !reg_error; + assign alert_cause_39_we = addr_hit[249] & reg_we & !reg_error; assign alert_cause_39_wd = reg_wdata[0]; - assign alert_cause_40_we = addr_hit[247] & reg_we & !reg_error; + assign alert_cause_40_we = addr_hit[250] & reg_we & !reg_error; assign alert_cause_40_wd = reg_wdata[0]; - assign alert_cause_41_we = addr_hit[248] & reg_we & !reg_error; + assign alert_cause_41_we = addr_hit[251] & reg_we & !reg_error; assign alert_cause_41_wd = reg_wdata[0]; - assign alert_cause_42_we = addr_hit[249] & reg_we & !reg_error; + assign alert_cause_42_we = addr_hit[252] & reg_we & !reg_error; assign alert_cause_42_wd = reg_wdata[0]; - assign alert_cause_43_we = addr_hit[250] & reg_we & !reg_error; + assign alert_cause_43_we = addr_hit[253] & reg_we & !reg_error; assign alert_cause_43_wd = reg_wdata[0]; - assign alert_cause_44_we = addr_hit[251] & reg_we & !reg_error; + assign alert_cause_44_we = addr_hit[254] & reg_we & !reg_error; assign alert_cause_44_wd = reg_wdata[0]; - assign alert_cause_45_we = addr_hit[252] & reg_we & !reg_error; + assign alert_cause_45_we = addr_hit[255] & reg_we & !reg_error; assign alert_cause_45_wd = reg_wdata[0]; - assign alert_cause_46_we = addr_hit[253] & reg_we & !reg_error; + assign alert_cause_46_we = addr_hit[256] & reg_we & !reg_error; assign alert_cause_46_wd = reg_wdata[0]; - assign alert_cause_47_we = addr_hit[254] & reg_we & !reg_error; + assign alert_cause_47_we = addr_hit[257] & reg_we & !reg_error; assign alert_cause_47_wd = reg_wdata[0]; - assign alert_cause_48_we = addr_hit[255] & reg_we & !reg_error; + assign alert_cause_48_we = addr_hit[258] & reg_we & !reg_error; assign alert_cause_48_wd = reg_wdata[0]; - assign alert_cause_49_we = addr_hit[256] & reg_we & !reg_error; + assign alert_cause_49_we = addr_hit[259] & reg_we & !reg_error; assign alert_cause_49_wd = reg_wdata[0]; - assign alert_cause_50_we = addr_hit[257] & reg_we & !reg_error; + assign alert_cause_50_we = addr_hit[260] & reg_we & !reg_error; assign alert_cause_50_wd = reg_wdata[0]; - assign alert_cause_51_we = addr_hit[258] & reg_we & !reg_error; + assign alert_cause_51_we = addr_hit[261] & reg_we & !reg_error; assign alert_cause_51_wd = reg_wdata[0]; - assign alert_cause_52_we = addr_hit[259] & reg_we & !reg_error; + assign alert_cause_52_we = addr_hit[262] & reg_we & !reg_error; assign alert_cause_52_wd = reg_wdata[0]; - assign alert_cause_53_we = addr_hit[260] & reg_we & !reg_error; + assign alert_cause_53_we = addr_hit[263] & reg_we & !reg_error; assign alert_cause_53_wd = reg_wdata[0]; - assign alert_cause_54_we = addr_hit[261] & reg_we & !reg_error; + assign alert_cause_54_we = addr_hit[264] & reg_we & !reg_error; assign alert_cause_54_wd = reg_wdata[0]; - assign alert_cause_55_we = addr_hit[262] & reg_we & !reg_error; + assign alert_cause_55_we = addr_hit[265] & reg_we & !reg_error; assign alert_cause_55_wd = reg_wdata[0]; - assign alert_cause_56_we = addr_hit[263] & reg_we & !reg_error; + assign alert_cause_56_we = addr_hit[266] & reg_we & !reg_error; assign alert_cause_56_wd = reg_wdata[0]; - assign alert_cause_57_we = addr_hit[264] & reg_we & !reg_error; + assign alert_cause_57_we = addr_hit[267] & reg_we & !reg_error; assign alert_cause_57_wd = reg_wdata[0]; - assign alert_cause_58_we = addr_hit[265] & reg_we & !reg_error; + assign alert_cause_58_we = addr_hit[268] & reg_we & !reg_error; assign alert_cause_58_wd = reg_wdata[0]; - assign alert_cause_59_we = addr_hit[266] & reg_we & !reg_error; + assign alert_cause_59_we = addr_hit[269] & reg_we & !reg_error; assign alert_cause_59_wd = reg_wdata[0]; - assign alert_cause_60_we = addr_hit[267] & reg_we & !reg_error; + assign alert_cause_60_we = addr_hit[270] & reg_we & !reg_error; assign alert_cause_60_wd = reg_wdata[0]; - assign alert_cause_61_we = addr_hit[268] & reg_we & !reg_error; + assign alert_cause_61_we = addr_hit[271] & reg_we & !reg_error; assign alert_cause_61_wd = reg_wdata[0]; - assign alert_cause_62_we = addr_hit[269] & reg_we & !reg_error; + assign alert_cause_62_we = addr_hit[272] & reg_we & !reg_error; assign alert_cause_62_wd = reg_wdata[0]; - assign alert_cause_63_we = addr_hit[270] & reg_we & !reg_error; + assign alert_cause_63_we = addr_hit[273] & reg_we & !reg_error; assign alert_cause_63_wd = reg_wdata[0]; - assign alert_cause_64_we = addr_hit[271] & reg_we & !reg_error; + assign alert_cause_64_we = addr_hit[274] & reg_we & !reg_error; assign alert_cause_64_wd = reg_wdata[0]; - assign alert_cause_65_we = addr_hit[272] & reg_we & !reg_error; + assign alert_cause_65_we = addr_hit[275] & reg_we & !reg_error; assign alert_cause_65_wd = reg_wdata[0]; - assign alert_cause_66_we = addr_hit[273] & reg_we & !reg_error; + assign alert_cause_66_we = addr_hit[276] & reg_we & !reg_error; assign alert_cause_66_wd = reg_wdata[0]; - assign loc_alert_regwen_0_we = addr_hit[274] & reg_we & !reg_error; + assign alert_cause_67_we = addr_hit[277] & reg_we & !reg_error; + + assign alert_cause_67_wd = reg_wdata[0]; + assign loc_alert_regwen_0_we = addr_hit[278] & reg_we & !reg_error; assign loc_alert_regwen_0_wd = reg_wdata[0]; - assign loc_alert_regwen_1_we = addr_hit[275] & reg_we & !reg_error; + assign loc_alert_regwen_1_we = addr_hit[279] & reg_we & !reg_error; assign loc_alert_regwen_1_wd = reg_wdata[0]; - assign loc_alert_regwen_2_we = addr_hit[276] & reg_we & !reg_error; + assign loc_alert_regwen_2_we = addr_hit[280] & reg_we & !reg_error; assign loc_alert_regwen_2_wd = reg_wdata[0]; - assign loc_alert_regwen_3_we = addr_hit[277] & reg_we & !reg_error; + assign loc_alert_regwen_3_we = addr_hit[281] & reg_we & !reg_error; assign loc_alert_regwen_3_wd = reg_wdata[0]; - assign loc_alert_regwen_4_we = addr_hit[278] & reg_we & !reg_error; + assign loc_alert_regwen_4_we = addr_hit[282] & reg_we & !reg_error; assign loc_alert_regwen_4_wd = reg_wdata[0]; - assign loc_alert_en_0_we = addr_hit[279] & reg_we & !reg_error; + assign loc_alert_en_0_we = addr_hit[283] & reg_we & !reg_error; assign loc_alert_en_0_wd = reg_wdata[0]; - assign loc_alert_en_1_we = addr_hit[280] & reg_we & !reg_error; + assign loc_alert_en_1_we = addr_hit[284] & reg_we & !reg_error; assign loc_alert_en_1_wd = reg_wdata[0]; - assign loc_alert_en_2_we = addr_hit[281] & reg_we & !reg_error; + assign loc_alert_en_2_we = addr_hit[285] & reg_we & !reg_error; assign loc_alert_en_2_wd = reg_wdata[0]; - assign loc_alert_en_3_we = addr_hit[282] & reg_we & !reg_error; + assign loc_alert_en_3_we = addr_hit[286] & reg_we & !reg_error; assign loc_alert_en_3_wd = reg_wdata[0]; - assign loc_alert_en_4_we = addr_hit[283] & reg_we & !reg_error; + assign loc_alert_en_4_we = addr_hit[287] & reg_we & !reg_error; assign loc_alert_en_4_wd = reg_wdata[0]; - assign loc_alert_class_0_we = addr_hit[284] & reg_we & !reg_error; + assign loc_alert_class_0_we = addr_hit[288] & reg_we & !reg_error; assign loc_alert_class_0_wd = reg_wdata[1:0]; - assign loc_alert_class_1_we = addr_hit[285] & reg_we & !reg_error; + assign loc_alert_class_1_we = addr_hit[289] & reg_we & !reg_error; assign loc_alert_class_1_wd = reg_wdata[1:0]; - assign loc_alert_class_2_we = addr_hit[286] & reg_we & !reg_error; + assign loc_alert_class_2_we = addr_hit[290] & reg_we & !reg_error; assign loc_alert_class_2_wd = reg_wdata[1:0]; - assign loc_alert_class_3_we = addr_hit[287] & reg_we & !reg_error; + assign loc_alert_class_3_we = addr_hit[291] & reg_we & !reg_error; assign loc_alert_class_3_wd = reg_wdata[1:0]; - assign loc_alert_class_4_we = addr_hit[288] & reg_we & !reg_error; + assign loc_alert_class_4_we = addr_hit[292] & reg_we & !reg_error; assign loc_alert_class_4_wd = reg_wdata[1:0]; - assign loc_alert_cause_0_we = addr_hit[289] & reg_we & !reg_error; + assign loc_alert_cause_0_we = addr_hit[293] & reg_we & !reg_error; assign loc_alert_cause_0_wd = reg_wdata[0]; - assign loc_alert_cause_1_we = addr_hit[290] & reg_we & !reg_error; + assign loc_alert_cause_1_we = addr_hit[294] & reg_we & !reg_error; assign loc_alert_cause_1_wd = reg_wdata[0]; - assign loc_alert_cause_2_we = addr_hit[291] & reg_we & !reg_error; + assign loc_alert_cause_2_we = addr_hit[295] & reg_we & !reg_error; assign loc_alert_cause_2_wd = reg_wdata[0]; - assign loc_alert_cause_3_we = addr_hit[292] & reg_we & !reg_error; + assign loc_alert_cause_3_we = addr_hit[296] & reg_we & !reg_error; assign loc_alert_cause_3_wd = reg_wdata[0]; - assign loc_alert_cause_4_we = addr_hit[293] & reg_we & !reg_error; + assign loc_alert_cause_4_we = addr_hit[297] & reg_we & !reg_error; assign loc_alert_cause_4_wd = reg_wdata[0]; - assign classa_regwen_we = addr_hit[294] & reg_we & !reg_error; + assign classa_regwen_we = addr_hit[298] & reg_we & !reg_error; assign classa_regwen_wd = reg_wdata[0]; - assign classa_ctrl_we = addr_hit[295] & reg_we & !reg_error; + assign classa_ctrl_we = addr_hit[299] & reg_we & !reg_error; assign classa_ctrl_en_wd = reg_wdata[0]; @@ -13202,37 +13342,37 @@ assign classa_ctrl_map_e2_wd = reg_wdata[11:10]; assign classa_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classa_clr_regwen_we = addr_hit[296] & reg_we & !reg_error; + assign classa_clr_regwen_we = addr_hit[300] & reg_we & !reg_error; assign classa_clr_regwen_wd = reg_wdata[0]; - assign classa_clr_we = addr_hit[297] & reg_we & !reg_error; + assign classa_clr_we = addr_hit[301] & reg_we & !reg_error; assign classa_clr_wd = reg_wdata[0]; - assign classa_accum_cnt_re = addr_hit[298] & reg_re & !reg_error; - assign classa_accum_thresh_we = addr_hit[299] & reg_we & !reg_error; + assign classa_accum_cnt_re = addr_hit[302] & reg_re & !reg_error; + assign classa_accum_thresh_we = addr_hit[303] & reg_we & !reg_error; assign classa_accum_thresh_wd = reg_wdata[15:0]; - assign classa_timeout_cyc_we = addr_hit[300] & reg_we & !reg_error; + assign classa_timeout_cyc_we = addr_hit[304] & reg_we & !reg_error; assign classa_timeout_cyc_wd = reg_wdata[31:0]; - assign classa_phase0_cyc_we = addr_hit[301] & reg_we & !reg_error; + assign classa_phase0_cyc_we = addr_hit[305] & reg_we & !reg_error; assign classa_phase0_cyc_wd = reg_wdata[31:0]; - assign classa_phase1_cyc_we = addr_hit[302] & reg_we & !reg_error; + assign classa_phase1_cyc_we = addr_hit[306] & reg_we & !reg_error; assign classa_phase1_cyc_wd = reg_wdata[31:0]; - assign classa_phase2_cyc_we = addr_hit[303] & reg_we & !reg_error; + assign classa_phase2_cyc_we = addr_hit[307] & reg_we & !reg_error; assign classa_phase2_cyc_wd = reg_wdata[31:0]; - assign classa_phase3_cyc_we = addr_hit[304] & reg_we & !reg_error; + assign classa_phase3_cyc_we = addr_hit[308] & reg_we & !reg_error; assign classa_phase3_cyc_wd = reg_wdata[31:0]; - assign classa_esc_cnt_re = addr_hit[305] & reg_re & !reg_error; - assign classa_state_re = addr_hit[306] & reg_re & !reg_error; - assign classb_regwen_we = addr_hit[307] & reg_we & !reg_error; + assign classa_esc_cnt_re = addr_hit[309] & reg_re & !reg_error; + assign classa_state_re = addr_hit[310] & reg_re & !reg_error; + assign classb_regwen_we = addr_hit[311] & reg_we & !reg_error; assign classb_regwen_wd = reg_wdata[0]; - assign classb_ctrl_we = addr_hit[308] & reg_we & !reg_error; + assign classb_ctrl_we = addr_hit[312] & reg_we & !reg_error; assign classb_ctrl_en_wd = reg_wdata[0]; @@ -13253,37 +13393,37 @@ assign classb_ctrl_map_e2_wd = reg_wdata[11:10]; assign classb_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classb_clr_regwen_we = addr_hit[309] & reg_we & !reg_error; + assign classb_clr_regwen_we = addr_hit[313] & reg_we & !reg_error; assign classb_clr_regwen_wd = reg_wdata[0]; - assign classb_clr_we = addr_hit[310] & reg_we & !reg_error; + assign classb_clr_we = addr_hit[314] & reg_we & !reg_error; assign classb_clr_wd = reg_wdata[0]; - assign classb_accum_cnt_re = addr_hit[311] & reg_re & !reg_error; - assign classb_accum_thresh_we = addr_hit[312] & reg_we & !reg_error; + assign classb_accum_cnt_re = addr_hit[315] & reg_re & !reg_error; + assign classb_accum_thresh_we = addr_hit[316] & reg_we & !reg_error; assign classb_accum_thresh_wd = reg_wdata[15:0]; - assign classb_timeout_cyc_we = addr_hit[313] & reg_we & !reg_error; + assign classb_timeout_cyc_we = addr_hit[317] & reg_we & !reg_error; assign classb_timeout_cyc_wd = reg_wdata[31:0]; - assign classb_phase0_cyc_we = addr_hit[314] & reg_we & !reg_error; + assign classb_phase0_cyc_we = addr_hit[318] & reg_we & !reg_error; assign classb_phase0_cyc_wd = reg_wdata[31:0]; - assign classb_phase1_cyc_we = addr_hit[315] & reg_we & !reg_error; + assign classb_phase1_cyc_we = addr_hit[319] & reg_we & !reg_error; assign classb_phase1_cyc_wd = reg_wdata[31:0]; - assign classb_phase2_cyc_we = addr_hit[316] & reg_we & !reg_error; + assign classb_phase2_cyc_we = addr_hit[320] & reg_we & !reg_error; assign classb_phase2_cyc_wd = reg_wdata[31:0]; - assign classb_phase3_cyc_we = addr_hit[317] & reg_we & !reg_error; + assign classb_phase3_cyc_we = addr_hit[321] & reg_we & !reg_error; assign classb_phase3_cyc_wd = reg_wdata[31:0]; - assign classb_esc_cnt_re = addr_hit[318] & reg_re & !reg_error; - assign classb_state_re = addr_hit[319] & reg_re & !reg_error; - assign classc_regwen_we = addr_hit[320] & reg_we & !reg_error; + assign classb_esc_cnt_re = addr_hit[322] & reg_re & !reg_error; + assign classb_state_re = addr_hit[323] & reg_re & !reg_error; + assign classc_regwen_we = addr_hit[324] & reg_we & !reg_error; assign classc_regwen_wd = reg_wdata[0]; - assign classc_ctrl_we = addr_hit[321] & reg_we & !reg_error; + assign classc_ctrl_we = addr_hit[325] & reg_we & !reg_error; assign classc_ctrl_en_wd = reg_wdata[0]; @@ -13304,37 +13444,37 @@ assign classc_ctrl_map_e2_wd = reg_wdata[11:10]; assign classc_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classc_clr_regwen_we = addr_hit[322] & reg_we & !reg_error; + assign classc_clr_regwen_we = addr_hit[326] & reg_we & !reg_error; assign classc_clr_regwen_wd = reg_wdata[0]; - assign classc_clr_we = addr_hit[323] & reg_we & !reg_error; + assign classc_clr_we = addr_hit[327] & reg_we & !reg_error; assign classc_clr_wd = reg_wdata[0]; - assign classc_accum_cnt_re = addr_hit[324] & reg_re & !reg_error; - assign classc_accum_thresh_we = addr_hit[325] & reg_we & !reg_error; + assign classc_accum_cnt_re = addr_hit[328] & reg_re & !reg_error; + assign classc_accum_thresh_we = addr_hit[329] & reg_we & !reg_error; assign classc_accum_thresh_wd = reg_wdata[15:0]; - assign classc_timeout_cyc_we = addr_hit[326] & reg_we & !reg_error; + assign classc_timeout_cyc_we = addr_hit[330] & reg_we & !reg_error; assign classc_timeout_cyc_wd = reg_wdata[31:0]; - assign classc_phase0_cyc_we = addr_hit[327] & reg_we & !reg_error; + assign classc_phase0_cyc_we = addr_hit[331] & reg_we & !reg_error; assign classc_phase0_cyc_wd = reg_wdata[31:0]; - assign classc_phase1_cyc_we = addr_hit[328] & reg_we & !reg_error; + assign classc_phase1_cyc_we = addr_hit[332] & reg_we & !reg_error; assign classc_phase1_cyc_wd = reg_wdata[31:0]; - assign classc_phase2_cyc_we = addr_hit[329] & reg_we & !reg_error; + assign classc_phase2_cyc_we = addr_hit[333] & reg_we & !reg_error; assign classc_phase2_cyc_wd = reg_wdata[31:0]; - assign classc_phase3_cyc_we = addr_hit[330] & reg_we & !reg_error; + assign classc_phase3_cyc_we = addr_hit[334] & reg_we & !reg_error; assign classc_phase3_cyc_wd = reg_wdata[31:0]; - assign classc_esc_cnt_re = addr_hit[331] & reg_re & !reg_error; - assign classc_state_re = addr_hit[332] & reg_re & !reg_error; - assign classd_regwen_we = addr_hit[333] & reg_we & !reg_error; + assign classc_esc_cnt_re = addr_hit[335] & reg_re & !reg_error; + assign classc_state_re = addr_hit[336] & reg_re & !reg_error; + assign classd_regwen_we = addr_hit[337] & reg_we & !reg_error; assign classd_regwen_wd = reg_wdata[0]; - assign classd_ctrl_we = addr_hit[334] & reg_we & !reg_error; + assign classd_ctrl_we = addr_hit[338] & reg_we & !reg_error; assign classd_ctrl_en_wd = reg_wdata[0]; @@ -13355,33 +13495,33 @@ assign classd_ctrl_map_e2_wd = reg_wdata[11:10]; assign classd_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classd_clr_regwen_we = addr_hit[335] & reg_we & !reg_error; + assign classd_clr_regwen_we = addr_hit[339] & reg_we & !reg_error; assign classd_clr_regwen_wd = reg_wdata[0]; - assign classd_clr_we = addr_hit[336] & reg_we & !reg_error; + assign classd_clr_we = addr_hit[340] & reg_we & !reg_error; assign classd_clr_wd = reg_wdata[0]; - assign classd_accum_cnt_re = addr_hit[337] & reg_re & !reg_error; - assign classd_accum_thresh_we = addr_hit[338] & reg_we & !reg_error; + assign classd_accum_cnt_re = addr_hit[341] & reg_re & !reg_error; + assign classd_accum_thresh_we = addr_hit[342] & reg_we & !reg_error; assign classd_accum_thresh_wd = reg_wdata[15:0]; - assign classd_timeout_cyc_we = addr_hit[339] & reg_we & !reg_error; + assign classd_timeout_cyc_we = addr_hit[343] & reg_we & !reg_error; assign classd_timeout_cyc_wd = reg_wdata[31:0]; - assign classd_phase0_cyc_we = addr_hit[340] & reg_we & !reg_error; + assign classd_phase0_cyc_we = addr_hit[344] & reg_we & !reg_error; assign classd_phase0_cyc_wd = reg_wdata[31:0]; - assign classd_phase1_cyc_we = addr_hit[341] & reg_we & !reg_error; + assign classd_phase1_cyc_we = addr_hit[345] & reg_we & !reg_error; assign classd_phase1_cyc_wd = reg_wdata[31:0]; - assign classd_phase2_cyc_we = addr_hit[342] & reg_we & !reg_error; + assign classd_phase2_cyc_we = addr_hit[346] & reg_we & !reg_error; assign classd_phase2_cyc_wd = reg_wdata[31:0]; - assign classd_phase3_cyc_we = addr_hit[343] & reg_we & !reg_error; + assign classd_phase3_cyc_we = addr_hit[347] & reg_we & !reg_error; assign classd_phase3_cyc_wd = reg_wdata[31:0]; - assign classd_esc_cnt_re = addr_hit[344] & reg_re & !reg_error; - assign classd_state_re = addr_hit[345] & reg_re & !reg_error; + assign classd_esc_cnt_re = addr_hit[348] & reg_re & !reg_error; + assign classd_state_re = addr_hit[349] & reg_re & !reg_error; // Read data return always_comb begin @@ -13689,894 +13829,910 @@ end addr_hit[73]: begin - reg_rdata_next[0] = alert_en_0_qs; + reg_rdata_next[0] = alert_regwen_67_qs; end addr_hit[74]: begin - reg_rdata_next[0] = alert_en_1_qs; + reg_rdata_next[0] = alert_en_0_qs; end addr_hit[75]: begin - reg_rdata_next[0] = alert_en_2_qs; + reg_rdata_next[0] = alert_en_1_qs; end addr_hit[76]: begin - reg_rdata_next[0] = alert_en_3_qs; + reg_rdata_next[0] = alert_en_2_qs; end addr_hit[77]: begin - reg_rdata_next[0] = alert_en_4_qs; + reg_rdata_next[0] = alert_en_3_qs; end addr_hit[78]: begin - reg_rdata_next[0] = alert_en_5_qs; + reg_rdata_next[0] = alert_en_4_qs; end addr_hit[79]: begin - reg_rdata_next[0] = alert_en_6_qs; + reg_rdata_next[0] = alert_en_5_qs; end addr_hit[80]: begin - reg_rdata_next[0] = alert_en_7_qs; + reg_rdata_next[0] = alert_en_6_qs; end addr_hit[81]: begin - reg_rdata_next[0] = alert_en_8_qs; + reg_rdata_next[0] = alert_en_7_qs; end addr_hit[82]: begin - reg_rdata_next[0] = alert_en_9_qs; + reg_rdata_next[0] = alert_en_8_qs; end addr_hit[83]: begin - reg_rdata_next[0] = alert_en_10_qs; + reg_rdata_next[0] = alert_en_9_qs; end addr_hit[84]: begin - reg_rdata_next[0] = alert_en_11_qs; + reg_rdata_next[0] = alert_en_10_qs; end addr_hit[85]: begin - reg_rdata_next[0] = alert_en_12_qs; + reg_rdata_next[0] = alert_en_11_qs; end addr_hit[86]: begin - reg_rdata_next[0] = alert_en_13_qs; + reg_rdata_next[0] = alert_en_12_qs; end addr_hit[87]: begin - reg_rdata_next[0] = alert_en_14_qs; + reg_rdata_next[0] = alert_en_13_qs; end addr_hit[88]: begin - reg_rdata_next[0] = alert_en_15_qs; + reg_rdata_next[0] = alert_en_14_qs; end addr_hit[89]: begin - reg_rdata_next[0] = alert_en_16_qs; + reg_rdata_next[0] = alert_en_15_qs; end addr_hit[90]: begin - reg_rdata_next[0] = alert_en_17_qs; + reg_rdata_next[0] = alert_en_16_qs; end addr_hit[91]: begin - reg_rdata_next[0] = alert_en_18_qs; + reg_rdata_next[0] = alert_en_17_qs; end addr_hit[92]: begin - reg_rdata_next[0] = alert_en_19_qs; + reg_rdata_next[0] = alert_en_18_qs; end addr_hit[93]: begin - reg_rdata_next[0] = alert_en_20_qs; + reg_rdata_next[0] = alert_en_19_qs; end addr_hit[94]: begin - reg_rdata_next[0] = alert_en_21_qs; + reg_rdata_next[0] = alert_en_20_qs; end addr_hit[95]: begin - reg_rdata_next[0] = alert_en_22_qs; + reg_rdata_next[0] = alert_en_21_qs; end addr_hit[96]: begin - reg_rdata_next[0] = alert_en_23_qs; + reg_rdata_next[0] = alert_en_22_qs; end addr_hit[97]: begin - reg_rdata_next[0] = alert_en_24_qs; + reg_rdata_next[0] = alert_en_23_qs; end addr_hit[98]: begin - reg_rdata_next[0] = alert_en_25_qs; + reg_rdata_next[0] = alert_en_24_qs; end addr_hit[99]: begin - reg_rdata_next[0] = alert_en_26_qs; + reg_rdata_next[0] = alert_en_25_qs; end addr_hit[100]: begin - reg_rdata_next[0] = alert_en_27_qs; + reg_rdata_next[0] = alert_en_26_qs; end addr_hit[101]: begin - reg_rdata_next[0] = alert_en_28_qs; + reg_rdata_next[0] = alert_en_27_qs; end addr_hit[102]: begin - reg_rdata_next[0] = alert_en_29_qs; + reg_rdata_next[0] = alert_en_28_qs; end addr_hit[103]: begin - reg_rdata_next[0] = alert_en_30_qs; + reg_rdata_next[0] = alert_en_29_qs; end addr_hit[104]: begin - reg_rdata_next[0] = alert_en_31_qs; + reg_rdata_next[0] = alert_en_30_qs; end addr_hit[105]: begin - reg_rdata_next[0] = alert_en_32_qs; + reg_rdata_next[0] = alert_en_31_qs; end addr_hit[106]: begin - reg_rdata_next[0] = alert_en_33_qs; + reg_rdata_next[0] = alert_en_32_qs; end addr_hit[107]: begin - reg_rdata_next[0] = alert_en_34_qs; + reg_rdata_next[0] = alert_en_33_qs; end addr_hit[108]: begin - reg_rdata_next[0] = alert_en_35_qs; + reg_rdata_next[0] = alert_en_34_qs; end addr_hit[109]: begin - reg_rdata_next[0] = alert_en_36_qs; + reg_rdata_next[0] = alert_en_35_qs; end addr_hit[110]: begin - reg_rdata_next[0] = alert_en_37_qs; + reg_rdata_next[0] = alert_en_36_qs; end addr_hit[111]: begin - reg_rdata_next[0] = alert_en_38_qs; + reg_rdata_next[0] = alert_en_37_qs; end addr_hit[112]: begin - reg_rdata_next[0] = alert_en_39_qs; + reg_rdata_next[0] = alert_en_38_qs; end addr_hit[113]: begin - reg_rdata_next[0] = alert_en_40_qs; + reg_rdata_next[0] = alert_en_39_qs; end addr_hit[114]: begin - reg_rdata_next[0] = alert_en_41_qs; + reg_rdata_next[0] = alert_en_40_qs; end addr_hit[115]: begin - reg_rdata_next[0] = alert_en_42_qs; + reg_rdata_next[0] = alert_en_41_qs; end addr_hit[116]: begin - reg_rdata_next[0] = alert_en_43_qs; + reg_rdata_next[0] = alert_en_42_qs; end addr_hit[117]: begin - reg_rdata_next[0] = alert_en_44_qs; + reg_rdata_next[0] = alert_en_43_qs; end addr_hit[118]: begin - reg_rdata_next[0] = alert_en_45_qs; + reg_rdata_next[0] = alert_en_44_qs; end addr_hit[119]: begin - reg_rdata_next[0] = alert_en_46_qs; + reg_rdata_next[0] = alert_en_45_qs; end addr_hit[120]: begin - reg_rdata_next[0] = alert_en_47_qs; + reg_rdata_next[0] = alert_en_46_qs; end addr_hit[121]: begin - reg_rdata_next[0] = alert_en_48_qs; + reg_rdata_next[0] = alert_en_47_qs; end addr_hit[122]: begin - reg_rdata_next[0] = alert_en_49_qs; + reg_rdata_next[0] = alert_en_48_qs; end addr_hit[123]: begin - reg_rdata_next[0] = alert_en_50_qs; + reg_rdata_next[0] = alert_en_49_qs; end addr_hit[124]: begin - reg_rdata_next[0] = alert_en_51_qs; + reg_rdata_next[0] = alert_en_50_qs; end addr_hit[125]: begin - reg_rdata_next[0] = alert_en_52_qs; + reg_rdata_next[0] = alert_en_51_qs; end addr_hit[126]: begin - reg_rdata_next[0] = alert_en_53_qs; + reg_rdata_next[0] = alert_en_52_qs; end addr_hit[127]: begin - reg_rdata_next[0] = alert_en_54_qs; + reg_rdata_next[0] = alert_en_53_qs; end addr_hit[128]: begin - reg_rdata_next[0] = alert_en_55_qs; + reg_rdata_next[0] = alert_en_54_qs; end addr_hit[129]: begin - reg_rdata_next[0] = alert_en_56_qs; + reg_rdata_next[0] = alert_en_55_qs; end addr_hit[130]: begin - reg_rdata_next[0] = alert_en_57_qs; + reg_rdata_next[0] = alert_en_56_qs; end addr_hit[131]: begin - reg_rdata_next[0] = alert_en_58_qs; + reg_rdata_next[0] = alert_en_57_qs; end addr_hit[132]: begin - reg_rdata_next[0] = alert_en_59_qs; + reg_rdata_next[0] = alert_en_58_qs; end addr_hit[133]: begin - reg_rdata_next[0] = alert_en_60_qs; + reg_rdata_next[0] = alert_en_59_qs; end addr_hit[134]: begin - reg_rdata_next[0] = alert_en_61_qs; + reg_rdata_next[0] = alert_en_60_qs; end addr_hit[135]: begin - reg_rdata_next[0] = alert_en_62_qs; + reg_rdata_next[0] = alert_en_61_qs; end addr_hit[136]: begin - reg_rdata_next[0] = alert_en_63_qs; + reg_rdata_next[0] = alert_en_62_qs; end addr_hit[137]: begin - reg_rdata_next[0] = alert_en_64_qs; + reg_rdata_next[0] = alert_en_63_qs; end addr_hit[138]: begin - reg_rdata_next[0] = alert_en_65_qs; + reg_rdata_next[0] = alert_en_64_qs; end addr_hit[139]: begin - reg_rdata_next[0] = alert_en_66_qs; + reg_rdata_next[0] = alert_en_65_qs; end addr_hit[140]: begin - reg_rdata_next[1:0] = alert_class_0_qs; + reg_rdata_next[0] = alert_en_66_qs; end addr_hit[141]: begin - reg_rdata_next[1:0] = alert_class_1_qs; + reg_rdata_next[0] = alert_en_67_qs; end addr_hit[142]: begin - reg_rdata_next[1:0] = alert_class_2_qs; + reg_rdata_next[1:0] = alert_class_0_qs; end addr_hit[143]: begin - reg_rdata_next[1:0] = alert_class_3_qs; + reg_rdata_next[1:0] = alert_class_1_qs; end addr_hit[144]: begin - reg_rdata_next[1:0] = alert_class_4_qs; + reg_rdata_next[1:0] = alert_class_2_qs; end addr_hit[145]: begin - reg_rdata_next[1:0] = alert_class_5_qs; + reg_rdata_next[1:0] = alert_class_3_qs; end addr_hit[146]: begin - reg_rdata_next[1:0] = alert_class_6_qs; + reg_rdata_next[1:0] = alert_class_4_qs; end addr_hit[147]: begin - reg_rdata_next[1:0] = alert_class_7_qs; + reg_rdata_next[1:0] = alert_class_5_qs; end addr_hit[148]: begin - reg_rdata_next[1:0] = alert_class_8_qs; + reg_rdata_next[1:0] = alert_class_6_qs; end addr_hit[149]: begin - reg_rdata_next[1:0] = alert_class_9_qs; + reg_rdata_next[1:0] = alert_class_7_qs; end addr_hit[150]: begin - reg_rdata_next[1:0] = alert_class_10_qs; + reg_rdata_next[1:0] = alert_class_8_qs; end addr_hit[151]: begin - reg_rdata_next[1:0] = alert_class_11_qs; + reg_rdata_next[1:0] = alert_class_9_qs; end addr_hit[152]: begin - reg_rdata_next[1:0] = alert_class_12_qs; + reg_rdata_next[1:0] = alert_class_10_qs; end addr_hit[153]: begin - reg_rdata_next[1:0] = alert_class_13_qs; + reg_rdata_next[1:0] = alert_class_11_qs; end addr_hit[154]: begin - reg_rdata_next[1:0] = alert_class_14_qs; + reg_rdata_next[1:0] = alert_class_12_qs; end addr_hit[155]: begin - reg_rdata_next[1:0] = alert_class_15_qs; + reg_rdata_next[1:0] = alert_class_13_qs; end addr_hit[156]: begin - reg_rdata_next[1:0] = alert_class_16_qs; + reg_rdata_next[1:0] = alert_class_14_qs; end addr_hit[157]: begin - reg_rdata_next[1:0] = alert_class_17_qs; + reg_rdata_next[1:0] = alert_class_15_qs; end addr_hit[158]: begin - reg_rdata_next[1:0] = alert_class_18_qs; + reg_rdata_next[1:0] = alert_class_16_qs; end addr_hit[159]: begin - reg_rdata_next[1:0] = alert_class_19_qs; + reg_rdata_next[1:0] = alert_class_17_qs; end addr_hit[160]: begin - reg_rdata_next[1:0] = alert_class_20_qs; + reg_rdata_next[1:0] = alert_class_18_qs; end addr_hit[161]: begin - reg_rdata_next[1:0] = alert_class_21_qs; + reg_rdata_next[1:0] = alert_class_19_qs; end addr_hit[162]: begin - reg_rdata_next[1:0] = alert_class_22_qs; + reg_rdata_next[1:0] = alert_class_20_qs; end addr_hit[163]: begin - reg_rdata_next[1:0] = alert_class_23_qs; + reg_rdata_next[1:0] = alert_class_21_qs; end addr_hit[164]: begin - reg_rdata_next[1:0] = alert_class_24_qs; + reg_rdata_next[1:0] = alert_class_22_qs; end addr_hit[165]: begin - reg_rdata_next[1:0] = alert_class_25_qs; + reg_rdata_next[1:0] = alert_class_23_qs; end addr_hit[166]: begin - reg_rdata_next[1:0] = alert_class_26_qs; + reg_rdata_next[1:0] = alert_class_24_qs; end addr_hit[167]: begin - reg_rdata_next[1:0] = alert_class_27_qs; + reg_rdata_next[1:0] = alert_class_25_qs; end addr_hit[168]: begin - reg_rdata_next[1:0] = alert_class_28_qs; + reg_rdata_next[1:0] = alert_class_26_qs; end addr_hit[169]: begin - reg_rdata_next[1:0] = alert_class_29_qs; + reg_rdata_next[1:0] = alert_class_27_qs; end addr_hit[170]: begin - reg_rdata_next[1:0] = alert_class_30_qs; + reg_rdata_next[1:0] = alert_class_28_qs; end addr_hit[171]: begin - reg_rdata_next[1:0] = alert_class_31_qs; + reg_rdata_next[1:0] = alert_class_29_qs; end addr_hit[172]: begin - reg_rdata_next[1:0] = alert_class_32_qs; + reg_rdata_next[1:0] = alert_class_30_qs; end addr_hit[173]: begin - reg_rdata_next[1:0] = alert_class_33_qs; + reg_rdata_next[1:0] = alert_class_31_qs; end addr_hit[174]: begin - reg_rdata_next[1:0] = alert_class_34_qs; + reg_rdata_next[1:0] = alert_class_32_qs; end addr_hit[175]: begin - reg_rdata_next[1:0] = alert_class_35_qs; + reg_rdata_next[1:0] = alert_class_33_qs; end addr_hit[176]: begin - reg_rdata_next[1:0] = alert_class_36_qs; + reg_rdata_next[1:0] = alert_class_34_qs; end addr_hit[177]: begin - reg_rdata_next[1:0] = alert_class_37_qs; + reg_rdata_next[1:0] = alert_class_35_qs; end addr_hit[178]: begin - reg_rdata_next[1:0] = alert_class_38_qs; + reg_rdata_next[1:0] = alert_class_36_qs; end addr_hit[179]: begin - reg_rdata_next[1:0] = alert_class_39_qs; + reg_rdata_next[1:0] = alert_class_37_qs; end addr_hit[180]: begin - reg_rdata_next[1:0] = alert_class_40_qs; + reg_rdata_next[1:0] = alert_class_38_qs; end addr_hit[181]: begin - reg_rdata_next[1:0] = alert_class_41_qs; + reg_rdata_next[1:0] = alert_class_39_qs; end addr_hit[182]: begin - reg_rdata_next[1:0] = alert_class_42_qs; + reg_rdata_next[1:0] = alert_class_40_qs; end addr_hit[183]: begin - reg_rdata_next[1:0] = alert_class_43_qs; + reg_rdata_next[1:0] = alert_class_41_qs; end addr_hit[184]: begin - reg_rdata_next[1:0] = alert_class_44_qs; + reg_rdata_next[1:0] = alert_class_42_qs; end addr_hit[185]: begin - reg_rdata_next[1:0] = alert_class_45_qs; + reg_rdata_next[1:0] = alert_class_43_qs; end addr_hit[186]: begin - reg_rdata_next[1:0] = alert_class_46_qs; + reg_rdata_next[1:0] = alert_class_44_qs; end addr_hit[187]: begin - reg_rdata_next[1:0] = alert_class_47_qs; + reg_rdata_next[1:0] = alert_class_45_qs; end addr_hit[188]: begin - reg_rdata_next[1:0] = alert_class_48_qs; + reg_rdata_next[1:0] = alert_class_46_qs; end addr_hit[189]: begin - reg_rdata_next[1:0] = alert_class_49_qs; + reg_rdata_next[1:0] = alert_class_47_qs; end addr_hit[190]: begin - reg_rdata_next[1:0] = alert_class_50_qs; + reg_rdata_next[1:0] = alert_class_48_qs; end addr_hit[191]: begin - reg_rdata_next[1:0] = alert_class_51_qs; + reg_rdata_next[1:0] = alert_class_49_qs; end addr_hit[192]: begin - reg_rdata_next[1:0] = alert_class_52_qs; + reg_rdata_next[1:0] = alert_class_50_qs; end addr_hit[193]: begin - reg_rdata_next[1:0] = alert_class_53_qs; + reg_rdata_next[1:0] = alert_class_51_qs; end addr_hit[194]: begin - reg_rdata_next[1:0] = alert_class_54_qs; + reg_rdata_next[1:0] = alert_class_52_qs; end addr_hit[195]: begin - reg_rdata_next[1:0] = alert_class_55_qs; + reg_rdata_next[1:0] = alert_class_53_qs; end addr_hit[196]: begin - reg_rdata_next[1:0] = alert_class_56_qs; + reg_rdata_next[1:0] = alert_class_54_qs; end addr_hit[197]: begin - reg_rdata_next[1:0] = alert_class_57_qs; + reg_rdata_next[1:0] = alert_class_55_qs; end addr_hit[198]: begin - reg_rdata_next[1:0] = alert_class_58_qs; + reg_rdata_next[1:0] = alert_class_56_qs; end addr_hit[199]: begin - reg_rdata_next[1:0] = alert_class_59_qs; + reg_rdata_next[1:0] = alert_class_57_qs; end addr_hit[200]: begin - reg_rdata_next[1:0] = alert_class_60_qs; + reg_rdata_next[1:0] = alert_class_58_qs; end addr_hit[201]: begin - reg_rdata_next[1:0] = alert_class_61_qs; + reg_rdata_next[1:0] = alert_class_59_qs; end addr_hit[202]: begin - reg_rdata_next[1:0] = alert_class_62_qs; + reg_rdata_next[1:0] = alert_class_60_qs; end addr_hit[203]: begin - reg_rdata_next[1:0] = alert_class_63_qs; + reg_rdata_next[1:0] = alert_class_61_qs; end addr_hit[204]: begin - reg_rdata_next[1:0] = alert_class_64_qs; + reg_rdata_next[1:0] = alert_class_62_qs; end addr_hit[205]: begin - reg_rdata_next[1:0] = alert_class_65_qs; + reg_rdata_next[1:0] = alert_class_63_qs; end addr_hit[206]: begin - reg_rdata_next[1:0] = alert_class_66_qs; + reg_rdata_next[1:0] = alert_class_64_qs; end addr_hit[207]: begin - reg_rdata_next[0] = alert_cause_0_qs; + reg_rdata_next[1:0] = alert_class_65_qs; end addr_hit[208]: begin - reg_rdata_next[0] = alert_cause_1_qs; + reg_rdata_next[1:0] = alert_class_66_qs; end addr_hit[209]: begin - reg_rdata_next[0] = alert_cause_2_qs; + reg_rdata_next[1:0] = alert_class_67_qs; end addr_hit[210]: begin - reg_rdata_next[0] = alert_cause_3_qs; + reg_rdata_next[0] = alert_cause_0_qs; end addr_hit[211]: begin - reg_rdata_next[0] = alert_cause_4_qs; + reg_rdata_next[0] = alert_cause_1_qs; end addr_hit[212]: begin - reg_rdata_next[0] = alert_cause_5_qs; + reg_rdata_next[0] = alert_cause_2_qs; end addr_hit[213]: begin - reg_rdata_next[0] = alert_cause_6_qs; + reg_rdata_next[0] = alert_cause_3_qs; end addr_hit[214]: begin - reg_rdata_next[0] = alert_cause_7_qs; + reg_rdata_next[0] = alert_cause_4_qs; end addr_hit[215]: begin - reg_rdata_next[0] = alert_cause_8_qs; + reg_rdata_next[0] = alert_cause_5_qs; end addr_hit[216]: begin - reg_rdata_next[0] = alert_cause_9_qs; + reg_rdata_next[0] = alert_cause_6_qs; end addr_hit[217]: begin - reg_rdata_next[0] = alert_cause_10_qs; + reg_rdata_next[0] = alert_cause_7_qs; end addr_hit[218]: begin - reg_rdata_next[0] = alert_cause_11_qs; + reg_rdata_next[0] = alert_cause_8_qs; end addr_hit[219]: begin - reg_rdata_next[0] = alert_cause_12_qs; + reg_rdata_next[0] = alert_cause_9_qs; end addr_hit[220]: begin - reg_rdata_next[0] = alert_cause_13_qs; + reg_rdata_next[0] = alert_cause_10_qs; end addr_hit[221]: begin - reg_rdata_next[0] = alert_cause_14_qs; + reg_rdata_next[0] = alert_cause_11_qs; end addr_hit[222]: begin - reg_rdata_next[0] = alert_cause_15_qs; + reg_rdata_next[0] = alert_cause_12_qs; end addr_hit[223]: begin - reg_rdata_next[0] = alert_cause_16_qs; + reg_rdata_next[0] = alert_cause_13_qs; end addr_hit[224]: begin - reg_rdata_next[0] = alert_cause_17_qs; + reg_rdata_next[0] = alert_cause_14_qs; end addr_hit[225]: begin - reg_rdata_next[0] = alert_cause_18_qs; + reg_rdata_next[0] = alert_cause_15_qs; end addr_hit[226]: begin - reg_rdata_next[0] = alert_cause_19_qs; + reg_rdata_next[0] = alert_cause_16_qs; end addr_hit[227]: begin - reg_rdata_next[0] = alert_cause_20_qs; + reg_rdata_next[0] = alert_cause_17_qs; end addr_hit[228]: begin - reg_rdata_next[0] = alert_cause_21_qs; + reg_rdata_next[0] = alert_cause_18_qs; end addr_hit[229]: begin - reg_rdata_next[0] = alert_cause_22_qs; + reg_rdata_next[0] = alert_cause_19_qs; end addr_hit[230]: begin - reg_rdata_next[0] = alert_cause_23_qs; + reg_rdata_next[0] = alert_cause_20_qs; end addr_hit[231]: begin - reg_rdata_next[0] = alert_cause_24_qs; + reg_rdata_next[0] = alert_cause_21_qs; end addr_hit[232]: begin - reg_rdata_next[0] = alert_cause_25_qs; + reg_rdata_next[0] = alert_cause_22_qs; end addr_hit[233]: begin - reg_rdata_next[0] = alert_cause_26_qs; + reg_rdata_next[0] = alert_cause_23_qs; end addr_hit[234]: begin - reg_rdata_next[0] = alert_cause_27_qs; + reg_rdata_next[0] = alert_cause_24_qs; end addr_hit[235]: begin - reg_rdata_next[0] = alert_cause_28_qs; + reg_rdata_next[0] = alert_cause_25_qs; end addr_hit[236]: begin - reg_rdata_next[0] = alert_cause_29_qs; + reg_rdata_next[0] = alert_cause_26_qs; end addr_hit[237]: begin - reg_rdata_next[0] = alert_cause_30_qs; + reg_rdata_next[0] = alert_cause_27_qs; end addr_hit[238]: begin - reg_rdata_next[0] = alert_cause_31_qs; + reg_rdata_next[0] = alert_cause_28_qs; end addr_hit[239]: begin - reg_rdata_next[0] = alert_cause_32_qs; + reg_rdata_next[0] = alert_cause_29_qs; end addr_hit[240]: begin - reg_rdata_next[0] = alert_cause_33_qs; + reg_rdata_next[0] = alert_cause_30_qs; end addr_hit[241]: begin - reg_rdata_next[0] = alert_cause_34_qs; + reg_rdata_next[0] = alert_cause_31_qs; end addr_hit[242]: begin - reg_rdata_next[0] = alert_cause_35_qs; + reg_rdata_next[0] = alert_cause_32_qs; end addr_hit[243]: begin - reg_rdata_next[0] = alert_cause_36_qs; + reg_rdata_next[0] = alert_cause_33_qs; end addr_hit[244]: begin - reg_rdata_next[0] = alert_cause_37_qs; + reg_rdata_next[0] = alert_cause_34_qs; end addr_hit[245]: begin - reg_rdata_next[0] = alert_cause_38_qs; + reg_rdata_next[0] = alert_cause_35_qs; end addr_hit[246]: begin - reg_rdata_next[0] = alert_cause_39_qs; + reg_rdata_next[0] = alert_cause_36_qs; end addr_hit[247]: begin - reg_rdata_next[0] = alert_cause_40_qs; + reg_rdata_next[0] = alert_cause_37_qs; end addr_hit[248]: begin - reg_rdata_next[0] = alert_cause_41_qs; + reg_rdata_next[0] = alert_cause_38_qs; end addr_hit[249]: begin - reg_rdata_next[0] = alert_cause_42_qs; + reg_rdata_next[0] = alert_cause_39_qs; end addr_hit[250]: begin - reg_rdata_next[0] = alert_cause_43_qs; + reg_rdata_next[0] = alert_cause_40_qs; end addr_hit[251]: begin - reg_rdata_next[0] = alert_cause_44_qs; + reg_rdata_next[0] = alert_cause_41_qs; end addr_hit[252]: begin - reg_rdata_next[0] = alert_cause_45_qs; + reg_rdata_next[0] = alert_cause_42_qs; end addr_hit[253]: begin - reg_rdata_next[0] = alert_cause_46_qs; + reg_rdata_next[0] = alert_cause_43_qs; end addr_hit[254]: begin - reg_rdata_next[0] = alert_cause_47_qs; + reg_rdata_next[0] = alert_cause_44_qs; end addr_hit[255]: begin - reg_rdata_next[0] = alert_cause_48_qs; + reg_rdata_next[0] = alert_cause_45_qs; end addr_hit[256]: begin - reg_rdata_next[0] = alert_cause_49_qs; + reg_rdata_next[0] = alert_cause_46_qs; end addr_hit[257]: begin - reg_rdata_next[0] = alert_cause_50_qs; + reg_rdata_next[0] = alert_cause_47_qs; end addr_hit[258]: begin - reg_rdata_next[0] = alert_cause_51_qs; + reg_rdata_next[0] = alert_cause_48_qs; end addr_hit[259]: begin - reg_rdata_next[0] = alert_cause_52_qs; + reg_rdata_next[0] = alert_cause_49_qs; end addr_hit[260]: begin - reg_rdata_next[0] = alert_cause_53_qs; + reg_rdata_next[0] = alert_cause_50_qs; end addr_hit[261]: begin - reg_rdata_next[0] = alert_cause_54_qs; + reg_rdata_next[0] = alert_cause_51_qs; end addr_hit[262]: begin - reg_rdata_next[0] = alert_cause_55_qs; + reg_rdata_next[0] = alert_cause_52_qs; end addr_hit[263]: begin - reg_rdata_next[0] = alert_cause_56_qs; + reg_rdata_next[0] = alert_cause_53_qs; end addr_hit[264]: begin - reg_rdata_next[0] = alert_cause_57_qs; + reg_rdata_next[0] = alert_cause_54_qs; end addr_hit[265]: begin - reg_rdata_next[0] = alert_cause_58_qs; + reg_rdata_next[0] = alert_cause_55_qs; end addr_hit[266]: begin - reg_rdata_next[0] = alert_cause_59_qs; + reg_rdata_next[0] = alert_cause_56_qs; end addr_hit[267]: begin - reg_rdata_next[0] = alert_cause_60_qs; + reg_rdata_next[0] = alert_cause_57_qs; end addr_hit[268]: begin - reg_rdata_next[0] = alert_cause_61_qs; + reg_rdata_next[0] = alert_cause_58_qs; end addr_hit[269]: begin - reg_rdata_next[0] = alert_cause_62_qs; + reg_rdata_next[0] = alert_cause_59_qs; end addr_hit[270]: begin - reg_rdata_next[0] = alert_cause_63_qs; + reg_rdata_next[0] = alert_cause_60_qs; end addr_hit[271]: begin - reg_rdata_next[0] = alert_cause_64_qs; + reg_rdata_next[0] = alert_cause_61_qs; end addr_hit[272]: begin - reg_rdata_next[0] = alert_cause_65_qs; + reg_rdata_next[0] = alert_cause_62_qs; end addr_hit[273]: begin - reg_rdata_next[0] = alert_cause_66_qs; + reg_rdata_next[0] = alert_cause_63_qs; end addr_hit[274]: begin - reg_rdata_next[0] = loc_alert_regwen_0_qs; + reg_rdata_next[0] = alert_cause_64_qs; end addr_hit[275]: begin - reg_rdata_next[0] = loc_alert_regwen_1_qs; + reg_rdata_next[0] = alert_cause_65_qs; end addr_hit[276]: begin - reg_rdata_next[0] = loc_alert_regwen_2_qs; + reg_rdata_next[0] = alert_cause_66_qs; end addr_hit[277]: begin - reg_rdata_next[0] = loc_alert_regwen_3_qs; + reg_rdata_next[0] = alert_cause_67_qs; end addr_hit[278]: begin - reg_rdata_next[0] = loc_alert_regwen_4_qs; + reg_rdata_next[0] = loc_alert_regwen_0_qs; end addr_hit[279]: begin - reg_rdata_next[0] = loc_alert_en_0_qs; + reg_rdata_next[0] = loc_alert_regwen_1_qs; end addr_hit[280]: begin - reg_rdata_next[0] = loc_alert_en_1_qs; + reg_rdata_next[0] = loc_alert_regwen_2_qs; end addr_hit[281]: begin - reg_rdata_next[0] = loc_alert_en_2_qs; + reg_rdata_next[0] = loc_alert_regwen_3_qs; end addr_hit[282]: begin - reg_rdata_next[0] = loc_alert_en_3_qs; + reg_rdata_next[0] = loc_alert_regwen_4_qs; end addr_hit[283]: begin - reg_rdata_next[0] = loc_alert_en_4_qs; + reg_rdata_next[0] = loc_alert_en_0_qs; end addr_hit[284]: begin - reg_rdata_next[1:0] = loc_alert_class_0_qs; + reg_rdata_next[0] = loc_alert_en_1_qs; end addr_hit[285]: begin - reg_rdata_next[1:0] = loc_alert_class_1_qs; + reg_rdata_next[0] = loc_alert_en_2_qs; end addr_hit[286]: begin - reg_rdata_next[1:0] = loc_alert_class_2_qs; + reg_rdata_next[0] = loc_alert_en_3_qs; end addr_hit[287]: begin - reg_rdata_next[1:0] = loc_alert_class_3_qs; + reg_rdata_next[0] = loc_alert_en_4_qs; end addr_hit[288]: begin - reg_rdata_next[1:0] = loc_alert_class_4_qs; + reg_rdata_next[1:0] = loc_alert_class_0_qs; end addr_hit[289]: begin - reg_rdata_next[0] = loc_alert_cause_0_qs; + reg_rdata_next[1:0] = loc_alert_class_1_qs; end addr_hit[290]: begin - reg_rdata_next[0] = loc_alert_cause_1_qs; + reg_rdata_next[1:0] = loc_alert_class_2_qs; end addr_hit[291]: begin - reg_rdata_next[0] = loc_alert_cause_2_qs; + reg_rdata_next[1:0] = loc_alert_class_3_qs; end addr_hit[292]: begin - reg_rdata_next[0] = loc_alert_cause_3_qs; + reg_rdata_next[1:0] = loc_alert_class_4_qs; end addr_hit[293]: begin - reg_rdata_next[0] = loc_alert_cause_4_qs; + reg_rdata_next[0] = loc_alert_cause_0_qs; end addr_hit[294]: begin - reg_rdata_next[0] = classa_regwen_qs; + reg_rdata_next[0] = loc_alert_cause_1_qs; end addr_hit[295]: begin + reg_rdata_next[0] = loc_alert_cause_2_qs; + end + + addr_hit[296]: begin + reg_rdata_next[0] = loc_alert_cause_3_qs; + end + + addr_hit[297]: begin + reg_rdata_next[0] = loc_alert_cause_4_qs; + end + + addr_hit[298]: begin + reg_rdata_next[0] = classa_regwen_qs; + end + + addr_hit[299]: begin reg_rdata_next[0] = classa_ctrl_en_qs; reg_rdata_next[1] = classa_ctrl_lock_qs; reg_rdata_next[2] = classa_ctrl_en_e0_qs; @@ -14589,55 +14745,55 @@ reg_rdata_next[13:12] = classa_ctrl_map_e3_qs; end - addr_hit[296]: begin + addr_hit[300]: begin reg_rdata_next[0] = classa_clr_regwen_qs; end - addr_hit[297]: begin + addr_hit[301]: begin reg_rdata_next[0] = '0; end - addr_hit[298]: begin + addr_hit[302]: begin reg_rdata_next[15:0] = classa_accum_cnt_qs; end - addr_hit[299]: begin + addr_hit[303]: begin reg_rdata_next[15:0] = classa_accum_thresh_qs; end - addr_hit[300]: begin + addr_hit[304]: begin reg_rdata_next[31:0] = classa_timeout_cyc_qs; end - addr_hit[301]: begin + addr_hit[305]: begin reg_rdata_next[31:0] = classa_phase0_cyc_qs; end - addr_hit[302]: begin + addr_hit[306]: begin reg_rdata_next[31:0] = classa_phase1_cyc_qs; end - addr_hit[303]: begin + addr_hit[307]: begin reg_rdata_next[31:0] = classa_phase2_cyc_qs; end - addr_hit[304]: begin + addr_hit[308]: begin reg_rdata_next[31:0] = classa_phase3_cyc_qs; end - addr_hit[305]: begin + addr_hit[309]: begin reg_rdata_next[31:0] = classa_esc_cnt_qs; end - addr_hit[306]: begin + addr_hit[310]: begin reg_rdata_next[2:0] = classa_state_qs; end - addr_hit[307]: begin + addr_hit[311]: begin reg_rdata_next[0] = classb_regwen_qs; end - addr_hit[308]: begin + addr_hit[312]: begin reg_rdata_next[0] = classb_ctrl_en_qs; reg_rdata_next[1] = classb_ctrl_lock_qs; reg_rdata_next[2] = classb_ctrl_en_e0_qs; @@ -14650,55 +14806,55 @@ reg_rdata_next[13:12] = classb_ctrl_map_e3_qs; end - addr_hit[309]: begin + addr_hit[313]: begin reg_rdata_next[0] = classb_clr_regwen_qs; end - addr_hit[310]: begin + addr_hit[314]: begin reg_rdata_next[0] = '0; end - addr_hit[311]: begin + addr_hit[315]: begin reg_rdata_next[15:0] = classb_accum_cnt_qs; end - addr_hit[312]: begin + addr_hit[316]: begin reg_rdata_next[15:0] = classb_accum_thresh_qs; end - addr_hit[313]: begin + addr_hit[317]: begin reg_rdata_next[31:0] = classb_timeout_cyc_qs; end - addr_hit[314]: begin + addr_hit[318]: begin reg_rdata_next[31:0] = classb_phase0_cyc_qs; end - addr_hit[315]: begin + addr_hit[319]: begin reg_rdata_next[31:0] = classb_phase1_cyc_qs; end - addr_hit[316]: begin + addr_hit[320]: begin reg_rdata_next[31:0] = classb_phase2_cyc_qs; end - addr_hit[317]: begin + addr_hit[321]: begin reg_rdata_next[31:0] = classb_phase3_cyc_qs; end - addr_hit[318]: begin + addr_hit[322]: begin reg_rdata_next[31:0] = classb_esc_cnt_qs; end - addr_hit[319]: begin + addr_hit[323]: begin reg_rdata_next[2:0] = classb_state_qs; end - addr_hit[320]: begin + addr_hit[324]: begin reg_rdata_next[0] = classc_regwen_qs; end - addr_hit[321]: begin + addr_hit[325]: begin reg_rdata_next[0] = classc_ctrl_en_qs; reg_rdata_next[1] = classc_ctrl_lock_qs; reg_rdata_next[2] = classc_ctrl_en_e0_qs; @@ -14711,55 +14867,55 @@ reg_rdata_next[13:12] = classc_ctrl_map_e3_qs; end - addr_hit[322]: begin + addr_hit[326]: begin reg_rdata_next[0] = classc_clr_regwen_qs; end - addr_hit[323]: begin + addr_hit[327]: begin reg_rdata_next[0] = '0; end - addr_hit[324]: begin + addr_hit[328]: begin reg_rdata_next[15:0] = classc_accum_cnt_qs; end - addr_hit[325]: begin + addr_hit[329]: begin reg_rdata_next[15:0] = classc_accum_thresh_qs; end - addr_hit[326]: begin + addr_hit[330]: begin reg_rdata_next[31:0] = classc_timeout_cyc_qs; end - addr_hit[327]: begin + addr_hit[331]: begin reg_rdata_next[31:0] = classc_phase0_cyc_qs; end - addr_hit[328]: begin + addr_hit[332]: begin reg_rdata_next[31:0] = classc_phase1_cyc_qs; end - addr_hit[329]: begin + addr_hit[333]: begin reg_rdata_next[31:0] = classc_phase2_cyc_qs; end - addr_hit[330]: begin + addr_hit[334]: begin reg_rdata_next[31:0] = classc_phase3_cyc_qs; end - addr_hit[331]: begin + addr_hit[335]: begin reg_rdata_next[31:0] = classc_esc_cnt_qs; end - addr_hit[332]: begin + addr_hit[336]: begin reg_rdata_next[2:0] = classc_state_qs; end - addr_hit[333]: begin + addr_hit[337]: begin reg_rdata_next[0] = classd_regwen_qs; end - addr_hit[334]: begin + addr_hit[338]: begin reg_rdata_next[0] = classd_ctrl_en_qs; reg_rdata_next[1] = classd_ctrl_lock_qs; reg_rdata_next[2] = classd_ctrl_en_e0_qs; @@ -14772,47 +14928,47 @@ reg_rdata_next[13:12] = classd_ctrl_map_e3_qs; end - addr_hit[335]: begin + addr_hit[339]: begin reg_rdata_next[0] = classd_clr_regwen_qs; end - addr_hit[336]: begin + addr_hit[340]: begin reg_rdata_next[0] = '0; end - addr_hit[337]: begin + addr_hit[341]: begin reg_rdata_next[15:0] = classd_accum_cnt_qs; end - addr_hit[338]: begin + addr_hit[342]: begin reg_rdata_next[15:0] = classd_accum_thresh_qs; end - addr_hit[339]: begin + addr_hit[343]: begin reg_rdata_next[31:0] = classd_timeout_cyc_qs; end - addr_hit[340]: begin + addr_hit[344]: begin reg_rdata_next[31:0] = classd_phase0_cyc_qs; end - addr_hit[341]: begin + addr_hit[345]: begin reg_rdata_next[31:0] = classd_phase1_cyc_qs; end - addr_hit[342]: begin + addr_hit[346]: begin reg_rdata_next[31:0] = classd_phase2_cyc_qs; end - addr_hit[343]: begin + addr_hit[347]: begin reg_rdata_next[31:0] = classd_phase3_cyc_qs; end - addr_hit[344]: begin + addr_hit[348]: begin reg_rdata_next[31:0] = classd_esc_cnt_qs; end - addr_hit[345]: begin + addr_hit[349]: begin reg_rdata_next[2:0] = classd_state_qs; end
diff --git a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson index 0ec9616..11fac45 100644 --- a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson +++ b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
@@ -83,11 +83,15 @@ package: "rstmgr_pkg", // Origin package (only needs for the req) }, - { struct: "rstmgr_cpu", + { struct: "logic", type: "uni", - name: "cpu", + name: "rst_cpu_n", act: "rcv", - package: "rstmgr_pkg", // Origin package (only needs for the req) + }, + { struct: "logic", + type: "uni", + name: "ndmreset_req", + act: "rcv", }, { struct: "alert_crashdump",
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv index ed7d30f..0902c33 100644 --- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv +++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -42,7 +42,8 @@ output pwrmgr_pkg::pwr_rst_rsp_t pwr_o, // cpu related inputs - input rstmgr_cpu_t cpu_i, + input logic rst_cpu_n_i, + input logic ndmreset_req_i, // Interface to alert handler input alert_pkg::alert_crashdump_t alert_dump_i, @@ -157,7 +158,7 @@ ) u_sync ( .clk_i, .rst_ni(local_rst_n), - .d_i(cpu_i.ndmreset_req), + .d_i(ndmreset_req_i), .q_o(ndmreset_req_q) ); @@ -722,7 +723,7 @@ ) u_cpu_reset_synced ( .clk_i, .rst_ni(local_rst_n), - .d_i(cpu_i.rst_cpu_n), + .d_i(rst_cpu_n_i), .q_o(rst_cpu_nq) );
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index bbc4e8d..5444b9f 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -31,7 +31,7 @@ corei: [ rom_ctrl.rom - debug_mem + rv_dm.rom ram_main eflash ] @@ -39,7 +39,8 @@ [ rom_ctrl.rom rom_ctrl.regs - debug_mem + rv_dm.rom + rv_dm.regs ram_main eflash peri @@ -58,10 +59,11 @@ sram_ctrl_main rv_core_ibex_peri ] - dm_sba: + rv_dm.sba: [ rom_ctrl.rom rom_ctrl.regs + rv_dm.regs ram_main eflash peri @@ -106,14 +108,50 @@ pipeline_byp: "true" } { - name: dm_sba + name: rv_dm.sba type: host clock: clk_main_i reset: rst_main_ni pipeline_byp: "false" xbar: false stub: false + inst_type: "" + pipeline: "true" + } + { + name: rv_dm.regs + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline_byp: "false" inst_type: rv_dm + addr_range: + [ + { + base_addr: 0x41200000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: "true" + } + { + name: rv_dm.rom + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline_byp: "false" + inst_type: rv_dm + addr_range: + [ + { + base_addr: 0x10000 + size_byte: 0x1000 + } + ] + xbar: false + stub: false pipeline: "true" } { @@ -153,24 +191,6 @@ pipeline_byp: "true" } { - name: debug_mem - type: device - clock: clk_main_i - reset: rst_main_ni - pipeline_byp: "false" - inst_type: rv_dm - addr_range: - [ - { - base_addr: 0x1A110000 - size_byte: 0x1000 - } - ] - xbar: false - stub: false - pipeline: "true" - } - { name: ram_main type: device clock: clk_main_i
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson index 410ee1a..a079521 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
@@ -26,13 +26,25 @@ } { struct: "tl" type: "req_rsp" - name: "tl_dm_sba" + name: "tl_rv_dm__sba" act: "rsp" package: "tlul_pkg" } // device { struct: "tl" type: "req_rsp" + name: "tl_rv_dm__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_dm__rom" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" name: "tl_rom_ctrl__rom" act: "req" package: "tlul_pkg" @@ -45,12 +57,6 @@ } { struct: "tl" type: "req_rsp" - name: "tl_debug_mem" - act: "req" - package: "tlul_pkg" - } - { struct: "tl" - type: "req_rsp" name: "tl_ram_main" act: "req" package: "tlul_pkg"
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv index 142e90f..607bada 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
@@ -19,12 +19,13 @@ // Host TileLink interface connections `CONNECT_TL_HOST_IF(corei, dut, clk_main_i, rst_n) `CONNECT_TL_HOST_IF(cored, dut, clk_main_i, rst_n) -`CONNECT_TL_HOST_IF(dm_sba, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(rv_dm__sba, dut, clk_main_i, rst_n) // Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(rv_dm__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rv_dm__rom, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rom_ctrl__rom, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rom_ctrl__regs, dut, clk_main_i, rst_n) -`CONNECT_TL_DEVICE_IF(debug_mem, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(ram_main, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(eflash, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(peri, dut, clk_fixed_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg index dd50cb8..6d1825c 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
@@ -16,17 +16,18 @@ -node tb.dut tl_*.d_opcode[2:1] // [UNR] these device address bits are always 0 +-node tb.dut tl_rv_dm__regs_o.a_address[20:12] +-node tb.dut tl_rv_dm__regs_o.a_address[23:22] +-node tb.dut tl_rv_dm__regs_o.a_address[29:25] +-node tb.dut tl_rv_dm__regs_o.a_address[31:31] +-node tb.dut tl_rv_dm__rom_o.a_address[15:12] +-node tb.dut tl_rv_dm__rom_o.a_address[31:17] -node tb.dut tl_rom_ctrl__rom_o.a_address[14:14] -node tb.dut tl_rom_ctrl__rom_o.a_address[31:16] -node tb.dut tl_rom_ctrl__regs_o.a_address[16:12] -node tb.dut tl_rom_ctrl__regs_o.a_address[23:21] -node tb.dut tl_rom_ctrl__regs_o.a_address[29:25] -node tb.dut tl_rom_ctrl__regs_o.a_address[31:31] --node tb.dut tl_debug_mem_o.a_address[15:12] --node tb.dut tl_debug_mem_o.a_address[19:17] --node tb.dut tl_debug_mem_o.a_address[24:21] --node tb.dut tl_debug_mem_o.a_address[26:26] --node tb.dut tl_debug_mem_o.a_address[31:29] -node tb.dut tl_ram_main_o.a_address[27:17] -node tb.dut tl_ram_main_o.a_address[31:29] -node tb.dut tl_eflash_o.a_address[28:20]
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index 4498d6a..7d34b7e 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -7,15 +7,18 @@ // List of Xbar device memory map tl_device_t xbar_devices[$] = '{ + '{"rv_dm__regs", '{ + '{32'h41200000, 32'h41200fff} + }}, + '{"rv_dm__rom", '{ + '{32'h00010000, 32'h00010fff} + }}, '{"rom_ctrl__rom", '{ '{32'h00008000, 32'h0000bfff} }}, '{"rom_ctrl__regs", '{ '{32'h411e0000, 32'h411e0fff} }}, - '{"debug_mem", '{ - '{32'h1a110000, 32'h1a110fff} - }}, '{"ram_main", '{ '{32'h10000000, 32'h1001ffff} }}, @@ -72,14 +75,15 @@ tl_host_t xbar_hosts[$] = '{ '{"corei", 0, '{ "rom_ctrl__rom", - "debug_mem", + "rv_dm__rom", "ram_main", "eflash"}} , '{"cored", 1, '{ "rom_ctrl__rom", "rom_ctrl__regs", - "debug_mem", + "rv_dm__rom", + "rv_dm__regs", "ram_main", "eflash", "peri", @@ -98,9 +102,10 @@ "sram_ctrl_main", "rv_core_ibex_peri"}} , - '{"dm_sba", 2, '{ + '{"rv_dm__sba", 2, '{ "rom_ctrl__rom", "rom_ctrl__regs", + "rv_dm__regs", "ram_main", "eflash", "peri",
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv index 6c6c752..28772a2 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
@@ -18,14 +18,26 @@ .h2d (tl_cored_i), .d2h (tl_cored_o) ); - bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_dm_sba ( + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_dm__sba ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .h2d (tl_dm_sba_i), - .d2h (tl_dm_sba_o) + .h2d (tl_rv_dm__sba_i), + .d2h (tl_rv_dm__sba_o) ); // Device interfaces + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_dm__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_dm__regs_o), + .d2h (tl_rv_dm__regs_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_dm__rom ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_dm__rom_o), + .d2h (tl_rv_dm__rom_i) + ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl__rom ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), @@ -38,12 +50,6 @@ .h2d (tl_rom_ctrl__regs_o), .d2h (tl_rom_ctrl__regs_i) ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_debug_mem ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .h2d (tl_debug_mem_o), - .d2h (tl_debug_mem_i) - ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_ram_main ( .clk_i (clk_main_i), .rst_ni (rst_main_ni),
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index 21f65fc..90d93b4 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -6,9 +6,10 @@ package tl_main_pkg; + localparam logic [31:0] ADDR_SPACE_RV_DM__REGS = 32'h 41200000; + localparam logic [31:0] ADDR_SPACE_RV_DM__ROM = 32'h 00010000; localparam logic [31:0] ADDR_SPACE_ROM_CTRL__ROM = 32'h 00008000; localparam logic [31:0] ADDR_SPACE_ROM_CTRL__REGS = 32'h 411e0000; - localparam logic [31:0] ADDR_SPACE_DEBUG_MEM = 32'h 1a110000; localparam logic [31:0] ADDR_SPACE_RAM_MAIN = 32'h 10000000; localparam logic [31:0] ADDR_SPACE_EFLASH = 32'h 20000000; localparam logic [0:0][31:0] ADDR_SPACE_PERI = { @@ -29,9 +30,10 @@ localparam logic [31:0] ADDR_SPACE_RV_CORE_IBEX_PERI = 32'h 411f0000; localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN = 32'h 411c0000; + localparam logic [31:0] ADDR_MASK_RV_DM__REGS = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_RV_DM__ROM = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_ROM_CTRL__ROM = 32'h 00003fff; localparam logic [31:0] ADDR_MASK_ROM_CTRL__REGS = 32'h 00000fff; - localparam logic [31:0] ADDR_MASK_DEBUG_MEM = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_RAM_MAIN = 32'h 0001ffff; localparam logic [31:0] ADDR_MASK_EFLASH = 32'h 000fffff; localparam logic [0:0][31:0] ADDR_MASK_PERI = { @@ -53,35 +55,36 @@ localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN = 32'h 00000fff; localparam int N_HOST = 3; - localparam int N_DEVICE = 20; + localparam int N_DEVICE = 21; typedef enum int { - TlRomCtrlRom = 0, - TlRomCtrlRegs = 1, - TlDebugMem = 2, - TlRamMain = 3, - TlEflash = 4, - TlPeri = 5, - TlFlashCtrlCore = 6, - TlFlashCtrlPrim = 7, - TlHmac = 8, - TlKmac = 9, - TlAes = 10, - TlEntropySrc = 11, - TlCsrng = 12, - TlEdn0 = 13, - TlEdn1 = 14, - TlRvPlic = 15, - TlOtbn = 16, - TlKeymgr = 17, - TlRvCoreIbexPeri = 18, - TlSramCtrlMain = 19 + TlRvDmRegs = 0, + TlRvDmRom = 1, + TlRomCtrlRom = 2, + TlRomCtrlRegs = 3, + TlRamMain = 4, + TlEflash = 5, + TlPeri = 6, + TlFlashCtrlCore = 7, + TlFlashCtrlPrim = 8, + TlHmac = 9, + TlKmac = 10, + TlAes = 11, + TlEntropySrc = 12, + TlCsrng = 13, + TlEdn0 = 14, + TlEdn1 = 15, + TlRvPlic = 16, + TlOtbn = 17, + TlKeymgr = 18, + TlRvCoreIbexPeri = 19, + TlSramCtrlMain = 20 } tl_device_e; typedef enum int { TlCorei = 0, TlCored = 1, - TlDmSba = 2 + TlRvDmSba = 2 } tl_host_e; endpackage
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv index 85ff77a..88dc6a8 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -7,98 +7,102 @@ // // Interconnect // corei -// -> s1n_23 -// -> sm1_24 -// -> rom_ctrl.rom +// -> s1n_24 // -> sm1_25 -// -> debug_mem +// -> rom_ctrl.rom // -> sm1_26 -// -> ram_main +// -> rv_dm.rom // -> sm1_27 +// -> ram_main +// -> sm1_28 // -> eflash // cored -// -> s1n_28 -// -> sm1_24 -// -> rom_ctrl.rom -// -> sm1_29 -// -> rom_ctrl.regs +// -> s1n_29 // -> sm1_25 -// -> debug_mem -// -> sm1_26 -// -> ram_main -// -> sm1_27 -// -> eflash -// -> sm1_31 -// -> asf_30 -// -> peri -// -> sm1_32 -// -> flash_ctrl.core -// -> sm1_33 -// -> flash_ctrl.prim -// -> sm1_34 -// -> aes -// -> sm1_35 -// -> entropy_src -// -> sm1_36 -// -> csrng -// -> sm1_37 -// -> edn0 -// -> sm1_38 -// -> edn1 -// -> sm1_39 -// -> hmac -// -> sm1_40 -// -> rv_plic -// -> sm1_41 -// -> otbn -// -> sm1_42 -// -> keymgr -// -> sm1_43 -// -> kmac -// -> sm1_44 -// -> sram_ctrl_main -// -> sm1_45 -// -> rv_core_ibex_peri -// dm_sba -// -> s1n_46 -// -> sm1_24 // -> rom_ctrl.rom -// -> sm1_29 +// -> sm1_30 // -> rom_ctrl.regs // -> sm1_26 -// -> ram_main -// -> sm1_27 -// -> eflash +// -> rv_dm.rom // -> sm1_31 -// -> asf_30 -// -> peri -// -> sm1_32 -// -> flash_ctrl.core +// -> rv_dm.regs +// -> sm1_27 +// -> ram_main +// -> sm1_28 +// -> eflash // -> sm1_33 -// -> flash_ctrl.prim +// -> asf_32 +// -> peri // -> sm1_34 -// -> aes +// -> flash_ctrl.core // -> sm1_35 -// -> entropy_src +// -> flash_ctrl.prim // -> sm1_36 -// -> csrng +// -> aes // -> sm1_37 -// -> edn0 +// -> entropy_src // -> sm1_38 -// -> edn1 +// -> csrng // -> sm1_39 -// -> hmac +// -> edn0 // -> sm1_40 -// -> rv_plic +// -> edn1 // -> sm1_41 -// -> otbn +// -> hmac // -> sm1_42 -// -> keymgr +// -> rv_plic // -> sm1_43 -// -> kmac +// -> otbn // -> sm1_44 -// -> sram_ctrl_main +// -> keymgr // -> sm1_45 +// -> kmac +// -> sm1_46 +// -> sram_ctrl_main +// -> sm1_47 +// -> rv_core_ibex_peri +// rv_dm.sba +// -> s1n_48 +// -> sm1_25 +// -> rom_ctrl.rom +// -> sm1_30 +// -> rom_ctrl.regs +// -> sm1_31 +// -> rv_dm.regs +// -> sm1_27 +// -> ram_main +// -> sm1_28 +// -> eflash +// -> sm1_33 +// -> asf_32 +// -> peri +// -> sm1_34 +// -> flash_ctrl.core +// -> sm1_35 +// -> flash_ctrl.prim +// -> sm1_36 +// -> aes +// -> sm1_37 +// -> entropy_src +// -> sm1_38 +// -> csrng +// -> sm1_39 +// -> edn0 +// -> sm1_40 +// -> edn1 +// -> sm1_41 +// -> hmac +// -> sm1_42 +// -> rv_plic +// -> sm1_43 +// -> otbn +// -> sm1_44 +// -> keymgr +// -> sm1_45 +// -> kmac +// -> sm1_46 +// -> sram_ctrl_main +// -> sm1_47 // -> rv_core_ibex_peri module xbar_main ( @@ -112,16 +116,18 @@ output tlul_pkg::tl_d2h_t tl_corei_o, input tlul_pkg::tl_h2d_t tl_cored_i, output tlul_pkg::tl_d2h_t tl_cored_o, - input tlul_pkg::tl_h2d_t tl_dm_sba_i, - output tlul_pkg::tl_d2h_t tl_dm_sba_o, + input tlul_pkg::tl_h2d_t tl_rv_dm__sba_i, + output tlul_pkg::tl_d2h_t tl_rv_dm__sba_o, // Device interfaces + output tlul_pkg::tl_h2d_t tl_rv_dm__regs_o, + input tlul_pkg::tl_d2h_t tl_rv_dm__regs_i, + output tlul_pkg::tl_h2d_t tl_rv_dm__rom_o, + input tlul_pkg::tl_d2h_t tl_rv_dm__rom_i, output tlul_pkg::tl_h2d_t tl_rom_ctrl__rom_o, input tlul_pkg::tl_d2h_t tl_rom_ctrl__rom_i, output tlul_pkg::tl_h2d_t tl_rom_ctrl__regs_o, input tlul_pkg::tl_d2h_t tl_rom_ctrl__regs_i, - output tlul_pkg::tl_h2d_t tl_debug_mem_o, - input tlul_pkg::tl_d2h_t tl_debug_mem_i, output tlul_pkg::tl_h2d_t tl_ram_main_o, input tlul_pkg::tl_d2h_t tl_ram_main_i, output tlul_pkg::tl_h2d_t tl_eflash_o, @@ -168,33 +174,26 @@ lc_ctrl_pkg::lc_tx_t unused_scanmode; assign unused_scanmode = scanmode_i; - tl_h2d_t tl_s1n_23_us_h2d ; - tl_d2h_t tl_s1n_23_us_d2h ; + tl_h2d_t tl_s1n_24_us_h2d ; + tl_d2h_t tl_s1n_24_us_d2h ; - tl_h2d_t tl_s1n_23_ds_h2d [4]; - tl_d2h_t tl_s1n_23_ds_d2h [4]; + tl_h2d_t tl_s1n_24_ds_h2d [4]; + tl_d2h_t tl_s1n_24_ds_d2h [4]; // Create steering signal - logic [2:0] dev_sel_s1n_23; + logic [2:0] dev_sel_s1n_24; - tl_h2d_t tl_sm1_24_us_h2d [3]; - tl_d2h_t tl_sm1_24_us_d2h [3]; - - tl_h2d_t tl_sm1_24_ds_h2d ; - tl_d2h_t tl_sm1_24_ds_d2h ; - - - tl_h2d_t tl_sm1_25_us_h2d [2]; - tl_d2h_t tl_sm1_25_us_d2h [2]; + tl_h2d_t tl_sm1_25_us_h2d [3]; + tl_d2h_t tl_sm1_25_us_d2h [3]; tl_h2d_t tl_sm1_25_ds_h2d ; tl_d2h_t tl_sm1_25_ds_d2h ; - tl_h2d_t tl_sm1_26_us_h2d [3]; - tl_d2h_t tl_sm1_26_us_d2h [3]; + tl_h2d_t tl_sm1_26_us_h2d [2]; + tl_d2h_t tl_sm1_26_us_d2h [2]; tl_h2d_t tl_sm1_26_ds_h2d ; tl_d2h_t tl_sm1_26_ds_d2h ; @@ -206,27 +205,29 @@ tl_h2d_t tl_sm1_27_ds_h2d ; tl_d2h_t tl_sm1_27_ds_d2h ; - tl_h2d_t tl_s1n_28_us_h2d ; - tl_d2h_t tl_s1n_28_us_d2h ; + + tl_h2d_t tl_sm1_28_us_h2d [3]; + tl_d2h_t tl_sm1_28_us_d2h [3]; + + tl_h2d_t tl_sm1_28_ds_h2d ; + tl_d2h_t tl_sm1_28_ds_d2h ; + + tl_h2d_t tl_s1n_29_us_h2d ; + tl_d2h_t tl_s1n_29_us_d2h ; - tl_h2d_t tl_s1n_28_ds_h2d [20]; - tl_d2h_t tl_s1n_28_ds_d2h [20]; + tl_h2d_t tl_s1n_29_ds_h2d [21]; + tl_d2h_t tl_s1n_29_ds_d2h [21]; // Create steering signal - logic [4:0] dev_sel_s1n_28; + logic [4:0] dev_sel_s1n_29; - tl_h2d_t tl_sm1_29_us_h2d [2]; - tl_d2h_t tl_sm1_29_us_d2h [2]; + tl_h2d_t tl_sm1_30_us_h2d [2]; + tl_d2h_t tl_sm1_30_us_d2h [2]; - tl_h2d_t tl_sm1_29_ds_h2d ; - tl_d2h_t tl_sm1_29_ds_d2h ; - - tl_h2d_t tl_asf_30_us_h2d ; - tl_d2h_t tl_asf_30_us_d2h ; - tl_h2d_t tl_asf_30_ds_h2d ; - tl_d2h_t tl_asf_30_ds_d2h ; + tl_h2d_t tl_sm1_30_ds_h2d ; + tl_d2h_t tl_sm1_30_ds_d2h ; tl_h2d_t tl_sm1_31_us_h2d [2]; @@ -235,12 +236,10 @@ tl_h2d_t tl_sm1_31_ds_h2d ; tl_d2h_t tl_sm1_31_ds_d2h ; - - tl_h2d_t tl_sm1_32_us_h2d [2]; - tl_d2h_t tl_sm1_32_us_d2h [2]; - - tl_h2d_t tl_sm1_32_ds_h2d ; - tl_d2h_t tl_sm1_32_ds_d2h ; + tl_h2d_t tl_asf_32_us_h2d ; + tl_d2h_t tl_asf_32_us_d2h ; + tl_h2d_t tl_asf_32_ds_h2d ; + tl_d2h_t tl_asf_32_ds_d2h ; tl_h2d_t tl_sm1_33_us_h2d [2]; @@ -333,403 +332,434 @@ tl_h2d_t tl_sm1_45_ds_h2d ; tl_d2h_t tl_sm1_45_ds_d2h ; - tl_h2d_t tl_s1n_46_us_h2d ; - tl_d2h_t tl_s1n_46_us_d2h ; + + tl_h2d_t tl_sm1_46_us_h2d [2]; + tl_d2h_t tl_sm1_46_us_d2h [2]; + + tl_h2d_t tl_sm1_46_ds_h2d ; + tl_d2h_t tl_sm1_46_ds_d2h ; - tl_h2d_t tl_s1n_46_ds_h2d [19]; - tl_d2h_t tl_s1n_46_ds_d2h [19]; + tl_h2d_t tl_sm1_47_us_h2d [2]; + tl_d2h_t tl_sm1_47_us_d2h [2]; + + tl_h2d_t tl_sm1_47_ds_h2d ; + tl_d2h_t tl_sm1_47_ds_d2h ; + + tl_h2d_t tl_s1n_48_us_h2d ; + tl_d2h_t tl_s1n_48_us_d2h ; + + + tl_h2d_t tl_s1n_48_ds_h2d [20]; + tl_d2h_t tl_s1n_48_ds_d2h [20]; // Create steering signal - logic [4:0] dev_sel_s1n_46; + logic [4:0] dev_sel_s1n_48; - assign tl_sm1_24_us_h2d[0] = tl_s1n_23_ds_h2d[0]; - assign tl_s1n_23_ds_d2h[0] = tl_sm1_24_us_d2h[0]; + assign tl_sm1_25_us_h2d[0] = tl_s1n_24_ds_h2d[0]; + assign tl_s1n_24_ds_d2h[0] = tl_sm1_25_us_d2h[0]; - assign tl_sm1_25_us_h2d[0] = tl_s1n_23_ds_h2d[1]; - assign tl_s1n_23_ds_d2h[1] = tl_sm1_25_us_d2h[0]; + assign tl_sm1_26_us_h2d[0] = tl_s1n_24_ds_h2d[1]; + assign tl_s1n_24_ds_d2h[1] = tl_sm1_26_us_d2h[0]; - assign tl_sm1_26_us_h2d[0] = tl_s1n_23_ds_h2d[2]; - assign tl_s1n_23_ds_d2h[2] = tl_sm1_26_us_d2h[0]; + assign tl_sm1_27_us_h2d[0] = tl_s1n_24_ds_h2d[2]; + assign tl_s1n_24_ds_d2h[2] = tl_sm1_27_us_d2h[0]; - assign tl_sm1_27_us_h2d[0] = tl_s1n_23_ds_h2d[3]; - assign tl_s1n_23_ds_d2h[3] = tl_sm1_27_us_d2h[0]; + assign tl_sm1_28_us_h2d[0] = tl_s1n_24_ds_h2d[3]; + assign tl_s1n_24_ds_d2h[3] = tl_sm1_28_us_d2h[0]; - assign tl_sm1_24_us_h2d[1] = tl_s1n_28_ds_h2d[0]; - assign tl_s1n_28_ds_d2h[0] = tl_sm1_24_us_d2h[1]; + assign tl_sm1_25_us_h2d[1] = tl_s1n_29_ds_h2d[0]; + assign tl_s1n_29_ds_d2h[0] = tl_sm1_25_us_d2h[1]; - assign tl_sm1_29_us_h2d[0] = tl_s1n_28_ds_h2d[1]; - assign tl_s1n_28_ds_d2h[1] = tl_sm1_29_us_d2h[0]; + assign tl_sm1_30_us_h2d[0] = tl_s1n_29_ds_h2d[1]; + assign tl_s1n_29_ds_d2h[1] = tl_sm1_30_us_d2h[0]; - assign tl_sm1_25_us_h2d[1] = tl_s1n_28_ds_h2d[2]; - assign tl_s1n_28_ds_d2h[2] = tl_sm1_25_us_d2h[1]; + assign tl_sm1_26_us_h2d[1] = tl_s1n_29_ds_h2d[2]; + assign tl_s1n_29_ds_d2h[2] = tl_sm1_26_us_d2h[1]; - assign tl_sm1_26_us_h2d[1] = tl_s1n_28_ds_h2d[3]; - assign tl_s1n_28_ds_d2h[3] = tl_sm1_26_us_d2h[1]; + assign tl_sm1_31_us_h2d[0] = tl_s1n_29_ds_h2d[3]; + assign tl_s1n_29_ds_d2h[3] = tl_sm1_31_us_d2h[0]; - assign tl_sm1_27_us_h2d[1] = tl_s1n_28_ds_h2d[4]; - assign tl_s1n_28_ds_d2h[4] = tl_sm1_27_us_d2h[1]; + assign tl_sm1_27_us_h2d[1] = tl_s1n_29_ds_h2d[4]; + assign tl_s1n_29_ds_d2h[4] = tl_sm1_27_us_d2h[1]; - assign tl_sm1_31_us_h2d[0] = tl_s1n_28_ds_h2d[5]; - assign tl_s1n_28_ds_d2h[5] = tl_sm1_31_us_d2h[0]; + assign tl_sm1_28_us_h2d[1] = tl_s1n_29_ds_h2d[5]; + assign tl_s1n_29_ds_d2h[5] = tl_sm1_28_us_d2h[1]; - assign tl_sm1_32_us_h2d[0] = tl_s1n_28_ds_h2d[6]; - assign tl_s1n_28_ds_d2h[6] = tl_sm1_32_us_d2h[0]; + assign tl_sm1_33_us_h2d[0] = tl_s1n_29_ds_h2d[6]; + assign tl_s1n_29_ds_d2h[6] = tl_sm1_33_us_d2h[0]; - assign tl_sm1_33_us_h2d[0] = tl_s1n_28_ds_h2d[7]; - assign tl_s1n_28_ds_d2h[7] = tl_sm1_33_us_d2h[0]; + assign tl_sm1_34_us_h2d[0] = tl_s1n_29_ds_h2d[7]; + assign tl_s1n_29_ds_d2h[7] = tl_sm1_34_us_d2h[0]; - assign tl_sm1_34_us_h2d[0] = tl_s1n_28_ds_h2d[8]; - assign tl_s1n_28_ds_d2h[8] = tl_sm1_34_us_d2h[0]; + assign tl_sm1_35_us_h2d[0] = tl_s1n_29_ds_h2d[8]; + assign tl_s1n_29_ds_d2h[8] = tl_sm1_35_us_d2h[0]; - assign tl_sm1_35_us_h2d[0] = tl_s1n_28_ds_h2d[9]; - assign tl_s1n_28_ds_d2h[9] = tl_sm1_35_us_d2h[0]; + assign tl_sm1_36_us_h2d[0] = tl_s1n_29_ds_h2d[9]; + assign tl_s1n_29_ds_d2h[9] = tl_sm1_36_us_d2h[0]; - assign tl_sm1_36_us_h2d[0] = tl_s1n_28_ds_h2d[10]; - assign tl_s1n_28_ds_d2h[10] = tl_sm1_36_us_d2h[0]; + assign tl_sm1_37_us_h2d[0] = tl_s1n_29_ds_h2d[10]; + assign tl_s1n_29_ds_d2h[10] = tl_sm1_37_us_d2h[0]; - assign tl_sm1_37_us_h2d[0] = tl_s1n_28_ds_h2d[11]; - assign tl_s1n_28_ds_d2h[11] = tl_sm1_37_us_d2h[0]; + assign tl_sm1_38_us_h2d[0] = tl_s1n_29_ds_h2d[11]; + assign tl_s1n_29_ds_d2h[11] = tl_sm1_38_us_d2h[0]; - assign tl_sm1_38_us_h2d[0] = tl_s1n_28_ds_h2d[12]; - assign tl_s1n_28_ds_d2h[12] = tl_sm1_38_us_d2h[0]; + assign tl_sm1_39_us_h2d[0] = tl_s1n_29_ds_h2d[12]; + assign tl_s1n_29_ds_d2h[12] = tl_sm1_39_us_d2h[0]; - assign tl_sm1_39_us_h2d[0] = tl_s1n_28_ds_h2d[13]; - assign tl_s1n_28_ds_d2h[13] = tl_sm1_39_us_d2h[0]; + assign tl_sm1_40_us_h2d[0] = tl_s1n_29_ds_h2d[13]; + assign tl_s1n_29_ds_d2h[13] = tl_sm1_40_us_d2h[0]; - assign tl_sm1_40_us_h2d[0] = tl_s1n_28_ds_h2d[14]; - assign tl_s1n_28_ds_d2h[14] = tl_sm1_40_us_d2h[0]; + assign tl_sm1_41_us_h2d[0] = tl_s1n_29_ds_h2d[14]; + assign tl_s1n_29_ds_d2h[14] = tl_sm1_41_us_d2h[0]; - assign tl_sm1_41_us_h2d[0] = tl_s1n_28_ds_h2d[15]; - assign tl_s1n_28_ds_d2h[15] = tl_sm1_41_us_d2h[0]; + assign tl_sm1_42_us_h2d[0] = tl_s1n_29_ds_h2d[15]; + assign tl_s1n_29_ds_d2h[15] = tl_sm1_42_us_d2h[0]; - assign tl_sm1_42_us_h2d[0] = tl_s1n_28_ds_h2d[16]; - assign tl_s1n_28_ds_d2h[16] = tl_sm1_42_us_d2h[0]; + assign tl_sm1_43_us_h2d[0] = tl_s1n_29_ds_h2d[16]; + assign tl_s1n_29_ds_d2h[16] = tl_sm1_43_us_d2h[0]; - assign tl_sm1_43_us_h2d[0] = tl_s1n_28_ds_h2d[17]; - assign tl_s1n_28_ds_d2h[17] = tl_sm1_43_us_d2h[0]; + assign tl_sm1_44_us_h2d[0] = tl_s1n_29_ds_h2d[17]; + assign tl_s1n_29_ds_d2h[17] = tl_sm1_44_us_d2h[0]; - assign tl_sm1_44_us_h2d[0] = tl_s1n_28_ds_h2d[18]; - assign tl_s1n_28_ds_d2h[18] = tl_sm1_44_us_d2h[0]; + assign tl_sm1_45_us_h2d[0] = tl_s1n_29_ds_h2d[18]; + assign tl_s1n_29_ds_d2h[18] = tl_sm1_45_us_d2h[0]; - assign tl_sm1_45_us_h2d[0] = tl_s1n_28_ds_h2d[19]; - assign tl_s1n_28_ds_d2h[19] = tl_sm1_45_us_d2h[0]; + assign tl_sm1_46_us_h2d[0] = tl_s1n_29_ds_h2d[19]; + assign tl_s1n_29_ds_d2h[19] = tl_sm1_46_us_d2h[0]; - assign tl_sm1_24_us_h2d[2] = tl_s1n_46_ds_h2d[0]; - assign tl_s1n_46_ds_d2h[0] = tl_sm1_24_us_d2h[2]; + assign tl_sm1_47_us_h2d[0] = tl_s1n_29_ds_h2d[20]; + assign tl_s1n_29_ds_d2h[20] = tl_sm1_47_us_d2h[0]; - assign tl_sm1_29_us_h2d[1] = tl_s1n_46_ds_h2d[1]; - assign tl_s1n_46_ds_d2h[1] = tl_sm1_29_us_d2h[1]; + assign tl_sm1_25_us_h2d[2] = tl_s1n_48_ds_h2d[0]; + assign tl_s1n_48_ds_d2h[0] = tl_sm1_25_us_d2h[2]; - assign tl_sm1_26_us_h2d[2] = tl_s1n_46_ds_h2d[2]; - assign tl_s1n_46_ds_d2h[2] = tl_sm1_26_us_d2h[2]; + assign tl_sm1_30_us_h2d[1] = tl_s1n_48_ds_h2d[1]; + assign tl_s1n_48_ds_d2h[1] = tl_sm1_30_us_d2h[1]; - assign tl_sm1_27_us_h2d[2] = tl_s1n_46_ds_h2d[3]; - assign tl_s1n_46_ds_d2h[3] = tl_sm1_27_us_d2h[2]; + assign tl_sm1_31_us_h2d[1] = tl_s1n_48_ds_h2d[2]; + assign tl_s1n_48_ds_d2h[2] = tl_sm1_31_us_d2h[1]; - assign tl_sm1_31_us_h2d[1] = tl_s1n_46_ds_h2d[4]; - assign tl_s1n_46_ds_d2h[4] = tl_sm1_31_us_d2h[1]; + assign tl_sm1_27_us_h2d[2] = tl_s1n_48_ds_h2d[3]; + assign tl_s1n_48_ds_d2h[3] = tl_sm1_27_us_d2h[2]; - assign tl_sm1_32_us_h2d[1] = tl_s1n_46_ds_h2d[5]; - assign tl_s1n_46_ds_d2h[5] = tl_sm1_32_us_d2h[1]; + assign tl_sm1_28_us_h2d[2] = tl_s1n_48_ds_h2d[4]; + assign tl_s1n_48_ds_d2h[4] = tl_sm1_28_us_d2h[2]; - assign tl_sm1_33_us_h2d[1] = tl_s1n_46_ds_h2d[6]; - assign tl_s1n_46_ds_d2h[6] = tl_sm1_33_us_d2h[1]; + assign tl_sm1_33_us_h2d[1] = tl_s1n_48_ds_h2d[5]; + assign tl_s1n_48_ds_d2h[5] = tl_sm1_33_us_d2h[1]; - assign tl_sm1_34_us_h2d[1] = tl_s1n_46_ds_h2d[7]; - assign tl_s1n_46_ds_d2h[7] = tl_sm1_34_us_d2h[1]; + assign tl_sm1_34_us_h2d[1] = tl_s1n_48_ds_h2d[6]; + assign tl_s1n_48_ds_d2h[6] = tl_sm1_34_us_d2h[1]; - assign tl_sm1_35_us_h2d[1] = tl_s1n_46_ds_h2d[8]; - assign tl_s1n_46_ds_d2h[8] = tl_sm1_35_us_d2h[1]; + assign tl_sm1_35_us_h2d[1] = tl_s1n_48_ds_h2d[7]; + assign tl_s1n_48_ds_d2h[7] = tl_sm1_35_us_d2h[1]; + + assign tl_sm1_36_us_h2d[1] = tl_s1n_48_ds_h2d[8]; + assign tl_s1n_48_ds_d2h[8] = tl_sm1_36_us_d2h[1]; + + assign tl_sm1_37_us_h2d[1] = tl_s1n_48_ds_h2d[9]; + assign tl_s1n_48_ds_d2h[9] = tl_sm1_37_us_d2h[1]; + + assign tl_sm1_38_us_h2d[1] = tl_s1n_48_ds_h2d[10]; + assign tl_s1n_48_ds_d2h[10] = tl_sm1_38_us_d2h[1]; - assign tl_sm1_36_us_h2d[1] = tl_s1n_46_ds_h2d[9]; - assign tl_s1n_46_ds_d2h[9] = tl_sm1_36_us_d2h[1]; + assign tl_sm1_39_us_h2d[1] = tl_s1n_48_ds_h2d[11]; + assign tl_s1n_48_ds_d2h[11] = tl_sm1_39_us_d2h[1]; - assign tl_sm1_37_us_h2d[1] = tl_s1n_46_ds_h2d[10]; - assign tl_s1n_46_ds_d2h[10] = tl_sm1_37_us_d2h[1]; + assign tl_sm1_40_us_h2d[1] = tl_s1n_48_ds_h2d[12]; + assign tl_s1n_48_ds_d2h[12] = tl_sm1_40_us_d2h[1]; - assign tl_sm1_38_us_h2d[1] = tl_s1n_46_ds_h2d[11]; - assign tl_s1n_46_ds_d2h[11] = tl_sm1_38_us_d2h[1]; + assign tl_sm1_41_us_h2d[1] = tl_s1n_48_ds_h2d[13]; + assign tl_s1n_48_ds_d2h[13] = tl_sm1_41_us_d2h[1]; - assign tl_sm1_39_us_h2d[1] = tl_s1n_46_ds_h2d[12]; - assign tl_s1n_46_ds_d2h[12] = tl_sm1_39_us_d2h[1]; + assign tl_sm1_42_us_h2d[1] = tl_s1n_48_ds_h2d[14]; + assign tl_s1n_48_ds_d2h[14] = tl_sm1_42_us_d2h[1]; - assign tl_sm1_40_us_h2d[1] = tl_s1n_46_ds_h2d[13]; - assign tl_s1n_46_ds_d2h[13] = tl_sm1_40_us_d2h[1]; + assign tl_sm1_43_us_h2d[1] = tl_s1n_48_ds_h2d[15]; + assign tl_s1n_48_ds_d2h[15] = tl_sm1_43_us_d2h[1]; - assign tl_sm1_41_us_h2d[1] = tl_s1n_46_ds_h2d[14]; - assign tl_s1n_46_ds_d2h[14] = tl_sm1_41_us_d2h[1]; + assign tl_sm1_44_us_h2d[1] = tl_s1n_48_ds_h2d[16]; + assign tl_s1n_48_ds_d2h[16] = tl_sm1_44_us_d2h[1]; - assign tl_sm1_42_us_h2d[1] = tl_s1n_46_ds_h2d[15]; - assign tl_s1n_46_ds_d2h[15] = tl_sm1_42_us_d2h[1]; + assign tl_sm1_45_us_h2d[1] = tl_s1n_48_ds_h2d[17]; + assign tl_s1n_48_ds_d2h[17] = tl_sm1_45_us_d2h[1]; - assign tl_sm1_43_us_h2d[1] = tl_s1n_46_ds_h2d[16]; - assign tl_s1n_46_ds_d2h[16] = tl_sm1_43_us_d2h[1]; + assign tl_sm1_46_us_h2d[1] = tl_s1n_48_ds_h2d[18]; + assign tl_s1n_48_ds_d2h[18] = tl_sm1_46_us_d2h[1]; - assign tl_sm1_44_us_h2d[1] = tl_s1n_46_ds_h2d[17]; - assign tl_s1n_46_ds_d2h[17] = tl_sm1_44_us_d2h[1]; + assign tl_sm1_47_us_h2d[1] = tl_s1n_48_ds_h2d[19]; + assign tl_s1n_48_ds_d2h[19] = tl_sm1_47_us_d2h[1]; - assign tl_sm1_45_us_h2d[1] = tl_s1n_46_ds_h2d[18]; - assign tl_s1n_46_ds_d2h[18] = tl_sm1_45_us_d2h[1]; + assign tl_s1n_24_us_h2d = tl_corei_i; + assign tl_corei_o = tl_s1n_24_us_d2h; - assign tl_s1n_23_us_h2d = tl_corei_i; - assign tl_corei_o = tl_s1n_23_us_d2h; + assign tl_rom_ctrl__rom_o = tl_sm1_25_ds_h2d; + assign tl_sm1_25_ds_d2h = tl_rom_ctrl__rom_i; - assign tl_rom_ctrl__rom_o = tl_sm1_24_ds_h2d; - assign tl_sm1_24_ds_d2h = tl_rom_ctrl__rom_i; + assign tl_rv_dm__rom_o = tl_sm1_26_ds_h2d; + assign tl_sm1_26_ds_d2h = tl_rv_dm__rom_i; - assign tl_debug_mem_o = tl_sm1_25_ds_h2d; - assign tl_sm1_25_ds_d2h = tl_debug_mem_i; + assign tl_ram_main_o = tl_sm1_27_ds_h2d; + assign tl_sm1_27_ds_d2h = tl_ram_main_i; - assign tl_ram_main_o = tl_sm1_26_ds_h2d; - assign tl_sm1_26_ds_d2h = tl_ram_main_i; + assign tl_eflash_o = tl_sm1_28_ds_h2d; + assign tl_sm1_28_ds_d2h = tl_eflash_i; - assign tl_eflash_o = tl_sm1_27_ds_h2d; - assign tl_sm1_27_ds_d2h = tl_eflash_i; + assign tl_s1n_29_us_h2d = tl_cored_i; + assign tl_cored_o = tl_s1n_29_us_d2h; - assign tl_s1n_28_us_h2d = tl_cored_i; - assign tl_cored_o = tl_s1n_28_us_d2h; + assign tl_rom_ctrl__regs_o = tl_sm1_30_ds_h2d; + assign tl_sm1_30_ds_d2h = tl_rom_ctrl__regs_i; - assign tl_rom_ctrl__regs_o = tl_sm1_29_ds_h2d; - assign tl_sm1_29_ds_d2h = tl_rom_ctrl__regs_i; + assign tl_rv_dm__regs_o = tl_sm1_31_ds_h2d; + assign tl_sm1_31_ds_d2h = tl_rv_dm__regs_i; - assign tl_peri_o = tl_asf_30_ds_h2d; - assign tl_asf_30_ds_d2h = tl_peri_i; + assign tl_peri_o = tl_asf_32_ds_h2d; + assign tl_asf_32_ds_d2h = tl_peri_i; - assign tl_asf_30_us_h2d = tl_sm1_31_ds_h2d; - assign tl_sm1_31_ds_d2h = tl_asf_30_us_d2h; + assign tl_asf_32_us_h2d = tl_sm1_33_ds_h2d; + assign tl_sm1_33_ds_d2h = tl_asf_32_us_d2h; - assign tl_flash_ctrl__core_o = tl_sm1_32_ds_h2d; - assign tl_sm1_32_ds_d2h = tl_flash_ctrl__core_i; + assign tl_flash_ctrl__core_o = tl_sm1_34_ds_h2d; + assign tl_sm1_34_ds_d2h = tl_flash_ctrl__core_i; - assign tl_flash_ctrl__prim_o = tl_sm1_33_ds_h2d; - assign tl_sm1_33_ds_d2h = tl_flash_ctrl__prim_i; + assign tl_flash_ctrl__prim_o = tl_sm1_35_ds_h2d; + assign tl_sm1_35_ds_d2h = tl_flash_ctrl__prim_i; - assign tl_aes_o = tl_sm1_34_ds_h2d; - assign tl_sm1_34_ds_d2h = tl_aes_i; + assign tl_aes_o = tl_sm1_36_ds_h2d; + assign tl_sm1_36_ds_d2h = tl_aes_i; - assign tl_entropy_src_o = tl_sm1_35_ds_h2d; - assign tl_sm1_35_ds_d2h = tl_entropy_src_i; + assign tl_entropy_src_o = tl_sm1_37_ds_h2d; + assign tl_sm1_37_ds_d2h = tl_entropy_src_i; - assign tl_csrng_o = tl_sm1_36_ds_h2d; - assign tl_sm1_36_ds_d2h = tl_csrng_i; + assign tl_csrng_o = tl_sm1_38_ds_h2d; + assign tl_sm1_38_ds_d2h = tl_csrng_i; - assign tl_edn0_o = tl_sm1_37_ds_h2d; - assign tl_sm1_37_ds_d2h = tl_edn0_i; + assign tl_edn0_o = tl_sm1_39_ds_h2d; + assign tl_sm1_39_ds_d2h = tl_edn0_i; - assign tl_edn1_o = tl_sm1_38_ds_h2d; - assign tl_sm1_38_ds_d2h = tl_edn1_i; + assign tl_edn1_o = tl_sm1_40_ds_h2d; + assign tl_sm1_40_ds_d2h = tl_edn1_i; - assign tl_hmac_o = tl_sm1_39_ds_h2d; - assign tl_sm1_39_ds_d2h = tl_hmac_i; + assign tl_hmac_o = tl_sm1_41_ds_h2d; + assign tl_sm1_41_ds_d2h = tl_hmac_i; - assign tl_rv_plic_o = tl_sm1_40_ds_h2d; - assign tl_sm1_40_ds_d2h = tl_rv_plic_i; + assign tl_rv_plic_o = tl_sm1_42_ds_h2d; + assign tl_sm1_42_ds_d2h = tl_rv_plic_i; - assign tl_otbn_o = tl_sm1_41_ds_h2d; - assign tl_sm1_41_ds_d2h = tl_otbn_i; + assign tl_otbn_o = tl_sm1_43_ds_h2d; + assign tl_sm1_43_ds_d2h = tl_otbn_i; - assign tl_keymgr_o = tl_sm1_42_ds_h2d; - assign tl_sm1_42_ds_d2h = tl_keymgr_i; + assign tl_keymgr_o = tl_sm1_44_ds_h2d; + assign tl_sm1_44_ds_d2h = tl_keymgr_i; - assign tl_kmac_o = tl_sm1_43_ds_h2d; - assign tl_sm1_43_ds_d2h = tl_kmac_i; + assign tl_kmac_o = tl_sm1_45_ds_h2d; + assign tl_sm1_45_ds_d2h = tl_kmac_i; - assign tl_sram_ctrl_main_o = tl_sm1_44_ds_h2d; - assign tl_sm1_44_ds_d2h = tl_sram_ctrl_main_i; + assign tl_sram_ctrl_main_o = tl_sm1_46_ds_h2d; + assign tl_sm1_46_ds_d2h = tl_sram_ctrl_main_i; - assign tl_rv_core_ibex_peri_o = tl_sm1_45_ds_h2d; - assign tl_sm1_45_ds_d2h = tl_rv_core_ibex_peri_i; + assign tl_rv_core_ibex_peri_o = tl_sm1_47_ds_h2d; + assign tl_sm1_47_ds_d2h = tl_rv_core_ibex_peri_i; - assign tl_s1n_46_us_h2d = tl_dm_sba_i; - assign tl_dm_sba_o = tl_s1n_46_us_d2h; + assign tl_s1n_48_us_h2d = tl_rv_dm__sba_i; + assign tl_rv_dm__sba_o = tl_s1n_48_us_d2h; always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_23 = 3'd4; - if ((tl_s1n_23_us_h2d.a_address & + dev_sel_s1n_24 = 3'd4; + if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin - dev_sel_s1n_23 = 3'd0; + dev_sel_s1n_24 = 3'd0; - end else if ((tl_s1n_23_us_h2d.a_address & - ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin - dev_sel_s1n_23 = 3'd1; + end else if ((tl_s1n_24_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__ROM)) == ADDR_SPACE_RV_DM__ROM) begin + dev_sel_s1n_24 = 3'd1; - end else if ((tl_s1n_23_us_h2d.a_address & + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin - dev_sel_s1n_23 = 3'd2; + dev_sel_s1n_24 = 3'd2; - end else if ((tl_s1n_23_us_h2d.a_address & + end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin - dev_sel_s1n_23 = 3'd3; + dev_sel_s1n_24 = 3'd3; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_28 = 5'd20; - if ((tl_s1n_28_us_h2d.a_address & + dev_sel_s1n_29 = 5'd21; + if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin - dev_sel_s1n_28 = 5'd0; + dev_sel_s1n_29 = 5'd0; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin - dev_sel_s1n_28 = 5'd1; + dev_sel_s1n_29 = 5'd1; - end else if ((tl_s1n_28_us_h2d.a_address & - ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin - dev_sel_s1n_28 = 5'd2; + end else if ((tl_s1n_29_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__ROM)) == ADDR_SPACE_RV_DM__ROM) begin + dev_sel_s1n_29 = 5'd2; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin + dev_sel_s1n_29 = 5'd3; + + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin - dev_sel_s1n_28 = 5'd3; + dev_sel_s1n_29 = 5'd4; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin - dev_sel_s1n_28 = 5'd4; + dev_sel_s1n_29 = 5'd5; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin - dev_sel_s1n_28 = 5'd5; + dev_sel_s1n_29 = 5'd6; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin - dev_sel_s1n_28 = 5'd6; + dev_sel_s1n_29 = 5'd7; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin - dev_sel_s1n_28 = 5'd7; + dev_sel_s1n_29 = 5'd8; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_28 = 5'd8; + dev_sel_s1n_29 = 5'd9; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin - dev_sel_s1n_28 = 5'd9; + dev_sel_s1n_29 = 5'd10; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin - dev_sel_s1n_28 = 5'd10; + dev_sel_s1n_29 = 5'd11; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin - dev_sel_s1n_28 = 5'd11; + dev_sel_s1n_29 = 5'd12; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin - dev_sel_s1n_28 = 5'd12; + dev_sel_s1n_29 = 5'd13; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_28 = 5'd13; + dev_sel_s1n_29 = 5'd14; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_28 = 5'd14; + dev_sel_s1n_29 = 5'd15; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin - dev_sel_s1n_28 = 5'd15; + dev_sel_s1n_29 = 5'd16; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin - dev_sel_s1n_28 = 5'd16; + dev_sel_s1n_29 = 5'd17; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin - dev_sel_s1n_28 = 5'd17; + dev_sel_s1n_29 = 5'd18; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN)) == ADDR_SPACE_SRAM_CTRL_MAIN) begin - dev_sel_s1n_28 = 5'd18; + dev_sel_s1n_29 = 5'd19; - end else if ((tl_s1n_28_us_h2d.a_address & + end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RV_CORE_IBEX_PERI)) == ADDR_SPACE_RV_CORE_IBEX_PERI) begin - dev_sel_s1n_28 = 5'd19; + dev_sel_s1n_29 = 5'd20; end end always_comb begin // default steering to generate error response if address is not within the range - dev_sel_s1n_46 = 5'd19; - if ((tl_s1n_46_us_h2d.a_address & + dev_sel_s1n_48 = 5'd20; + if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__ROM)) == ADDR_SPACE_ROM_CTRL__ROM) begin - dev_sel_s1n_46 = 5'd0; + dev_sel_s1n_48 = 5'd0; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_ROM_CTRL__REGS)) == ADDR_SPACE_ROM_CTRL__REGS) begin - dev_sel_s1n_46 = 5'd1; + dev_sel_s1n_48 = 5'd1; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin + dev_sel_s1n_48 = 5'd2; + + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin - dev_sel_s1n_46 = 5'd2; + dev_sel_s1n_48 = 5'd3; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin - dev_sel_s1n_46 = 5'd3; + dev_sel_s1n_48 = 5'd4; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin - dev_sel_s1n_46 = 5'd4; + dev_sel_s1n_48 = 5'd5; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__CORE)) == ADDR_SPACE_FLASH_CTRL__CORE) begin - dev_sel_s1n_46 = 5'd5; + dev_sel_s1n_48 = 5'd6; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin - dev_sel_s1n_46 = 5'd6; + dev_sel_s1n_48 = 5'd7; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin - dev_sel_s1n_46 = 5'd7; + dev_sel_s1n_48 = 5'd8; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin - dev_sel_s1n_46 = 5'd8; + dev_sel_s1n_48 = 5'd9; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin - dev_sel_s1n_46 = 5'd9; + dev_sel_s1n_48 = 5'd10; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin - dev_sel_s1n_46 = 5'd10; + dev_sel_s1n_48 = 5'd11; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin - dev_sel_s1n_46 = 5'd11; + dev_sel_s1n_48 = 5'd12; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin - dev_sel_s1n_46 = 5'd12; + dev_sel_s1n_48 = 5'd13; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin - dev_sel_s1n_46 = 5'd13; + dev_sel_s1n_48 = 5'd14; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin - dev_sel_s1n_46 = 5'd14; + dev_sel_s1n_48 = 5'd15; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin - dev_sel_s1n_46 = 5'd15; + dev_sel_s1n_48 = 5'd16; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin - dev_sel_s1n_46 = 5'd16; + dev_sel_s1n_48 = 5'd17; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN)) == ADDR_SPACE_SRAM_CTRL_MAIN) begin - dev_sel_s1n_46 = 5'd17; + dev_sel_s1n_48 = 5'd18; - end else if ((tl_s1n_46_us_h2d.a_address & + end else if ((tl_s1n_48_us_h2d.a_address & ~(ADDR_MASK_RV_CORE_IBEX_PERI)) == ADDR_SPACE_RV_CORE_IBEX_PERI) begin - dev_sel_s1n_46 = 5'd18; + dev_sel_s1n_48 = 5'd19; end end @@ -741,14 +771,14 @@ .DReqDepth (16'h0), .DRspDepth (16'h0), .N (4) - ) u_s1n_23 ( + ) u_s1n_24 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_23_us_h2d), - .tl_h_o (tl_s1n_23_us_d2h), - .tl_d_o (tl_s1n_23_ds_h2d), - .tl_d_i (tl_s1n_23_ds_d2h), - .dev_select_i (dev_sel_s1n_23) + .tl_h_i (tl_s1n_24_us_h2d), + .tl_h_o (tl_s1n_24_us_d2h), + .tl_d_o (tl_s1n_24_ds_h2d), + .tl_d_i (tl_s1n_24_ds_d2h), + .dev_select_i (dev_sel_s1n_24) ); tlul_socket_m1 #( .HReqDepth (12'h0), @@ -756,20 +786,6 @@ .DReqDepth (4'h0), .DRspDepth (4'h0), .M (3) - ) u_sm1_24 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_24_us_h2d), - .tl_h_o (tl_sm1_24_us_d2h), - .tl_d_o (tl_sm1_24_ds_h2d), - .tl_d_i (tl_sm1_24_ds_d2h) - ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) ) u_sm1_25 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), @@ -779,11 +795,11 @@ .tl_d_i (tl_sm1_25_ds_d2h) ); tlul_socket_m1 #( - .HReqDepth (12'h0), - .HRspDepth (12'h0), - .DReqDepth (4'h0), - .DRspDepth (4'h0), - .M (3) + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) ) u_sm1_26 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), @@ -806,20 +822,34 @@ .tl_d_o (tl_sm1_27_ds_h2d), .tl_d_i (tl_sm1_27_ds_d2h) ); + tlul_socket_m1 #( + .HReqDepth (12'h0), + .HRspDepth (12'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (3) + ) u_sm1_28 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_28_us_h2d), + .tl_h_o (tl_sm1_28_us_d2h), + .tl_d_o (tl_sm1_28_ds_h2d), + .tl_d_i (tl_sm1_28_ds_d2h) + ); tlul_socket_1n #( .HReqDepth (4'h0), .HRspDepth (4'h0), - .DReqDepth (80'h0), - .DRspDepth (80'h0), - .N (20) - ) u_s1n_28 ( + .DReqDepth (84'h0), + .DRspDepth (84'h0), + .N (21) + ) u_s1n_29 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_28_us_h2d), - .tl_h_o (tl_s1n_28_us_d2h), - .tl_d_o (tl_s1n_28_ds_h2d), - .tl_d_i (tl_s1n_28_ds_d2h), - .dev_select_i (dev_sel_s1n_28) + .tl_h_i (tl_s1n_29_us_h2d), + .tl_h_o (tl_s1n_29_us_d2h), + .tl_d_o (tl_s1n_29_ds_h2d), + .tl_d_i (tl_s1n_29_ds_d2h), + .dev_select_i (dev_sel_s1n_29) ); tlul_socket_m1 #( .HReqDepth (8'h0), @@ -827,32 +857,19 @@ .DReqDepth (4'h0), .DRspDepth (4'h0), .M (2) - ) u_sm1_29 ( + ) u_sm1_30 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_29_us_h2d), - .tl_h_o (tl_sm1_29_us_d2h), - .tl_d_o (tl_sm1_29_ds_h2d), - .tl_d_i (tl_sm1_29_ds_d2h) - ); - tlul_fifo_async #( - .ReqDepth (4),// At least 4 to make async work - .RspDepth (4) // At least 4 to make async work - ) u_asf_30 ( - .clk_h_i (clk_main_i), - .rst_h_ni (rst_main_ni), - .clk_d_i (clk_fixed_i), - .rst_d_ni (rst_fixed_ni), - .tl_h_i (tl_asf_30_us_h2d), - .tl_h_o (tl_asf_30_us_d2h), - .tl_d_o (tl_asf_30_ds_h2d), - .tl_d_i (tl_asf_30_ds_d2h) + .tl_h_i (tl_sm1_30_us_h2d), + .tl_h_o (tl_sm1_30_us_d2h), + .tl_d_o (tl_sm1_30_ds_h2d), + .tl_d_i (tl_sm1_30_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), .HRspDepth (8'h0), - .DReqDepth (4'h0), - .DRspDepth (4'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), .M (2) ) u_sm1_31 ( .clk_i (clk_main_i), @@ -862,25 +879,24 @@ .tl_d_o (tl_sm1_31_ds_h2d), .tl_d_i (tl_sm1_31_ds_d2h) ); - tlul_socket_m1 #( - .HReqDepth (8'h0), - .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), - .M (2) - ) u_sm1_32 ( - .clk_i (clk_main_i), - .rst_ni (rst_main_ni), - .tl_h_i (tl_sm1_32_us_h2d), - .tl_h_o (tl_sm1_32_us_d2h), - .tl_d_o (tl_sm1_32_ds_h2d), - .tl_d_i (tl_sm1_32_ds_d2h) + tlul_fifo_async #( + .ReqDepth (4),// At least 4 to make async work + .RspDepth (4) // At least 4 to make async work + ) u_asf_32 ( + .clk_h_i (clk_main_i), + .rst_h_ni (rst_main_ni), + .clk_d_i (clk_fixed_i), + .rst_d_ni (rst_fixed_ni), + .tl_h_i (tl_asf_32_us_h2d), + .tl_h_o (tl_asf_32_us_d2h), + .tl_d_o (tl_asf_32_ds_h2d), + .tl_d_i (tl_asf_32_ds_d2h) ); tlul_socket_m1 #( .HReqDepth (8'h0), .HRspDepth (8'h0), - .DReqPass (1'b0), - .DRspPass (1'b0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), .M (2) ) u_sm1_33 ( .clk_i (clk_main_i), @@ -1033,8 +1049,8 @@ tlul_socket_m1 #( .HReqDepth (8'h0), .HRspDepth (8'h0), - .DReqDepth (4'h0), - .DRspDepth (4'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), .M (2) ) u_sm1_44 ( .clk_i (clk_main_i), @@ -1058,20 +1074,48 @@ .tl_d_o (tl_sm1_45_ds_h2d), .tl_d_i (tl_sm1_45_ds_d2h) ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_46 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_46_us_h2d), + .tl_h_o (tl_sm1_46_us_d2h), + .tl_d_o (tl_sm1_46_ds_h2d), + .tl_d_i (tl_sm1_46_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_47 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_47_us_h2d), + .tl_h_o (tl_sm1_47_us_d2h), + .tl_d_o (tl_sm1_47_ds_h2d), + .tl_d_i (tl_sm1_47_ds_d2h) + ); tlul_socket_1n #( .HReqPass (1'b0), .HRspPass (1'b0), - .DReqDepth (76'h0), - .DRspDepth (76'h0), - .N (19) - ) u_s1n_46 ( + .DReqDepth (80'h0), + .DRspDepth (80'h0), + .N (20) + ) u_s1n_48 ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .tl_h_i (tl_s1n_46_us_h2d), - .tl_h_o (tl_s1n_46_us_d2h), - .tl_d_o (tl_s1n_46_ds_h2d), - .tl_d_i (tl_s1n_46_ds_d2h), - .dev_select_i (dev_sel_s1n_46) + .tl_h_i (tl_s1n_48_us_h2d), + .tl_h_o (tl_s1n_48_us_d2h), + .tl_d_o (tl_s1n_48_ds_h2d), + .tl_d_i (tl_s1n_48_ds_d2h), + .dev_select_i (dev_sel_s1n_48) ); endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index ab5d1c1..4009f28 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -14,6 +14,7 @@ parameter OtpCtrlMemInitFile = "", parameter pinmux_pkg::target_cfg_t PinmuxAonTargetCfg = pinmux_pkg::DefaultTargetCfg, parameter bit SramCtrlRetAonInstrExec = 1, + parameter logic [31:0] RvDmIdcodeValue = 32'h 0000_0001, parameter bit AesMasking = 1'b1, parameter aes_pkg::sbox_impl_e AesSBoxImpl = aes_pkg::SBoxImplDom, parameter int unsigned SecAesStartTriggerDelay = 0, @@ -271,6 +272,7 @@ logic cio_flash_ctrl_tdi_p2d; logic cio_flash_ctrl_tdo_d2p; logic cio_flash_ctrl_tdo_en_d2p; + // rv_dm // rv_plic // aes // hmac @@ -546,8 +548,15 @@ rv_core_ibex_peri_pkg::region_cfg_t rv_core_ibex_peri_dbus_region_cfg; spi_device_pkg::passthrough_req_t spi_device_passthrough_req; spi_device_pkg::passthrough_rsp_t spi_device_passthrough_rsp; + logic rv_dm_ndmreset_req; logic [4:0] pwrmgr_aon_wakeups; logic [1:0] pwrmgr_aon_rstreqs; + tlul_pkg::tl_h2d_t main_tl_rv_dm__sba_req; + tlul_pkg::tl_d2h_t main_tl_rv_dm__sba_rsp; + tlul_pkg::tl_h2d_t rv_dm_regs_tl_d_req; + tlul_pkg::tl_d2h_t rv_dm_regs_tl_d_rsp; + tlul_pkg::tl_h2d_t rv_dm_rom_tl_d_req; + tlul_pkg::tl_d2h_t rv_dm_rom_tl_d_rsp; tlul_pkg::tl_h2d_t rom_ctrl_rom_tl_req; tlul_pkg::tl_d2h_t rom_ctrl_rom_tl_rsp; tlul_pkg::tl_h2d_t rom_ctrl_regs_tl_req; @@ -643,18 +652,15 @@ tlul_pkg::tl_h2d_t adc_ctrl_aon_tl_req; tlul_pkg::tl_d2h_t adc_ctrl_aon_tl_rsp; rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets; - rstmgr_pkg::rstmgr_cpu_t rstmgr_aon_cpu; + logic rstmgr_aon_rst_cpu_n; pwrmgr_pkg::pwr_cpu_t pwrmgr_aon_pwr_cpu; - clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; lc_ctrl_pkg::lc_tx_t pwrmgr_aon_fetch_en; + clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; + logic rv_dm_debug_req; tlul_pkg::tl_h2d_t main_tl_corei_req; tlul_pkg::tl_d2h_t main_tl_corei_rsp; tlul_pkg::tl_h2d_t main_tl_cored_req; tlul_pkg::tl_d2h_t main_tl_cored_rsp; - tlul_pkg::tl_h2d_t main_tl_dm_sba_req; - tlul_pkg::tl_d2h_t main_tl_dm_sba_rsp; - tlul_pkg::tl_h2d_t main_tl_debug_mem_req; - tlul_pkg::tl_d2h_t main_tl_debug_mem_rsp; jtag_pkg::jtag_req_t pinmux_aon_dft_jtag_req; jtag_pkg::jtag_rsp_t pinmux_aon_dft_jtag_rsp; otp_ctrl_part_pkg::otp_hw_cfg_t otp_ctrl_otp_hw_cfg; @@ -749,12 +755,6 @@ assign unused_daon_rst_i2c1 = rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::DomainAonSel]; assign unused_daon_rst_i2c2 = rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::DomainAonSel]; - // Non-debug module reset == reset for everything except for the debug module - logic ndmreset_req; - - // debug request from rv_dm to core - logic debug_req; - // processor core rv_core_ibex #( .PMPEnable (1), @@ -773,8 +773,8 @@ .BranchPredictor (0), .DbgTriggerEn (1), .SecureIbex (SecureIbex), - .DmHaltAddr (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress[31:0]), - .DmExceptionAddr (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress[31:0]), + .DmHaltAddr (ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0]), + .DmExceptionAddr (ADDR_SPACE_RV_DM__ROM + dm::ExceptionAddress[31:0]), .PipeLine (IbexPipeLine) ) u_rv_core_ibex ( // clock and reset @@ -782,6 +782,8 @@ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_timers), .rst_esc_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]), + // reset feedback to the clock manager + .rst_cpu_n_o (rstmgr_aon_rst_cpu_n), .ram_cfg_i (ast_ram_1p_cfg), // static pinning .hart_id_i (32'b0), @@ -799,7 +801,7 @@ .esc_tx_i (alert_handler_esc_tx[0]), .esc_rx_o (alert_handler_esc_rx[0]), // debug interface - .debug_req_i (debug_req), + .debug_req_i (rv_dm_debug_req), // crash dump interface .crash_dump_o (rv_core_ibex_crash_dump), // CPU control signals @@ -818,39 +820,6 @@ .scanmode_i ); - // Debug Module (RISC-V Debug Spec 0.13) - // - - rv_dm #( - .NrHarts (1), - .IdcodeValue (JTAG_IDCODE) - ) u_dm_top ( - .clk_i (clkmgr_aon_clocks.clk_proc_main), - .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), - .hw_debug_en_i (lc_ctrl_lc_hw_debug_en), - .scanmode_i, - .scan_rst_ni, - .ndmreset_o (ndmreset_req), - .dmactive_o (), - .debug_req_o (debug_req), - .unavailable_i (1'b0), - - // bus device with debug memory (for execution-based debug) - .tl_d_i (main_tl_debug_mem_req), - .tl_d_o (main_tl_debug_mem_rsp), - - // bus host (for system bus accesses, SBA) - .tl_h_o (main_tl_dm_sba_req), - .tl_h_i (main_tl_dm_sba_rsp), - - //JTAG - .jtag_req_i (pinmux_aon_rv_jtag_req), - .jtag_rsp_o (pinmux_aon_rv_jtag_rsp) - ); - - assign rstmgr_aon_cpu.ndmreset_req = ndmreset_req; - assign rstmgr_aon_cpu.rst_cpu_n = rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]; - // Struct breakout module tool-inserted DFT TAP signals pinmux_jtag_breakout u_dft_tap_breakout ( .req_i (pinmux_aon_dft_jtag_req), @@ -1792,7 +1761,8 @@ .pwr_i(pwrmgr_aon_pwr_rst_req), .pwr_o(pwrmgr_aon_pwr_rst_rsp), .resets_o(rstmgr_aon_resets), - .cpu_i(rstmgr_aon_cpu), + .rst_cpu_n_i(rstmgr_aon_rst_cpu_n), + .ndmreset_req_i(rv_dm_ndmreset_req), .alert_dump_i(alert_handler_crashdump), .cpu_dump_i(rv_core_ibex_crash_dump), .resets_ast_o(rsts_ast_o), @@ -2157,14 +2127,44 @@ .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) ); - rv_plic #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:46]) - ) u_rv_plic ( + rv_dm #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:46]), + .IdcodeValue(RvDmIdcodeValue) + ) u_rv_dm ( // [46]: fatal_fault .alert_tx_o ( alert_tx[46:46] ), .alert_rx_i ( alert_rx[46:46] ), // Inter-module signals + .jtag_i(pinmux_aon_rv_jtag_req), + .jtag_o(pinmux_aon_rv_jtag_rsp), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .unavailable_i(1'b0), + .ndmreset_req_o(rv_dm_ndmreset_req), + .dmactive_o(), + .debug_req_o(rv_dm_debug_req), + .sba_tl_h_o(main_tl_rv_dm__sba_req), + .sba_tl_h_i(main_tl_rv_dm__sba_rsp), + .regs_tl_d_i(rv_dm_regs_tl_d_req), + .regs_tl_d_o(rv_dm_regs_tl_d_rsp), + .rom_tl_d_i(rv_dm_rom_tl_d_req), + .rom_tl_d_o(rv_dm_rom_tl_d_rsp), + .scanmode_i, + .scan_rst_ni, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + + rv_plic #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:47]) + ) u_rv_plic ( + // [47]: fatal_fault + .alert_tx_o ( alert_tx[47:47] ), + .alert_rx_i ( alert_rx[47:47] ), + + // Inter-module signals .tl_i(rv_plic_tl_req), .tl_o(rv_plic_tl_rsp), @@ -2179,7 +2179,7 @@ ); aes #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:48]), .AES192Enable(1'b1), .Masking(AesMasking), .SBoxImpl(AesSBoxImpl), @@ -2192,10 +2192,10 @@ .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed), .RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm) ) u_aes ( - // [47]: recov_ctrl_update_err - // [48]: fatal_fault - .alert_tx_o ( alert_tx[48:47] ), - .alert_rx_i ( alert_rx[48:47] ), + // [48]: recov_ctrl_update_err + // [49]: fatal_fault + .alert_tx_o ( alert_tx[49:48] ), + .alert_rx_i ( alert_rx[49:48] ), // Inter-module signals .idle_o(clkmgr_aon_idle[0]), @@ -2213,16 +2213,16 @@ ); hmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:49]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:50]) ) u_hmac ( // Interrupt .intr_hmac_done_o (intr_hmac_hmac_done), .intr_fifo_empty_o (intr_hmac_fifo_empty), .intr_hmac_err_o (intr_hmac_hmac_err), - // [49]: fatal_fault - .alert_tx_o ( alert_tx[49:49] ), - .alert_rx_i ( alert_rx[49:49] ), + // [50]: fatal_fault + .alert_tx_o ( alert_tx[50:50] ), + .alert_rx_i ( alert_rx[50:50] ), // Inter-module signals .idle_o(clkmgr_aon_idle[1]), @@ -2235,7 +2235,7 @@ ); kmac #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:50]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[51:51]), .EnMasking(KmacEnMasking), .ReuseShare(KmacReuseShare) ) u_kmac ( @@ -2244,9 +2244,9 @@ .intr_kmac_done_o (intr_kmac_kmac_done), .intr_fifo_empty_o (intr_kmac_fifo_empty), .intr_kmac_err_o (intr_kmac_kmac_err), - // [50]: fatal_fault - .alert_tx_o ( alert_tx[50:50] ), - .alert_rx_i ( alert_rx[50:50] ), + // [51]: fatal_fault + .alert_tx_o ( alert_tx[51:51] ), + .alert_rx_i ( alert_rx[51:51] ), // Inter-module signals .keymgr_key_i(keymgr_kmac_key), @@ -2266,7 +2266,7 @@ ); keymgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:52]), .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed), .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm), .RndCnstRandPerm(RndCnstKeymgrRandPerm), @@ -2284,10 +2284,10 @@ // Interrupt .intr_op_done_o (intr_keymgr_op_done), - // [51]: fatal_fault_err - // [52]: recov_operation_err - .alert_tx_o ( alert_tx[52:51] ), - .alert_rx_i ( alert_rx[52:51] ), + // [52]: fatal_fault_err + // [53]: recov_operation_err + .alert_tx_o ( alert_tx[53:52] ), + .alert_rx_i ( alert_rx[53:52] ), // Inter-module signals .edn_o(edn0_edn_req[0]), @@ -2314,7 +2314,7 @@ ); csrng #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:53]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:54]), .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction), .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction), .SBoxImpl(CsrngSBoxImpl) @@ -2325,9 +2325,9 @@ .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req), .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), - // [53]: fatal_alert - .alert_tx_o ( alert_tx[53:53] ), - .alert_rx_i ( alert_rx[53:53] ), + // [54]: fatal_alert + .alert_tx_o ( alert_tx[54:54] ), + .alert_rx_i ( alert_rx[54:54] ), // Inter-module signals .csrng_cmd_i(csrng_csrng_cmd_req), @@ -2347,7 +2347,7 @@ ); entropy_src #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:54]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55]), .Stub(EntropySrcStub) ) u_entropy_src ( @@ -2356,10 +2356,10 @@ .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed), .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready), .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err), - // [54]: recov_alert - // [55]: fatal_alert - .alert_tx_o ( alert_tx[55:54] ), - .alert_rx_i ( alert_rx[55:54] ), + // [55]: recov_alert + // [56]: fatal_alert + .alert_tx_o ( alert_tx[56:55] ), + .alert_rx_i ( alert_rx[56:55] ), // Inter-module signals .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req), @@ -2382,15 +2382,15 @@ ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:56]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:57]) ) u_edn0 ( // Interrupt .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err), - // [56]: fatal_alert - .alert_tx_o ( alert_tx[56:56] ), - .alert_rx_i ( alert_rx[56:56] ), + // [57]: fatal_alert + .alert_tx_o ( alert_tx[57:57] ), + .alert_rx_i ( alert_rx[57:57] ), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[0]), @@ -2406,15 +2406,15 @@ ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:57]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:58]) ) u_edn1 ( // Interrupt .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err), - // [57]: fatal_alert - .alert_tx_o ( alert_tx[57:57] ), - .alert_rx_i ( alert_rx[57:57] ), + // [58]: fatal_alert + .alert_tx_o ( alert_tx[58:58] ), + .alert_rx_i ( alert_rx[58:58] ), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[1]), @@ -2430,16 +2430,16 @@ ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:58]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:59]), .RndCnstSramKey(RndCnstSramCtrlMainSramKey), .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce), .RndCnstSramLfsrPerm(RndCnstSramCtrlMainSramLfsrPerm), .InstrExec(SramCtrlMainInstrExec) ) u_sram_ctrl_main ( - // [58]: fatal_intg_error - // [59]: fatal_parity_error - .alert_tx_o ( alert_tx[59:58] ), - .alert_rx_i ( alert_rx[59:58] ), + // [59]: fatal_intg_error + // [60]: fatal_parity_error + .alert_tx_o ( alert_tx[60:59] ), + .alert_rx_i ( alert_rx[60:59] ), // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), @@ -2464,7 +2464,7 @@ ); otbn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[61:60]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[62:61]), .Stub(OtbnStub), .RegFile(OtbnRegFile), .RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed), @@ -2475,10 +2475,10 @@ // Interrupt .intr_done_o (intr_otbn_done), - // [60]: fatal - // [61]: recov - .alert_tx_o ( alert_tx[61:60] ), - .alert_rx_i ( alert_rx[61:60] ), + // [61]: fatal + // [62]: recov + .alert_tx_o ( alert_tx[62:61] ), + .alert_rx_i ( alert_rx[62:61] ), // Inter-module signals .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), @@ -2502,14 +2502,14 @@ ); rom_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[62:62]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[63:63]), .BootRomInitFile(RomCtrlBootRomInitFile), .RndCnstScrNonce(RndCnstRomCtrlScrNonce), .RndCnstScrKey(RndCnstRomCtrlScrKey) ) u_rom_ctrl ( - // [62]: fatal - .alert_tx_o ( alert_tx[62:62] ), - .alert_rx_i ( alert_rx[62:62] ), + // [63]: fatal + .alert_tx_o ( alert_tx[63:63] ), + .alert_rx_i ( alert_rx[63:63] ), // Inter-module signals .rom_cfg_i(ast_rom_cfg), @@ -2528,14 +2528,14 @@ ); rv_core_ibex_peri #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[66:63]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[67:64]) ) u_rv_core_ibex_peri ( - // [63]: fatal_sw_err - // [64]: recov_sw_err - // [65]: fatal_hw_err - // [66]: recov_hw_err - .alert_tx_o ( alert_tx[66:63] ), - .alert_rx_i ( alert_rx[66:63] ), + // [64]: fatal_sw_err + // [65]: recov_sw_err + // [66]: fatal_hw_err + // [67]: recov_hw_err + .alert_tx_o ( alert_tx[67:64] ), + .alert_rx_i ( alert_rx[67:64] ), // Inter-module signals .fatal_intg_event_i(rv_core_ibex_fatal_intg_event), @@ -2719,9 +2719,17 @@ .tl_cored_i(main_tl_cored_req), .tl_cored_o(main_tl_cored_rsp), - // port: tl_dm_sba - .tl_dm_sba_i(main_tl_dm_sba_req), - .tl_dm_sba_o(main_tl_dm_sba_rsp), + // port: tl_rv_dm__sba + .tl_rv_dm__sba_i(main_tl_rv_dm__sba_req), + .tl_rv_dm__sba_o(main_tl_rv_dm__sba_rsp), + + // port: tl_rv_dm__regs + .tl_rv_dm__regs_o(rv_dm_regs_tl_d_req), + .tl_rv_dm__regs_i(rv_dm_regs_tl_d_rsp), + + // port: tl_rv_dm__rom + .tl_rv_dm__rom_o(rv_dm_rom_tl_d_req), + .tl_rv_dm__rom_i(rv_dm_rom_tl_d_rsp), // port: tl_rom_ctrl__rom .tl_rom_ctrl__rom_o(rom_ctrl_rom_tl_req), @@ -2731,10 +2739,6 @@ .tl_rom_ctrl__regs_o(rom_ctrl_regs_tl_req), .tl_rom_ctrl__regs_i(rom_ctrl_regs_tl_rsp), - // port: tl_debug_mem - .tl_debug_mem_o(main_tl_debug_mem_req), - .tl_debug_mem_i(main_tl_debug_mem_rsp), - // port: tl_ram_main .tl_ram_main_o(ram_main_tl_req), .tl_ram_main_i(ram_main_tl_rsp),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index 7705230..f6cf6cb 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -311,6 +311,26 @@ parameter int unsigned TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES = 32'h1000; /** + * Peripheral base address for regs device on rv_dm in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RV_DM_REGS_BASE_ADDR = 32'h41200000; + + /** + * Peripheral size in bytes for regs device on rv_dm in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for rom device on rv_dm in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RV_DM_ROM_BASE_ADDR = 32'h10000; + + /** + * Peripheral size in bytes for rom device on rv_dm in top earlgrey. + */ + parameter int unsigned TOP_EARLGREY_RV_DM_ROM_SIZE_BYTES = 32'h1000; + + /** * Peripheral base address for rv_plic in top earlgrey. */ parameter int unsigned TOP_EARLGREY_RV_PLIC_BASE_ADDR = 32'h41010000;
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index 989f0f4..620e77d 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -202,7 +202,7 @@ * `top_earlgrey_alert_peripheral_t`. */ const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[67] = { + top_earlgrey_alert_for_peripheral[68] = { [kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0, [kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1, [kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2, @@ -249,6 +249,7 @@ [kTopEarlgreyAlertIdFlashCtrlRecovMpErr] = kTopEarlgreyAlertPeripheralFlashCtrl, [kTopEarlgreyAlertIdFlashCtrlRecovEccErr] = kTopEarlgreyAlertPeripheralFlashCtrl, [kTopEarlgreyAlertIdFlashCtrlFatalIntgErr] = kTopEarlgreyAlertPeripheralFlashCtrl, + [kTopEarlgreyAlertIdRvDmFatalFault] = kTopEarlgreyAlertPeripheralRvDm, [kTopEarlgreyAlertIdRvPlicFatalFault] = kTopEarlgreyAlertPeripheralRvPlic, [kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes, [kTopEarlgreyAlertIdAesFatalFault] = kTopEarlgreyAlertPeripheralAes,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 97bd54b..ad2b847 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -566,6 +566,42 @@ #define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x1000u /** + * Peripheral base address for regs device on rv_dm in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RV_DM_REGS_BASE_ADDR 0x41200000u + +/** + * Peripheral size for regs device on rv_dm in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_RV_DM_REGS_BASE_ADDR and + * `TOP_EARLGREY_RV_DM_REGS_BASE_ADDR + TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES`. + */ +#define TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for rom device on rv_dm in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RV_DM_ROM_BASE_ADDR 0x10000u + +/** + * Peripheral size for rom device on rv_dm in top earlgrey. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_EARLGREY_RV_DM_ROM_BASE_ADDR and + * `TOP_EARLGREY_RV_DM_ROM_BASE_ADDR + TOP_EARLGREY_RV_DM_ROM_SIZE_BYTES`. + */ +#define TOP_EARLGREY_RV_DM_ROM_SIZE_BYTES 0x1000u + +/** * Peripheral base address for rv_plic in top earlgrey. * * This should be used with #mmio_region_from_addr to access the memory-mapped @@ -1132,20 +1168,21 @@ kTopEarlgreyAlertPeripheralSensorCtrlAon = 23, /**< sensor_ctrl_aon */ kTopEarlgreyAlertPeripheralSramCtrlRetAon = 24, /**< sram_ctrl_ret_aon */ kTopEarlgreyAlertPeripheralFlashCtrl = 25, /**< flash_ctrl */ - kTopEarlgreyAlertPeripheralRvPlic = 26, /**< rv_plic */ - kTopEarlgreyAlertPeripheralAes = 27, /**< aes */ - kTopEarlgreyAlertPeripheralHmac = 28, /**< hmac */ - kTopEarlgreyAlertPeripheralKmac = 29, /**< kmac */ - kTopEarlgreyAlertPeripheralKeymgr = 30, /**< keymgr */ - kTopEarlgreyAlertPeripheralCsrng = 31, /**< csrng */ - kTopEarlgreyAlertPeripheralEntropySrc = 32, /**< entropy_src */ - kTopEarlgreyAlertPeripheralEdn0 = 33, /**< edn0 */ - kTopEarlgreyAlertPeripheralEdn1 = 34, /**< edn1 */ - kTopEarlgreyAlertPeripheralSramCtrlMain = 35, /**< sram_ctrl_main */ - kTopEarlgreyAlertPeripheralOtbn = 36, /**< otbn */ - kTopEarlgreyAlertPeripheralRomCtrl = 37, /**< rom_ctrl */ - kTopEarlgreyAlertPeripheralRvCoreIbexPeri = 38, /**< rv_core_ibex_peri */ - kTopEarlgreyAlertPeripheralLast = 38, /**< \internal Final Alert peripheral */ + kTopEarlgreyAlertPeripheralRvDm = 26, /**< rv_dm */ + kTopEarlgreyAlertPeripheralRvPlic = 27, /**< rv_plic */ + kTopEarlgreyAlertPeripheralAes = 28, /**< aes */ + kTopEarlgreyAlertPeripheralHmac = 29, /**< hmac */ + kTopEarlgreyAlertPeripheralKmac = 30, /**< kmac */ + kTopEarlgreyAlertPeripheralKeymgr = 31, /**< keymgr */ + kTopEarlgreyAlertPeripheralCsrng = 32, /**< csrng */ + kTopEarlgreyAlertPeripheralEntropySrc = 33, /**< entropy_src */ + kTopEarlgreyAlertPeripheralEdn0 = 34, /**< edn0 */ + kTopEarlgreyAlertPeripheralEdn1 = 35, /**< edn1 */ + kTopEarlgreyAlertPeripheralSramCtrlMain = 36, /**< sram_ctrl_main */ + kTopEarlgreyAlertPeripheralOtbn = 37, /**< otbn */ + kTopEarlgreyAlertPeripheralRomCtrl = 38, /**< rom_ctrl */ + kTopEarlgreyAlertPeripheralRvCoreIbexPeri = 39, /**< rv_core_ibex_peri */ + kTopEarlgreyAlertPeripheralLast = 39, /**< \internal Final Alert peripheral */ } top_earlgrey_alert_peripheral_t; /** @@ -1201,28 +1238,29 @@ kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 43, /**< flash_ctrl_recov_mp_err */ kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 44, /**< flash_ctrl_recov_ecc_err */ kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 45, /**< flash_ctrl_fatal_intg_err */ - kTopEarlgreyAlertIdRvPlicFatalFault = 46, /**< rv_plic_fatal_fault */ - kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 47, /**< aes_recov_ctrl_update_err */ - kTopEarlgreyAlertIdAesFatalFault = 48, /**< aes_fatal_fault */ - kTopEarlgreyAlertIdHmacFatalFault = 49, /**< hmac_fatal_fault */ - kTopEarlgreyAlertIdKmacFatalFault = 50, /**< kmac_fatal_fault */ - kTopEarlgreyAlertIdKeymgrFatalFaultErr = 51, /**< keymgr_fatal_fault_err */ - kTopEarlgreyAlertIdKeymgrRecovOperationErr = 52, /**< keymgr_recov_operation_err */ - kTopEarlgreyAlertIdCsrngFatalAlert = 53, /**< csrng_fatal_alert */ - kTopEarlgreyAlertIdEntropySrcRecovAlert = 54, /**< entropy_src_recov_alert */ - kTopEarlgreyAlertIdEntropySrcFatalAlert = 55, /**< entropy_src_fatal_alert */ - kTopEarlgreyAlertIdEdn0FatalAlert = 56, /**< edn0_fatal_alert */ - kTopEarlgreyAlertIdEdn1FatalAlert = 57, /**< edn1_fatal_alert */ - kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 58, /**< sram_ctrl_main_fatal_intg_error */ - kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 59, /**< sram_ctrl_main_fatal_parity_error */ - kTopEarlgreyAlertIdOtbnFatal = 60, /**< otbn_fatal */ - kTopEarlgreyAlertIdOtbnRecov = 61, /**< otbn_recov */ - kTopEarlgreyAlertIdRomCtrlFatal = 62, /**< rom_ctrl_fatal */ - kTopEarlgreyAlertIdRvCoreIbexPeriFatalSwErr = 63, /**< rv_core_ibex_peri_fatal_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexPeriRecovSwErr = 64, /**< rv_core_ibex_peri_recov_sw_err */ - kTopEarlgreyAlertIdRvCoreIbexPeriFatalHwErr = 65, /**< rv_core_ibex_peri_fatal_hw_err */ - kTopEarlgreyAlertIdRvCoreIbexPeriRecovHwErr = 66, /**< rv_core_ibex_peri_recov_hw_err */ - kTopEarlgreyAlertIdLast = 66, /**< \internal The Last Valid Alert ID. */ + kTopEarlgreyAlertIdRvDmFatalFault = 46, /**< rv_dm_fatal_fault */ + kTopEarlgreyAlertIdRvPlicFatalFault = 47, /**< rv_plic_fatal_fault */ + kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 48, /**< aes_recov_ctrl_update_err */ + kTopEarlgreyAlertIdAesFatalFault = 49, /**< aes_fatal_fault */ + kTopEarlgreyAlertIdHmacFatalFault = 50, /**< hmac_fatal_fault */ + kTopEarlgreyAlertIdKmacFatalFault = 51, /**< kmac_fatal_fault */ + kTopEarlgreyAlertIdKeymgrFatalFaultErr = 52, /**< keymgr_fatal_fault_err */ + kTopEarlgreyAlertIdKeymgrRecovOperationErr = 53, /**< keymgr_recov_operation_err */ + kTopEarlgreyAlertIdCsrngFatalAlert = 54, /**< csrng_fatal_alert */ + kTopEarlgreyAlertIdEntropySrcRecovAlert = 55, /**< entropy_src_recov_alert */ + kTopEarlgreyAlertIdEntropySrcFatalAlert = 56, /**< entropy_src_fatal_alert */ + kTopEarlgreyAlertIdEdn0FatalAlert = 57, /**< edn0_fatal_alert */ + kTopEarlgreyAlertIdEdn1FatalAlert = 58, /**< edn1_fatal_alert */ + kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 59, /**< sram_ctrl_main_fatal_intg_error */ + kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 60, /**< sram_ctrl_main_fatal_parity_error */ + kTopEarlgreyAlertIdOtbnFatal = 61, /**< otbn_fatal */ + kTopEarlgreyAlertIdOtbnRecov = 62, /**< otbn_recov */ + kTopEarlgreyAlertIdRomCtrlFatal = 63, /**< rom_ctrl_fatal */ + kTopEarlgreyAlertIdRvCoreIbexPeriFatalSwErr = 64, /**< rv_core_ibex_peri_fatal_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexPeriRecovSwErr = 65, /**< rv_core_ibex_peri_recov_sw_err */ + kTopEarlgreyAlertIdRvCoreIbexPeriFatalHwErr = 66, /**< rv_core_ibex_peri_fatal_hw_err */ + kTopEarlgreyAlertIdRvCoreIbexPeriRecovHwErr = 67, /**< rv_core_ibex_peri_recov_hw_err */ + kTopEarlgreyAlertIdLast = 67, /**< \internal The Last Valid Alert ID. */ } top_earlgrey_alert_id_t; /** @@ -1232,7 +1270,7 @@ * `top_earlgrey_alert_peripheral_t`. */ extern const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[67]; + top_earlgrey_alert_for_peripheral[68]; #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h index ddb51d4..63db6fc 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
@@ -272,6 +272,20 @@ */ #define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000 /** + * Peripheral base address for regs device on rv_dm in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RV_DM_REGS_BASE_ADDR 0x41200000 +/** + * Peripheral base address for rom device on rv_dm in top earlgrey. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_EARLGREY_RV_DM_ROM_BASE_ADDR 0x10000 +/** * Peripheral base address for rv_plic in top earlgrey. * * This should be used with #mmio_region_from_addr to access the memory-mapped
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson index e9ce058..0ba108a 100644 --- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson +++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -200,17 +200,6 @@ }, ], } - { name: "rv_dm", - type: "rv_dm", - inter_signal_list: [ - { struct: "jtag", - type: "req_rsp", - name: "jtag", - act: "rsp", - package: "jtag_pkg", - }, - ] - } ] // `module` defines the peripherals. @@ -369,6 +358,14 @@ base_addrs: {core: "0x41000000", prim: "0x41008000"} attr: "templated", }, + { name: "rv_dm", + type: "rv_dm", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + // Note that this module also contains a bus host. + base_addrs: {rom: "0x00010000", regs: "0x41200000"} + }, { name: "rv_plic", type: "rv_plic", clock_srcs: {clk_i: "main"}, @@ -699,7 +696,8 @@ 'lc_ctrl.lc_nvm_debug_en' : ['eflash.lc_nvm_debug_en'], 'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en', 'sram_ctrl_ret_aon.lc_hw_debug_en', - 'pinmux_aon.lc_hw_debug_en'], + 'pinmux_aon.lc_hw_debug_en', + 'rv_dm.lc_hw_debug_en'], 'lc_ctrl.lc_cpu_en' : ['rv_core_ibex.lc_cpu_en'], 'lc_ctrl.lc_keymgr_en' : [], 'lc_ctrl.lc_escalate_en' : ['aes.lc_escalate_en', @@ -718,16 +716,24 @@ // TODO: Put passthrough here? //'spi_device.passthrough': ['spi_host0.passthrough'] + + // Debug module reset request to reset manager + 'rv_dm.ndmreset_req' : ['rstmgr_aon.ndmreset_req'] } // top is to connect to top net/struct. // It defines the signal in the top and connect from the module, // use of the signal is up to top template 'top': [ - 'rstmgr_aon.resets', 'rstmgr_aon.cpu', 'pwrmgr_aon.pwr_cpu', 'clkmgr_aon.clocks', - 'pwrmgr_aon.fetch_en', + 'rstmgr_aon.resets', 'rstmgr_aon.rst_cpu_n', + 'pwrmgr_aon.pwr_cpu', 'pwrmgr_aon.fetch_en', + 'clkmgr_aon.clocks', + + // Debug request from debug module to CPU + 'rv_dm.debug_req', + // Xbars - 'main.tl_corei', 'main.tl_cored', 'main.tl_dm_sba', 'main.tl_debug_mem' + 'main.tl_corei', 'main.tl_cored' ], // ext is to create port in the top. @@ -765,8 +771,6 @@ }, }, - debug_mem_base_addr: "0x1A110000", - // Crossbars: having a top level crossbar // This version assumes all crossbars are instantiated at the top. // Assume xbar.hjson is located in the same directory of top.hjson
diff --git a/hw/top_englishbreakfast/data/xbar_main.hjson b/hw/top_englishbreakfast/data/xbar_main.hjson index d1f1a3c..cb99c77 100644 --- a/hw/top_englishbreakfast/data/xbar_main.hjson +++ b/hw/top_englishbreakfast/data/xbar_main.hjson
@@ -23,12 +23,23 @@ pipeline: "false" }, - { name: "dm_sba", // DM - type: "host", - clock: "clk_main_i", - reset: "rst_main_ni", + { name: "rv_dm.sba", + type: "host", + clock: "clk_main_i", + reset: "rst_main_ni", pipeline_byp: "false" - + }, + { name: "rv_dm.regs", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline_byp: "false" + }, + { name: "rv_dm.rom", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline_byp: "false" }, { name: "rom", type: "device", @@ -36,12 +47,6 @@ reset: "rst_main_ni", pipeline: "false", }, - { name: "debug_mem", - type: "device", - clock: "clk_main_i", - reset: "rst_main_ni", - pipeline_byp: "false" - }, { name: "ram_main", type: "device", clock: "clk_main_i", @@ -99,14 +104,10 @@ }, ], connections: { - corei: ["rom", "debug_mem", "ram_main", "eflash"], - cored: ["rom", "debug_mem", "ram_main", "eflash", "peri", "flash_ctrl.core", - "flash_ctrl.prim", - "aes", - "hmac", "rv_plic", "sram_ctrl_main"], - dm_sba: ["rom", "ram_main", "eflash", "peri", "flash_ctrl.core", - "flash_ctrl.prim" - "aes", - "hmac", "rv_plic", "sram_ctrl_main"], + corei: ["rom", "rv_dm.rom", "ram_main", "eflash"], + cored: ["rom", "rv_dm.rom", "rv_dm.regs", "ram_main", "eflash", "peri", + "flash_ctrl.core", "flash_ctrl.prim", "aes", "hmac", "rv_plic", "sram_ctrl_main"], + rv_dm.sba: ["rom", "rv_dm.regs", "ram_main", "eflash", "peri", "flash_ctrl.core", + "flash_ctrl.prim", "aes", "hmac", "rv_plic", "sram_ctrl_main"], }, }