[doc] Updated Render documentation CI check
CI now requires `mdbook` to build the documentation.
The site is now built with the documentation,
so `ci/scripts/build-site.sh` can be removed.
Ran `make -k -C hw top` to stop the check-generated lint from
complaining. `topgen.py` isn't completely compatible with the new
documentation system; it still uses yaml front-matter for example.
So, a couple of pages aren't as functional as they using were,
i.e. some links are broken etc.
Updated CI configuration for building docker containers
with the new container locations.
Signed-off-by: Hugo McNally <hugo.mcnally@gmail.com>
diff --git a/azure-pipelines.yml b/azure-pipelines.yml
index bb1bc23..18eb207 100644
--- a/azure-pipelines.yml
+++ b/azure-pipelines.yml
@@ -128,8 +128,6 @@
displayName: Check trailing whitespace
- bash: ci/scripts/build-docs.sh
displayName: Render documentation
- - bash: ci/scripts/build-site.sh
- displayName: Render landing site
- bash: ci/scripts/get-build-type.sh "$SYSTEM_PULLREQUEST_TARGETBRANCH" "$(Build.Reason)"
displayName: Type of change
# Check what kinds of changes the PR contains
@@ -674,11 +672,11 @@
inputs:
command: build
tags: gcr.io/active-premise-257318/builder
- Dockerfile: ./site/docs/builder.Dockerfile
+ Dockerfile: ./util/site/site-builder/builder.Dockerfile
buildContext: .
- task: Docker@2
displayName: Build Documentation Redirector Container
inputs:
command: build
- Dockerfile: ./site/redirector/Dockerfile
- buildContext: ./site/redirector
+ Dockerfile: ./site/redirector/landing/Dockerfile
+ buildContext: ./site/redirector/landing
diff --git a/ci/install-package-dependencies.sh b/ci/install-package-dependencies.sh
index a13027b..0a2050d 100755
--- a/ci/install-package-dependencies.sh
+++ b/ci/install-package-dependencies.sh
@@ -142,5 +142,21 @@
--default-toolchain "${RUST_VERSION}"
export PATH=$HOME/.cargo/bin:$PATH
+# Install mdbook
+MDBOOK_VERSION="v0.4.27"
+MDBOOK_BASE_URL="https://github.com/rust-lang/mdBook/releases/download"
+MDBOOK_TARBALL="mdbook-${MDBOOK_VERSION}-x86_64-unknown-linux-gnu.tar.gz"
+MDBOOK_URL="${MDBOOK_BASE_URL}/${MDBOOK_VERSION}/${MDBOOK_TARBALL}"
+MDBOOK_DOWNLOAD="$TMPDIR/mdbook.tar.gz"
+
+curl -f -Ls -o "$MDBOOK_DOWNLOAD" "${MDBOOK_URL}" || {
+ error "Failed to download verible from ${MDBOOK_URL}"
+}
+
+sudo mkdir -p /tools/mdbook
+sudo chmod 777 /tools/mdbook
+tar -C /tools/mdbook -xf "$MDBOOK_DOWNLOAD"
+export PATH=/tools/mdbook:$PATH
+
# Propagate PATH changes to all subsequent steps of the job
echo "##vso[task.setvariable variable=PATH]$PATH"
diff --git a/ci/scripts/build-docs.sh b/ci/scripts/build-docs.sh
index eabbb85..40885e6 100755
--- a/ci/scripts/build-docs.sh
+++ b/ci/scripts/build-docs.sh
@@ -6,7 +6,7 @@
# Build docs and tell the Azure runner to upload any doxygen warnings
set -e
-util/build_docs.py || {
+util/site/build-docs.sh || {
echo -n "##vso[task.logissue type=error]"
echo "Documentation build failed."
exit 1
diff --git a/ci/scripts/build-site.sh b/ci/scripts/build-site.sh
deleted file mode 100755
index 2353f4f..0000000
--- a/ci/scripts/build-site.sh
+++ /dev/null
@@ -1,10 +0,0 @@
-#!/bin/bash
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-
-# Build the landing site
-
-set -e
-cd site/landing
-../../build/docs-hugo/hugo
diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md
index a93fe16..7179441 100644
--- a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md
+++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md
@@ -1,4 +1,6 @@
-# ASIC Target Pinout and Pinmux Connectivity
+---
+title: ASIC Target Pinout and Pinmux Connectivity
+---
<!--
DO NOT EDIT THIS FILE DIRECTLY.
It has been generated with the following command:
diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md
index f735e29..82cc3e8 100644
--- a/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md
+++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md
@@ -1,4 +1,6 @@
-# CW310 Target Pinout and Pinmux Connectivity
+---
+title: CW310 Target Pinout and Pinmux Connectivity
+---
<!--
DO NOT EDIT THIS FILE DIRECTLY.
It has been generated with the following command:
diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md
index b475239..dc8f616 100644
--- a/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md
+++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md
@@ -7,5 +7,5 @@
| Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables |
|:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:-----------------------------------------------------------------------------------:|
-| ASIC | 4 | 47 | 14 | 10 | 71 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_asic.md) |
-| CW310 | 4 | 47 | 14 | 15 | 76 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310.md) |
+| ASIC | 4 | 47 | 14 | 10 | 71 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_asic/index.html) |
+| CW310 | 4 | 47 | 14 | 15 | 76 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310/index.html) |
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/README.md b/hw/top_earlgrey/ip_autogen/alert_handler/README.md
index 704d8f6..574804e 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/README.md
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/README.md
@@ -4,7 +4,7 @@
# Overview
This document specifies the functionality of the alert handler mechanism.
-The alert handler is a module that is a peripheral on the chip interconnect bus, and thus follows the [Comportability Specification](../../../../doc/contributing/hw/comportability/README.md).
+The alert handler is a module that is a peripheral on the chip interconnect bus, and thus follows the [Comportability Specification](../../../doc/contributing/hw/comportability/README.md).
It gathers alerts - defined as interrupt-type signals from other peripherals that are designated as potential security threats - throughout the design, and converts them to interrupts that the processor can handle.
If the processor does not handle them, the alert handler mechanism provides hardware responses to handle the threat.
@@ -111,7 +111,7 @@
### Signals
-* [Interface Tables](data/alert_handler.hjson#interfaces)
+* [Interface Tables](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#interfaces)
The table below lists other alert handler module signals.
The number of alert instances is parametric and hence alert and ping diff pairs are grouped together in packed arrays.
@@ -151,7 +151,7 @@
#### Low-power Indication Signals
-The `lpg_cg_en_i` and `lpg_rst_en_i` are two arrays with multibit indication signals from the [clock](../../../ip/clkmgr/README.md) and [reset managers](../../../ip/rstmgr/README.md).
+The `lpg_cg_en_i` and `lpg_rst_en_i` are two arrays with multibit indication signals from the [clock](../../ip/clkmgr/README.md) and [reset managers](../../ip/rstmgr/README.md).
These indication signals convey whether a specific group of alert senders are either clock gated or in reset.
As explained in [more detail below](#low-power-management-of-alert-channels), this information is used to temporarily halt the ping timer mechanism on channels that are in a low-power state in order to prevent false positives.
@@ -174,7 +174,7 @@
This can be useful for extracting more information about possible failures or bugs without having to use the tile-link bus interface (which may become unresponsive under certain circumstances).
It is recommended for the top level to store this information in an always-on location.
-Note that the crashdump state is continuously output via `crashdump_o` until the latching trigger condition is true for the first time (see [`CLASSA_CRASHDUMP_TRIGGER_SHADOWED`](data/alert_handler.hjson#classa_crashdump_trigger_shadowed)).
+Note that the crashdump state is continuously output via `crashdump_o` until the latching trigger condition is true for the first time (see [`CLASSA_CRASHDUMP_TRIGGER_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_crashdump_trigger_shadowed)).
After that, the `crashdump_o` is held constant until all classes that have escalated are cleared.
This is done so that it is possible to capture the true alert cause before spurious alert events start to pop up due to escalation countermeasures with excessive side effects (like life cycle scrapping for example).
If classes that have escalated are not configured as clearable, then it is not possible to re-arm the crashdump latching mechanism at runtime and the alert handler has to be reset.
@@ -370,7 +370,7 @@
Further, this ping timer also randomly selects a particular alert line to be pinged (escalation senders are always pinged in-order due to the [ping monitoring mechanism](#monitoring-of-pings-at-the-escalation-receiver-side) on the escalation side).
That should make it more difficult to predict the next ping occurrence based on past observations.
-The ping timer is implemented using an [LFSR-based PRNG of Galois type](../../../ip/prim/doc/prim_lfsr.md).
+The ping timer is implemented using an [LFSR-based PRNG of Galois type](../../ip/prim/doc/prim_lfsr.md).
This ping timer is reseeded with fresh entropy from EDN roughly every 500k cycles which corresponds to around 16 ping operations on average.
The LFSR is 32bits wide, but only 24bits of its state are actually being used to generate the random timer count and select the alert line to be pinged.
I.e., the 32bits first go through a fixed permutation function, and then bits `[23:16]` are used to determine which alert line to ping.
@@ -386,7 +386,7 @@
In both cases, the LFSR timer proceeds with the next ping, but in the second case it will additionally raise a "pingfail" alert.
The ping enable signal remains asserted during the time where the LFSR counter waits.
-The timeout value is a function of the ratios between the alert handler clock and peripheral clocks present in the system, and can be programmed at startup time via the register [`PING_TIMEOUT_CYC_SHADOWED`](data/alert_handler.hjson#ping_timeout_cyc_shadowed).
+The timeout value is a function of the ratios between the alert handler clock and peripheral clocks present in the system, and can be programmed at startup time via the register [`PING_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#ping_timeout_cyc_shadowed).
Note that the ping timer directly flags a "pingfail" alert if a spurious "ping ok" message comes in that has not been requested.
@@ -395,7 +395,7 @@
Only alerts that have been *enabled and locked* will be pinged in order to avoid spurious alerts.
Escalation channels are always enabled, and hence will always be pinged once this mechanism has been turned on.
-In addition to the ping timer mechanism described above, the escalation receivers contain monitoring counters that monitor the liveness of the alert handler (described in more detail in [this section](#monitoring-of-pings-at-the-escalation-receiver-side)).
+In addition to the ping timer mechanism described above, the escalation receivers contain monitoring counters that monitor the liveness of the alert handler (described in more detail in [this section](#monitoring-of-pings-at-the-escalation-receiver-side).
This mechanism requires that the maximum wait time between escalation receiver pings is bounded.
To that end, escalation senders are pinged in-order every second ping operation (i.e., the wait time is randomized, but the selection of the escalation line is not).
@@ -444,20 +444,20 @@
- Accumulation max value.
This is the total number (sum of all alerts classified in this group) of alerts required to enter escalation phase (see below).
- Example register is [`CLASSA_ACCUM_THRESH_SHADOWED`](data/alert_handler.hjson#classa_accum_thresh_shadowed).
+ Example register is [`CLASSA_ACCUM_THRESH_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_accum_thresh_shadowed).
- Current accumulation register.
This clearable register indicates how many alerts have been accumulated to date.
Software should clear before it reaches the accumulation setting to avoid escalation.
- Example register is [`CLASSA_ACCUM_CNT`](data/alert_handler.hjson#classa_accum_cnt).
+ Example register is [`CLASSA_ACCUM_CNT`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_accum_cnt).
2. The second way is an interrupt timeout counter which triggers escalation if an alert interrupt is not handled within the programmable timeout window.
Once the counter hits the timeout threshold, the escalation protocol is triggered.
The corresponding CSRs are:
- - Interrupt timeout value in cycles [`CLASSA_TIMEOUT_CYC_SHADOWED`](data/alert_handler.hjson#classa_timeout_cyc_shadowed).
+ - Interrupt timeout value in cycles [`CLASSA_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_timeout_cyc_shadowed).
The interrupt timeout is disabled if this is set to 0 (default).
- - The current interrupt timeout value can be read via [`CLASSA_ESC_CNT`](data/alert_handler.hjson#classa_esc_cnt) if [`CLASSA_STATE`](data/alert_handler.hjson#classa_state) is in the `Timeout` state.
- Software should clear the corresponding interrupt state bit [`INTR_STATE.CLASSA`](data/alert_handler.hjson#intr_state) before the timeout expires to avoid escalation.
+ - The current interrupt timeout value can be read via [`CLASSA_ESC_CNT`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_esc_cnt) if [`CLASSA_STATE`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_state) is in the `Timeout` state.
+ Software should clear the corresponding interrupt state bit [`INTR_STATE.CLASSA`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#intr_state) before the timeout expires to avoid escalation.
Technically, the interrupt timeout feature (2. above) is implemented using the same counter used to time the escalation phases.
This is possible since escalation phases or interrupt timeout periods are non-overlapping (escalation always takes precedence should it be triggered).
@@ -474,13 +474,13 @@
Each class can be programmed with its own escalation protocol.
If one of the two mechanisms described above fires, a timer for that particular class is started.
-The timer can be programmed with up to 4 delays (e.g., [`CLASSA_PHASE0_CYC`](data/alert_handler.hjson#classa_phase0_cyc)), each representing a distinct escalation phase (0 - 3).
+The timer can be programmed with up to 4 delays (e.g., [`CLASSA_PHASE0_CYC`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_phase0_cyc)), each representing a distinct escalation phase (0 - 3).
Each of the four escalation severity outputs (0 - 3) are by default configured to be asserted during the corresponding phase, e.g., severity 0 in phase 0, severity 1 in phase 1, etc.
-However, this mapping can be freely reassigned by modifying the corresponding enable/phase mappings (e.g., [`CLASSA_CTRL_SHADOWED.E0_MAP`](data/alert_handler.hjson#classa_ctrl_shadowed) for enable bit 0 of class A).
+However, this mapping can be freely reassigned by modifying the corresponding enable/phase mappings (e.g., [`CLASSA_CTRL_SHADOWED.E0_MAP`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) for enable bit 0 of class A).
This mapping will be locked in together with the alert enable configuration after initial configuration.
-SW can stop a triggered escalation protocol by clearing the corresponding escalation counter (e.g., [`CLASSA_ESC_CNT`](data/alert_handler.hjson#classa_esc_cnt)).
-Protection of this clearing is up to software, see the register control section that follows for [`CLASSA_CTRL_SHADOWED.LOCK`](data/alert_handler.hjson#classa_ctrl_shadowed).
+SW can stop a triggered escalation protocol by clearing the corresponding escalation counter (e.g., [`CLASSA_ESC_CNT`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_esc_cnt)).
+Protection of this clearing is up to software, see the register control section that follows for [`CLASSA_CTRL_SHADOWED.LOCK`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed).
It should be noted that each of the escalation phases have a duration of at least 1 clock cycle, even if the cycle count of a particular phase has been
set to 0.
@@ -818,7 +818,7 @@
It is consequently possible for a group of alert senders to already be in reset or clock gated state, while the corresponding LPG logic does not yet know about this state change - and vice versa.
In practice, this means that ping requests may be pending for several cycles until the LPG logic detects a reset or clock-gated condition and disables the corresponding alert channel(s).
-Fortunately, such delay can be tolerated by setting the ping timeout to a sufficiently large value (see [`CLASSA_TIMEOUT_CYC_SHADOWED`](data/alert_handler.hjson#classa_timeout_cyc_shadowed)).
+Fortunately, such delay can be tolerated by setting the ping timeout to a sufficiently large value (see [`CLASSA_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_timeout_cyc_shadowed)).
As for alert events, this latency difference should not pose a problem.
Alert events may get stuck in the alert sender due to a reset or clock-gated condition - but this is to be expected.
@@ -866,7 +866,7 @@
Note however that the LPGs inherit the security properties of the associated clock groups and resets.
This means that the low-power state of certain alerts can be controlled by SW by means of clock gating or block reset.
For example, certain crypto blocks are located in a transactional clock group which can be clock gated by SW - and this also affects the associated alerts of these crypto blocks.
-See [clock](../../../ip/clkmgr/README.md) and [reset managers](../../../ip/rstmgr/README.md) for more detail.
+See [clock](../../ip/clkmgr/README.md) and [reset managers](../../ip/rstmgr/README.md) for more detail.
## Initialization
@@ -876,44 +876,44 @@
1. For each alert and each local alert:
- Determine if alert is enabled (should only be false if alert is known to be faulty).
- Set [`ALERT_EN_SHADOWED_0.EN_A_0`](data/alert_handler.hjson#alert_en_shadowed_0) and [`LOC_ALERT_EN_SHADOWED_0.EN_LA_0`](data/alert_handler.hjson#loc_alert_en_shadowed_0) accordingly.
+ Set [`ALERT_EN_SHADOWED_0.EN_A_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#alert_en_shadowed_0) and [`LOC_ALERT_EN_SHADOWED_0.EN_LA_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#loc_alert_en_shadowed_0) accordingly.
- Determine which class (A..D) the alert is associated with.
- Set [`ALERT_CLASS_SHADOWED_0.CLASS_A_0`](data/alert_handler.hjson#alert_class_shadowed_0) and [`LOC_ALERT_CLASS_SHADOWED_0.CLASS_LA_0`](data/alert_handler.hjson#loc_alert_class_shadowed_0) accordingly.
+ Set [`ALERT_CLASS_SHADOWED_0.CLASS_A_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#alert_class_shadowed_0) and [`LOC_ALERT_CLASS_SHADOWED_0.CLASS_LA_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#loc_alert_class_shadowed_0) accordingly.
- - Optionally lock each alert configuration by writing 0 to [`ALERT_REGWEN_0.EN_0`](data/alert_handler.hjson#alert_regwen_0) or [`LOC_ALERT_REGWEN_0.EN_0`](data/alert_handler.hjson#loc_alert_regwen_0).
+ - Optionally lock each alert configuration by writing 0 to [`ALERT_REGWEN_0.EN_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#alert_regwen_0) or [`LOC_ALERT_REGWEN_0.EN_0`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#loc_alert_regwen_0).
Note however that only **locked and enabled** alerts are going to be pinged using the ping mechanism.
This ensures that spurious ping failures cannot occur when previously enabled alerts are being disabled again (before locking).
-2. Set the ping timeout value [`PING_TIMEOUT_CYC_SHADOWED`](data/alert_handler.hjson#ping_timeout_cyc_shadowed).
+2. Set the ping timeout value [`PING_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#ping_timeout_cyc_shadowed).
This value is dependent on the clock ratios present in the system.
3. For each class (A..D):
- - Determine whether to enable escalation mechanisms (accumulation / interrupt timeout) for this particular class. Set [`CLASSA_CTRL_SHADOWED.EN`](data/alert_handler.hjson#classa_ctrl_shadowed) accordingly.
+ - Determine whether to enable escalation mechanisms (accumulation / interrupt timeout) for this particular class. Set [`CLASSA_CTRL_SHADOWED.EN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) accordingly.
- Determine if this class of alerts allows clearing of escalation once it has begun.
- Set [`CLASSA_CTRL_SHADOWED.LOCK`](data/alert_handler.hjson#classa_ctrl_shadowed) to true if clearing should be disabled.
+ Set [`CLASSA_CTRL_SHADOWED.LOCK`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) to true if clearing should be disabled.
If true, once escalation protocol begins, it can not be stopped, the assumption being that it ends in a chip reset else it will be rendered useless thenceforth.
- - Determine the number of alerts required to be accumulated before escalation protocol kicks in. Set [`CLASSA_ACCUM_THRESH`](data/alert_handler.hjson#classa_accum_thresh) accordingly.
+ - Determine the number of alerts required to be accumulated before escalation protocol kicks in. Set [`CLASSA_ACCUM_THRESH`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_accum_thresh) accordingly.
- Determine whether the interrupt associated with that class needs a timeout.
- If yes, set [`CLASSA_TIMEOUT_CYC_SHADOWED`](data/alert_handler.hjson#classa_timeout_cyc_shadowed) to an appropriate value greater than zero (zero corresponds to an infinite timeout and disables the mechanism).
+ If yes, set [`CLASSA_TIMEOUT_CYC_SHADOWED`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_timeout_cyc_shadowed) to an appropriate value greater than zero (zero corresponds to an infinite timeout and disables the mechanism).
- For each escalation phase (0..3):
- - Determine length of each escalation phase by setting [`CLASSA_PHASE0_CYC`](data/alert_handler.hjson#classa_phase0_cyc) accordingly
+ - Determine length of each escalation phase by setting [`CLASSA_PHASE0_CYC`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_phase0_cyc) accordingly
- For each escalation signal (0..3):
- - Determine whether to enable the escalation signal, and set the [`CLASSA_CTRL_SHADOWED.E0_EN`](data/alert_handler.hjson#classa_ctrl_shadowed) bit accordingly (default is enabled).
- Note that setting all of the `E*_EN` bits to 0 within a class has the same effect of disabling the entire class by setting [`CLASSA_CTRL_SHADOWED.EN`](data/alert_handler.hjson#classa_ctrl_shadowed) to zero.
- - Determine the phase -> escalation mapping of this class and program it via the [`CLASSA_CTRL_SHADOWED.E0_MAP`](data/alert_handler.hjson#classa_ctrl_shadowed) values if it needs to be changed from the default mapping (0->0, 1->1, 2->2, 3->3).
+ - Determine whether to enable the escalation signal, and set the [`CLASSA_CTRL_SHADOWED.E0_EN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) bit accordingly (default is enabled).
+ Note that setting all of the `E*_EN` bits to 0 within a class has the same effect of disabling the entire class by setting [`CLASSA_CTRL_SHADOWED.EN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) to zero.
+ - Determine the phase -> escalation mapping of this class and program it via the [`CLASSA_CTRL_SHADOWED.E0_MAP`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed) values if it needs to be changed from the default mapping (0->0, 1->1, 2->2, 3->3).
- - Optionally lock the class configuration by writing 0 to [`CLASSA_CTRL_SHADOWED.REGWEN`](data/alert_handler.hjson#classa_ctrl_shadowed).
+ - Optionally lock the class configuration by writing 0 to [`CLASSA_CTRL_SHADOWED.REGWEN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed).
-4. After initial configuration at startup, enable the ping timer mechanism by writing 1 to [`PING_TIMER_EN`](data/alert_handler.hjson#ping_timer_en).
-It is also recommended to lock the ping timer configuration by clearing [`PING_TIMER_REGWEN`](data/alert_handler.hjson#ping_timer_regwen).
+4. After initial configuration at startup, enable the ping timer mechanism by writing 1 to [`PING_TIMER_EN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#ping_timer_en).
+It is also recommended to lock the ping timer configuration by clearing [`PING_TIMER_REGWEN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#ping_timer_regwen).
Note that only **locked and enabled** alerts are going to be pinged using the ping mechanism.
This ensures that spurious ping failures cannot occur when previously enabled alerts are being disabled again (before locking).
@@ -922,12 +922,12 @@
For every alert that is enabled, an interrupt will be triggered on class A, B, C, or D.
To handle an interrupt of a particular class, software should execute the following steps:
-1. If needed, check the escalation state of this class by reading [`CLASSA_STATE`](data/alert_handler.hjson#classa_state).
+1. If needed, check the escalation state of this class by reading [`CLASSA_STATE`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_state).
This reveals whether escalation protocol has been triggered and in which escalation phase the class is.
In case interrupt timeouts are enabled the class will be in timeout state unless escalation has already been triggered.
- The current interrupt or escalation cycle counter can be read via [`CLASSA_ESC_CNT`](data/alert_handler.hjson#classa_esc_cnt).
+ The current interrupt or escalation cycle counter can be read via [`CLASSA_ESC_CNT`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_esc_cnt).
-2. Since the interrupt does not indicate which alert triggered, SW must read the cause registers [`LOC_ALERT_CAUSE`](data/alert_handler.hjson#loc_alert_cause) and [`ALERT_CAUSE`](data/alert_handler.hjson#alert_cause) etc.
+2. Since the interrupt does not indicate which alert triggered, SW must read the cause registers [`LOC_ALERT_CAUSE`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#loc_alert_cause) and [`ALERT_CAUSE`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#alert_cause) etc.
The cause bits of all alerts are concatenated and chunked into 32bit words.
Hence the register file contains as many cause words as needed to cover all alerts present in the system.
Each cause register contains a sticky bit that is set by the incoming alert, and is clearable with a write by software.
@@ -938,12 +938,12 @@
3. After the event is cleared (if needed or possible), software should handle the interrupt as follows:
- - Resetting the accumulation register for the class by writing [`CLASSA_CLR`](data/alert_handler.hjson#classa_clr).
+ - Resetting the accumulation register for the class by writing [`CLASSA_CLR`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_clr).
This also aborts the escalation protocol if it has been triggered.
- If for some reason it is desired to never allow the accumulator or escalation to be cleared, software can initialize the [`CLASSA_CLR_REGWEN`](data/alert_handler.hjson#classa_clr_regwen) register to zero.
- If [`CLASSA_CLR_REGWEN`](data/alert_handler.hjson#classa_clr_regwen) is already false when an alert interrupt is detected (either due to software control or hardware trigger via [`CLASSA_CTRL_SHADOWED.LOCK`](data/alert_handler.hjson#classa_ctrl_shadowed)), then the accumulation counter can not be cleared and this step has no effect.
+ If for some reason it is desired to never allow the accumulator or escalation to be cleared, software can initialize the [`CLASSA_CLR_REGWEN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_clr_regwen) register to zero.
+ If [`CLASSA_CLR_REGWEN`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_clr_regwen) is already false when an alert interrupt is detected (either due to software control or hardware trigger via [`CLASSA_CTRL_SHADOWED.LOCK`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#classa_ctrl_shadowed)), then the accumulation counter can not be cleared and this step has no effect.
- - After the accumulation counter is reset (if applicable), software should clear the class A interrupt state bit [`INTR_STATE.CLASSA`](data/alert_handler.hjson#intr_state).
+ - After the accumulation counter is reset (if applicable), software should clear the class A interrupt state bit [`INTR_STATE.CLASSA`](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#intr_state).
Clearing the class A interrupt state bit also clears and stops the interrupt timeout counter (if enabled).
Note that testing interrupts by writing to the interrupt test registers does also trigger the internal interrupt timeout (if enabled), since the interrupt state is used as enable signal for the timer.
@@ -955,7 +955,7 @@
## Register Table
-* [Register Table](data/alert_handler.hjson#registers)
+* [Register Table](../../top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson#registers)
# Additional Notes
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/doc/checklist.md b/hw/top_earlgrey/ip_autogen/alert_handler/doc/checklist.md
index bdc3192..3d3b7fe 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/doc/checklist.md
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/doc/checklist.md
@@ -1,7 +1,7 @@
# Alert Handler Checklist
-This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [Alert Handler peripheral.](../README.md)
-All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md)
+This checklist is for [Hardware Stage](../../../../doc/project_governance/development_stages.md) transitions for the [Alert Handler peripheral.](../README.md)
+All checklist items refer to the content in the [Checklist.](../../../../doc/project_governance/checklist/README.md)
## Design Checklist
@@ -19,15 +19,15 @@
RTL | [ASSERT_KNOWN_ADDED][] | Done |
Code Quality | [LINT_SETUP][] | Done |
-[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete
-[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined
-[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected
-[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top
-[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable
-[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80
-[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented
-[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added
-[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup
+[SPEC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#spec_complete
+[CSR_DEFINED]: ../../../../doc/project_governance/checklist/README.md#csr_defined
+[CLKRST_CONNECTED]: ../../../../doc/project_governance/checklist/README.md#clkrst_connected
+[IP_TOP]: ../../../../doc/project_governance/checklist/README.md#ip_top
+[IP_INSTANTIABLE]: ../../../../doc/project_governance/checklist/README.md#ip_instantiable
+[PHYSICAL_MACROS_DEFINED_80]: ../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80
+[FUNC_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#func_implemented
+[ASSERT_KNOWN_ADDED]: ../../../../doc/project_governance/checklist/README.md#assert_known_added
+[LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#lint_setup
### D2
@@ -52,24 +52,24 @@
Code Quality | [TIMING_CHECK][] | Done |
Security | [SEC_CM_DOCUMENTED][] | Done |
-[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features
-[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram
-[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface
-[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide
-[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func
-[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen
-[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete
-[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen
-[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen
-[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo
-[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x
-[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro
-[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass
-[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup
-[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup
-[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check
-[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check
-[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented
+[NEW_FEATURES]: ../../../../doc/project_governance/checklist/README.md#new_features
+[BLOCK_DIAGRAM]: ../../../../doc/project_governance/checklist/README.md#block_diagram
+[DOC_INTERFACE]: ../../../../doc/project_governance/checklist/README.md#doc_interface
+[DOC_INTEGRATION_GUIDE]: ../../../../doc/project_governance/checklist/README.md#doc_integration_guide
+[MISSING_FUNC]: ../../../../doc/project_governance/checklist/README.md#missing_func
+[FEATURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#feature_frozen
+[FEATURE_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#feature_complete
+[PORT_FROZEN]: ../../../../doc/project_governance/checklist/README.md#port_frozen
+[ARCHITECTURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#architecture_frozen
+[REVIEW_TODO]: ../../../../doc/project_governance/checklist/README.md#review_todo
+[STYLE_X]: ../../../../doc/project_governance/checklist/README.md#style_x
+[CDC_SYNCMACRO]: ../../../../doc/project_governance/checklist/README.md#cdc_syncmacro
+[LINT_PASS]: ../../../../doc/project_governance/checklist/README.md#lint_pass
+[CDC_SETUP]: ../../../../doc/project_governance/checklist/README.md#cdc_setup
+[RDC_SETUP]: ../../../../doc/project_governance/checklist/README.md#rdc_setup
+[AREA_CHECK]: ../../../../doc/project_governance/checklist/README.md#area_check
+[TIMING_CHECK]: ../../../../doc/project_governance/checklist/README.md#timing_check
+[SEC_CM_DOCUMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_documented
### D2S
@@ -83,13 +83,13 @@
Security | [SEC_CM_RTL_REVIEWED][] | Done |
Security | [SEC_CM_COUNCIL_REVIEWED][] | Done |
-[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed
-[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented
-[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst
-[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops
-[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs
-[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed
-[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed
+[SEC_CM_ASSETS_LISTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed
+[SEC_CM_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_implemented
+[SEC_CM_RND_CNST]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst
+[SEC_CM_NON_RESET_FLOPS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops
+[SEC_CM_SHADOW_REGS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs
+[SEC_CM_RTL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed
+[SEC_CM_COUNCIL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed
### D3
@@ -107,15 +107,15 @@
Review | Reviewer(s) | Done | msf@ vogelpi@ chencindy@ ttrippel@ tjaychen@
Review | Signoff date | Done | 2022-07-11
-[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3
-[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete
-[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete
-[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete
-[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete
-[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl
-[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff
-[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change
-[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata
+[NEW_FEATURES_D3]: ../../../../doc/project_governance/checklist/README.md#new_features_d3
+[TODO_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#todo_complete
+[LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#lint_complete
+[CDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#cdc_complete
+[RDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#rdc_complete
+[REVIEW_RTL]: ../../../../doc/project_governance/checklist/README.md#review_rtl
+[REVIEW_DELETED_FF]: ../../../../doc/project_governance/checklist/README.md#review_deleted_ff
+[REVIEW_SW_CHANGE]: ../../../../doc/project_governance/checklist/README.md#review_sw_change
+[REVIEW_SW_ERRATA]: ../../../../doc/project_governance/checklist/README.md#review_sw_errata
## Verification Checklist
@@ -146,28 +146,28 @@
Review | [STD_TEST_CATEGORIES_PLANNED][] | Done |
Review | [V2_CHECKLIST_SCOPED][] | Done |
-[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed
-[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed
-[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created
-[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added
-[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created
-[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated
-[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated
-[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated
-[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing
-[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing
-[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven
-[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup
-[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup
-[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup
-[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup
-[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added
-[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup
-[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1
-[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed
-[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed
-[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned
-[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped
+[DV_DOC_DRAFT_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed
+[TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#testplan_completed
+[TB_TOP_CREATED]: ../../../../doc/project_governance/checklist/README.md#tb_top_created
+[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added
+[SIM_TB_ENV_CREATED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_created
+[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated
+[CSR_CHECK_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated
+[TB_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#tb_gen_automated
+[SIM_SMOKE_TEST_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing
+[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing
+[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven
+[SIM_ALT_TOOL_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup
+[SIM_SMOKE_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup
+[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup
+[FPV_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#fpv_regression_setup
+[SIM_COVERAGE_MODEL_ADDED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added
+[TB_LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#tb_lint_setup
+[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1
+[DESIGN_SPEC_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#design_spec_reviewed
+[TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#testplan_reviewed
+[STD_TEST_CATEGORIES_PLANNED]: ../../../../doc/project_governance/checklist/README.md#std_test_categories_planned
+[V2_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped
### V2
@@ -194,26 +194,26 @@
Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done |
Review | [V3_CHECKLIST_SCOPED][] | Done |
-[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2
-[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed
-[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented
-[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised
-[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added
-[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed
-[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing
-[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written
-[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed
-[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated
-[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2
-[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2
-[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2
-[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2
-[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2
-[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2
-[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending
-[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused
-[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed
-[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped
+[DESIGN_DELTAS_CAPTURED_V2]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2
+[DV_DOC_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_completed
+[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented
+[ALL_INTERFACES_EXERCISED]: ../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised
+[ALL_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added
+[SIM_TB_ENV_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed
+[SIM_ALL_TESTS_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing
+[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written
+[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed
+[SIM_FW_SIMULATED]: ../../../../doc/project_governance/checklist/README.md#sim_fw_simulated
+[SIM_NIGHTLY_REGRESSION_V2]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2
+[SIM_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2
+[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2
+[FPV_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2
+[FPV_COI_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2
+[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2
+[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending
+[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused
+[DV_DOC_TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed
+[V3_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped
### V2S
@@ -225,11 +225,11 @@
Coverage | [SIM_COVERAGE_REVIEWED][] | Done |
Review | [SEC_CM_DV_REVIEWED][] | Done |
-[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed
-[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified
-[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified
-[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed
-[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed
+[SEC_CM_TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed
+[FPV_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified
+[SIM_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified
+[SIM_COVERAGE_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed
+[SEC_CM_DV_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed
### V3
@@ -251,16 +251,16 @@
Review | Reviewer(s) | Not Started |
Review | Signoff date | Not Started |
-[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3
-[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed
-[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3
-[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3
-[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100
-[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100
-[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100
-[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100
-[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved
-[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown
-[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete
-[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3
-[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending
+[DESIGN_DELTAS_CAPTURED_V3]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3
+[X_PROP_ANALYSIS_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed
+[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3
+[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3
+[SIM_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100
+[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100
+[FPV_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100
+[FPV_COI_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100
+[ALL_TODOS_RESOLVED]: ../../../../doc/project_governance/checklist/README.md#all_todos_resolved
+[NO_TOOL_WARNINGS_THROWN]: ../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown
+[TB_LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#tb_lint_complete
+[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3
+[NO_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_issues_pending
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/dv/README.md b/hw/top_earlgrey/ip_autogen/alert_handler/dv/README.md
index 4eee0cc..b1f14cd 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/dv/README.md
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/dv/README.md
@@ -11,15 +11,15 @@
* Verify alert_handler_esc_timer and alert_handler_ping_timer
## Current status
-* [Design & verification stage](../../../../README.md)
- * [HW development stages](../../../../../doc/project_governance/development_stages.md)
+* [Design & verification stage](../../../README.md)
+ * [HW development stages](../../../../doc/project_governance/development_stages.md)
* [Simulation results](https://reports.opentitan.org/hw/ip/alert_handler/dv/latest/results.html)
## Design features
For detailed information on ALERT_HANDLER design features, please see the [ALERT_HANDLER HWIP technical specification](../README.md).
## Testbench architecture
-ALERT_HANDLER testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md).
+ALERT_HANDLER testbench has been constructed based on the [CIP testbench architecture](../../../dv/sv/cip_lib/README.md).
### Block diagram
@@ -27,19 +27,19 @@
### Top level testbench
Top level testbench is located at `hw/ip/alert_handler/dv/tb/tb.sv`. It instantiates the ALERT_HANDLER DUT module `hw/ip/alert_handler/rtl/alert_handler.sv`.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
-* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md)
-* [TileLink host interface](../../../../dv/sv/tl_agent/README.md)
+* [Clock and reset interface](../../../dv/sv/common_ifs/README.md)
+* [TileLink host interface](../../../dv/sv/tl_agent/README.md)
* ALERT_HANDLER IOs
-* Alerts and escalations([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md))
-* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md))
-* Devmode ([`pins_if`](../../../../dv/sv/common_ifs/README.md))
+* Alerts and escalations([`alert_esc_if`](../../../dv/sv/alert_esc_agent/README.md))
+* Interrupts ([`pins_if`](../../../dv/sv/common_ifs/README.md))
+* Devmode ([`pins_if`](../../../dv/sv/common_ifs/README.md))
The alert_handler testbench environment can be reused in chip level testing.
### Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
-* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md)
-* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md)
+* [dv_utils_pkg](../../../dv/sv/dv_utils/README.md)
+* [csr_utils_pkg](../../../dv/sv/csr_utils/README.md)
### Global types & methods
All common types and methods defined at the package level can be found in
@@ -49,18 +49,18 @@
```
### TL_agent
-ALERT_HANDLER testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md)
+ALERT_HANDLER testbench instantiates (already handled in CIP base env) [tl_agent](../../../dv/sv/tl_agent/README.md)
which provides the ability to drive and independently monitor random traffic via
TL host interface into ALERT_HANDLER device.
### ALERT_ESC Agent
-[ALERT_ESC agent](../../../../dv/sv/alert_esc_agent/README.md) is used to drive and monitor transmitter and receiver pairs for the alerts and escalators.
+[ALERT_ESC agent](../../../dv/sv/alert_esc_agent/README.md) is used to drive and monitor transmitter and receiver pairs for the alerts and escalators.
Alert_handler DUT includes alert_receivers and esc_senders, so the alert_esc agent will drive output signals of the alert_senders and esc_receivers.
### UVM RAL Model
-The ALERT_HANDLER RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage.
+The ALERT_HANDLER RAL model is created with the [`ralgen`](../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage.
-It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md).
+It can be created manually by invoking [`regtool`](../../../../util/reggen/doc/setup_and_use.md).
### Stimulus strategy
#### Test sequences
@@ -104,11 +104,11 @@
The alert_handler scoreboard is parameterized to support different number of classes, alert pairs, and escalation pairs.
#### Assertions
-* TLUL assertions: The `tb/alert_handler_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance.
+* TLUL assertions: The `tb/alert_handler_bind.sv` binds the `tlul_assert` [assertions](../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance.
* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
## Building and running tests
-We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions.
+We are using our in-house developed [regression tool](../../../../util/dvsim/README.md) for building and running our tests and regressions.
Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
Here's how to run a smoke test:
```console
diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/README.md b/hw/top_earlgrey/ip_autogen/rv_plic/README.md
index 9abbbf0..d642009 100644
--- a/hw/top_earlgrey/ip_autogen/rv_plic/README.md
+++ b/hw/top_earlgrey/ip_autogen/rv_plic/README.md
@@ -4,7 +4,7 @@
This document specifies the Interrupt Controller (RV_PLIC) functionality. This
module conforms to the
-[Comportable guideline for peripheral functionality](../../../../doc/contributing/hw/comportability/README.md).
+[Comportable guideline for peripheral functionality](../../../doc/contributing/hw/comportability/README.md).
See that document for integration overview within the broader top level system.
@@ -33,7 +33,7 @@
## Hardware Interfaces
-* [Interface Tables](data/rv_plic.hjson#interfaces)
+* [Interface Tables](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#interfaces)
## Design Details
@@ -50,7 +50,7 @@
Interrupt sources have configurable priority values. The maximum value of the
priority is configurable through the localparam `MAX_PRIO` in the rv_plic
-top-level module. For each target there is a threshold value ([`THRESHOLD0`](data/rv_plic.hjson#threshold0) for
+top-level module. For each target there is a threshold value ([`THRESHOLD0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#threshold0) for
target 0). RV_PLIC notifies a target of an interrupt only if it's priority is
strictly greater than the target's threshold. Note this means an interrupt with
a priority is 0 is effectively prevented from causing an interrupt at any target
@@ -70,25 +70,25 @@
The choice is a system-integration decision and can be configured via the design parameter `LevelEdgeTrig` for each interrupt request.
When the gateway detects an interrupt event it raises the interrupt pending bit
-([`IP`](data/rv_plic.hjson#ip)) for that interrupt source. When an interrupt is claimed by a target the
-relevant bit of [`IP`](data/rv_plic.hjson#ip) is cleared. A bit in [`IP`](data/rv_plic.hjson#ip) will not be reasserted until the
+([`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip)) for that interrupt source. When an interrupt is claimed by a target the
+relevant bit of [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) is cleared. A bit in [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) will not be reasserted until the
target signals completion of the interrupt. Any new interrupt event between a
-bit in [`IP`](data/rv_plic.hjson#ip) asserting and completing that interrupt is ignored. In particular
+bit in [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) asserting and completing that interrupt is ignored. In particular
this means that for edge triggered interrupts if a new edge is seen after the
-source's [`IP`](data/rv_plic.hjson#ip) bit is asserted but before completion, that edge will be ignored
+source's [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip) bit is asserted but before completion, that edge will be ignored
(counting missed edges as discussed in the RISC-V PLIC specification is not
supported).
Note that there is no ability for a level triggered interrupt to be cancelled.
-If the interrupt drops after the gateway has set a bit in [`IP`](data/rv_plic.hjson#ip), the bit will
+If the interrupt drops after the gateway has set a bit in [`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip), the bit will
remain set until the interrupt is completed. The SW handler should be conscious
of this and check the interrupt still requires handling in the handler if this
behaviour is possible.
### Interrupt Enables
-Each target has a set of Interrupt Enable ([`IE0`](data/rv_plic.hjson#ie0) for target 0) registers. Each
-bit in the [`IE0`](data/rv_plic.hjson#ie0) registers controls the corresponding interrupt source. If an
+Each target has a set of Interrupt Enable ([`IE0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ie0) for target 0) registers. Each
+bit in the [`IE0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ie0) registers controls the corresponding interrupt source. If an
interrupt source is disabled for a target, then interrupt events from that
source won't trigger an interrupt at the target. RV_PLIC doesn't have a global
interrupt disable feature.
@@ -96,23 +96,23 @@
### Interrupt Claims
"Claiming" an interrupt is done by a target reading the associated
-Claim/Completion register for the target ([`CC0`](data/rv_plic.hjson#cc0) for target 0). The return value
-of the [`CC0`](data/rv_plic.hjson#cc0) read represents the ID of the pending interrupt that has the
+Claim/Completion register for the target ([`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) for target 0). The return value
+of the [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) read represents the ID of the pending interrupt that has the
highest priority. If two or more pending interrupts have the same priority,
RV_PLIC chooses the one with lowest ID. Only interrupts that that are enabled
for the target can be claimed. The target priority threshold doesn't matter
(this only factors into whether an interrupt is signalled to the target) so
-lower priority interrupt IDs can be returned on a read from [`CC0`](data/rv_plic.hjson#cc0). If no
+lower priority interrupt IDs can be returned on a read from [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0). If no
interrupt is pending (or all pending interrupts are disabled for the target) a
-read of [`CC0`](data/rv_plic.hjson#cc0) returns an ID of 0.
+read of [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) returns an ID of 0.
### Interrupt Completion
-After an interrupt is claimed, the relevant bit of interrupt pending ([`IP`](data/rv_plic.hjson#ip)) is
+After an interrupt is claimed, the relevant bit of interrupt pending ([`IP`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#ip)) is
cleared, regardless of the status of the `intr_src_i` input value. Until a
target "completes" the interrupt, it won't be re-asserted if a new event for the
interrupt occurs. A target completes the interrupt by writing the ID of the
-interrupt to the Claim/Complete register ([`CC0`](data/rv_plic.hjson#cc0) for target 0). The write event
+interrupt to the Claim/Complete register ([`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) for target 0). The write event
is forwarded to the Gateway logic, which resets the interrupt status to accept a
new interrupt event. The assumption is that the processor has cleaned up the
originating interrupt event during the time between claim and complete such that
@@ -153,7 +153,7 @@
interrupt sources are set, as all priorities and thresholds are 0 by default and
all ``IE`` values are 0. Software should configure the above three registers.
-[`PRIO0`](data/rv_plic.hjson#prio0) .. [`PRIO31`](data/rv_plic.hjson#prio1) registers are unique. So, only one of the targets
+[`PRIO0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#prio0) .. [`PRIO31`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#prio1) registers are unique. So, only one of the targets
shall configure them.
```c
@@ -181,14 +181,14 @@
## Handling Interrupt Request Events
If software receives an interrupt request, it is recommended to follow the steps
-shown below (assuming target 0 which uses [`CC0`](data/rv_plic.hjson#cc0) for claim/complete).
+shown below (assuming target 0 which uses [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) for claim/complete).
1. Claim the interrupts right after entering to the interrupt service routine
- by reading the [`CC0`](data/rv_plic.hjson#cc0) register.
+ by reading the [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) register.
2. Determine which interrupt should be serviced based on the values read from
- the [`CC0`](data/rv_plic.hjson#cc0) register.
+ the [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0) register.
3. Execute ISR, clearing the originating peripheral interrupt.
-4. Write Interrupt ID to [`CC0`](data/rv_plic.hjson#cc0)
+4. Write Interrupt ID to [`CC0`](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#cc0)
5. Repeat as necessary for other pending interrupts.
It is possible to have multiple interrupt events claimed. If software claims one
@@ -244,4 +244,4 @@
- CC: N_TARGET
Claim by read, complete by write
-* [Register Table](data/rv_plic.hjson#registers)
+* [Register Table](../../top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson#interfaces)
diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/doc/checklist.md b/hw/top_earlgrey/ip_autogen/rv_plic/doc/checklist.md
index 0fe1557..2095ed8 100644
--- a/hw/top_earlgrey/ip_autogen/rv_plic/doc/checklist.md
+++ b/hw/top_earlgrey/ip_autogen/rv_plic/doc/checklist.md
@@ -1,7 +1,7 @@
# RV_PLIC Checklist
-This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [RV_PLIC peripheral](../README.md).
-All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md)
+This checklist is for [Hardware Stage](../../../../doc/project_governance/development_stages.md) transitions for the [RV_PLIC peripheral](../README.md).
+All checklist items refer to the content in the [Checklist.](../../../../doc/project_governance/checklist/README.md)
## Design Checklist
@@ -21,15 +21,15 @@
[RV_PLIC Spec]: ../README.md
-[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete
-[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined
-[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected
-[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top
-[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable
-[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80
-[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented
-[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added
-[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup
+[SPEC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#spec_complete
+[CSR_DEFINED]: ../../../../doc/project_governance/checklist/README.md#csr_defined
+[CLKRST_CONNECTED]: ../../../../doc/project_governance/checklist/README.md#clkrst_connected
+[IP_TOP]: ../../../../doc/project_governance/checklist/README.md#ip_top
+[IP_INSTANTIABLE]: ../../../../doc/project_governance/checklist/README.md#ip_instantiable
+[PHYSICAL_MACROS_DEFINED_80]: ../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80
+[FUNC_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#func_implemented
+[ASSERT_KNOWN_ADDED]: ../../../../doc/project_governance/checklist/README.md#assert_known_added
+[LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#lint_setup
### D2
@@ -53,23 +53,23 @@
Security | [SEC_CM_DOCUMENTED][] | N/A |
Security | [SEC_RND_CNST][] | N/A |
-[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features
-[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram
-[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface
-[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func
-[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen
-[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete
-[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check
-[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen
-[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen
-[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo
-[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x
-[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass
-[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup
-[FPGA_TIMING]: ../../../../../doc/project_governance/checklist/README.md#fpga_timing
-[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro
-[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented
-[SEC_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_rnd_cnst
+[NEW_FEATURES]: ../../../../doc/project_governance/checklist/README.md#new_features
+[BLOCK_DIAGRAM]: ../../../../doc/project_governance/checklist/README.md#block_diagram
+[DOC_INTERFACE]: ../../../../doc/project_governance/checklist/README.md#doc_interface
+[MISSING_FUNC]: ../../../../doc/project_governance/checklist/README.md#missing_func
+[FEATURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#feature_frozen
+[FEATURE_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#feature_complete
+[AREA_CHECK]: ../../../../doc/project_governance/checklist/README.md#area_check
+[PORT_FROZEN]: ../../../../doc/project_governance/checklist/README.md#port_frozen
+[ARCHITECTURE_FROZEN]: ../../../../doc/project_governance/checklist/README.md#architecture_frozen
+[REVIEW_TODO]: ../../../../doc/project_governance/checklist/README.md#review_todo
+[STYLE_X]: ../../../../doc/project_governance/checklist/README.md#style_x
+[LINT_PASS]: ../../../../doc/project_governance/checklist/README.md#lint_pass
+[CDC_SETUP]: ../../../../doc/project_governance/checklist/README.md#cdc_setup
+[FPGA_TIMING]: ../../../../doc/project_governance/checklist/README.md#fpga_timing
+[CDC_SYNCMACRO]: ../../../../doc/project_governance/checklist/README.md#cdc_syncmacro
+[SEC_CM_DOCUMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_documented
+[SEC_RND_CNST]: ../../../../doc/project_governance/checklist/README.md#sec_rnd_cnst
### D2S
@@ -83,13 +83,13 @@
Security | [SEC_CM_RTL_REVIEWED][] | N/A |
Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A | This block only contains the bus-integrity CM.
-[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed
-[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented
-[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst
-[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops
-[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs
-[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed
-[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed
+[SEC_CM_ASSETS_LISTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed
+[SEC_CM_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_implemented
+[SEC_CM_RND_CNST]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst
+[SEC_CM_NON_RESET_FLOPS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops
+[SEC_CM_SHADOW_REGS]: ../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs
+[SEC_CM_RTL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed
+[SEC_CM_COUNCIL_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed
### D3
@@ -107,15 +107,15 @@
Review | Reviewer(s) | Done | eunchan@ gac@ chencindy@ ttrippel@
Review | Signoff date | Done | 2022-07-25
-[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3
-[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete
-[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete
-[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete
-[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete
-[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl
-[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff
-[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change
-[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata
+[NEW_FEATURES_D3]: ../../../../doc/project_governance/checklist/README.md#new_features_d3
+[TODO_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#todo_complete
+[LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#lint_complete
+[CDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#cdc_complete
+[RDC_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#rdc_complete
+[REVIEW_RTL]: ../../../../doc/project_governance/checklist/README.md#review_rtl
+[REVIEW_DELETED_FF]: ../../../../doc/project_governance/checklist/README.md#review_deleted_ff
+[REVIEW_SW_CHANGE]: ../../../../doc/project_governance/checklist/README.md#review_sw_change
+[REVIEW_SW_ERRATA]: ../../../../doc/project_governance/checklist/README.md#review_sw_errata
## Verification Checklist
@@ -146,28 +146,28 @@
Review | [STD_TEST_CATEGORIES_PLANNED][] | N/A |
Review | [V2_CHECKLIST_SCOPED][] | Done |
-[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed
-[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed
-[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created
-[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added
-[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created
-[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated
-[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated
-[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated
-[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing
-[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing
-[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven
-[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup
-[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup
-[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup
-[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup
-[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added
-[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup
-[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1
-[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed
-[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed
-[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned
-[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped
+[DV_DOC_DRAFT_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed
+[TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#testplan_completed
+[TB_TOP_CREATED]: ../../../../doc/project_governance/checklist/README.md#tb_top_created
+[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added
+[SIM_TB_ENV_CREATED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_created
+[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated
+[CSR_CHECK_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated
+[TB_GEN_AUTOMATED]: ../../../../doc/project_governance/checklist/README.md#tb_gen_automated
+[SIM_SMOKE_TEST_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing
+[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing
+[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven
+[SIM_ALT_TOOL_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup
+[SIM_SMOKE_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup
+[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup
+[FPV_REGRESSION_SETUP]: ../../../../doc/project_governance/checklist/README.md#fpv_regression_setup
+[SIM_COVERAGE_MODEL_ADDED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added
+[TB_LINT_SETUP]: ../../../../doc/project_governance/checklist/README.md#tb_lint_setup
+[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1
+[DESIGN_SPEC_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#design_spec_reviewed
+[TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#testplan_reviewed
+[STD_TEST_CATEGORIES_PLANNED]: ../../../../doc/project_governance/checklist/README.md#std_test_categories_planned
+[V2_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped
### V2
@@ -194,26 +194,26 @@
Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started |
Review | [V3_CHECKLIST_SCOPED][] | Done |
-[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2
-[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed
-[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented
-[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised
-[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added
-[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed
-[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing
-[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written
-[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed
-[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated
-[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2
-[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2
-[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2
-[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2
-[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2
-[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2
-[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending
-[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused
-[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed
-[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped
+[DESIGN_DELTAS_CAPTURED_V2]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2
+[DV_DOC_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_completed
+[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented
+[ALL_INTERFACES_EXERCISED]: ../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised
+[ALL_ASSERTION_CHECKS_ADDED]: ../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added
+[SIM_TB_ENV_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed
+[SIM_ALL_TESTS_PASSING]: ../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing
+[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written
+[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed
+[SIM_FW_SIMULATED]: ../../../../doc/project_governance/checklist/README.md#sim_fw_simulated
+[SIM_NIGHTLY_REGRESSION_V2]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2
+[SIM_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2
+[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2
+[FPV_CODE_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2
+[FPV_COI_COVERAGE_V2]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2
+[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2
+[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending
+[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused
+[DV_DOC_TESTPLAN_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed
+[V3_CHECKLIST_SCOPED]: ../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped
### V2S
@@ -225,11 +225,11 @@
Coverage | [SIM_COVERAGE_REVIEWED][] | Not Started |
Review | [SEC_CM_DV_REVIEWED][] | Not Started |
-[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed
-[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified
-[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified
-[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed
-[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed
+[SEC_CM_TESTPLAN_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed
+[FPV_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified
+[SIM_SEC_CM_VERIFIED]: ../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified
+[SIM_COVERAGE_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed
+[SEC_CM_DV_REVIEWED]: ../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed
### V3
@@ -251,16 +251,16 @@
Review | Reviewer(s) | Not Started |
Review | Signoff date | Not Started |
-[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3
-[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed
-[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3
-[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3
-[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100
-[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100
-[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100
-[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100
-[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved
-[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown
-[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete
-[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3
-[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending
+[DESIGN_DELTAS_CAPTURED_V3]: ../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3
+[X_PROP_ANALYSIS_COMPLETED]: ../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed
+[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3
+[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3
+[SIM_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100
+[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100
+[FPV_CODE_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100
+[FPV_COI_COVERAGE_AT_100]: ../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100
+[ALL_TODOS_RESOLVED]: ../../../../doc/project_governance/checklist/README.md#all_todos_resolved
+[NO_TOOL_WARNINGS_THROWN]: ../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown
+[TB_LINT_COMPLETE]: ../../../../doc/project_governance/checklist/README.md#tb_lint_complete
+[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3
+[NO_ISSUES_PENDING]: ../../../../doc/project_governance/checklist/README.md#no_issues_pending
diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/doc/dv/README.md b/hw/top_earlgrey/ip_autogen/rv_plic/doc/dv/README.md
index 0abd4e2..b672493 100644
--- a/hw/top_earlgrey/ip_autogen/rv_plic/doc/dv/README.md
+++ b/hw/top_earlgrey/ip_autogen/rv_plic/doc/dv/README.md
@@ -10,8 +10,8 @@
* Verify TileLink device protocol compliance with a FPV based testbench
## Current status
-* [Design & verification stage](../../../../../README.md)
- * [HW development stages](../../../../../../doc/project_governance/development_stages.md)
+* [Design & verification stage](../../../../README.md)
+ * [HW development stages](../../../../../doc/project_governance/development_stages.md)
* FPV dashboard (link TBD)
## Design features
@@ -20,13 +20,13 @@
## Testbench architecture
RV_PLIC FPV testbench has been constructed based on the [formal
-architecture](../../../../../formal/README.md).
+architecture](../../../../formal/README.md).
### Block diagram
#### TLUL assertions
-* The file `rv_plic_bind.sv` binds the `tlul_assert` [assertions](../../../../../ip/tlul/doc/TlulProtocolChecker.md)
+* The file `rv_plic_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md)
to rv_plic to ensure TileLink interface protocol compliance.
* The `hw/rv_plic/fpv/tb/rv_plic_bind.sv` also binds the `rv_plic_csr_assert_fpv`
under `fpv/vip/` to check if TileLink writes and reads correct
@@ -42,7 +42,7 @@
declared two symbolic variables `src_sel` and `tgt_sel` to represent the index for
interrupt source and interrupt target.
Detailed explanation is listed in the
-[Symbolic Variables](../../../../../formal/README.md#symbolic-variables) section.
+[Symbolic Variables](../../../../formal/README.md#symbolic-variables) section.
## Testplan
-[Testplan](../../data/rv_plic_fpv_testplan.hjson)
+[Testplan](../data/rv_plic_fpv_testplan.hjson)
