[top] change prim_generic usage into prim - this ensures synthesis constraints can be properly applied Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/prim/rtl/prim_lc_sender.sv b/hw/ip/prim/rtl/prim_lc_sender.sv index d8e5a02..6502f83 100644 --- a/hw/ip/prim/rtl/prim_lc_sender.sv +++ b/hw/ip/prim/rtl/prim_lc_sender.sv
@@ -20,10 +20,10 @@ logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); - prim_generic_flop #( + prim_flop #( .Width(lc_ctrl_pkg::TxWidth), .ResetValue(lc_ctrl_pkg::TxWidth'(lc_ctrl_pkg::Off)) - ) u_prim_generic_flop ( + ) u_prim_flop ( .clk_i, .rst_ni, .d_i ( lc_en ),
diff --git a/hw/ip/prim/rtl/prim_multibit_sync.sv b/hw/ip/prim/rtl/prim_multibit_sync.sv index e9addde..79a3ab6 100644 --- a/hw/ip/prim/rtl/prim_multibit_sync.sv +++ b/hw/ip/prim/rtl/prim_multibit_sync.sv
@@ -59,10 +59,10 @@ logic [NumChecks:0][Width-1:0] data_check_d; logic [NumChecks-1:0][Width-1:0] data_check_q; - prim_generic_flop_2sync #( + prim_flop_2sync #( .Width(Width), .ResetValue(ResetValue) - ) i_prim_generic_flop_2sync ( + ) i_prim_flop_2sync ( .clk_i, .rst_ni, .d_i(data_i),
diff --git a/hw/ip/pwm/rtl/pwm_cdc.sv b/hw/ip/pwm/rtl/pwm_cdc.sv index ae1af4a..d288a1f 100644 --- a/hw/ip/pwm/rtl/pwm_cdc.sv +++ b/hw/ip/pwm/rtl/pwm_cdc.sv
@@ -29,7 +29,7 @@ reg [31:0] common_sync_q; - prim_generic_flop_2sync #( + prim_flop_2sync #( .Width(32), .ResetValue(32'h0) ) u_common_sync ( @@ -79,7 +79,7 @@ reg [83:0] chan_sync_q; - prim_generic_flop_2sync #( + prim_flop_2sync #( .Width(84), .ResetValue(84'h0) ) u_common_sync (
diff --git a/hw/ip/spi_host/rtl/spi_host.sv b/hw/ip/spi_host/rtl/spi_host.sv index 8769d05..e366ab6 100644 --- a/hw/ip/spi_host/rtl/spi_host.sv +++ b/hw/ip/spi_host/rtl/spi_host.sv
@@ -357,7 +357,7 @@ assign sw_rst = reg2hw.control.sw_rst.q; assign en_sw = reg2hw.control.spien.q; - prim_generic_flop_2sync #( + prim_flop_2sync #( .Width(3) ) u_sync_stat_from_core ( .clk_i, @@ -366,7 +366,7 @@ .q_o ({ rx_stall, tx_stall, active}) ); - prim_generic_flop_2sync #( + prim_flop_2sync #( .Width(2) ) u_sync_en_to_core ( .clk_i (clk_core_i),
diff --git a/hw/ip/usbdev/rtl/usbdev_iomux.sv b/hw/ip/usbdev/rtl/usbdev_iomux.sv index ca70d74..7c28140 100644 --- a/hw/ip/usbdev/rtl/usbdev_iomux.sv +++ b/hw/ip/usbdev/rtl/usbdev_iomux.sv
@@ -126,7 +126,7 @@ // D+/D- can be swapped based on a config register. assign pinflip = sys_reg2hw_config_i.pinflip.q; - prim_generic_clock_mux2 #( + prim_clock_mux2 #( .NoFpgaBufG(1) ) i_mux_tx_d_flip ( .clk0_i (usb_tx_d_i), @@ -134,7 +134,7 @@ .sel_i (pinflip), .clk_o (cio_usb_d_flipped) ); - prim_generic_clock_mux2 #( + prim_clock_mux2 #( .NoFpgaBufG(1) ) i_mux_dp_pull_flip ( .clk0_i (usb_pullup_en_i), @@ -142,7 +142,7 @@ .sel_i (pinflip), .clk_o (cio_usb_dp_pullup_en) ); - prim_generic_clock_mux2 #( + prim_clock_mux2 #( .NoFpgaBufG(1) ) i_mux_dn_pull_flip ( .clk0_i (1'b0), @@ -195,7 +195,7 @@ // Clock muxes should be used here to achieve the best match between // rising and falling edges on an ASIC. This mismatch on the data line // degrades performance in the JK-KJ jitter test. - prim_generic_clock_mux2 #( + prim_clock_mux2 #( .NoFpgaBufG(1) ) i_mux_tx_d ( .clk0_i (cio_usb_d_flipped), @@ -203,7 +203,7 @@ .sel_i (sys_reg2hw_drive_i.en.q), .clk_o (cio_usb_d_o) ); - prim_generic_clock_mux2 #( + prim_clock_mux2 #( .NoFpgaBufG(1) ) i_mux_tx_se0 ( .clk0_i (usb_tx_se0_i), @@ -211,7 +211,7 @@ .sel_i (sys_reg2hw_drive_i.en.q), .clk_o (cio_usb_se0_o) ); - prim_generic_clock_mux2 #( + prim_clock_mux2 #( .NoFpgaBufG(1) ) i_mux_tx_oe ( .clk0_i (usb_tx_oe_i),