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opensecura / 3p / lowrisc / opentitan / 611a642e691a94d5ccc0f6d7eafeb1358d536e2c / . / hw / top_earlgrey / data / autogen / top_earlgrey.gen.hjson
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// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
//
// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson \
// -o hw/top_earlgrey/ \
// --hjson-only \
// --rnd_cnst_seed 4881560218908238235
{
name: earlgrey
type: top
rnd_cnst_seed: 4881560218908238235
datawidth: "32"
power:
{
domains:
[
Aon
"0"
]
default: "0"
}
clocks:
{
hier_paths:
{
top: clkmgr_aon_clocks.
ext: ""
}
srcs:
[
{
name: main
aon: no
freq: "100000000"
derived: no
params: {}
}
{
name: io
aon: no
freq: "96000000"
derived: no
params: {}
}
{
name: usb
aon: no
freq: "48000000"
derived: no
params: {}
}
{
name: aon
aon: yes
freq: "200000"
derived: no
params: {}
}
]
derived_srcs:
[
{
name: io_div2
aon: no
div: 2
src: io
freq: "48000000"
}
{
name: io_div4
aon: no
div: 4
src: io
freq: "24000000"
}
]
groups:
[
{
name: powerup
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_powerup: io_div4
clk_aon_powerup: aon
clk_main_powerup: main
clk_io_powerup: io
clk_usb_powerup: usb
clk_io_div2_powerup: io_div2
}
}
{
name: trans
src: top
sw_cg: hint
unique: yes
clocks:
{
clk_main_aes: main
clk_main_hmac: main
clk_main_kmac: main
clk_main_otbn: main
}
}
{
name: infra
src: top
sw_cg: no
unique: no
clocks:
{
clk_main_infra: main
clk_io_div4_infra: io_div4
}
}
{
name: secure
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_secure: io_div4
clk_main_secure: main
}
}
{
name: peri
src: top
sw_cg: yes
unique: no
clocks:
{
clk_io_div4_peri: io_div4
clk_io_div2_peri: io_div2
clk_aon_peri: aon
clk_usb_peri: usb
}
}
{
name: timers
src: top
sw_cg: no
unique: no
clocks:
{
clk_io_div4_timers: io_div4
clk_main_timers: main
clk_aon_timers: aon
}
}
{
name: proc
src: no
sw_cg: no
unique: no
clocks:
{
clk_proc_main: main
}
}
]
}
resets:
{
hier_paths:
{
top: rstmgr_aon_resets.
ext: ""
}
nodes:
[
{
name: rst_ni
gen: false
type: ext
}
{
name: por_aon
gen: false
type: top
domains:
[
Aon
]
clk: aon
}
{
name: lc_src
gen: false
type: int
domains:
[
Aon
"0"
]
clk: io_div4
}
{
name: sys_src
gen: false
type: int
domains:
[
Aon
"0"
]
clk: io_div4
}
{
name: por
gen: true
type: top
domains:
[
Aon
]
parent: por_aon
clk: main
}
{
name: por_io
gen: true
type: top
domains:
[
Aon
]
parent: por_aon
clk: io
}
{
name: por_io_div2
gen: true
type: top
domains:
[
Aon
]
parent: por_aon
clk: io_div2
}
{
name: por_io_div4
gen: true
type: top
domains:
[
Aon
]
parent: por_aon
clk: io_div4
}
{
name: por_usb
gen: true
type: top
domains:
[
Aon
]
parent: por_aon
clk: usb
}
{
name: lc
gen: true
type: top
domains:
[
"0"
]
parent: lc_src
clk: main
}
{
name: lc_io_div4
gen: true
type: top
domains:
[
"0"
]
parent: lc_src
clk: io_div4
}
{
name: sys
gen: true
type: top
domains:
[
"0"
]
parent: sys_src
clk: main
}
{
name: sys_io_div4
gen: true
type: top
domains:
[
Aon
"0"
]
parent: sys_src
clk: io_div4
}
{
name: sys_aon
gen: true
type: top
domains:
[
Aon
"0"
]
parent: sys_src
clk: aon
}
{
name: spi_device
gen: true
type: top
domains:
[
"0"
]
parent: sys_src
clk: io_div2
sw: 1
}
{
name: spi_host0
gen: true
type: top
domains:
[
"0"
]
parent: sys_src
clk: io_div2
sw: 1
}
{
name: spi_host1
gen: true
type: top
domains:
[
"0"
]
parent: sys_src
clk: io_div2
sw: 1
}
{
name: usb
gen: true
type: top
domains:
[
"0"
]
parent: sys_src
clk: usb
sw: 1
}
{
name: i2c0
gen: true
type: top
domains:
[
"0"
]
parent: sys_src
clk: io_div2
sw: 1
}
{
name: i2c1
gen: true
type: top
domains:
[
"0"
]
parent: sys_src
clk: io_div2
sw: 1
}
{
name: i2c2
gen: true
type: top
domains:
[
"0"
]
parent: sys_src
clk: io_div2
sw: 1
}
]
}
num_cores: "1"
host:
[
{
name: rv_core_ibex
type: rv_core_ibex
inter_signal_list:
[
{
struct: esc_tx
type: uni
name: esc_nmi_tx
act: rcv
package: prim_esc_pkg
inst_name: rv_core_ibex
width: 1
default: ""
top_signame: alert_handler_esc_tx
index: 0
}
{
struct: esc_rx
type: uni
name: esc_nmi_rx
act: req
package: prim_esc_pkg
inst_name: rv_core_ibex
width: 1
default: ""
top_signame: alert_handler_esc_rx
index: 0
}
{
struct: crash_dump
type: uni
name: crash_dump
act: req
package: ibex_pkg
inst_name: rv_core_ibex
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: rv_core_ibex_crash_dump
index: -1
}
{
struct: lc_tx_t
type: uni
name: lc_cpu_en
act: rcv
package: lc_ctrl_pkg
inst_name: rv_core_ibex
width: 1
default: ""
top_signame: lc_ctrl_lc_cpu_en
index: -1
}
]
}
]
module:
[
{
name: uart0
type: uart
clock_srcs:
{
clk_i: io_div4
}
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40000000
clock_group: secure
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list:
[
{
name: rx
width: 1
type: input
}
]
available_output_list:
[
{
name: tx
width: 1
type: output
}
]
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: tx_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: tx_empty
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: rx_frame_err
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
{
name: rx_break_err
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
}
{
name: rx_timeout
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
}
{
name: rx_parity_err
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: uart0
width: 1
default: ""
end_idx: -1
top_signame: uart0_tl
index: -1
}
]
}
{
name: uart1
type: uart
clock_srcs:
{
clk_i: io_div4
}
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40010000
clock_group: secure
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list:
[
{
name: rx
width: 1
type: input
}
]
available_output_list:
[
{
name: tx
width: 1
type: output
}
]
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: tx_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: tx_empty
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: rx_frame_err
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
{
name: rx_break_err
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
}
{
name: rx_timeout
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
}
{
name: rx_parity_err
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: uart1
width: 1
default: ""
end_idx: -1
top_signame: uart1_tl
index: -1
}
]
}
{
name: uart2
type: uart
clock_srcs:
{
clk_i: io_div4
}
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40020000
clock_group: secure
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list:
[
{
name: rx
width: 1
type: input
}
]
available_output_list:
[
{
name: tx
width: 1
type: output
}
]
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: tx_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: tx_empty
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: rx_frame_err
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
{
name: rx_break_err
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
}
{
name: rx_timeout
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
}
{
name: rx_parity_err
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: uart2
width: 1
default: ""
end_idx: -1
top_signame: uart2_tl
index: -1
}
]
}
{
name: uart3
type: uart
clock_srcs:
{
clk_i: io_div4
}
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40030000
clock_group: secure
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list:
[
{
name: rx
width: 1
type: input
}
]
available_output_list:
[
{
name: tx
width: 1
type: output
}
]
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: tx_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: tx_empty
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: rx_frame_err
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
{
name: rx_break_err
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
}
{
name: rx_timeout
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
}
{
name: rx_parity_err
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: uart3
width: 1
default: ""
end_idx: -1
top_signame: uart3_tl
index: -1
}
]
}
{
name: gpio
type: gpio
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40040000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list:
[
{
name: gpio
width: 32
type: inout
}
]
param_list: []
interrupt_list:
[
{
name: gpio
width: 32
bits: 31:0
bitinfo:
[
4294967295
32
0
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: gpio
width: 1
default: ""
end_idx: -1
top_signame: gpio_tl
index: -1
}
]
}
{
name: spi_device
type: spi_device
clock_srcs:
{
clk_i: io_div4
scan_clk_i: io_div2
}
clock_group: peri
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40050000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
scan_clk_i: clkmgr_aon_clocks.clk_io_div2_peri
}
domain: "0"
size: 0x2000
bus_device: tlul
bus_host: none
available_input_list:
[
{
name: sck
width: 1
type: input
}
{
name: csb
width: 1
type: input
}
]
available_output_list: []
available_inout_list:
[
{
name: sd
width: 4
type: inout
}
]
param_list: []
interrupt_list:
[
{
name: rxf
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: rxlvl
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: txlvl
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: rxerr
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: rxoverflow
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
{
name: txunderflow
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "true"
scan_reset: "true"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: spi_device
width: 1
default: ""
end_idx: -1
top_signame: spi_device_tl
index: -1
}
]
}
{
name: spi_host0
type: spi_host
clock_srcs:
{
clk_i: io_div4
clk_core_i: io_div2
}
clock_group: peri
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]
rst_core_ni: rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40060000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
clk_core_i: clkmgr_aon_clocks.clk_io_div2_peri
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list:
[
{
name: sck
width: 1
type: output
}
{
name: csb
width: 1
type: output
}
]
available_inout_list:
[
{
name: sd
width: 4
type: inout
}
]
param_list: []
interrupt_list:
[
{
name: error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: spi_event
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: spi_host0
width: 1
default: ""
end_idx: -1
top_signame: spi_host0_tl
index: -1
}
]
}
{
name: spi_host1
type: spi_host
clock_srcs:
{
clk_i: io_div4
clk_core_i: io_div2
}
clock_group: peri
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]
rst_core_ni: rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40070000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
clk_core_i: clkmgr_aon_clocks.clk_io_div2_peri
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list:
[
{
name: sck
width: 1
type: output
}
{
name: csb
width: 1
type: output
}
]
available_inout_list:
[
{
name: sd
width: 4
type: inout
}
]
param_list: []
interrupt_list:
[
{
name: error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: spi_event
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: spi_host1
width: 1
default: ""
end_idx: -1
top_signame: spi_host1_tl
index: -1
}
]
}
{
name: i2c0
type: i2c
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40080000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list:
[
{
name: sda
width: 1
type: inout
}
{
name: scl
width: 1
type: inout
}
]
param_list: []
interrupt_list:
[
{
name: fmt_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: fmt_overflow
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: nak
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
{
name: scl_interference
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
}
{
name: sda_interference
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
}
{
name: stretch_timeout
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
}
{
name: sda_unstable
width: 1
bits: "8"
bitinfo:
[
256
1
8
]
type: interrupt
}
{
name: trans_complete
width: 1
bits: "9"
bitinfo:
[
512
1
9
]
type: interrupt
}
{
name: tx_empty
width: 1
bits: "10"
bitinfo:
[
1024
1
10
]
type: interrupt
}
{
name: tx_nonempty
width: 1
bits: "11"
bitinfo:
[
2048
1
11
]
type: interrupt
}
{
name: tx_overflow
width: 1
bits: "12"
bitinfo:
[
4096
1
12
]
type: interrupt
}
{
name: acq_overflow
width: 1
bits: "13"
bitinfo:
[
8192
1
13
]
type: interrupt
}
{
name: ack_stop
width: 1
bits: "14"
bitinfo:
[
16384
1
14
]
type: interrupt
}
{
name: host_timeout
width: 1
bits: "15"
bitinfo:
[
32768
1
15
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: i2c0
width: 1
default: ""
end_idx: -1
top_signame: i2c0_tl
index: -1
}
]
}
{
name: i2c1
type: i2c
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40090000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list:
[
{
name: sda
width: 1
type: inout
}
{
name: scl
width: 1
type: inout
}
]
param_list: []
interrupt_list:
[
{
name: fmt_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: fmt_overflow
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: nak
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
{
name: scl_interference
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
}
{
name: sda_interference
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
}
{
name: stretch_timeout
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
}
{
name: sda_unstable
width: 1
bits: "8"
bitinfo:
[
256
1
8
]
type: interrupt
}
{
name: trans_complete
width: 1
bits: "9"
bitinfo:
[
512
1
9
]
type: interrupt
}
{
name: tx_empty
width: 1
bits: "10"
bitinfo:
[
1024
1
10
]
type: interrupt
}
{
name: tx_nonempty
width: 1
bits: "11"
bitinfo:
[
2048
1
11
]
type: interrupt
}
{
name: tx_overflow
width: 1
bits: "12"
bitinfo:
[
4096
1
12
]
type: interrupt
}
{
name: acq_overflow
width: 1
bits: "13"
bitinfo:
[
8192
1
13
]
type: interrupt
}
{
name: ack_stop
width: 1
bits: "14"
bitinfo:
[
16384
1
14
]
type: interrupt
}
{
name: host_timeout
width: 1
bits: "15"
bitinfo:
[
32768
1
15
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: i2c1
width: 1
default: ""
end_idx: -1
top_signame: i2c1_tl
index: -1
}
]
}
{
name: i2c2
type: i2c
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x400A0000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list:
[
{
name: sda
width: 1
type: inout
}
{
name: scl
width: 1
type: inout
}
]
param_list: []
interrupt_list:
[
{
name: fmt_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: fmt_overflow
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: nak
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
{
name: scl_interference
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
}
{
name: sda_interference
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
}
{
name: stretch_timeout
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
}
{
name: sda_unstable
width: 1
bits: "8"
bitinfo:
[
256
1
8
]
type: interrupt
}
{
name: trans_complete
width: 1
bits: "9"
bitinfo:
[
512
1
9
]
type: interrupt
}
{
name: tx_empty
width: 1
bits: "10"
bitinfo:
[
1024
1
10
]
type: interrupt
}
{
name: tx_nonempty
width: 1
bits: "11"
bitinfo:
[
2048
1
11
]
type: interrupt
}
{
name: tx_overflow
width: 1
bits: "12"
bitinfo:
[
4096
1
12
]
type: interrupt
}
{
name: acq_overflow
width: 1
bits: "13"
bitinfo:
[
8192
1
13
]
type: interrupt
}
{
name: ack_stop
width: 1
bits: "14"
bitinfo:
[
16384
1
14
]
type: interrupt
}
{
name: host_timeout
width: 1
bits: "15"
bitinfo:
[
32768
1
15
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: i2c2
width: 1
default: ""
end_idx: -1
top_signame: i2c2_tl
index: -1
}
]
}
{
name: pattgen
type: pattgen
clock_srcs:
{
clk_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x400E0000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list:
[
{
name: pda0_tx
width: 1
type: output
}
{
name: pcl0_tx
width: 1
type: output
}
{
name: pda1_tx
width: 1
type: output
}
{
name: pcl1_tx
width: 1
type: output
}
]
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: done_ch0
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: done_ch1
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: pattgen
width: 1
default: ""
end_idx: -1
top_signame: pattgen_tl
index: -1
}
]
}
{
name: rv_timer
type: rv_timer
clock_srcs:
{
clk_i: io_div4
}
clock_group: timers
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40100000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_timers
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: timer_expired_0_0
width: 1
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: rv_timer
width: 1
default: ""
end_idx: -1
top_signame: rv_timer_tl
index: -1
}
]
}
{
name: usbdev
type: usbdev
clock_srcs:
{
clk_i: io_div4
clk_aon_i: aon
clk_usb_48mhz_i: usb
}
clock_group: peri
clock_reset_export:
[
ast
]
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
rst_aon_ni: rstmgr_aon_resets.rst_sys_aon_n[rstmgr_pkg::Domain0Sel]
rst_usb_48mhz_ni: rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40110000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
clk_aon_i: clkmgr_aon_clocks.clk_aon_peri
clk_usb_48mhz_i: clkmgr_aon_clocks.clk_usb_peri
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list:
[
{
name: sense
width: 1
type: input
}
]
available_output_list:
[
{
name: se0
width: 1
type: output
}
{
name: dp_pullup
width: 1
type: output
}
{
name: dn_pullup
width: 1
type: output
}
{
name: tx_mode_se
width: 1
type: output
}
{
name: suspend
width: 1
type: output
}
]
available_inout_list:
[
{
name: d
width: 1
type: inout
}
{
name: dp
width: 1
type: inout
}
{
name: dn
width: 1
type: inout
}
]
param_list: []
interrupt_list:
[
{
name: pkt_received
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: pkt_sent
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: disconnected
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: host_lost
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: link_reset
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
{
name: link_suspend
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
}
{
name: link_resume
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
}
{
name: av_empty
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
}
{
name: rx_full
width: 1
bits: "8"
bitinfo:
[
256
1
8
]
type: interrupt
}
{
name: av_overflow
width: 1
bits: "9"
bitinfo:
[
512
1
9
]
type: interrupt
}
{
name: link_in_err
width: 1
bits: "10"
bitinfo:
[
1024
1
10
]
type: interrupt
}
{
name: rx_crc_err
width: 1
bits: "11"
bitinfo:
[
2048
1
11
]
type: interrupt
}
{
name: rx_pid_err
width: 1
bits: "12"
bitinfo:
[
4096
1
12
]
type: interrupt
}
{
name: rx_bitstuff_err
width: 1
bits: "13"
bitinfo:
[
8192
1
13
]
type: interrupt
}
{
name: frame
width: 1
bits: "14"
bitinfo:
[
16384
1
14
]
type: interrupt
}
{
name: connected
width: 1
bits: "15"
bitinfo:
[
32768
1
15
]
type: interrupt
}
{
name: link_out_err
width: 1
bits: "16"
bitinfo:
[
65536
1
16
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
name: usb_ref_val
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
external: true
top_signame: usbdev_usb_ref_val
index: -1
}
{
name: usb_ref_pulse
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
external: true
top_signame: usbdev_usb_ref_pulse
index: -1
}
{
name: usb_out_of_rst
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_out_of_rst
index: -1
}
{
name: usb_aon_wake_en
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_wake_en
index: -1
}
{
name: usb_aon_wake_ack
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_wake_ack
index: -1
}
{
name: usb_suspend
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_suspend
index: -1
}
{
name: usb_state_debug
type: uni
act: rcv
package: usbdev_pkg
struct: awk_state
inst_name: usbdev
width: 1
default: ""
top_signame: pinmux_aon_usb_state_debug
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: usbdev
width: 1
default: ""
end_idx: -1
top_signame: usbdev_tl
index: -1
}
]
}
{
name: otp_ctrl
type: otp_ctrl
clock_srcs:
{
clk_i: io_div4
clk_edn_i: main
}
clock_group: timers
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40130000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_timers
clk_edn_i: clkmgr_aon_clocks.clk_main_timers
}
domain: "0"
size: 0x4000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: MemInitFile
desc: VMEM file to initialize the OTP macro.
type: ""
default: '''""'''
expose: "true"
name_top: OtpCtrlMemInitFile
}
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: otp_ctrl_pkg::lfsr_seed_t
randcount: 40
randtype: data
name_top: RndCnstOtpCtrlLfsrSeed
default: 0xf45def7861
randwidth: 40
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: otp_ctrl_pkg::lfsr_perm_t
randcount: 40
randtype: perm
name_top: RndCnstOtpCtrlLfsrPerm
default: 0x5d294061e29a7c404f4593035a19097666e37072064153623855022d39e0
randwidth: 240
}
]
interrupt_list:
[
{
name: otp_operation_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: otp_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
]
alert_list:
[
{
name: fatal_macro_error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 0
}
{
name: fatal_check_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 0
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: otp_ast_req
type: uni
name: otp_ast_pwr_seq
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
external: true
top_signame: otp_ctrl_otp_ast_pwr_seq
index: -1
}
{
struct: otp_ast_rsp
type: uni
name: otp_ast_pwr_seq_h
act: rcv
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
external: true
top_signame: otp_ctrl_otp_ast_pwr_seq_h
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: req
package: edn_pkg
inst_name: otp_ctrl
width: 1
default: ""
top_signame: edn0_edn
index: 1
}
{
struct: pwr_otp
type: req_rsp
name: pwr_otp
act: rsp
default: "'0"
package: pwrmgr_pkg
inst_name: otp_ctrl
width: 1
top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
struct: lc_otp_program
type: req_rsp
name: lc_otp_program
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_otp_program
index: -1
}
{
struct: lc_otp_token
type: req_rsp
name: lc_otp_token
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_otp_token
index: -1
}
{
struct: otp_lc_data
type: uni
name: otp_lc_data
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_lc_data
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_creator_seed_sw_rw_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_seed_hw_rd_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_dft_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_check_byp_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
struct: otp_keymgr_key
type: uni
name: otp_keymgr_key
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_keymgr_key
index: -1
}
{
struct: flash_otp_key
type: req_rsp
name: flash_otp_key
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: flash_ctrl_otp
index: -1
}
{
struct: sram_otp_key
width: 2
type: req_rsp
name: sram_otp_key
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
end_idx: -1
top_type: one-to-N
top_signame: otp_ctrl_sram_otp_key
index: -1
}
{
struct: otbn_otp_key
type: req_rsp
name: otbn_otp_key
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: req
default: "'0"
package: otp_ctrl_part_pkg
inst_name: otp_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: otp_ctrl
width: 1
default: ""
end_idx: -1
top_signame: otp_ctrl_tl
index: -1
}
]
}
{
name: lc_ctrl
type: lc_ctrl
clock_srcs:
{
clk_i: io_div4
}
clock_group: timers
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40140000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_timers
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: RndCnstLcKeymgrDivInvalid
desc: Compile-time random bits for lc state group diversification value
type: lc_ctrl_pkg::lc_keymgr_div_t
randcount: 64
randtype: data
name_top: RndCnstLcCtrlLcKeymgrDivInvalid
default: 0xf4c3471c5def7861
randwidth: 64
}
{
name: RndCnstLcKeymgrDivTestDevRma
desc: Compile-time random bits for lc state group diversification value
type: lc_ctrl_pkg::lc_keymgr_div_t
randcount: 64
randtype: data
name_top: RndCnstLcCtrlLcKeymgrDivTestDevRma
default: 0x83d0550b80e84eb1
randwidth: 64
}
{
name: RndCnstLcKeymgrDivProduction
desc: Compile-time random bits for lc state group diversification value
type: lc_ctrl_pkg::lc_keymgr_div_t
randcount: 64
randtype: data
name_top: RndCnstLcCtrlLcKeymgrDivProduction
default: 0x2d73930d4cac3785
randwidth: 64
}
]
interrupt_list: []
alert_list:
[
{
name: fatal_prog_error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 0
}
{
name: fatal_state_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 0
}
]
wakeup_list: []
reset_request_list: []
scan: "true"
scan_reset: "false"
inter_signal_list:
[
{
struct: jtag
type: req_rsp
name: jtag
act: rsp
package: jtag_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: pinmux_aon_lc_jtag
index: -1
}
{
struct: esc_tx
type: uni
name: esc_wipe_secrets_tx
act: rcv
package: prim_esc_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: alert_handler_esc_tx
index: 1
}
{
struct: esc_rx
type: uni
name: esc_wipe_secrets_rx
act: req
package: prim_esc_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: alert_handler_esc_rx
index: 1
}
{
struct: esc_tx
type: uni
name: esc_scrap_state_tx
act: rcv
package: prim_esc_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: alert_handler_esc_tx
index: 2
}
{
struct: esc_rx
type: uni
name: esc_scrap_state_rx
act: req
package: prim_esc_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: alert_handler_esc_rx
index: 2
}
{
struct: pwr_lc
type: req_rsp
name: pwr_lc
act: rsp
package: pwrmgr_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
struct: otp_lc_data
type: uni
name: otp_lc_data
act: rcv
default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT
package: otp_ctrl_pkg
inst_name: lc_ctrl
width: 1
top_signame: otp_ctrl_otp_lc_data
index: -1
}
{
struct: lc_otp_program
type: req_rsp
name: lc_otp_program
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_signame: lc_ctrl_lc_otp_program
index: -1
}
{
struct: lc_otp_token
type: req_rsp
name: lc_otp_token
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_signame: lc_ctrl_lc_otp_token
index: -1
}
{
struct: lc_tx
type: uni
name: lc_dft_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_nvm_debug_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_nvm_debug_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_cpu_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_cpu_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_keymgr_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_keymgr_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_clk_byp_req
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
external: true
top_signame: lc_clk_byp_req
index: -1
}
{
struct: lc_tx
type: uni
name: lc_clk_byp_ack
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_clk_byp_ack
index: -1
}
{
struct: lc_tx
type: uni
name: lc_flash_rma_req
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
top_signame: flash_ctrl_rma_req
index: -1
}
{
struct: lc_flash_rma_seed
type: uni
name: lc_flash_rma_seed
act: req
default: "'0"
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
top_signame: flash_ctrl_rma_seed
index: -1
}
{
struct: lc_tx
type: uni
name: lc_flash_rma_ack
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
top_signame: flash_ctrl_rma_ack
index: -1
}
{
struct: lc_tx
type: uni
name: lc_check_byp_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_creator_seed_sw_rw_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_owner_seed_sw_rw_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_iso_part_sw_rd_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_iso_part_sw_rd_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_iso_part_sw_wr_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_iso_part_sw_wr_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_seed_hw_rd_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
struct: lc_keymgr_div
type: uni
name: lc_keymgr_div
act: req
default: "'0"
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_keymgr_div
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: rcv
default: "'0"
package: otp_ctrl_part_pkg
inst_name: lc_ctrl
width: 1
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: lc_ctrl
width: 1
default: ""
end_idx: -1
top_signame: lc_ctrl_tl
index: -1
}
]
}
{
name: alert_handler
type: alert_handler
clock_srcs:
{
clk_i: io_div4
clk_edn_i: main
}
clock_group: timers
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40150000
attr: templated
localparam:
{
EscCntDw: 32
AccuCntDw: 16
LfsrSeed: 0x7FFFFFFF
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_timers
clk_edn_i: clkmgr_aon_clocks.clk_main_timers
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: alert_pkg::lfsr_seed_t
randcount: 32
randtype: data
name_top: RndCnstAlertHandlerLfsrSeed
default: 0x5def7861
randwidth: 32
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: alert_pkg::lfsr_perm_t
randcount: 32
randtype: perm
name_top: RndCnstAlertHandlerLfsrPerm
default: 0x5f00c4cafd73fc4ac479a61068375f38956d84b3
randwidth: 160
}
]
interrupt_list:
[
{
name: classa
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: classb
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: classc
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: classd
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: alert_crashdump
type: uni
name: crashdump
act: req
package: alert_pkg
inst_name: alert_handler
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: alert_handler_crashdump
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: req
width: 1
package: edn_pkg
inst_name: alert_handler
default: ""
top_signame: edn1_edn
index: 0
}
{
struct: esc_rx
type: uni
name: esc_rx
act: rcv
width: 4
package: prim_esc_pkg
inst_name: alert_handler
default: ""
end_idx: -1
top_type: one-to-N
top_signame: alert_handler_esc_rx
index: -1
}
{
struct: esc_tx
type: uni
name: esc_tx
act: req
width: 4
package: prim_esc_pkg
inst_name: alert_handler
default: ""
end_idx: -1
top_type: one-to-N
top_signame: alert_handler_esc_tx
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: alert_handler
width: 1
default: ""
end_idx: -1
top_signame: alert_handler_tl
index: -1
}
]
}
{
name: pwrmgr_aon
type: pwrmgr
clock_srcs:
{
clk_i: io_div4
clk_slow_i: aon
}
clock_group: powerup
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]
rst_slow_ni: rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
base_addr: 0x40400000
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
clk_slow_i: clkmgr_aon_clocks.clk_aon_powerup
}
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: wakeup
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: pwr_ast
type: req_rsp
name: pwr_ast
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
external: true
top_signame: pwrmgr_ast
index: -1
}
{
struct: pwr_rst
type: req_rsp
name: pwr_rst
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
struct: pwr_clk
type: req_rsp
name: pwr_clk
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
struct: pwr_otp
type: req_rsp
name: pwr_otp
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
struct: pwr_lc
type: req_rsp
name: pwr_lc
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
struct: pwr_flash
type: req_rsp
name: pwr_flash
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
struct: esc_tx
type: uni
name: esc_rst_tx
act: rcv
package: prim_esc_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
top_signame: alert_handler_esc_tx
index: 3
}
{
struct: esc_rx
type: uni
name: esc_rst_rx
act: req
package: prim_esc_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
top_signame: alert_handler_esc_rx
index: 3
}
{
struct: pwr_cpu
type: uni
name: pwr_cpu
act: rcv
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
top_signame: pwrmgr_aon_pwr_cpu
index: -1
}
{
struct: logic
width: 3
type: uni
name: wakeups
act: rcv
package: ""
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_type: one-to-N
top_signame: pwrmgr_aon_wakeups
index: -1
}
{
struct: logic
width: 1
type: uni
name: rstreqs
act: rcv
package: ""
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_rstreqs
index: -1
}
{
struct: logic
type: uni
name: strap
act: req
package: ""
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_strap
index: -1
}
{
struct: logic
type: uni
name: low_power
act: req
package: ""
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_low_power
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_tl
index: -1
}
]
}
{
name: rstmgr_aon
type: rstmgr
clock_srcs:
{
clk_i: io_div4
clk_aon_i: aon
clk_main_i: main
clk_io_i: io
clk_usb_i: usb
clk_io_div2_i: io_div2
clk_io_div4_i: io_div4
}
clock_group: powerup
reset_connections:
{
rst_ni: rst_ni
}
domain: Aon
base_addr: 0x40410000
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup
clk_main_i: clkmgr_aon_clocks.clk_main_powerup
clk_io_i: clkmgr_aon_clocks.clk_io_powerup
clk_usb_i: clkmgr_aon_clocks.clk_usb_powerup
clk_io_div2_i: clkmgr_aon_clocks.clk_io_div2_powerup
clk_io_div4_i: clkmgr_aon_clocks.clk_io_div4_powerup
}
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list: []
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "true"
scan_reset: "true"
inter_signal_list:
[
{
struct: pwr_rst
type: req_rsp
name: pwr
act: rsp
inst_name: rstmgr_aon
width: 1
default: ""
package: pwrmgr_pkg
top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
struct: rstmgr_out
type: uni
name: resets
act: req
package: rstmgr_pkg
inst_name: rstmgr_aon
width: 1
default: ""
top_signame: rstmgr_aon_resets
index: -1
}
{
struct: rstmgr_cpu
type: uni
name: cpu
act: rcv
package: rstmgr_pkg
inst_name: rstmgr_aon
width: 1
default: ""
top_signame: rstmgr_aon_cpu
index: -1
}
{
struct: alert_crashdump
type: uni
name: alert_dump
act: rcv
package: alert_pkg
inst_name: rstmgr_aon
width: 1
default: ""
top_signame: alert_handler_crashdump
index: -1
}
{
struct: crash_dump
type: uni
name: cpu_dump
act: rcv
package: ibex_pkg
inst_name: rstmgr_aon
width: 1
default: ""
top_signame: rv_core_ibex_crash_dump
index: -1
}
{
struct: rstmgr_ast_out
type: uni
name: resets_ast
act: req
package: rstmgr_pkg
inst_name: rstmgr_aon
width: 1
default: ""
external: true
top_signame: rsts_ast
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: rstmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: rstmgr_aon_tl
index: -1
}
]
}
{
name: clkmgr_aon
type: clkmgr
clock_srcs:
{
clk_i: io_div4
}
clock_group: powerup
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]
rst_main_ni: rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]
rst_io_ni: rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]
rst_usb_ni: rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel]
rst_io_div2_ni: rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]
rst_io_div4_ni: rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
base_addr: 0x40420000
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
}
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list: []
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "true"
scan_reset: "false"
inter_signal_list:
[
{
struct: clkmgr_out
type: uni
name: clocks
act: req
package: clkmgr_pkg
inst_name: clkmgr_aon
width: 1
default: ""
top_signame: clkmgr_aon_clocks
index: -1
}
{
struct: lc_tx
type: uni
name: ast_clk_bypass_ack
act: rcv
package: lc_ctrl_pkg
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: lc_clk_byp_ack
index: -1
}
{
struct: lc_tx
type: uni
name: lc_clk_bypass_ack
act: req
package: lc_ctrl_pkg
inst_name: clkmgr_aon
width: 1
default: ""
top_signame: lc_ctrl_lc_clk_byp_ack
index: -1
}
{
struct: logic
type: uni
name: jitter_en
act: req
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_main_jitter_en
index: -1
}
{
struct: logic
type: uni
name: clk_main
act: rcv
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_main
index: -1
}
{
struct: logic
type: uni
name: clk_io
act: rcv
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_io
index: -1
}
{
struct: logic
type: uni
name: clk_usb
act: rcv
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_usb
index: -1
}
{
struct: logic
type: uni
name: clk_aon
act: rcv
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_aon
index: -1
}
{
struct: clkmgr_ast_out
type: uni
name: clocks_ast
act: req
package: clkmgr_pkg
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clks_ast
index: -1
}
{
struct: pwr_clk
type: req_rsp
name: pwr
act: rsp
inst_name: clkmgr_aon
width: 1
default: ""
package: pwrmgr_pkg
top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
struct: logic
type: uni
name: idle
act: rcv
package: ""
width: 4
inst_name: clkmgr_aon
default: ""
end_idx: -1
top_type: one-to-N
top_signame: clkmgr_aon_idle
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: clkmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: clkmgr_aon_tl
index: -1
}
]
}
{
name: pinmux_aon
type: pinmux
clock_srcs:
{
clk_i: io_div4
clk_aon_i: aon
}
clock_group: powerup
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
rst_aon_ni: rstmgr_aon_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
base_addr: 0x40460000
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup
}
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list: []
alert_list: []
wakeup_list:
[
{
name: aon_wkup_req
width: "1"
}
{
name: usb_wkup_req
width: "1"
}
]
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: pinmux_aon
width: 1
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_dft_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: pinmux_aon
width: 1
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
struct: jtag
type: req_rsp
name: lc_jtag
act: req
package: jtag_pkg
inst_name: pinmux_aon
width: 1
default: ""
end_idx: -1
top_signame: pinmux_aon_lc_jtag
index: -1
}
{
struct: jtag
type: req_rsp
name: rv_jtag
act: req
package: jtag_pkg
inst_name: pinmux_aon
index: -1
}
{
struct: jtag
type: req_rsp
name: dft_jtag
act: req
package: jtag_pkg
inst_name: pinmux_aon
index: -1
}
{
struct: dft_strap_test
type: uni
name: dft_strap_test
act: req
package: pinmux_pkg
default: "'0"
inst_name: pinmux_aon
index: -1
}
{
struct: logic
type: uni
name: sleep_en
act: rcv
package: ""
default: 1'b0
inst_name: pinmux_aon
width: 1
top_signame: pwrmgr_aon_low_power
index: -1
}
{
struct: logic
type: uni
name: strap_en
act: rcv
package: ""
default: 1'b0
inst_name: pinmux_aon
width: 1
top_signame: pwrmgr_aon_strap
index: -1
}
{
struct: logic
type: uni
name: aon_wkup_req
act: req
package: ""
default: 1'b0
inst_name: pinmux_aon
width: 1
top_signame: pwrmgr_aon_wakeups
index: 0
}
{
struct: logic
type: uni
name: usb_wkup_req
act: req
package: ""
default: 1'b0
inst_name: pinmux_aon
width: 1
top_signame: pwrmgr_aon_wakeups
index: 1
}
{
name: usb_out_of_rst
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_out_of_rst
index: -1
}
{
name: usb_aon_wake_en
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_aon_wake_en
index: -1
}
{
name: usb_aon_wake_ack
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_aon_wake_ack
index: -1
}
{
name: usb_suspend
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_suspend
index: -1
}
{
name: usb_state_debug
type: uni
act: req
package: usbdev_pkg
struct: awk_state
inst_name: pinmux_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: pinmux_aon_usb_state_debug
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: pinmux_aon
width: 1
default: ""
end_idx: -1
top_signame: pinmux_aon_tl
index: -1
}
]
}
{
name: aon_timer_aon
type: aon_timer
clock_srcs:
{
clk_i: io_div4
clk_aon_i: aon
}
clock_group: timers
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
rst_aon_ni: rstmgr_aon_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
base_addr: 0x40470000
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_timers
clk_aon_i: clkmgr_aon_clocks.clk_aon_timers
}
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: wkup_timer_expired
width: 1
type: interrupt
}
{
name: wdog_timer_bark
width: 1
type: interrupt
}
]
alert_list: []
wakeup_list:
[
{
name: aon_timer_wkup_req
width: "1"
}
]
reset_request_list:
[
{
name: aon_timer_rst_req
}
]
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: logic
type: uni
name: aon_timer_wkup_req
act: req
package: ""
default: 1'b0
inst_name: aon_timer_aon
width: 1
top_signame: pwrmgr_aon_wakeups
index: 2
}
{
struct: logic
type: uni
name: aon_timer_rst_req
act: req
package: ""
default: 1'b0
inst_name: aon_timer_aon
width: 1
top_signame: pwrmgr_aon_rstreqs
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: aon_timer_aon
index: -1
}
{
name: sleep_mode
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: aon_timer_aon
default: ""
top_signame: pwrmgr_aon_low_power
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: aon_timer_aon
width: 1
default: ""
end_idx: -1
top_signame: aon_timer_aon_tl
index: -1
}
]
}
{
name: ast
type: ast
clock_srcs:
{
clk_i: io_div4
}
clock_group: secure
clock_reset_export:
[
ast
]
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40480000
attr: reggen_only
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list: []
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: ast
index: -1
}
]
}
{
name: sensor_ctrl_aon
type: sensor_ctrl
clock_srcs:
{
clk_i: io_div4
}
clock_group: secure
clock_reset_export:
[
ast
]
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
base_addr: 0x40490000
attr: reggen_top
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list: []
alert_list:
[
{
name: recov_as
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 0
}
{
name: recov_cg
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 0
}
{
name: recov_gd
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: alert
async: 0
}
{
name: recov_ts_hi
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: alert
async: 0
}
{
name: recov_ts_lo
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: alert
async: 0
}
{
name: recov_ls
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: alert
async: 0
}
{
name: recov_ot
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: alert
async: 0
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: ast_alert
type: req_rsp
name: ast_alert
act: rsp
package: ast_pkg
inst_name: sensor_ctrl_aon
width: 1
default: ""
external: true
top_signame: sensor_ctrl_ast_alert
index: -1
}
{
struct: ast_status
type: uni
name: ast_status
act: rcv
package: ast_pkg
inst_name: sensor_ctrl_aon
width: 1
default: ""
external: true
top_signame: sensor_ctrl_ast_status
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: sensor_ctrl_aon
width: 1
default: ""
end_idx: -1
top_signame: sensor_ctrl_aon_tl
index: -1
}
]
}
{
name: sram_ctrl_ret_aon
type: sram_ctrl
clock_srcs:
{
clk_i: io_div4
clk_otp_i: io_div4
}
clock_group: peri
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
rst_otp_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
base_addr: 0x40500000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_peri
}
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: RndCnstSramKey
desc: Compile-time random reset value for SRAM scrambling key.
type: otp_ctrl_pkg::sram_key_t
randcount: 128
randtype: data
name_top: RndCnstSramCtrlRetAonSramKey
default: 0x83d0550b80e84eb1f4c3471c5def7861
randwidth: 128
}
{
name: RndCnstSramNonce
desc: Compile-time random reset value for SRAM scrambling nonce.
type: otp_ctrl_pkg::sram_nonce_t
randcount: 64
randtype: data
name_top: RndCnstSramCtrlRetAonSramNonce
default: 0x2d73930d4cac3785
randwidth: 64
}
{
name: InstrExec
desc: Support execution from SRAM
type: bit
default: "1"
expose: "true"
name_top: SramCtrlRetAonInstrExec
}
]
interrupt_list: []
alert_list:
[
{
name: fatal_intg_error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 0
}
{
name: fatal_parity_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 0
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: sram_otp_key
type: req_rsp
name: sram_otp_key
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: sram_ctrl_ret_aon
width: 1
top_signame: otp_ctrl_sram_otp_key
index: 1
}
{
struct: sram_scr
type: req_rsp
name: sram_scr
act: req
default: "'0"
package: sram_ctrl_pkg
inst_name: sram_ctrl_ret_aon
width: 1
end_idx: -1
top_signame: sram_ctrl_ret_aon_sram_scr
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: sram_ctrl_ret_aon
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: sram_ctrl_ret_aon
width: 1
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: rcv
package: otp_ctrl_part_pkg
inst_name: sram_ctrl_ret_aon
width: 1
default: ""
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: tl_instr_en
type: uni
name: en_ifetch
act: req
package: tlul_pkg
inst_name: sram_ctrl_ret_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: sram_ctrl_ret_aon_en_ifetch
index: -1
}
{
struct: logic
type: uni
name: intg_error
act: rcv
package: ""
inst_name: sram_ctrl_ret_aon
width: 1
default: ""
top_signame: ram_ret_aon_intg_error
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: sram_ctrl_ret_aon
width: 1
default: ""
end_idx: -1
top_signame: sram_ctrl_ret_aon_tl
index: -1
}
]
}
{
name: flash_ctrl
type: flash_ctrl
clock_srcs:
{
clk_i: main
clk_otp_i: io_div4
}
clock_group: infra
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]
rst_otp_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41000000
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list:
[
{
name: tck
width: 1
type: input
}
{
name: tms
width: 1
type: input
}
{
name: tdi
width: 1
type: input
}
]
available_output_list:
[
{
name: tdo
width: 1
type: output
}
]
available_inout_list: []
param_list:
[
{
name: RndCnstAddrKey
desc: Compile-time random bits for default address key
type: flash_ctrl_pkg::flash_key_t
randcount: 128
randtype: data
name_top: RndCnstFlashCtrlAddrKey
default: 0x83d0550b80e84eb1f4c3471c5def7861
randwidth: 128
}
{
name: RndCnstDataKey
desc: Compile-time random bits for default data key
type: flash_ctrl_pkg::flash_key_t
randcount: 128
randtype: data
name_top: RndCnstFlashCtrlDataKey
default: 0xfabd19450b238d4c2d73930d4cac3785
randwidth: 128
}
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: flash_ctrl_pkg::lfsr_seed_t
randcount: 32
randtype: data
name_top: RndCnstFlashCtrlLfsrSeed
default: 0xd89f9dfc
randwidth: 32
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: flash_ctrl_pkg::lfsr_perm_t
randcount: 32
randtype: perm
name_top: RndCnstFlashCtrlLfsrPerm
default: 0x26ff203d990d87c5e8a98bafec7506855aa99c54
randwidth: 160
}
]
interrupt_list:
[
{
name: prog_empty
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: prog_lvl
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: rd_full
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: rd_lvl
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
{
name: op_done
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
}
]
alert_list:
[
{
name: recov_err
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
}
{
name: recov_mp_err
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
}
{
name: recov_ecc_err
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: alert
async: 1
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: flash
type: req_rsp
name: flash
act: req
package: flash_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_signame: flash_ctrl_flash
index: -1
}
{
struct: flash_otp_key
type: req_rsp
name: otp
act: req
package: otp_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_signame: flash_ctrl_otp
index: -1
}
{
struct: lc_tx
type: uni
name: lc_creator_seed_sw_rw_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_owner_seed_sw_rw_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_iso_part_sw_rd_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_iso_part_sw_rd_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_iso_part_sw_wr_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_iso_part_sw_wr_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_seed_hw_rd_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
struct: lc_tx
type: uni
name: rma_req
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_req
index: -1
}
{
struct: lc_tx
type: uni
name: rma_ack
act: req
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_ack
index: -1
}
{
struct: lc_flash_rma_seed
type: uni
name: rma_seed
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_seed
index: -1
}
{
struct: pwr_flash
type: req_rsp
name: pwrmgr
act: rsp
package: pwrmgr_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
struct: keymgr_flash
type: uni
name: keymgr
act: req
package: flash_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_keymgr
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_signame: flash_ctrl_tl
index: -1
}
]
}
{
name: rv_plic
type: rv_plic
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41010000
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list: []
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: rv_plic
width: 1
default: ""
end_idx: -1
top_signame: rv_plic_tl
index: -1
}
]
}
{
name: aes
type: aes
clock_srcs:
{
clk_i: main
clk_edn_i: main
}
clock_group: trans
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41100000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_aes
clk_edn_i: clkmgr_aon_clocks.clk_main_aes
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: AES192Enable
desc: Disable (0) or enable (1) support for 192-bit key lengths (AES-192).
type: bit
default: 1'b1
expose: "false"
name_top: AesAES192Enable
}
{
name: Masking
desc:
'''
Disable (0) or enable (1) first-order masking of the AES cipher core.
Masking requires the use of a masked S-Box, see SBoxImpl parameter.
'''
type: bit
default: 1'b1
expose: "true"
name_top: AesMasking
}
{
name: SBoxImpl
desc: Selection of the S-Box implementation. See aes_pkg.sv.
type: aes_pkg::sbox_impl_e
default: aes_pkg::SBoxImplDom
expose: "true"
name_top: AesSBoxImpl
}
{
name: SecStartTriggerDelay
desc:
'''
Manual start trigger delay, useful for SCA measurements.
A value of e.g. 40 allows the processor to go into sleep before AES starts operation.
'''
type: int unsigned
default: "0"
expose: "true"
name_top: SecAesStartTriggerDelay
}
{
name: SecAllowForcingMasks
desc:
'''
Forbid (0) or allow (1) forcing the mask to zero via FORCE_ZERO_MASK bit in the Control Register.
Useful for SCA measurements.
Meaningful only if masking is enabled.
'''
type: bit
default: 1'b0
expose: "true"
name_top: SecAesAllowForcingMasks
}
{
name: SecSkipPRNGReseeding
desc:
'''
Perform (0) or skip (1) PRNG reseeding requests, useful for SCA measurements only.
The current SCA setup doesn't provide sufficient resources to implement the infrastructure required for PRNG reseeding (CSRNG, EDN).
To enable SCA resistance evaluations, we need to skip reseeding requests on the SCA platform.
'''
type: bit
default: 1'b0
expose: "true"
name_top: SecAesSkipPRNGReseeding
}
{
name: AlertAsyncOn
desc: One bit per alert specifying whether the corresponding sender in the AES module and the receiver in the alert handler are in the same clock domain (0) or whether there is an asynchronous boundary in between (1).
type: logic [aes_reg_pkg::NumAlerts-1:0]
default: "{aes_reg_pkg::NumAlerts{1'b1}}"
expose: "false"
name_top: AesAlertAsyncOn
}
{
name: RndCnstClearingLfsrSeed
desc: Default seed of the PRNG used for register clearing.
type: aes_pkg::clearing_lfsr_seed_t
randcount: 64
randtype: data
name_top: RndCnstAesClearingLfsrSeed
default: 0xf4c3471c5def7861
randwidth: 64
}
{
name: RndCnstClearingLfsrPerm
desc: Permutation applied to the LFSR of the PRNG used for clearing.
type: aes_pkg::clearing_lfsr_perm_t
randcount: 64
randtype: perm
name_top: RndCnstAesClearingLfsrPerm
default: 0x26ac29e186c1f4dc6f959d6ed08dc044a0f3f1519e8dca131275df1e48bbf964ac772e613d0320adaebf38552dd822e6
randwidth: 384
}
{
name: RndCnstMaskingLfsrSeed
desc: Default seed of the PRNG used for masking.
type: aes_pkg::masking_lfsr_seed_t
randcount: 160
randtype: data
name_top: RndCnstAesMaskingLfsrSeed
default: 0x19e5a91389b9fe0d3b818e46ce7d846469a3b8e3
randwidth: 160
}
{
name: RndCnstMskgChunkLfsrPerm
desc: Permutation applied to the LFSR chunks of the PRNG used for masking.
type: aes_pkg::mskg_chunk_lfsr_perm_t
randcount: 32
randtype: perm
name_top: RndCnstAesMskgChunkLfsrPerm
default: 0x23f6ba7ea92aa0e8e3b900f826cee835bc1648fa
randwidth: 160
}
]
interrupt_list: []
alert_list:
[
{
name: recov_ctrl_update_err
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
}
{
name: fatal_fault
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
name: idle
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: aes
default: ""
top_signame: clkmgr_aon_idle
index: 0
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: aes
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: req
package: edn_pkg
inst_name: aes
width: 1
default: ""
top_signame: edn1_edn
index: 2
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: aes
width: 1
default: ""
end_idx: -1
top_signame: aes_tl
index: -1
}
]
}
{
name: hmac
type: hmac
clock_srcs:
{
clk_i: main
}
clock_group: trans
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41110000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_hmac
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: hmac_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: fifo_empty
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: hmac_err
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
name: idle
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: hmac
default: ""
top_signame: clkmgr_aon_idle
index: 1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: hmac
width: 1
default: ""
end_idx: -1
top_signame: hmac_tl
index: -1
}
]
}
{
name: kmac
type: kmac
clock_srcs:
{
clk_i: main
clk_edn_i: main
}
clock_group: trans
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41120000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_kmac
clk_edn_i: clkmgr_aon_clocks.clk_main_kmac
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: EnMasking
desc:
'''
Disable(0) or enable(1) first-order masking of Keccak round.
If masking is enabled, ReuseShare parameter will impact the design.
'''
type: bit
default: "0"
expose: "true"
name_top: KmacEnMasking
}
{
name: ReuseShare
desc:
'''
If enabled (1), the internal Keccak round logic will re-use the
adjacent shares as entropy in Domain-Oriented Masking AND logic.
It improves the throughput of Keccak, as it only requires small
amount of entropy rather than 1600 bit per round.
This feature is not implemented yet.
'''
type: int
default: "0"
expose: "true"
name_top: KmacReuseShare
}
]
interrupt_list:
[
{
name: kmac_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: fifo_empty
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: kmac_err
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
]
alert_list: []
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: hw_key_req
type: uni
name: keymgr_key
act: rcv
package: keymgr_pkg
inst_name: kmac
width: 1
default: ""
top_signame: keymgr_kmac_key
index: -1
}
{
struct: kmac_data
type: req_rsp
name: keymgr_kdf
act: rsp
package: keymgr_pkg
inst_name: kmac
width: 1
default: ""
top_signame: keymgr_kmac_data
index: -1
}
{
struct: edn
type: req_rsp
name: entropy
act: req
width: 1
package: edn_pkg
inst_name: kmac
default: ""
top_signame: edn0_edn
index: 3
}
{
name: idle
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: kmac
default: ""
top_signame: clkmgr_aon_idle
index: 2
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: kmac
width: 1
default: ""
end_idx: -1
top_signame: kmac_tl
index: -1
}
]
}
{
name: keymgr
type: keymgr
clock_srcs:
{
clk_i: main
clk_edn_i: main
}
clock_group: secure
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41130000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
clk_edn_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: RndCnstLfsrSeed
desc: Compile-time random bits for initial LFSR seed
type: keymgr_pkg::lfsr_seed_t
randcount: 64
randtype: data
name_top: RndCnstKeymgrLfsrSeed
default: 0xf4c3471c5def7861
randwidth: 64
}
{
name: RndCnstLfsrPerm
desc: Compile-time random permutation for LFSR output
type: keymgr_pkg::lfsr_perm_t
randcount: 64
randtype: perm
name_top: RndCnstKeymgrLfsrPerm
default: 0x26ac29e186c1f4dc6f959d6ed08dc044a0f3f1519e8dca131275df1e48bbf964ac772e613d0320adaebf38552dd822e6
randwidth: 384
}
{
name: RndCnstRandPerm
desc: Compile-time random permutation for entropy used in share overriding
type: keymgr_pkg::rand_perm_t
randcount: 32
randtype: perm
name_top: RndCnstKeymgrRandPerm
default: 0x86cb85d79423d404d9d717e683782c975a389f3a
randwidth: 160
}
{
name: RndCnstRevisionSeed
desc: Compile-time random bits for revision seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrRevisionSeed
default: 0xa917f063c414964e46ce0fe8ddb271067884ebcc4f232c841702ef7147e71b5c
randwidth: 256
}
{
name: RndCnstCreatorIdentitySeed
desc: Compile-time random bits for creator identity seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrCreatorIdentitySeed
default: 0x84b1a5a63af5fa0aaf8c6a6b90f868a3f2590e4a1004f9cf620d8c56137d9287
randwidth: 256
}
{
name: RndCnstOwnerIntIdentitySeed
desc: Compile-time random bits for owner intermediate identity seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrOwnerIntIdentitySeed
default: 0x32949cc3635d1f47c8f05affc85f7d889ecd94b67eb674bbdf38d62d3622493
randwidth: 256
}
{
name: RndCnstOwnerIdentitySeed
desc: Compile-time random bits for owner identity seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrOwnerIdentitySeed
default: 0xeec5e43d4b16446726a27b8f0b30ad5048bae844c87b69111a24d5e4442bcfb7
randwidth: 256
}
{
name: RndCnstSoftOutputSeed
desc: Compile-time random bits for software generation seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrSoftOutputSeed
default: 0xab174a27f3e9a7da096f534d1a07eb42a37dbfb7be9bb6e69a7d3c5f369ae283
randwidth: 256
}
{
name: RndCnstHardOutputSeed
desc: Compile-time random bits for hardware generation seed
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrHardOutputSeed
default: 0x8fefbc18548dfcb2fd145395d417df2f55255e182efed724cf8370466a266421
randwidth: 256
}
{
name: RndCnstAesSeed
desc: Compile-time random bits for generation seed when aes destination selected
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrAesSeed
default: 0xe390fce7275f3bce5145a3b8edb5f33fd64e96a5b7a45278102f4c28f70a5b08
randwidth: 256
}
{
name: RndCnstHmacSeed
desc: Compile-time random bits for generation seed when hmac destination selected
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrHmacSeed
default: 0x5f0e50f0c4cdf307b6cf85bd7669c05b0e5dbc9627c050e4936e54cc761467e
randwidth: 256
}
{
name: RndCnstKmacSeed
desc: Compile-time random bits for generation seed when kmac destination selected
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrKmacSeed
default: 0xc19175299f2746ea860d6c0dd7a42245f8e1d251d66cef31bce5f18f586239c4
randwidth: 256
}
{
name: RndCnstNoneSeed
desc: Compile-time random bits for generation seed when no destination selected
type: keymgr_pkg::seed_t
randcount: 256
randtype: data
name_top: RndCnstKeymgrNoneSeed
default: 0x350bb6b68440934dcb834f93689fe9e88ebd53404a1d7296f0cbdb8b82989aa7
randwidth: 256
}
]
interrupt_list:
[
{
name: op_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
]
alert_list:
[
{
name: fatal_fault_err
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
}
{
name: recov_operation_err
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: edn
type: req_rsp
name: edn
act: req
package: edn_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: edn0_edn
index: 0
}
{
struct: hw_key_req
type: uni
name: aes_key
act: req
package: keymgr_pkg
inst_name: keymgr
index: -1
}
{
struct: hw_key_req
type: uni
name: hmac_key
act: req
package: keymgr_pkg
inst_name: keymgr
index: -1
}
{
struct: hw_key_req
type: uni
name: kmac_key
act: req
package: keymgr_pkg
inst_name: keymgr
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: keymgr_kmac_key
index: -1
}
{
struct: kmac_data
type: req_rsp
name: kmac_data
act: req
package: keymgr_pkg
inst_name: keymgr
width: 1
default: ""
end_idx: -1
top_signame: keymgr_kmac_data
index: -1
}
{
struct: otp_keymgr_key
type: uni
name: otp_key
act: rcv
package: otp_ctrl_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: otp_ctrl_otp_keymgr_key
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: rcv
package: otp_ctrl_part_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: keymgr_flash
type: uni
name: flash
act: rcv
package: flash_ctrl_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: flash_ctrl_keymgr
index: -1
}
{
struct: lc_tx
type: uni
name: lc_keymgr_en
act: rcv
package: lc_ctrl_pkg
default: lc_ctrl_pkg::On
inst_name: keymgr
width: 1
top_signame: lc_ctrl_lc_keymgr_en
index: -1
}
{
struct: lc_keymgr_div
type: uni
name: lc_keymgr_div
act: rcv
package: lc_ctrl_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: lc_ctrl_lc_keymgr_div
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: keymgr
width: 1
default: ""
end_idx: -1
top_signame: keymgr_tl
index: -1
}
]
}
{
name: csrng
type: csrng
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41150000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: SBoxImpl
desc: Selection of the S-Box implementation. See aes_pkg.sv.
type: aes_pkg::sbox_impl_e
default: aes_pkg::SBoxImplCanright
expose: "true"
name_top: CsrngSBoxImpl
}
]
interrupt_list:
[
{
name: cs_cmd_req_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: cs_entropy_req
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: cs_hw_inst_exc
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
{
name: cs_fatal_err
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
}
]
alert_list:
[
{
name: fatal_alert
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: csrng
type: req_rsp
name: csrng_cmd
act: rsp
package: csrng_pkg
width: 2
inst_name: csrng
default: ""
end_idx: -1
top_type: one-to-N
top_signame: csrng_csrng_cmd
index: -1
}
{
struct: entropy_src_hw_if
type: req_rsp
name: entropy_src_hw_if
act: req
package: entropy_src_pkg
inst_name: csrng
width: 1
default: ""
end_idx: -1
top_signame: csrng_entropy_src_hw_if
index: -1
}
{
struct: logic
type: uni
name: efuse_sw_app_enable
act: rcv
width: 1
package: ""
inst_name: csrng
index: -1
}
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: csrng
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: csrng
width: 1
default: ""
end_idx: -1
top_signame: csrng_tl
index: -1
}
]
}
{
name: entropy_src
type: entropy_src
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
clock_reset_export:
[
ast
]
base_addr: 0x41160000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: es_entropy_valid
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: es_health_test_failed
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
{
name: es_fatal_err
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
}
]
alert_list:
[
{
name: recov_alert
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
}
{
name: fatal_alert
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: entropy_src_hw_if
type: req_rsp
name: entropy_src_hw_if
act: rsp
package: entropy_src_pkg
inst_name: entropy_src
width: 1
default: ""
top_signame: csrng_entropy_src_hw_if
index: -1
}
{
struct: entropy_src_rng
type: req_rsp
name: entropy_src_rng
act: req
package: entropy_src_pkg
inst_name: entropy_src
width: 1
default: ""
external: true
top_signame: es_rng
index: -1
}
{
struct: entropy_src_xht
type: req_rsp
name: entropy_src_xht
act: req
package: entropy_src_pkg
inst_name: entropy_src
index: -1
}
{
struct: logic
type: uni
name: efuse_es_sw_reg_en
act: rcv
width: 1
package: ""
inst_name: entropy_src
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: entropy_src
width: 1
default: ""
end_idx: -1
top_signame: entropy_src_tl
index: -1
}
]
}
{
name: edn0
type: edn
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
clock_reset_export:
[
ast
]
base_addr: 0x41170000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: edn_cmd_req_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: edn_fatal_err
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
]
alert_list:
[
{
name: fatal_alert
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: csrng
type: req_rsp
name: csrng_cmd
act: req
width: 1
package: csrng_pkg
desc: EDN supports a signal CSRNG application interface.
inst_name: edn0
default: ""
top_signame: csrng_csrng_cmd
index: 0
}
{
struct: edn
type: req_rsp
name: edn
act: rsp
width: 4
default: "'0"
desc:
'''
The collection of peripheral ports supported by edn. The width (4)
indicates the number of peripheral ports on a single instance.
Due to limitations in the parametrization of top-level interconnects
this value is not currently parameterizable. However, the number
of peripheral ports may change in a future revision.
'''
package: edn_pkg
inst_name: edn0
end_idx: -1
top_type: one-to-N
top_signame: edn0_edn
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: edn0
width: 1
default: ""
end_idx: -1
top_signame: edn0_tl
index: -1
}
]
}
{
name: edn1
type: edn
clock_srcs:
{
clk_i: main
}
clock_group: secure
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41180000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list: []
interrupt_list:
[
{
name: edn_cmd_req_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
{
name: edn_fatal_err
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
}
]
alert_list:
[
{
name: fatal_alert
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: csrng
type: req_rsp
name: csrng_cmd
act: req
width: 1
package: csrng_pkg
desc: EDN supports a signal CSRNG application interface.
inst_name: edn1
default: ""
top_signame: csrng_csrng_cmd
index: 1
}
{
struct: edn
type: req_rsp
name: edn
act: rsp
width: 4
default: "'0"
desc:
'''
The collection of peripheral ports supported by edn. The width (4)
indicates the number of peripheral ports on a single instance.
Due to limitations in the parametrization of top-level interconnects
this value is not currently parameterizable. However, the number
of peripheral ports may change in a future revision.
'''
package: edn_pkg
inst_name: edn1
end_idx: 3
top_type: partial-one-to-N
top_signame: edn1_edn
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: edn1
width: 1
default: ""
end_idx: -1
top_signame: edn1_tl
index: -1
}
]
}
{
name: sram_ctrl_main
type: sram_ctrl
clock_srcs:
{
clk_i: main
clk_otp_i: io_div4
}
clock_group: secure
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_otp_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x411C0000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: RndCnstSramKey
desc: Compile-time random reset value for SRAM scrambling key.
type: otp_ctrl_pkg::sram_key_t
randcount: 128
randtype: data
name_top: RndCnstSramCtrlMainSramKey
default: 0xb6d4b556d89f9dfcfabd19450b238d4c
randwidth: 128
}
{
name: RndCnstSramNonce
desc: Compile-time random reset value for SRAM scrambling nonce.
type: otp_ctrl_pkg::sram_nonce_t
randcount: 64
randtype: data
name_top: RndCnstSramCtrlMainSramNonce
default: 0x160733e752cad615
randwidth: 64
}
{
name: InstrExec
desc: Support execution from SRAM
type: bit
default: "1"
expose: "true"
name_top: SramCtrlMainInstrExec
}
]
interrupt_list: []
alert_list:
[
{
name: fatal_intg_error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
}
{
name: fatal_parity_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: sram_otp_key
type: req_rsp
name: sram_otp_key
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: sram_ctrl_main
width: 1
top_signame: otp_ctrl_sram_otp_key
index: 0
}
{
struct: sram_scr
type: req_rsp
name: sram_scr
act: req
default: "'0"
package: sram_ctrl_pkg
inst_name: sram_ctrl_main
width: 1
end_idx: -1
top_signame: sram_ctrl_main_sram_scr
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: sram_ctrl_main
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: sram_ctrl_main
width: 1
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: rcv
package: otp_ctrl_part_pkg
inst_name: sram_ctrl_main
width: 1
default: ""
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: tl_instr_en
type: uni
name: en_ifetch
act: req
package: tlul_pkg
inst_name: sram_ctrl_main
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: sram_ctrl_main_en_ifetch
index: -1
}
{
struct: logic
type: uni
name: intg_error
act: rcv
package: ""
inst_name: sram_ctrl_main
width: 1
default: ""
top_signame: ram_main_intg_error
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: sram_ctrl_main
width: 1
default: ""
end_idx: -1
top_signame: sram_ctrl_main_tl
index: -1
}
]
}
{
name: otbn
type: otbn
clock_srcs:
{
clk_i: main
clk_edn_i: main
}
clock_group: trans
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x411D0000
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_otbn
clk_edn_i: clkmgr_aon_clocks.clk_main_otbn
}
domain: "0"
size: 0x10000
bus_device: tlul
bus_host: none
available_input_list: []
available_output_list: []
available_inout_list: []
param_list:
[
{
name: RegFile
desc: Selection of the register file implementation. See otbn_pkg.sv.
type: otbn_pkg::regfile_e
default: otbn_pkg::RegFileFF
expose: "true"
name_top: OtbnRegFile
}
]
interrupt_list:
[
{
name: done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
}
]
alert_list:
[
{
name: fatal
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
}
{
name: recov
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
}
]
wakeup_list: []
reset_request_list: []
scan: "false"
scan_reset: "false"
inter_signal_list:
[
{
struct: edn
type: req_rsp
name: edn
act: req
package: edn_pkg
inst_name: otbn
width: 1
default: ""
top_signame: edn1_edn
index: 1
}
{
name: idle
type: uni
struct: logic
width: 1
act: req
inst_name: otbn
default: ""
package: ""
top_signame: clkmgr_aon_idle
index: 3
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: otbn
width: 1
default: ""
end_idx: -1
top_signame: otbn_tl
index: -1
}
]
}
]
memory:
[
{
name: rom
clock_srcs:
{
clk_i: main
}
clock_group: infra
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
type: rom
base_addr: 0x00008000
swaccess: ro
size: 0x4000
integ_width: 8
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: rom
width: 1
default: ""
end_idx: -1
top_signame: rom_tl
index: -1
}
]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
}
domain: "0"
}
{
name: ram_main
clock_srcs:
{
clk_i: main
}
clock_group: infra
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
type: ram_1p_scr
base_addr: 0x10000000
size: 0x20000
byte_write: "true"
integ_width: 7
exec: "1"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: ram_main
width: 1
default: ""
end_idx: -1
top_signame: ram_main_tl
index: -1
}
{
struct: sram_scr
package: sram_ctrl_pkg
type: req_rsp
name: sram_scr
act: rsp
inst_name: ram_main
width: 1
default: ""
top_signame: sram_ctrl_main_sram_scr
index: -1
}
{
struct: tl_instr_en
package: tlul_pkg
type: uni
name: en_ifetch
act: rcv
inst_name: ram_main
width: 1
default: ""
top_signame: sram_ctrl_main_en_ifetch
index: -1
}
{
struct: logic
package: ""
type: uni
name: intg_error
act: req
inst_name: ram_main
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ram_main_intg_error
index: -1
}
]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
}
domain: "0"
}
{
name: ram_ret_aon
clock_srcs:
{
clk_i: io_div4
}
clock_group: infra
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
type: ram_1p_scr
base_addr: 0x40600000
size: 0x1000
byte_write: "true"
integ_width: 7
exec: "0"
inter_signal_list:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: ram_ret_aon
width: 1
default: ""
end_idx: -1
top_signame: ram_ret_aon_tl
index: -1
}
{
struct: sram_scr
package: sram_ctrl_pkg
type: req_rsp
name: sram_scr
act: rsp
inst_name: ram_ret_aon
width: 1
default: ""
top_signame: sram_ctrl_ret_aon_sram_scr
index: -1
}
{
struct: tl_instr_en
package: tlul_pkg
type: uni
name: en_ifetch
act: rcv
inst_name: ram_ret_aon
width: 1
default: ""
top_signame: sram_ctrl_ret_aon_en_ifetch
index: -1
}
{
struct: logic
package: ""
type: uni
name: intg_error
act: req
inst_name: ram_ret_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ram_ret_aon_intg_error
index: -1
}
]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_infra
}
}
{
name: eflash
clock_srcs:
{
clk_i: main
}
clock_group: infra
reset_connections:
{
rst_ni: rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]
}
type: eflash
base_addr: 0x20000000
banks: 2
pages_per_bank: 256
program_resolution: 8
swaccess: ro
inter_signal_list:
[
{
struct: flash
type: req_rsp
name: flash_ctrl
act: rsp
inst_name: eflash
width: 1
default: ""
package: flash_ctrl_pkg
top_signame: flash_ctrl_flash
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: eflash
width: 1
default: ""
end_idx: -1
top_signame: eflash_tl
index: -1
}
{
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
name: lc_nvm_debug_en
inst_name: eflash
width: 1
default: ""
top_signame: lc_ctrl_lc_nvm_debug_en
index: -1
}
{
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
name: flash_bist_enable
inst_name: eflash
width: 1
default: ""
external: true
top_signame: flash_bist_enable
index: -1
}
{
struct: logic
package: ""
type: uni
act: rcv
name: flash_power_down_h
inst_name: eflash
width: 1
default: ""
external: true
top_signame: flash_power_down_h
index: -1
}
{
struct: logic
package: ""
type: uni
act: rcv
name: flash_power_ready_h
inst_name: eflash
width: 1
default: ""
external: true
top_signame: flash_power_ready_h
index: -1
}
{
struct: logic
package: ""
width: 4
type: uni
act: rcv
name: flash_test_mode_a
inst_name: eflash
default: ""
external: true
top_signame: flash_test_mode_a
index: -1
}
{
struct: logic
package: ""
type: uni
act: rcv
name: flash_test_voltage_h
inst_name: eflash
width: 1
default: ""
external: true
top_signame: flash_test_voltage_h
index: -1
}
]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
}
words_per_page: 256
data_width: 64
metadata_width: 12
info_types: 3
infos_per_bank:
[
10
1
2
]
size: 0x100000
pgm_resolution_bytes: 64
domain: "0"
}
]
port:
[
{
name: ast_edn
inter_signal_list:
[
{
struct: edn
type: req_rsp
name: edn
act: rsp
package: edn_pkg
inst_name: ast_edn
width: 1
default: ""
top_signame: edn0_edn
index: 2
external: true
}
]
}
]
inter_module:
{
connect:
{
alert_handler.crashdump:
[
rstmgr_aon.alert_dump
]
alert_handler.esc_rx:
[
rv_core_ibex.esc_nmi_rx
lc_ctrl.esc_wipe_secrets_rx
lc_ctrl.esc_scrap_state_rx
pwrmgr_aon.esc_rst_rx
]
alert_handler.esc_tx:
[
rv_core_ibex.esc_nmi_tx
lc_ctrl.esc_wipe_secrets_tx
lc_ctrl.esc_scrap_state_tx
pwrmgr_aon.esc_rst_tx
]
csrng.csrng_cmd:
[
edn0.csrng_cmd
edn1.csrng_cmd
]
csrng.entropy_src_hw_if:
[
entropy_src.entropy_src_hw_if
]
flash_ctrl.flash:
[
eflash.flash_ctrl
]
flash_ctrl.keymgr:
[
keymgr.flash
]
flash_ctrl.otp:
[
otp_ctrl.flash_otp_key
]
flash_ctrl.rma_req:
[
lc_ctrl.lc_flash_rma_req
]
flash_ctrl.rma_ack:
[
lc_ctrl.lc_flash_rma_ack
]
flash_ctrl.rma_seed:
[
lc_ctrl.lc_flash_rma_seed
]
sram_ctrl_main.sram_scr:
[
ram_main.sram_scr
]
sram_ctrl_ret_aon.sram_scr:
[
ram_ret_aon.sram_scr
]
sram_ctrl_main.en_ifetch:
[
ram_main.en_ifetch
]
sram_ctrl_ret_aon.en_ifetch:
[
ram_ret_aon.en_ifetch
]
ram_main.intg_error:
[
sram_ctrl_main.intg_error
]
ram_ret_aon.intg_error:
[
sram_ctrl_ret_aon.intg_error
]
otp_ctrl.sram_otp_key:
[
sram_ctrl_main.sram_otp_key
sram_ctrl_ret_aon.sram_otp_key
]
pwrmgr_aon.pwr_flash:
[
flash_ctrl.pwrmgr
]
pwrmgr_aon.pwr_rst:
[
rstmgr_aon.pwr
]
pwrmgr_aon.pwr_clk:
[
clkmgr_aon.pwr
]
pwrmgr_aon.pwr_otp:
[
otp_ctrl.pwr_otp
]
pwrmgr_aon.pwr_lc:
[
lc_ctrl.pwr_lc
]
pwrmgr_aon.strap:
[
pinmux_aon.strap_en
]
pwrmgr_aon.low_power:
[
pinmux_aon.sleep_en
aon_timer_aon.sleep_mode
]
rv_core_ibex.crash_dump:
[
rstmgr_aon.cpu_dump
]
usbdev.usb_out_of_rst:
[
pinmux_aon.usb_out_of_rst
]
usbdev.usb_aon_wake_en:
[
pinmux_aon.usb_aon_wake_en
]
usbdev.usb_aon_wake_ack:
[
pinmux_aon.usb_aon_wake_ack
]
usbdev.usb_suspend:
[
pinmux_aon.usb_suspend
]
pinmux_aon.usb_state_debug:
[
usbdev.usb_state_debug
]
edn0.edn:
[
keymgr.edn
otp_ctrl.edn
ast_edn.edn
kmac.entropy
]
edn1.edn:
[
alert_handler.edn
otbn.edn
aes.edn
]
otp_ctrl.otp_keymgr_key:
[
keymgr.otp_key
]
keymgr.kmac_key:
[
kmac.keymgr_key
]
keymgr.kmac_data:
[
kmac.keymgr_kdf
]
clkmgr_aon.idle:
[
aes.idle
hmac.idle
kmac.idle
otbn.idle
]
pinmux_aon.lc_jtag:
[
lc_ctrl.jtag
]
otp_ctrl.otp_lc_data:
[
lc_ctrl.otp_lc_data
]
lc_ctrl.lc_otp_program:
[
otp_ctrl.lc_otp_program
]
lc_ctrl.lc_otp_token:
[
otp_ctrl.lc_otp_token
]
otp_ctrl.otp_hw_cfg:
[
lc_ctrl.otp_hw_cfg
keymgr.otp_hw_cfg
sram_ctrl_main.otp_hw_cfg
sram_ctrl_ret_aon.otp_hw_cfg
]
lc_ctrl.lc_keymgr_div:
[
keymgr.lc_keymgr_div
]
lc_ctrl.lc_dft_en:
[
otp_ctrl.lc_dft_en
pinmux_aon.lc_dft_en
]
lc_ctrl.lc_nvm_debug_en:
[
eflash.lc_nvm_debug_en
]
lc_ctrl.lc_hw_debug_en:
[
sram_ctrl_main.lc_hw_debug_en
sram_ctrl_ret_aon.lc_hw_debug_en
pinmux_aon.lc_hw_debug_en
]
lc_ctrl.lc_cpu_en:
[
rv_core_ibex.lc_cpu_en
]
lc_ctrl.lc_keymgr_en:
[
keymgr.lc_keymgr_en
]
lc_ctrl.lc_escalate_en:
[
aes.lc_escalate_en
otp_ctrl.lc_escalate_en
sram_ctrl_main.lc_escalate_en
sram_ctrl_ret_aon.lc_escalate_en
]
lc_ctrl.lc_check_byp_en:
[
otp_ctrl.lc_check_byp_en
]
lc_ctrl.lc_clk_byp_ack:
[
clkmgr_aon.lc_clk_bypass_ack
]
lc_ctrl.lc_creator_seed_sw_rw_en:
[
otp_ctrl.lc_creator_seed_sw_rw_en
flash_ctrl.lc_creator_seed_sw_rw_en
]
lc_ctrl.lc_owner_seed_sw_rw_en:
[
flash_ctrl.lc_owner_seed_sw_rw_en
]
lc_ctrl.lc_iso_part_sw_rd_en:
[
flash_ctrl.lc_iso_part_sw_rd_en
]
lc_ctrl.lc_iso_part_sw_wr_en:
[
flash_ctrl.lc_iso_part_sw_wr_en
]
lc_ctrl.lc_seed_hw_rd_en:
[
otp_ctrl.lc_seed_hw_rd_en
flash_ctrl.lc_seed_hw_rd_en
]
pwrmgr_aon.wakeups:
[
pinmux_aon.aon_wkup_req
pinmux_aon.usb_wkup_req
aon_timer_aon.aon_timer_wkup_req
]
pwrmgr_aon.rstreqs:
[
aon_timer_aon.aon_timer_rst_req
]
rom.tl:
[
main.tl_rom
]
ram_main.tl:
[
main.tl_ram_main
]
eflash.tl:
[
main.tl_eflash
]
main.tl_peri:
[
peri.tl_main
]
flash_ctrl.tl:
[
main.tl_flash_ctrl
]
hmac.tl:
[
main.tl_hmac
]
kmac.tl:
[
main.tl_kmac
]
aes.tl:
[
main.tl_aes
]
entropy_src.tl:
[
main.tl_entropy_src
]
csrng.tl:
[
main.tl_csrng
]
edn0.tl:
[
main.tl_edn0
]
edn1.tl:
[
main.tl_edn1
]
rv_plic.tl:
[
main.tl_rv_plic
]
otbn.tl:
[
main.tl_otbn
]
keymgr.tl:
[
main.tl_keymgr
]
sram_ctrl_main.tl:
[
main.tl_sram_ctrl_main
]
uart0.tl:
[
peri.tl_uart0
]
uart1.tl:
[
peri.tl_uart1
]
uart2.tl:
[
peri.tl_uart2
]
uart3.tl:
[
peri.tl_uart3
]
i2c0.tl:
[
peri.tl_i2c0
]
i2c1.tl:
[
peri.tl_i2c1
]
i2c2.tl:
[
peri.tl_i2c2
]
pattgen.tl:
[
peri.tl_pattgen
]
gpio.tl:
[
peri.tl_gpio
]
spi_device.tl:
[
peri.tl_spi_device
]
spi_host0.tl:
[
peri.tl_spi_host0
]
spi_host1.tl:
[
peri.tl_spi_host1
]
rv_timer.tl:
[
peri.tl_rv_timer
]
usbdev.tl:
[
peri.tl_usbdev
]
pwrmgr_aon.tl:
[
peri.tl_pwrmgr_aon
]
rstmgr_aon.tl:
[
peri.tl_rstmgr_aon
]
clkmgr_aon.tl:
[
peri.tl_clkmgr_aon
]
pinmux_aon.tl:
[
peri.tl_pinmux_aon
]
ram_ret_aon.tl:
[
peri.tl_ram_ret_aon
]
otp_ctrl.tl:
[
peri.tl_otp_ctrl
]
lc_ctrl.tl:
[
peri.tl_lc_ctrl
]
sensor_ctrl_aon.tl:
[
peri.tl_sensor_ctrl_aon
]
alert_handler.tl:
[
peri.tl_alert_handler
]
sram_ctrl_ret_aon.tl:
[
peri.tl_sram_ctrl_ret_aon
]
aon_timer_aon.tl:
[
peri.tl_aon_timer_aon
]
}
top:
[
rstmgr_aon.resets
rstmgr_aon.cpu
pwrmgr_aon.pwr_cpu
clkmgr_aon.clocks
main.tl_corei
main.tl_cored
main.tl_dm_sba
main.tl_debug_mem
]
external:
{
clkmgr_aon.clk_main: clk_main
clkmgr_aon.clk_io: clk_io
clkmgr_aon.clk_usb: clk_usb
clkmgr_aon.clk_aon: clk_aon
clkmgr_aon.jitter_en: clk_main_jitter_en
pwrmgr_aon.pwr_ast: pwrmgr_ast
sensor_ctrl_aon.ast_alert: sensor_ctrl_ast_alert
sensor_ctrl_aon.ast_status: sensor_ctrl_ast_status
usbdev.usb_ref_val: ""
usbdev.usb_ref_pulse: ""
peri.tl_ast: ast_tl
otp_ctrl.otp_ast_pwr_seq: ""
otp_ctrl.otp_ast_pwr_seq_h: ""
eflash.flash_bist_enable: flash_bist_enable
eflash.flash_power_down_h: flash_power_down_h
eflash.flash_power_ready_h: flash_power_ready_h
eflash.flash_test_mode_a: flash_test_mode_a
eflash.flash_test_voltage_h: flash_test_voltage_h
entropy_src.entropy_src_rng: es_rng
lc_ctrl.lc_clk_byp_req: lc_clk_byp_req
clkmgr_aon.ast_clk_bypass_ack: lc_clk_byp_ack
ast_edn.edn: ""
clkmgr_aon.clocks_ast: clks_ast
rstmgr_aon.resets_ast: rsts_ast
}
}
xbar:
[
{
name: main
clock_srcs:
{
clk_main_i: main
clk_fixed_i: io_div4
}
clock_group: infra
reset: rst_main_ni
reset_connections:
{
rst_main_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
rst_fixed_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
clock_connections:
{
clk_main_i: clkmgr_aon_clocks.clk_main_infra
clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain: "0"
connections:
{
corei:
[
rom
debug_mem
ram_main
eflash
]
cored:
[
rom
debug_mem
ram_main
eflash
peri
flash_ctrl
aes
entropy_src
csrng
edn0
edn1
hmac
rv_plic
otbn
keymgr
kmac
sram_ctrl_main
]
dm_sba:
[
rom
ram_main
eflash
peri
flash_ctrl
aes
entropy_src
csrng
edn0
edn1
hmac
rv_plic
otbn
kmac
sram_ctrl_main
]
}
nodes:
[
{
name: corei
type: host
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
xbar: false
stub: false
inst_type: rv_core_ibex
pipeline_byp: "true"
}
{
name: cored
type: host
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
xbar: false
stub: false
inst_type: rv_core_ibex
pipeline_byp: "true"
}
{
name: dm_sba
type: host
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
xbar: false
stub: false
inst_type: rv_dm
pipeline: "true"
}
{
name: rom
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
inst_type: rom
addr_range:
[
{
base_addr: 0x00008000
size_byte: 0x4000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: debug_mem
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: rv_dm
addr_range:
[
{
base_addr: 0x1A110000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: ram_main
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
inst_type: ram_1p_scr
addr_range:
[
{
base_addr: 0x10000000
size_byte: 0x20000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: eflash
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
inst_type: eflash
addr_range:
[
{
base_addr: 0x20000000
size_byte: 0x100000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: peri
type: device
clock: clk_fixed_i
reset: rst_fixed_ni
pipeline_byp: "false"
xbar: true
stub: false
pipeline: "true"
addr_range:
[
{
base_addr: 0x40000000
size_byte: 0x800000
}
]
}
{
name: flash_ctrl
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: flash_ctrl
addr_range:
[
{
base_addr: 0x41000000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: hmac
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: hmac
addr_range:
[
{
base_addr: 0x41110000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: kmac
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: kmac
addr_range:
[
{
base_addr: 0x41120000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: aes
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: aes
addr_range:
[
{
base_addr: 0x41100000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: entropy_src
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: entropy_src
addr_range:
[
{
base_addr: 0x41160000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: csrng
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: csrng
addr_range:
[
{
base_addr: 0x41150000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: edn0
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: edn
addr_range:
[
{
base_addr: 0x41170000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: edn1
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: edn
addr_range:
[
{
base_addr: 0x41180000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: rv_plic
type: device
clock: clk_main_i
reset: rst_main_ni
inst_type: rv_plic
addr_range:
[
{
base_addr: 0x41010000
size_byte: 0x1000
}
]
pipeline_byp: "false"
xbar: false
stub: false
pipeline: "true"
}
{
name: otbn
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: otbn
addr_range:
[
{
base_addr: 0x411D0000
size_byte: 0x10000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: keymgr
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline_byp: "false"
inst_type: keymgr
addr_range:
[
{
base_addr: 0x41130000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline: "true"
}
{
name: sram_ctrl_main
type: device
clock: clk_main_i
reset: rst_main_ni
pipeline: "false"
inst_type: sram_ctrl
addr_range:
[
{
base_addr: 0x411C0000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
]
clock: clk_main_i
type: xbar
inter_signal_list:
[
{
struct: tl
type: req_rsp
name: tl_corei
act: rsp
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: main_tl_corei
index: -1
}
{
struct: tl
type: req_rsp
name: tl_cored
act: rsp
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: main_tl_cored
index: -1
}
{
struct: tl
type: req_rsp
name: tl_dm_sba
act: rsp
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: main_tl_dm_sba
index: -1
}
{
struct: tl
type: req_rsp
name: tl_rom
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: rom_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_debug_mem
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: main_tl_debug_mem
index: -1
}
{
struct: tl
type: req_rsp
name: tl_ram_main
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: ram_main_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_eflash
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: eflash_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_peri
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
end_idx: -1
top_signame: main_tl_peri
index: -1
}
{
struct: tl
type: req_rsp
name: tl_flash_ctrl
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: flash_ctrl_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_hmac
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: hmac_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_kmac
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: kmac_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_aes
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: aes_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_entropy_src
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: entropy_src_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_csrng
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: csrng_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_edn0
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: edn0_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_edn1
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: edn1_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_rv_plic
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: rv_plic_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_otbn
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: otbn_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_keymgr
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: keymgr_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_sram_ctrl_main
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: sram_ctrl_main_tl
index: -1
}
]
}
{
name: peri
clock_srcs:
{
clk_peri_i: io_div4
}
clock_group: infra
reset: rst_peri_ni
reset_connections:
{
rst_peri_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
clock_connections:
{
clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain: "0"
connections:
{
main:
[
uart0
uart1
uart2
uart3
i2c0
i2c1
i2c2
pattgen
gpio
spi_device
spi_host0
spi_host1
rv_timer
usbdev
pwrmgr_aon
rstmgr_aon
clkmgr_aon
pinmux_aon
ram_ret_aon
otp_ctrl
lc_ctrl
sensor_ctrl_aon
alert_handler
ast
sram_ctrl_ret_aon
aon_timer_aon
]
}
nodes:
[
{
name: main
type: host
clock: clk_peri_i
reset: rst_peri_ni
xbar: true
pipeline: "false"
stub: false
inst_type: ""
pipeline_byp: "true"
}
{
name: uart0
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: uart
addr_range:
[
{
base_addr: 0x40000000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: uart1
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: uart
addr_range:
[
{
base_addr: 0x40010000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: uart2
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: uart
addr_range:
[
{
base_addr: 0x40020000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: uart3
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: uart
addr_range:
[
{
base_addr: 0x40030000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: i2c0
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: i2c
addr_range:
[
{
base_addr: 0x40080000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: i2c1
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: i2c
addr_range:
[
{
base_addr: 0x40090000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: i2c2
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: i2c
addr_range:
[
{
base_addr: 0x400A0000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: pattgen
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: pattgen
addr_range:
[
{
base_addr: 0x400E0000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: gpio
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: gpio
addr_range:
[
{
base_addr: 0x40040000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: spi_device
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: spi_device
addr_range:
[
{
base_addr: 0x40050000
size_byte: 0x2000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: spi_host0
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: spi_host
addr_range:
[
{
base_addr: 0x40060000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: spi_host1
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: spi_host
addr_range:
[
{
base_addr: 0x40070000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: rv_timer
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: rv_timer
addr_range:
[
{
base_addr: 0x40100000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: usbdev
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: usbdev
addr_range:
[
{
base_addr: 0x40110000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: pwrmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: pwrmgr
addr_range:
[
{
base_addr: 0x40400000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: rstmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: rstmgr
addr_range:
[
{
base_addr: 0x40410000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: clkmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: clkmgr
addr_range:
[
{
base_addr: 0x40420000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: pinmux_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: pinmux
addr_range:
[
{
base_addr: 0x40460000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: ram_ret_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: ram_1p_scr
addr_range:
[
{
base_addr: 0x40600000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: otp_ctrl
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: otp_ctrl
addr_range:
[
{
base_addr: 0x40130000
size_byte: 0x4000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: lc_ctrl
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: lc_ctrl
addr_range:
[
{
base_addr: 0x40140000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: sensor_ctrl_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: sensor_ctrl
addr_range:
[
{
base_addr: 0x40490000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: alert_handler
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: alert_handler
addr_range:
[
{
base_addr: 0x40150000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: sram_ctrl_ret_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: sram_ctrl
addr_range:
[
{
base_addr: 0x40500000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: aon_timer_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: aon_timer
addr_range:
[
{
base_addr: 0x40470000
size_byte: 0x1000
}
]
xbar: false
stub: false
pipeline_byp: "true"
}
{
name: ast
type: device
clock: clk_peri_i
reset: rst_peri_ni
pipeline: "false"
inst_type: ast
addr_range:
[
{
base_addr: 0x40480000
size_byte: 0x1000
}
]
xbar: false
stub: true
pipeline_byp: "true"
}
]
clock: clk_peri_i
type: xbar
inter_signal_list:
[
{
struct: tl
type: req_rsp
name: tl_main
act: rsp
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: main_tl_peri
index: -1
}
{
struct: tl
type: req_rsp
name: tl_uart0
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: uart0_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_uart1
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: uart1_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_uart2
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: uart2_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_uart3
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: uart3_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_i2c0
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: i2c0_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_i2c1
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: i2c1_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_i2c2
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: i2c2_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_pattgen
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: pattgen_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_gpio
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: gpio_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_spi_device
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: spi_device_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_spi_host0
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: spi_host0_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_spi_host1
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: spi_host1_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_rv_timer
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: rv_timer_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_usbdev
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: usbdev_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_pwrmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: pwrmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_rstmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: rstmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_clkmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: clkmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_pinmux_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: pinmux_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_ram_ret_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: ram_ret_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_otp_ctrl
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: otp_ctrl_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_lc_ctrl
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: lc_ctrl_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_sensor_ctrl_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: sensor_ctrl_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_alert_handler
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: alert_handler_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_sram_ctrl_ret_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: sram_ctrl_ret_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_aon_timer_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: aon_timer_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_ast
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
external: true
top_signame: ast_tl
index: -1
}
]
}
]
interrupt_module:
[
uart0
uart1
uart2
uart3
gpio
spi_device
i2c0
i2c1
i2c2
pattgen
flash_ctrl
hmac
alert_handler
usbdev
pwrmgr_aon
otbn
keymgr
kmac
otp_ctrl
csrng
edn0
edn1
aon_timer_aon
entropy_src
]
interrupt:
[
{
name: uart0_tx_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: uart0
}
{
name: uart0_rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: uart0
}
{
name: uart0_tx_empty
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: uart0
}
{
name: uart0_rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: uart0
}
{
name: uart0_rx_frame_err
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: uart0
}
{
name: uart0_rx_break_err
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
module_name: uart0
}
{
name: uart0_rx_timeout
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
module_name: uart0
}
{
name: uart0_rx_parity_err
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
module_name: uart0
}
{
name: uart1_tx_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: uart1
}
{
name: uart1_rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: uart1
}
{
name: uart1_tx_empty
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: uart1
}
{
name: uart1_rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: uart1
}
{
name: uart1_rx_frame_err
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: uart1
}
{
name: uart1_rx_break_err
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
module_name: uart1
}
{
name: uart1_rx_timeout
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
module_name: uart1
}
{
name: uart1_rx_parity_err
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
module_name: uart1
}
{
name: uart2_tx_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: uart2
}
{
name: uart2_rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: uart2
}
{
name: uart2_tx_empty
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: uart2
}
{
name: uart2_rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: uart2
}
{
name: uart2_rx_frame_err
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: uart2
}
{
name: uart2_rx_break_err
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
module_name: uart2
}
{
name: uart2_rx_timeout
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
module_name: uart2
}
{
name: uart2_rx_parity_err
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
module_name: uart2
}
{
name: uart3_tx_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: uart3
}
{
name: uart3_rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: uart3
}
{
name: uart3_tx_empty
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: uart3
}
{
name: uart3_rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: uart3
}
{
name: uart3_rx_frame_err
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: uart3
}
{
name: uart3_rx_break_err
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
module_name: uart3
}
{
name: uart3_rx_timeout
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
module_name: uart3
}
{
name: uart3_rx_parity_err
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
module_name: uart3
}
{
name: gpio_gpio
width: 32
bits: 31:0
bitinfo:
[
4294967295
32
0
]
type: interrupt
module_name: gpio
}
{
name: spi_device_rxf
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: spi_device
}
{
name: spi_device_rxlvl
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: spi_device
}
{
name: spi_device_txlvl
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: spi_device
}
{
name: spi_device_rxerr
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: spi_device
}
{
name: spi_device_rxoverflow
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: spi_device
}
{
name: spi_device_txunderflow
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
module_name: spi_device
}
{
name: i2c0_fmt_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_fmt_overflow
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_nak
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_scl_interference
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_sda_interference
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_stretch_timeout
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_sda_unstable
width: 1
bits: "8"
bitinfo:
[
256
1
8
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_trans_complete
width: 1
bits: "9"
bitinfo:
[
512
1
9
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_tx_empty
width: 1
bits: "10"
bitinfo:
[
1024
1
10
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_tx_nonempty
width: 1
bits: "11"
bitinfo:
[
2048
1
11
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_tx_overflow
width: 1
bits: "12"
bitinfo:
[
4096
1
12
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_acq_overflow
width: 1
bits: "13"
bitinfo:
[
8192
1
13
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_ack_stop
width: 1
bits: "14"
bitinfo:
[
16384
1
14
]
type: interrupt
module_name: i2c0
}
{
name: i2c0_host_timeout
width: 1
bits: "15"
bitinfo:
[
32768
1
15
]
type: interrupt
module_name: i2c0
}
{
name: i2c1_fmt_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_fmt_overflow
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_nak
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_scl_interference
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_sda_interference
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_stretch_timeout
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_sda_unstable
width: 1
bits: "8"
bitinfo:
[
256
1
8
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_trans_complete
width: 1
bits: "9"
bitinfo:
[
512
1
9
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_tx_empty
width: 1
bits: "10"
bitinfo:
[
1024
1
10
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_tx_nonempty
width: 1
bits: "11"
bitinfo:
[
2048
1
11
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_tx_overflow
width: 1
bits: "12"
bitinfo:
[
4096
1
12
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_acq_overflow
width: 1
bits: "13"
bitinfo:
[
8192
1
13
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_ack_stop
width: 1
bits: "14"
bitinfo:
[
16384
1
14
]
type: interrupt
module_name: i2c1
}
{
name: i2c1_host_timeout
width: 1
bits: "15"
bitinfo:
[
32768
1
15
]
type: interrupt
module_name: i2c1
}
{
name: i2c2_fmt_watermark
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_rx_watermark
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_fmt_overflow
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_rx_overflow
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_nak
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_scl_interference
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_sda_interference
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_stretch_timeout
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_sda_unstable
width: 1
bits: "8"
bitinfo:
[
256
1
8
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_trans_complete
width: 1
bits: "9"
bitinfo:
[
512
1
9
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_tx_empty
width: 1
bits: "10"
bitinfo:
[
1024
1
10
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_tx_nonempty
width: 1
bits: "11"
bitinfo:
[
2048
1
11
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_tx_overflow
width: 1
bits: "12"
bitinfo:
[
4096
1
12
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_acq_overflow
width: 1
bits: "13"
bitinfo:
[
8192
1
13
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_ack_stop
width: 1
bits: "14"
bitinfo:
[
16384
1
14
]
type: interrupt
module_name: i2c2
}
{
name: i2c2_host_timeout
width: 1
bits: "15"
bitinfo:
[
32768
1
15
]
type: interrupt
module_name: i2c2
}
{
name: pattgen_done_ch0
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: pattgen
}
{
name: pattgen_done_ch1
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: pattgen
}
{
name: flash_ctrl_prog_empty
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: flash_ctrl
}
{
name: flash_ctrl_prog_lvl
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: flash_ctrl
}
{
name: flash_ctrl_rd_full
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: flash_ctrl
}
{
name: flash_ctrl_rd_lvl
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: flash_ctrl
}
{
name: flash_ctrl_op_done
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: flash_ctrl
}
{
name: hmac_hmac_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: hmac
}
{
name: hmac_fifo_empty
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: hmac
}
{
name: hmac_hmac_err
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: hmac
}
{
name: alert_handler_classa
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: alert_handler
}
{
name: alert_handler_classb
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: alert_handler
}
{
name: alert_handler_classc
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: alert_handler
}
{
name: alert_handler_classd
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: alert_handler
}
{
name: usbdev_pkt_received
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_pkt_sent
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_disconnected
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_host_lost
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_reset
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_suspend
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_resume
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_av_empty
width: 1
bits: "7"
bitinfo:
[
128
1
7
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_rx_full
width: 1
bits: "8"
bitinfo:
[
256
1
8
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_av_overflow
width: 1
bits: "9"
bitinfo:
[
512
1
9
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_in_err
width: 1
bits: "10"
bitinfo:
[
1024
1
10
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_rx_crc_err
width: 1
bits: "11"
bitinfo:
[
2048
1
11
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_rx_pid_err
width: 1
bits: "12"
bitinfo:
[
4096
1
12
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_rx_bitstuff_err
width: 1
bits: "13"
bitinfo:
[
8192
1
13
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_frame
width: 1
bits: "14"
bitinfo:
[
16384
1
14
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_connected
width: 1
bits: "15"
bitinfo:
[
32768
1
15
]
type: interrupt
module_name: usbdev
}
{
name: usbdev_link_out_err
width: 1
bits: "16"
bitinfo:
[
65536
1
16
]
type: interrupt
module_name: usbdev
}
{
name: pwrmgr_aon_wakeup
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: pwrmgr_aon
}
{
name: otbn_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: otbn
}
{
name: keymgr_op_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: keymgr
}
{
name: kmac_kmac_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: kmac
}
{
name: kmac_fifo_empty
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: kmac
}
{
name: kmac_kmac_err
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: kmac
}
{
name: otp_ctrl_otp_operation_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: otp_ctrl
}
{
name: otp_ctrl_otp_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: otp_ctrl
}
{
name: csrng_cs_cmd_req_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: csrng
}
{
name: csrng_cs_entropy_req
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: csrng
}
{
name: csrng_cs_hw_inst_exc
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: csrng
}
{
name: csrng_cs_fatal_err
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: interrupt
module_name: csrng
}
{
name: edn0_edn_cmd_req_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: edn0
}
{
name: edn0_edn_fatal_err
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: edn0
}
{
name: edn1_edn_cmd_req_done
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: edn1
}
{
name: edn1_edn_fatal_err
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: edn1
}
{
name: aon_timer_aon_wkup_timer_expired
width: 1
type: interrupt
module_name: aon_timer_aon
}
{
name: aon_timer_aon_wdog_timer_bark
width: 1
type: interrupt
module_name: aon_timer_aon
}
{
name: entropy_src_es_entropy_valid
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: interrupt
module_name: entropy_src
}
{
name: entropy_src_es_health_test_failed
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: interrupt
module_name: entropy_src
}
{
name: entropy_src_es_fatal_err
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: interrupt
module_name: entropy_src
}
]
alert_module:
[
aes
otbn
sensor_ctrl_aon
keymgr
otp_ctrl
lc_ctrl
entropy_src
csrng
edn0
edn1
sram_ctrl_main
sram_ctrl_ret_aon
flash_ctrl
]
alert:
[
{
name: aes_recov_ctrl_update_err
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
module_name: aes
}
{
name: aes_fatal_fault
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
module_name: aes
}
{
name: otbn_fatal
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
module_name: otbn
}
{
name: otbn_recov
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
module_name: otbn
}
{
name: sensor_ctrl_aon_recov_as
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 0
module_name: sensor_ctrl_aon
}
{
name: sensor_ctrl_aon_recov_cg
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 0
module_name: sensor_ctrl_aon
}
{
name: sensor_ctrl_aon_recov_gd
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: alert
async: 0
module_name: sensor_ctrl_aon
}
{
name: sensor_ctrl_aon_recov_ts_hi
width: 1
bits: "3"
bitinfo:
[
8
1
3
]
type: alert
async: 0
module_name: sensor_ctrl_aon
}
{
name: sensor_ctrl_aon_recov_ts_lo
width: 1
bits: "4"
bitinfo:
[
16
1
4
]
type: alert
async: 0
module_name: sensor_ctrl_aon
}
{
name: sensor_ctrl_aon_recov_ls
width: 1
bits: "5"
bitinfo:
[
32
1
5
]
type: alert
async: 0
module_name: sensor_ctrl_aon
}
{
name: sensor_ctrl_aon_recov_ot
width: 1
bits: "6"
bitinfo:
[
64
1
6
]
type: alert
async: 0
module_name: sensor_ctrl_aon
}
{
name: keymgr_fatal_fault_err
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
module_name: keymgr
}
{
name: keymgr_recov_operation_err
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
module_name: keymgr
}
{
name: otp_ctrl_fatal_macro_error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 0
module_name: otp_ctrl
}
{
name: otp_ctrl_fatal_check_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 0
module_name: otp_ctrl
}
{
name: lc_ctrl_fatal_prog_error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 0
module_name: lc_ctrl
}
{
name: lc_ctrl_fatal_state_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 0
module_name: lc_ctrl
}
{
name: entropy_src_recov_alert
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
module_name: entropy_src
}
{
name: entropy_src_fatal_alert
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
module_name: entropy_src
}
{
name: csrng_fatal_alert
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
module_name: csrng
}
{
name: edn0_fatal_alert
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
module_name: edn0
}
{
name: edn1_fatal_alert
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
module_name: edn1
}
{
name: sram_ctrl_main_fatal_intg_error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
module_name: sram_ctrl_main
}
{
name: sram_ctrl_main_fatal_parity_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
module_name: sram_ctrl_main
}
{
name: sram_ctrl_ret_aon_fatal_intg_error
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 0
module_name: sram_ctrl_ret_aon
}
{
name: sram_ctrl_ret_aon_fatal_parity_error
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 0
module_name: sram_ctrl_ret_aon
}
{
name: flash_ctrl_recov_err
width: 1
bits: "0"
bitinfo:
[
1
1
0
]
type: alert
async: 1
module_name: flash_ctrl
}
{
name: flash_ctrl_recov_mp_err
width: 1
bits: "1"
bitinfo:
[
2
1
1
]
type: alert
async: 1
module_name: flash_ctrl
}
{
name: flash_ctrl_recov_ecc_err
width: 1
bits: "2"
bitinfo:
[
4
1
2
]
type: alert
async: 1
module_name: flash_ctrl
}
]
pinmux:
{
num_mio: 44
dio_modules:
[
{
name: spi_device
pad:
[
ChC[0..5]
]
}
{
name: spi_host0
pad:
[
ChB[0..5]
]
}
{
name: usbdev
pad:
[
ChA[0..8]
]
}
]
mio_modules:
[
gpio
uart0
uart1
uart2
uart3
i2c0
i2c1
i2c2
pattgen
spi_host1
flash_ctrl
]
nc_modules:
[
rv_timer
hmac
]
num_wkup_detect: 8
wkup_cnt_width: 8
dio:
[
{
name: spi_device_sck
width: 1
type: input
module_name: spi_device
pad:
[
{
name: ChC
index: 0
}
]
}
{
name: spi_device_csb
width: 1
type: input
module_name: spi_device
pad:
[
{
name: ChC
index: 1
}
]
}
{
name: spi_device_sd
width: 4
type: inout
module_name: spi_device
pad:
[
{
name: ChC
index: 2
}
{
name: ChC
index: 3
}
{
name: ChC
index: 4
}
{
name: ChC
index: 5
}
]
}
{
name: spi_host0_sck
width: 1
type: output
module_name: spi_host0
pad:
[
{
name: ChB
index: 0
}
]
}
{
name: spi_host0_csb
width: 1
type: output
module_name: spi_host0
pad:
[
{
name: ChB
index: 1
}
]
}
{
name: spi_host0_sd
width: 4
type: inout
module_name: spi_host0
pad:
[
{
name: ChB
index: 2
}
{
name: ChB
index: 3
}
{
name: ChB
index: 4
}
{
name: ChB
index: 5
}
]
}
{
name: usbdev_sense
width: 1
type: input
module_name: usbdev
pad:
[
{
name: ChA
index: 0
}
]
}
{
name: usbdev_se0
width: 1
type: output
module_name: usbdev
pad:
[
{
name: ChA
index: 1
}
]
}
{
name: usbdev_dp_pullup
width: 1
type: output
module_name: usbdev
pad:
[
{
name: ChA
index: 2
}
]
}
{
name: usbdev_dn_pullup
width: 1
type: output
module_name: usbdev
pad:
[
{
name: ChA
index: 3
}
]
}
{
name: usbdev_tx_mode_se
width: 1
type: output
module_name: usbdev
pad:
[
{
name: ChA
index: 4
}
]
}
{
name: usbdev_suspend
width: 1
type: output
module_name: usbdev
pad:
[
{
name: ChA
index: 5
}
]
}
{
name: usbdev_d
width: 1
type: inout
module_name: usbdev
pad:
[
{
name: ChA
index: 6
}
]
}
{
name: usbdev_dp
width: 1
type: inout
module_name: usbdev
pad:
[
{
name: ChA
index: 7
}
]
}
{
name: usbdev_dn
width: 1
type: inout
module_name: usbdev
pad:
[
{
name: ChA
index: 8
}
]
}
]
inputs:
[
{
name: gpio_gpio
width: 32
type: inout
module_name: gpio
}
{
name: uart0_rx
width: 1
type: input
module_name: uart0
}
{
name: uart1_rx
width: 1
type: input
module_name: uart1
}
{
name: uart2_rx
width: 1
type: input
module_name: uart2
}
{
name: uart3_rx
width: 1
type: input
module_name: uart3
}
{
name: i2c0_sda
width: 1
type: inout
module_name: i2c0
}
{
name: i2c0_scl
width: 1
type: inout
module_name: i2c0
}
{
name: i2c1_sda
width: 1
type: inout
module_name: i2c1
}
{
name: i2c1_scl
width: 1
type: inout
module_name: i2c1
}
{
name: i2c2_sda
width: 1
type: inout
module_name: i2c2
}
{
name: i2c2_scl
width: 1
type: inout
module_name: i2c2
}
{
name: spi_host1_sd
width: 4
type: inout
module_name: spi_host1
}
{
name: flash_ctrl_tck
width: 1
type: input
module_name: flash_ctrl
}
{
name: flash_ctrl_tms
width: 1
type: input
module_name: flash_ctrl
}
{
name: flash_ctrl_tdi
width: 1
type: input
module_name: flash_ctrl
}
]
outputs:
[
{
name: gpio_gpio
width: 32
type: inout
module_name: gpio
}
{
name: uart0_tx
width: 1
type: output
module_name: uart0
}
{
name: uart1_tx
width: 1
type: output
module_name: uart1
}
{
name: uart2_tx
width: 1
type: output
module_name: uart2
}
{
name: uart3_tx
width: 1
type: output
module_name: uart3
}
{
name: i2c0_sda
width: 1
type: inout
module_name: i2c0
}
{
name: i2c0_scl
width: 1
type: inout
module_name: i2c0
}
{
name: i2c1_sda
width: 1
type: inout
module_name: i2c1
}
{
name: i2c1_scl
width: 1
type: inout
module_name: i2c1
}
{
name: i2c2_sda
width: 1
type: inout
module_name: i2c2
}
{
name: i2c2_scl
width: 1
type: inout
module_name: i2c2
}
{
name: pattgen_pda0_tx
width: 1
type: output
module_name: pattgen
}
{
name: pattgen_pcl0_tx
width: 1
type: output
module_name: pattgen
}
{
name: pattgen_pda1_tx
width: 1
type: output
module_name: pattgen
}
{
name: pattgen_pcl1_tx
width: 1
type: output
module_name: pattgen
}
{
name: spi_host1_sd
width: 4
type: inout
module_name: spi_host1
}
{
name: spi_host1_sck
width: 1
type: output
module_name: spi_host1
}
{
name: spi_host1_csb
width: 1
type: output
module_name: spi_host1
}
{
name: flash_ctrl_tdo
width: 1
type: output
module_name: flash_ctrl
}
]
}
padctrl:
{
attr_default:
[
STRONG
]
pads:
[
{
name: ChA
type: IO_33V
count: 32
}
{
name: ChB
type: IO_33V
count: 4
attr:
[
KEEP
WEAK
]
}
{
name: ChC
type: IO_33V
count: 4
attr:
[
KEEP
STRONG
]
}
]
}
exported_clks:
{
ast:
{
usbdev:
[
io_div4_peri
aon_peri
usb_peri
]
ast:
[
io_div4_secure
]
sensor_ctrl_aon:
[
io_div4_secure
]
entropy_src:
[
main_secure
]
edn0:
[
main_secure
]
}
}
wakeups:
[
{
name: aon_wkup_req
width: "1"
module: pinmux_aon
}
{
name: usb_wkup_req
width: "1"
module: pinmux_aon
}
{
name: aon_timer_wkup_req
width: "1"
module: aon_timer_aon
}
]
reset_requests:
[
{
name: aon_timer_rst_req
module: aon_timer_aon
}
]
exported_rsts:
{
ast:
{
usbdev:
[
sys_io_div4
sys_aon
usb
]
ast:
[
sys_io_div4
]
sensor_ctrl_aon:
[
sys_io_div4
]
entropy_src:
[
sys
]
edn0:
[
sys
]
}
}
reset_paths:
{
rst_ni: rst_ni
por_aon: rstmgr_aon_resets.rst_por_aon_n
por: rstmgr_aon_resets.rst_por_n
por_io: rstmgr_aon_resets.rst_por_io_n
por_io_div2: rstmgr_aon_resets.rst_por_io_div2_n
por_io_div4: rstmgr_aon_resets.rst_por_io_div4_n
por_usb: rstmgr_aon_resets.rst_por_usb_n
lc: rstmgr_aon_resets.rst_lc_n
lc_io_div4: rstmgr_aon_resets.rst_lc_io_div4_n
sys: rstmgr_aon_resets.rst_sys_n
sys_io_div4: rstmgr_aon_resets.rst_sys_io_div4_n
sys_aon: rstmgr_aon_resets.rst_sys_aon_n
spi_device: rstmgr_aon_resets.rst_spi_device_n
spi_host0: rstmgr_aon_resets.rst_spi_host0_n
spi_host1: rstmgr_aon_resets.rst_spi_host1_n
usb: rstmgr_aon_resets.rst_usb_n
i2c0: rstmgr_aon_resets.rst_i2c0_n
i2c1: rstmgr_aon_resets.rst_i2c1_n
i2c2: rstmgr_aon_resets.rst_i2c2_n
}
inter_signal:
{
signals:
[
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: uart0
width: 1
default: ""
end_idx: -1
top_signame: uart0_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: uart1
width: 1
default: ""
end_idx: -1
top_signame: uart1_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: uart2
width: 1
default: ""
end_idx: -1
top_signame: uart2_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: uart3
width: 1
default: ""
end_idx: -1
top_signame: uart3_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: gpio
width: 1
default: ""
end_idx: -1
top_signame: gpio_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: spi_device
width: 1
default: ""
end_idx: -1
top_signame: spi_device_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: spi_host0
width: 1
default: ""
end_idx: -1
top_signame: spi_host0_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: spi_host1
width: 1
default: ""
end_idx: -1
top_signame: spi_host1_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: i2c0
width: 1
default: ""
end_idx: -1
top_signame: i2c0_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: i2c1
width: 1
default: ""
end_idx: -1
top_signame: i2c1_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: i2c2
width: 1
default: ""
end_idx: -1
top_signame: i2c2_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: pattgen
width: 1
default: ""
end_idx: -1
top_signame: pattgen_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: rv_timer
width: 1
default: ""
end_idx: -1
top_signame: rv_timer_tl
index: -1
}
{
name: usb_ref_val
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
external: true
top_signame: usbdev_usb_ref_val
index: -1
}
{
name: usb_ref_pulse
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
external: true
top_signame: usbdev_usb_ref_pulse
index: -1
}
{
name: usb_out_of_rst
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_out_of_rst
index: -1
}
{
name: usb_aon_wake_en
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_wake_en
index: -1
}
{
name: usb_aon_wake_ack
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_aon_wake_ack
index: -1
}
{
name: usb_suspend
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: usbdev
default: ""
end_idx: -1
top_type: broadcast
top_signame: usbdev_usb_suspend
index: -1
}
{
name: usb_state_debug
type: uni
act: rcv
package: usbdev_pkg
struct: awk_state
inst_name: usbdev
width: 1
default: ""
top_signame: pinmux_aon_usb_state_debug
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: usbdev
width: 1
default: ""
end_idx: -1
top_signame: usbdev_tl
index: -1
}
{
struct: otp_ast_req
type: uni
name: otp_ast_pwr_seq
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
external: true
top_signame: otp_ctrl_otp_ast_pwr_seq
index: -1
}
{
struct: otp_ast_rsp
type: uni
name: otp_ast_pwr_seq_h
act: rcv
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
external: true
top_signame: otp_ctrl_otp_ast_pwr_seq_h
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: req
package: edn_pkg
inst_name: otp_ctrl
width: 1
default: ""
top_signame: edn0_edn
index: 1
}
{
struct: pwr_otp
type: req_rsp
name: pwr_otp
act: rsp
default: "'0"
package: pwrmgr_pkg
inst_name: otp_ctrl
width: 1
top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
struct: lc_otp_program
type: req_rsp
name: lc_otp_program
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_otp_program
index: -1
}
{
struct: lc_otp_token
type: req_rsp
name: lc_otp_token
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_otp_token
index: -1
}
{
struct: otp_lc_data
type: uni
name: otp_lc_data
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_lc_data
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_creator_seed_sw_rw_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_seed_hw_rd_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_dft_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_check_byp_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
struct: otp_keymgr_key
type: uni
name: otp_keymgr_key
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_keymgr_key
index: -1
}
{
struct: flash_otp_key
type: req_rsp
name: flash_otp_key
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
width: 1
top_signame: flash_ctrl_otp
index: -1
}
{
struct: sram_otp_key
width: 2
type: req_rsp
name: sram_otp_key
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
end_idx: -1
top_type: one-to-N
top_signame: otp_ctrl_sram_otp_key
index: -1
}
{
struct: otbn_otp_key
type: req_rsp
name: otbn_otp_key
act: rsp
default: "'0"
package: otp_ctrl_pkg
inst_name: otp_ctrl
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: req
default: "'0"
package: otp_ctrl_part_pkg
inst_name: otp_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: otp_ctrl
width: 1
default: ""
end_idx: -1
top_signame: otp_ctrl_tl
index: -1
}
{
struct: jtag
type: req_rsp
name: jtag
act: rsp
package: jtag_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: pinmux_aon_lc_jtag
index: -1
}
{
struct: esc_tx
type: uni
name: esc_wipe_secrets_tx
act: rcv
package: prim_esc_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: alert_handler_esc_tx
index: 1
}
{
struct: esc_rx
type: uni
name: esc_wipe_secrets_rx
act: req
package: prim_esc_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: alert_handler_esc_rx
index: 1
}
{
struct: esc_tx
type: uni
name: esc_scrap_state_tx
act: rcv
package: prim_esc_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: alert_handler_esc_tx
index: 2
}
{
struct: esc_rx
type: uni
name: esc_scrap_state_rx
act: req
package: prim_esc_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: alert_handler_esc_rx
index: 2
}
{
struct: pwr_lc
type: req_rsp
name: pwr_lc
act: rsp
package: pwrmgr_pkg
inst_name: lc_ctrl
width: 1
default: ""
top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
struct: otp_lc_data
type: uni
name: otp_lc_data
act: rcv
default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT
package: otp_ctrl_pkg
inst_name: lc_ctrl
width: 1
top_signame: otp_ctrl_otp_lc_data
index: -1
}
{
struct: lc_otp_program
type: req_rsp
name: lc_otp_program
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_signame: lc_ctrl_lc_otp_program
index: -1
}
{
struct: lc_otp_token
type: req_rsp
name: lc_otp_token
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_signame: lc_ctrl_lc_otp_token
index: -1
}
{
struct: lc_tx
type: uni
name: lc_dft_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_nvm_debug_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_nvm_debug_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_cpu_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_cpu_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_keymgr_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_keymgr_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_clk_byp_req
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
external: true
top_signame: lc_clk_byp_req
index: -1
}
{
struct: lc_tx
type: uni
name: lc_clk_byp_ack
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_clk_byp_ack
index: -1
}
{
struct: lc_tx
type: uni
name: lc_flash_rma_req
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
top_signame: flash_ctrl_rma_req
index: -1
}
{
struct: lc_flash_rma_seed
type: uni
name: lc_flash_rma_seed
act: req
default: "'0"
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
top_signame: flash_ctrl_rma_seed
index: -1
}
{
struct: lc_tx
type: uni
name: lc_flash_rma_ack
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
top_signame: flash_ctrl_rma_ack
index: -1
}
{
struct: lc_tx
type: uni
name: lc_check_byp_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_check_byp_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_creator_seed_sw_rw_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_owner_seed_sw_rw_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_iso_part_sw_rd_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_iso_part_sw_rd_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_iso_part_sw_wr_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_iso_part_sw_wr_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_seed_hw_rd_en
act: req
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
struct: lc_keymgr_div
type: uni
name: lc_keymgr_div
act: req
default: "'0"
package: lc_ctrl_pkg
inst_name: lc_ctrl
width: 1
end_idx: -1
top_type: broadcast
top_signame: lc_ctrl_lc_keymgr_div
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: rcv
default: "'0"
package: otp_ctrl_part_pkg
inst_name: lc_ctrl
width: 1
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: lc_ctrl
width: 1
default: ""
end_idx: -1
top_signame: lc_ctrl_tl
index: -1
}
{
struct: alert_crashdump
type: uni
name: crashdump
act: req
package: alert_pkg
inst_name: alert_handler
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: alert_handler_crashdump
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: req
width: 1
package: edn_pkg
inst_name: alert_handler
default: ""
top_signame: edn1_edn
index: 0
}
{
struct: esc_rx
type: uni
name: esc_rx
act: rcv
width: 4
package: prim_esc_pkg
inst_name: alert_handler
default: ""
end_idx: -1
top_type: one-to-N
top_signame: alert_handler_esc_rx
index: -1
}
{
struct: esc_tx
type: uni
name: esc_tx
act: req
width: 4
package: prim_esc_pkg
inst_name: alert_handler
default: ""
end_idx: -1
top_type: one-to-N
top_signame: alert_handler_esc_tx
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: alert_handler
width: 1
default: ""
end_idx: -1
top_signame: alert_handler_tl
index: -1
}
{
struct: pwr_ast
type: req_rsp
name: pwr_ast
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
external: true
top_signame: pwrmgr_ast
index: -1
}
{
struct: pwr_rst
type: req_rsp
name: pwr_rst
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
struct: pwr_clk
type: req_rsp
name: pwr_clk
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
struct: pwr_otp
type: req_rsp
name: pwr_otp
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
struct: pwr_lc
type: req_rsp
name: pwr_lc
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
struct: pwr_flash
type: req_rsp
name: pwr_flash
act: req
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
struct: esc_tx
type: uni
name: esc_rst_tx
act: rcv
package: prim_esc_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
top_signame: alert_handler_esc_tx
index: 3
}
{
struct: esc_rx
type: uni
name: esc_rst_rx
act: req
package: prim_esc_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
top_signame: alert_handler_esc_rx
index: 3
}
{
struct: pwr_cpu
type: uni
name: pwr_cpu
act: rcv
package: pwrmgr_pkg
inst_name: pwrmgr_aon
width: 1
default: ""
top_signame: pwrmgr_aon_pwr_cpu
index: -1
}
{
struct: logic
width: 3
type: uni
name: wakeups
act: rcv
package: ""
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_type: one-to-N
top_signame: pwrmgr_aon_wakeups
index: -1
}
{
struct: logic
width: 1
type: uni
name: rstreqs
act: rcv
package: ""
inst_name: pwrmgr_aon
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_rstreqs
index: -1
}
{
struct: logic
type: uni
name: strap
act: req
package: ""
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_strap
index: -1
}
{
struct: logic
type: uni
name: low_power
act: req
package: ""
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: pwrmgr_aon_low_power
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: pwrmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: pwrmgr_aon_tl
index: -1
}
{
struct: pwr_rst
type: req_rsp
name: pwr
act: rsp
inst_name: rstmgr_aon
width: 1
default: ""
package: pwrmgr_pkg
top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
struct: rstmgr_out
type: uni
name: resets
act: req
package: rstmgr_pkg
inst_name: rstmgr_aon
width: 1
default: ""
top_signame: rstmgr_aon_resets
index: -1
}
{
struct: rstmgr_cpu
type: uni
name: cpu
act: rcv
package: rstmgr_pkg
inst_name: rstmgr_aon
width: 1
default: ""
top_signame: rstmgr_aon_cpu
index: -1
}
{
struct: alert_crashdump
type: uni
name: alert_dump
act: rcv
package: alert_pkg
inst_name: rstmgr_aon
width: 1
default: ""
top_signame: alert_handler_crashdump
index: -1
}
{
struct: crash_dump
type: uni
name: cpu_dump
act: rcv
package: ibex_pkg
inst_name: rstmgr_aon
width: 1
default: ""
top_signame: rv_core_ibex_crash_dump
index: -1
}
{
struct: rstmgr_ast_out
type: uni
name: resets_ast
act: req
package: rstmgr_pkg
inst_name: rstmgr_aon
width: 1
default: ""
external: true
top_signame: rsts_ast
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: rstmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: rstmgr_aon_tl
index: -1
}
{
struct: clkmgr_out
type: uni
name: clocks
act: req
package: clkmgr_pkg
inst_name: clkmgr_aon
width: 1
default: ""
top_signame: clkmgr_aon_clocks
index: -1
}
{
struct: lc_tx
type: uni
name: ast_clk_bypass_ack
act: rcv
package: lc_ctrl_pkg
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: lc_clk_byp_ack
index: -1
}
{
struct: lc_tx
type: uni
name: lc_clk_bypass_ack
act: req
package: lc_ctrl_pkg
inst_name: clkmgr_aon
width: 1
default: ""
top_signame: lc_ctrl_lc_clk_byp_ack
index: -1
}
{
struct: logic
type: uni
name: jitter_en
act: req
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_main_jitter_en
index: -1
}
{
struct: logic
type: uni
name: clk_main
act: rcv
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_main
index: -1
}
{
struct: logic
type: uni
name: clk_io
act: rcv
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_io
index: -1
}
{
struct: logic
type: uni
name: clk_usb
act: rcv
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_usb
index: -1
}
{
struct: logic
type: uni
name: clk_aon
act: rcv
package: ""
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clk_aon
index: -1
}
{
struct: clkmgr_ast_out
type: uni
name: clocks_ast
act: req
package: clkmgr_pkg
inst_name: clkmgr_aon
width: 1
default: ""
external: true
top_signame: clks_ast
index: -1
}
{
struct: pwr_clk
type: req_rsp
name: pwr
act: rsp
inst_name: clkmgr_aon
width: 1
default: ""
package: pwrmgr_pkg
top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
struct: logic
type: uni
name: idle
act: rcv
package: ""
width: 4
inst_name: clkmgr_aon
default: ""
end_idx: -1
top_type: one-to-N
top_signame: clkmgr_aon_idle
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: clkmgr_aon
width: 1
default: ""
end_idx: -1
top_signame: clkmgr_aon_tl
index: -1
}
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: pinmux_aon
width: 1
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_dft_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: pinmux_aon
width: 1
top_signame: lc_ctrl_lc_dft_en
index: -1
}
{
struct: jtag
type: req_rsp
name: lc_jtag
act: req
package: jtag_pkg
inst_name: pinmux_aon
width: 1
default: ""
end_idx: -1
top_signame: pinmux_aon_lc_jtag
index: -1
}
{
struct: jtag
type: req_rsp
name: rv_jtag
act: req
package: jtag_pkg
inst_name: pinmux_aon
index: -1
}
{
struct: jtag
type: req_rsp
name: dft_jtag
act: req
package: jtag_pkg
inst_name: pinmux_aon
index: -1
}
{
struct: dft_strap_test
type: uni
name: dft_strap_test
act: req
package: pinmux_pkg
default: "'0"
inst_name: pinmux_aon
index: -1
}
{
struct: logic
type: uni
name: sleep_en
act: rcv
package: ""
default: 1'b0
inst_name: pinmux_aon
width: 1
top_signame: pwrmgr_aon_low_power
index: -1
}
{
struct: logic
type: uni
name: strap_en
act: rcv
package: ""
default: 1'b0
inst_name: pinmux_aon
width: 1
top_signame: pwrmgr_aon_strap
index: -1
}
{
struct: logic
type: uni
name: aon_wkup_req
act: req
package: ""
default: 1'b0
inst_name: pinmux_aon
width: 1
top_signame: pwrmgr_aon_wakeups
index: 0
}
{
struct: logic
type: uni
name: usb_wkup_req
act: req
package: ""
default: 1'b0
inst_name: pinmux_aon
width: 1
top_signame: pwrmgr_aon_wakeups
index: 1
}
{
name: usb_out_of_rst
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_out_of_rst
index: -1
}
{
name: usb_aon_wake_en
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_aon_wake_en
index: -1
}
{
name: usb_aon_wake_ack
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_aon_wake_ack
index: -1
}
{
name: usb_suspend
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_suspend
index: -1
}
{
name: usb_state_debug
type: uni
act: req
package: usbdev_pkg
struct: awk_state
inst_name: pinmux_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: pinmux_aon_usb_state_debug
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: pinmux_aon
width: 1
default: ""
end_idx: -1
top_signame: pinmux_aon_tl
index: -1
}
{
struct: logic
type: uni
name: aon_timer_wkup_req
act: req
package: ""
default: 1'b0
inst_name: aon_timer_aon
width: 1
top_signame: pwrmgr_aon_wakeups
index: 2
}
{
struct: logic
type: uni
name: aon_timer_rst_req
act: req
package: ""
default: 1'b0
inst_name: aon_timer_aon
width: 1
top_signame: pwrmgr_aon_rstreqs
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: aon_timer_aon
index: -1
}
{
name: sleep_mode
type: uni
act: rcv
package: ""
struct: logic
width: 1
inst_name: aon_timer_aon
default: ""
top_signame: pwrmgr_aon_low_power
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: aon_timer_aon
width: 1
default: ""
end_idx: -1
top_signame: aon_timer_aon_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: ast
index: -1
}
{
struct: ast_alert
type: req_rsp
name: ast_alert
act: rsp
package: ast_pkg
inst_name: sensor_ctrl_aon
width: 1
default: ""
external: true
top_signame: sensor_ctrl_ast_alert
index: -1
}
{
struct: ast_status
type: uni
name: ast_status
act: rcv
package: ast_pkg
inst_name: sensor_ctrl_aon
width: 1
default: ""
external: true
top_signame: sensor_ctrl_ast_status
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: sensor_ctrl_aon
width: 1
default: ""
end_idx: -1
top_signame: sensor_ctrl_aon_tl
index: -1
}
{
struct: sram_otp_key
type: req_rsp
name: sram_otp_key
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: sram_ctrl_ret_aon
width: 1
top_signame: otp_ctrl_sram_otp_key
index: 1
}
{
struct: sram_scr
type: req_rsp
name: sram_scr
act: req
default: "'0"
package: sram_ctrl_pkg
inst_name: sram_ctrl_ret_aon
width: 1
end_idx: -1
top_signame: sram_ctrl_ret_aon_sram_scr
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: sram_ctrl_ret_aon
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: sram_ctrl_ret_aon
width: 1
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: rcv
package: otp_ctrl_part_pkg
inst_name: sram_ctrl_ret_aon
width: 1
default: ""
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: tl_instr_en
type: uni
name: en_ifetch
act: req
package: tlul_pkg
inst_name: sram_ctrl_ret_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: sram_ctrl_ret_aon_en_ifetch
index: -1
}
{
struct: logic
type: uni
name: intg_error
act: rcv
package: ""
inst_name: sram_ctrl_ret_aon
width: 1
default: ""
top_signame: ram_ret_aon_intg_error
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: sram_ctrl_ret_aon
width: 1
default: ""
end_idx: -1
top_signame: sram_ctrl_ret_aon_tl
index: -1
}
{
struct: flash
type: req_rsp
name: flash
act: req
package: flash_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_signame: flash_ctrl_flash
index: -1
}
{
struct: flash_otp_key
type: req_rsp
name: otp
act: req
package: otp_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_signame: flash_ctrl_otp
index: -1
}
{
struct: lc_tx
type: uni
name: lc_creator_seed_sw_rw_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_owner_seed_sw_rw_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_iso_part_sw_rd_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_iso_part_sw_rd_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_iso_part_sw_wr_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_iso_part_sw_wr_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_seed_hw_rd_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: lc_ctrl_lc_seed_hw_rd_en
index: -1
}
{
struct: lc_tx
type: uni
name: rma_req
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_req
index: -1
}
{
struct: lc_tx
type: uni
name: rma_ack
act: req
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_ack
index: -1
}
{
struct: lc_flash_rma_seed
type: uni
name: rma_seed
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_rma_seed
index: -1
}
{
struct: pwr_flash
type: req_rsp
name: pwrmgr
act: rsp
package: pwrmgr_pkg
inst_name: flash_ctrl
width: 1
default: ""
top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
struct: keymgr_flash
type: uni
name: keymgr
act: req
package: flash_ctrl_pkg
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: flash_ctrl_keymgr
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: flash_ctrl
width: 1
default: ""
end_idx: -1
top_signame: flash_ctrl_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: rv_plic
width: 1
default: ""
end_idx: -1
top_signame: rv_plic_tl
index: -1
}
{
name: idle
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: aes
default: ""
top_signame: clkmgr_aon_idle
index: 0
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: aes
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: req
package: edn_pkg
inst_name: aes
width: 1
default: ""
top_signame: edn1_edn
index: 2
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: aes
width: 1
default: ""
end_idx: -1
top_signame: aes_tl
index: -1
}
{
name: idle
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: hmac
default: ""
top_signame: clkmgr_aon_idle
index: 1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: hmac
width: 1
default: ""
end_idx: -1
top_signame: hmac_tl
index: -1
}
{
struct: hw_key_req
type: uni
name: keymgr_key
act: rcv
package: keymgr_pkg
inst_name: kmac
width: 1
default: ""
top_signame: keymgr_kmac_key
index: -1
}
{
struct: kmac_data
type: req_rsp
name: keymgr_kdf
act: rsp
package: keymgr_pkg
inst_name: kmac
width: 1
default: ""
top_signame: keymgr_kmac_data
index: -1
}
{
struct: edn
type: req_rsp
name: entropy
act: req
width: 1
package: edn_pkg
inst_name: kmac
default: ""
top_signame: edn0_edn
index: 3
}
{
name: idle
type: uni
act: req
package: ""
struct: logic
width: 1
inst_name: kmac
default: ""
top_signame: clkmgr_aon_idle
index: 2
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: kmac
width: 1
default: ""
end_idx: -1
top_signame: kmac_tl
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: req
package: edn_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: edn0_edn
index: 0
}
{
struct: hw_key_req
type: uni
name: aes_key
act: req
package: keymgr_pkg
inst_name: keymgr
index: -1
}
{
struct: hw_key_req
type: uni
name: hmac_key
act: req
package: keymgr_pkg
inst_name: keymgr
index: -1
}
{
struct: hw_key_req
type: uni
name: kmac_key
act: req
package: keymgr_pkg
inst_name: keymgr
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: keymgr_kmac_key
index: -1
}
{
struct: kmac_data
type: req_rsp
name: kmac_data
act: req
package: keymgr_pkg
inst_name: keymgr
width: 1
default: ""
end_idx: -1
top_signame: keymgr_kmac_data
index: -1
}
{
struct: otp_keymgr_key
type: uni
name: otp_key
act: rcv
package: otp_ctrl_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: otp_ctrl_otp_keymgr_key
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: rcv
package: otp_ctrl_part_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: keymgr_flash
type: uni
name: flash
act: rcv
package: flash_ctrl_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: flash_ctrl_keymgr
index: -1
}
{
struct: lc_tx
type: uni
name: lc_keymgr_en
act: rcv
package: lc_ctrl_pkg
default: lc_ctrl_pkg::On
inst_name: keymgr
width: 1
top_signame: lc_ctrl_lc_keymgr_en
index: -1
}
{
struct: lc_keymgr_div
type: uni
name: lc_keymgr_div
act: rcv
package: lc_ctrl_pkg
inst_name: keymgr
width: 1
default: ""
top_signame: lc_ctrl_lc_keymgr_div
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: keymgr
width: 1
default: ""
end_idx: -1
top_signame: keymgr_tl
index: -1
}
{
struct: csrng
type: req_rsp
name: csrng_cmd
act: rsp
package: csrng_pkg
width: 2
inst_name: csrng
default: ""
end_idx: -1
top_type: one-to-N
top_signame: csrng_csrng_cmd
index: -1
}
{
struct: entropy_src_hw_if
type: req_rsp
name: entropy_src_hw_if
act: req
package: entropy_src_pkg
inst_name: csrng
width: 1
default: ""
end_idx: -1
top_signame: csrng_entropy_src_hw_if
index: -1
}
{
struct: logic
type: uni
name: efuse_sw_app_enable
act: rcv
width: 1
package: ""
inst_name: csrng
index: -1
}
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: csrng
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: csrng
width: 1
default: ""
end_idx: -1
top_signame: csrng_tl
index: -1
}
{
struct: entropy_src_hw_if
type: req_rsp
name: entropy_src_hw_if
act: rsp
package: entropy_src_pkg
inst_name: entropy_src
width: 1
default: ""
top_signame: csrng_entropy_src_hw_if
index: -1
}
{
struct: entropy_src_rng
type: req_rsp
name: entropy_src_rng
act: req
package: entropy_src_pkg
inst_name: entropy_src
width: 1
default: ""
external: true
top_signame: es_rng
index: -1
}
{
struct: entropy_src_xht
type: req_rsp
name: entropy_src_xht
act: req
package: entropy_src_pkg
inst_name: entropy_src
index: -1
}
{
struct: logic
type: uni
name: efuse_es_sw_reg_en
act: rcv
width: 1
package: ""
inst_name: entropy_src
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: entropy_src
width: 1
default: ""
end_idx: -1
top_signame: entropy_src_tl
index: -1
}
{
struct: csrng
type: req_rsp
name: csrng_cmd
act: req
width: 1
package: csrng_pkg
desc: EDN supports a signal CSRNG application interface.
inst_name: edn0
default: ""
top_signame: csrng_csrng_cmd
index: 0
}
{
struct: edn
type: req_rsp
name: edn
act: rsp
width: 4
default: "'0"
desc:
'''
The collection of peripheral ports supported by edn. The width (4)
indicates the number of peripheral ports on a single instance.
Due to limitations in the parametrization of top-level interconnects
this value is not currently parameterizable. However, the number
of peripheral ports may change in a future revision.
'''
package: edn_pkg
inst_name: edn0
end_idx: -1
top_type: one-to-N
top_signame: edn0_edn
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: edn0
width: 1
default: ""
end_idx: -1
top_signame: edn0_tl
index: -1
}
{
struct: csrng
type: req_rsp
name: csrng_cmd
act: req
width: 1
package: csrng_pkg
desc: EDN supports a signal CSRNG application interface.
inst_name: edn1
default: ""
top_signame: csrng_csrng_cmd
index: 1
}
{
struct: edn
type: req_rsp
name: edn
act: rsp
width: 4
default: "'0"
desc:
'''
The collection of peripheral ports supported by edn. The width (4)
indicates the number of peripheral ports on a single instance.
Due to limitations in the parametrization of top-level interconnects
this value is not currently parameterizable. However, the number
of peripheral ports may change in a future revision.
'''
package: edn_pkg
inst_name: edn1
end_idx: 3
top_type: partial-one-to-N
top_signame: edn1_edn
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: edn1
width: 1
default: ""
end_idx: -1
top_signame: edn1_tl
index: -1
}
{
struct: sram_otp_key
type: req_rsp
name: sram_otp_key
act: req
default: "'0"
package: otp_ctrl_pkg
inst_name: sram_ctrl_main
width: 1
top_signame: otp_ctrl_sram_otp_key
index: 0
}
{
struct: sram_scr
type: req_rsp
name: sram_scr
act: req
default: "'0"
package: sram_ctrl_pkg
inst_name: sram_ctrl_main
width: 1
end_idx: -1
top_signame: sram_ctrl_main_sram_scr
index: -1
}
{
struct: lc_tx
type: uni
name: lc_escalate_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: sram_ctrl_main
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
}
{
struct: lc_tx
type: uni
name: lc_hw_debug_en
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
inst_name: sram_ctrl_main
width: 1
top_signame: lc_ctrl_lc_hw_debug_en
index: -1
}
{
struct: otp_hw_cfg
type: uni
name: otp_hw_cfg
act: rcv
package: otp_ctrl_part_pkg
inst_name: sram_ctrl_main
width: 1
default: ""
top_signame: otp_ctrl_otp_hw_cfg
index: -1
}
{
struct: tl_instr_en
type: uni
name: en_ifetch
act: req
package: tlul_pkg
inst_name: sram_ctrl_main
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: sram_ctrl_main_en_ifetch
index: -1
}
{
struct: logic
type: uni
name: intg_error
act: rcv
package: ""
inst_name: sram_ctrl_main
width: 1
default: ""
top_signame: ram_main_intg_error
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: sram_ctrl_main
width: 1
default: ""
end_idx: -1
top_signame: sram_ctrl_main_tl
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: req
package: edn_pkg
inst_name: otbn
width: 1
default: ""
top_signame: edn1_edn
index: 1
}
{
name: idle
type: uni
struct: logic
width: 1
act: req
inst_name: otbn
default: ""
package: ""
top_signame: clkmgr_aon_idle
index: 3
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: otbn
width: 1
default: ""
end_idx: -1
top_signame: otbn_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: rom
width: 1
default: ""
end_idx: -1
top_signame: rom_tl
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: ram_main
width: 1
default: ""
end_idx: -1
top_signame: ram_main_tl
index: -1
}
{
struct: sram_scr
package: sram_ctrl_pkg
type: req_rsp
name: sram_scr
act: rsp
inst_name: ram_main
width: 1
default: ""
top_signame: sram_ctrl_main_sram_scr
index: -1
}
{
struct: tl_instr_en
package: tlul_pkg
type: uni
name: en_ifetch
act: rcv
inst_name: ram_main
width: 1
default: ""
top_signame: sram_ctrl_main_en_ifetch
index: -1
}
{
struct: logic
package: ""
type: uni
name: intg_error
act: req
inst_name: ram_main
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ram_main_intg_error
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: ram_ret_aon
width: 1
default: ""
end_idx: -1
top_signame: ram_ret_aon_tl
index: -1
}
{
struct: sram_scr
package: sram_ctrl_pkg
type: req_rsp
name: sram_scr
act: rsp
inst_name: ram_ret_aon
width: 1
default: ""
top_signame: sram_ctrl_ret_aon_sram_scr
index: -1
}
{
struct: tl_instr_en
package: tlul_pkg
type: uni
name: en_ifetch
act: rcv
inst_name: ram_ret_aon
width: 1
default: ""
top_signame: sram_ctrl_ret_aon_en_ifetch
index: -1
}
{
struct: logic
package: ""
type: uni
name: intg_error
act: req
inst_name: ram_ret_aon
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: ram_ret_aon_intg_error
index: -1
}
{
struct: flash
type: req_rsp
name: flash_ctrl
act: rsp
inst_name: eflash
width: 1
default: ""
package: flash_ctrl_pkg
top_signame: flash_ctrl_flash
index: -1
}
{
struct: tl
package: tlul_pkg
type: req_rsp
act: rsp
name: tl
inst_name: eflash
width: 1
default: ""
end_idx: -1
top_signame: eflash_tl
index: -1
}
{
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
name: lc_nvm_debug_en
inst_name: eflash
width: 1
default: ""
top_signame: lc_ctrl_lc_nvm_debug_en
index: -1
}
{
struct: lc_tx
package: lc_ctrl_pkg
type: uni
act: rcv
name: flash_bist_enable
inst_name: eflash
width: 1
default: ""
external: true
top_signame: flash_bist_enable
index: -1
}
{
struct: logic
package: ""
type: uni
act: rcv
name: flash_power_down_h
inst_name: eflash
width: 1
default: ""
external: true
top_signame: flash_power_down_h
index: -1
}
{
struct: logic
package: ""
type: uni
act: rcv
name: flash_power_ready_h
inst_name: eflash
width: 1
default: ""
external: true
top_signame: flash_power_ready_h
index: -1
}
{
struct: logic
package: ""
width: 4
type: uni
act: rcv
name: flash_test_mode_a
inst_name: eflash
default: ""
external: true
top_signame: flash_test_mode_a
index: -1
}
{
struct: logic
package: ""
type: uni
act: rcv
name: flash_test_voltage_h
inst_name: eflash
width: 1
default: ""
external: true
top_signame: flash_test_voltage_h
index: -1
}
{
struct: tl
type: req_rsp
name: tl_corei
act: rsp
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: main_tl_corei
index: -1
}
{
struct: tl
type: req_rsp
name: tl_cored
act: rsp
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: main_tl_cored
index: -1
}
{
struct: tl
type: req_rsp
name: tl_dm_sba
act: rsp
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: main_tl_dm_sba
index: -1
}
{
struct: tl
type: req_rsp
name: tl_rom
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: rom_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_debug_mem
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: main_tl_debug_mem
index: -1
}
{
struct: tl
type: req_rsp
name: tl_ram_main
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: ram_main_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_eflash
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: eflash_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_peri
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
end_idx: -1
top_signame: main_tl_peri
index: -1
}
{
struct: tl
type: req_rsp
name: tl_flash_ctrl
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: flash_ctrl_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_hmac
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: hmac_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_kmac
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: kmac_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_aes
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: aes_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_entropy_src
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: entropy_src_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_csrng
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: csrng_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_edn0
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: edn0_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_edn1
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: edn1_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_rv_plic
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: rv_plic_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_otbn
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: otbn_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_keymgr
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: keymgr_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_sram_ctrl_main
act: req
package: tlul_pkg
inst_name: main
width: 1
default: ""
top_signame: sram_ctrl_main_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_main
act: rsp
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: main_tl_peri
index: -1
}
{
struct: tl
type: req_rsp
name: tl_uart0
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: uart0_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_uart1
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: uart1_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_uart2
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: uart2_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_uart3
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: uart3_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_i2c0
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: i2c0_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_i2c1
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: i2c1_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_i2c2
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: i2c2_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_pattgen
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: pattgen_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_gpio
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: gpio_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_spi_device
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: spi_device_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_spi_host0
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: spi_host0_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_spi_host1
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: spi_host1_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_rv_timer
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: rv_timer_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_usbdev
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: usbdev_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_pwrmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: pwrmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_rstmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: rstmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_clkmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: clkmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_pinmux_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: pinmux_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_ram_ret_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: ram_ret_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_otp_ctrl
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: otp_ctrl_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_lc_ctrl
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: lc_ctrl_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_sensor_ctrl_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: sensor_ctrl_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_alert_handler
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: alert_handler_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_sram_ctrl_ret_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: sram_ctrl_ret_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_aon_timer_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
top_signame: aon_timer_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
name: tl_ast
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
external: true
top_signame: ast_tl
index: -1
}
{
struct: esc_tx
type: uni
name: esc_nmi_tx
act: rcv
package: prim_esc_pkg
inst_name: rv_core_ibex
width: 1
default: ""
top_signame: alert_handler_esc_tx
index: 0
}
{
struct: esc_rx
type: uni
name: esc_nmi_rx
act: req
package: prim_esc_pkg
inst_name: rv_core_ibex
width: 1
default: ""
top_signame: alert_handler_esc_rx
index: 0
}
{
struct: crash_dump
type: uni
name: crash_dump
act: req
package: ibex_pkg
inst_name: rv_core_ibex
width: 1
default: ""
end_idx: -1
top_type: broadcast
top_signame: rv_core_ibex_crash_dump
index: -1
}
{
struct: lc_tx_t
type: uni
name: lc_cpu_en
act: rcv
package: lc_ctrl_pkg
inst_name: rv_core_ibex
width: 1
default: ""
top_signame: lc_ctrl_lc_cpu_en
index: -1
}
{
struct: edn
type: req_rsp
name: edn
act: rsp
package: edn_pkg
inst_name: ast_edn
width: 1
default: ""
top_signame: edn0_edn
index: 2
external: true
}
]
external:
[
{
package: ""
struct: logic
signame: clk_main_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: clk_main
}
{
package: ""
struct: logic
signame: clk_io_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: clk_io
}
{
package: ""
struct: logic
signame: clk_usb_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: clk_usb
}
{
package: ""
struct: logic
signame: clk_aon_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: clk_aon
}
{
package: ""
struct: logic
signame: clk_main_jitter_en_o
width: 1
type: uni
default: ""
direction: out
index: -1
netname: clk_main_jitter_en
}
{
package: pwrmgr_pkg
struct: pwr_ast_req
signame: pwrmgr_ast_req_o
width: 1
type: req_rsp
default: ""
direction: out
index: -1
netname: pwrmgr_ast_req
}
{
package: pwrmgr_pkg
struct: pwr_ast_rsp
signame: pwrmgr_ast_rsp_i
width: 1
type: req_rsp
default: ""
direction: in
index: -1
netname: pwrmgr_ast_rsp
}
{
package: ast_pkg
struct: ast_alert_req
signame: sensor_ctrl_ast_alert_req_i
width: 1
type: req_rsp
default: ""
direction: in
index: -1
netname: sensor_ctrl_ast_alert_req
}
{
package: ast_pkg
struct: ast_alert_rsp
signame: sensor_ctrl_ast_alert_rsp_o
width: 1
type: req_rsp
default: ""
direction: out
index: -1
netname: sensor_ctrl_ast_alert_rsp
}
{
package: ast_pkg
struct: ast_status
signame: sensor_ctrl_ast_status_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: sensor_ctrl_ast_status
}
{
package: ""
struct: logic
signame: usbdev_usb_ref_val_o
width: 1
type: uni
default: ""
direction: out
index: -1
netname: usbdev_usb_ref_val
}
{
package: ""
struct: logic
signame: usbdev_usb_ref_pulse_o
width: 1
type: uni
default: ""
direction: out
index: -1
netname: usbdev_usb_ref_pulse
}
{
package: tlul_pkg
struct: tl_h2d
signame: ast_tl_req_o
width: 1
type: req_rsp
default: ""
direction: out
index: -1
netname: ast_tl_h2d
}
{
package: tlul_pkg
struct: tl_d2h
signame: ast_tl_rsp_i
width: 1
type: req_rsp
default: ""
direction: in
index: -1
netname: ast_tl_d2h
}
{
package: otp_ctrl_pkg
struct: otp_ast_req
signame: otp_ctrl_otp_ast_pwr_seq_o
width: 1
type: uni
default: "'0"
direction: out
index: -1
netname: otp_ctrl_otp_ast_pwr_seq
}
{
package: otp_ctrl_pkg
struct: otp_ast_rsp
signame: otp_ctrl_otp_ast_pwr_seq_h_i
width: 1
type: uni
default: "'0"
direction: in
index: -1
netname: otp_ctrl_otp_ast_pwr_seq_h
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: flash_bist_enable_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: flash_bist_enable
}
{
package: ""
struct: logic
signame: flash_power_down_h_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: flash_power_down_h
}
{
package: ""
struct: logic
signame: flash_power_ready_h_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: flash_power_ready_h
}
{
package: ""
struct: logic
signame: flash_test_mode_a_i
width: 4
type: uni
default: ""
direction: in
index: -1
netname: flash_test_mode_a
}
{
package: ""
struct: logic
signame: flash_test_voltage_h_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: flash_test_voltage_h
}
{
package: entropy_src_pkg
struct: entropy_src_rng_req
signame: es_rng_req_o
width: 1
type: req_rsp
default: ""
direction: out
index: -1
netname: es_rng_req
}
{
package: entropy_src_pkg
struct: entropy_src_rng_rsp
signame: es_rng_rsp_i
width: 1
type: req_rsp
default: ""
direction: in
index: -1
netname: es_rng_rsp
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_clk_byp_req_o
width: 1
type: uni
default: lc_ctrl_pkg::Off
direction: out
index: -1
netname: lc_clk_byp_req
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_clk_byp_ack_i
width: 1
type: uni
default: ""
direction: in
index: -1
netname: lc_clk_byp_ack
}
{
package: edn_pkg
struct: edn_req
signame: ast_edn_edn_req_i
width: 1
type: req_rsp
default: ""
direction: in
index: 2
netname: edn0_edn_req
}
{
package: edn_pkg
struct: edn_rsp
signame: ast_edn_edn_rsp_o
width: 1
type: req_rsp
default: ""
direction: out
index: 2
netname: edn0_edn_rsp
}
{
package: clkmgr_pkg
struct: clkmgr_ast_out
signame: clks_ast_o
width: 1
type: uni
default: ""
direction: out
index: -1
netname: clks_ast
}
{
package: rstmgr_pkg
struct: rstmgr_ast_out
signame: rsts_ast_o
width: 1
type: uni
default: ""
direction: out
index: -1
netname: rsts_ast
}
]
definitions:
[
{
package: alert_pkg
struct: alert_crashdump
signame: alert_handler_crashdump
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: prim_esc_pkg
struct: esc_rx
signame: alert_handler_esc_rx
width: 4
type: uni
end_idx: -1
act: rcv
suffix: ""
default: ""
}
{
package: prim_esc_pkg
struct: esc_tx
signame: alert_handler_esc_tx
width: 4
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: csrng_pkg
struct: csrng_req
signame: csrng_csrng_cmd_req
width: 2
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: csrng_pkg
struct: csrng_rsp
signame: csrng_csrng_cmd_rsp
width: 2
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: entropy_src_pkg
struct: entropy_src_hw_if_req
signame: csrng_entropy_src_hw_if_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: entropy_src_pkg
struct: entropy_src_hw_if_rsp
signame: csrng_entropy_src_hw_if_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: flash_ctrl_pkg
struct: flash_req
signame: flash_ctrl_flash_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: flash_ctrl_pkg
struct: flash_rsp
signame: flash_ctrl_flash_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: flash_ctrl_pkg
struct: keymgr_flash
signame: flash_ctrl_keymgr
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: otp_ctrl_pkg
struct: flash_otp_key_req
signame: flash_ctrl_otp_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: otp_ctrl_pkg
struct: flash_otp_key_rsp
signame: flash_ctrl_otp_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: flash_ctrl_rma_req
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: ""
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: flash_ctrl_rma_ack
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: lc_ctrl_pkg
struct: lc_flash_rma_seed
signame: flash_ctrl_rma_seed
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: ""
}
{
package: sram_ctrl_pkg
struct: sram_scr_req
signame: sram_ctrl_main_sram_scr_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: "'0"
}
{
package: sram_ctrl_pkg
struct: sram_scr_rsp
signame: sram_ctrl_main_sram_scr_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: "'0"
}
{
package: sram_ctrl_pkg
struct: sram_scr_req
signame: sram_ctrl_ret_aon_sram_scr_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: "'0"
}
{
package: sram_ctrl_pkg
struct: sram_scr_rsp
signame: sram_ctrl_ret_aon_sram_scr_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: "'0"
}
{
package: tlul_pkg
struct: tl_instr_en
signame: sram_ctrl_main_en_ifetch
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: tlul_pkg
struct: tl_instr_en
signame: sram_ctrl_ret_aon_en_ifetch
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: ""
struct: logic
signame: ram_main_intg_error
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: ""
struct: logic
signame: ram_ret_aon_intg_error
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: otp_ctrl_pkg
struct: sram_otp_key_req
signame: otp_ctrl_sram_otp_key_req
width: 2
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: "'0"
}
{
package: otp_ctrl_pkg
struct: sram_otp_key_rsp
signame: otp_ctrl_sram_otp_key_rsp
width: 2
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: "'0"
}
{
package: pwrmgr_pkg
struct: pwr_flash_req
signame: pwrmgr_aon_pwr_flash_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_flash_rsp
signame: pwrmgr_aon_pwr_flash_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_rst_req
signame: pwrmgr_aon_pwr_rst_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_rst_rsp
signame: pwrmgr_aon_pwr_rst_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_clk_req
signame: pwrmgr_aon_pwr_clk_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_clk_rsp
signame: pwrmgr_aon_pwr_clk_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_otp_req
signame: pwrmgr_aon_pwr_otp_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_otp_rsp
signame: pwrmgr_aon_pwr_otp_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_lc_req
signame: pwrmgr_aon_pwr_lc_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_lc_rsp
signame: pwrmgr_aon_pwr_lc_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: ""
struct: logic
signame: pwrmgr_aon_strap
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: ""
struct: logic
signame: pwrmgr_aon_low_power
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: ibex_pkg
struct: crash_dump
signame: rv_core_ibex_crash_dump
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: ""
struct: logic
signame: usbdev_usb_out_of_rst
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: ""
struct: logic
signame: usbdev_usb_aon_wake_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: ""
struct: logic
signame: usbdev_usb_aon_wake_ack
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: ""
struct: logic
signame: usbdev_usb_suspend
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: usbdev_pkg
struct: awk_state
signame: pinmux_aon_usb_state_debug
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: edn_pkg
struct: edn_req
signame: edn0_edn_req
width: 4
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: "'0"
}
{
package: edn_pkg
struct: edn_rsp
signame: edn0_edn_rsp
width: 4
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: "'0"
}
{
package: edn_pkg
struct: edn_req
signame: edn1_edn_req
width: 4
type: req_rsp
end_idx: 3
act: rsp
suffix: req
default: "'0"
}
{
package: edn_pkg
struct: edn_rsp
signame: edn1_edn_rsp
width: 4
type: req_rsp
end_idx: 3
act: rsp
suffix: rsp
default: "'0"
}
{
package: otp_ctrl_pkg
struct: otp_keymgr_key
signame: otp_ctrl_otp_keymgr_key
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: keymgr_pkg
struct: hw_key_req
signame: keymgr_kmac_key
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: ""
}
{
package: keymgr_pkg
struct: kmac_data_req
signame: keymgr_kmac_data_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: keymgr_pkg
struct: kmac_data_rsp
signame: keymgr_kmac_data_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: ""
struct: logic
signame: clkmgr_aon_idle
width: 4
type: uni
end_idx: -1
act: rcv
suffix: ""
default: ""
}
{
package: jtag_pkg
struct: jtag_req
signame: pinmux_aon_lc_jtag_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: jtag_pkg
struct: jtag_rsp
signame: pinmux_aon_lc_jtag_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: otp_ctrl_pkg
struct: otp_lc_data
signame: otp_ctrl_otp_lc_data
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: otp_ctrl_pkg
struct: lc_otp_program_req
signame: lc_ctrl_lc_otp_program_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: "'0"
}
{
package: otp_ctrl_pkg
struct: lc_otp_program_rsp
signame: lc_ctrl_lc_otp_program_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: "'0"
}
{
package: otp_ctrl_pkg
struct: lc_otp_token_req
signame: lc_ctrl_lc_otp_token_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: "'0"
}
{
package: otp_ctrl_pkg
struct: lc_otp_token_rsp
signame: lc_ctrl_lc_otp_token_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: "'0"
}
{
package: otp_ctrl_part_pkg
struct: otp_hw_cfg
signame: otp_ctrl_otp_hw_cfg
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: lc_ctrl_pkg
struct: lc_keymgr_div
signame: lc_ctrl_lc_keymgr_div
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: "'0"
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_dft_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_nvm_debug_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_hw_debug_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_cpu_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_keymgr_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_escalate_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_check_byp_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_clk_byp_ack
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_creator_seed_sw_rw_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_owner_seed_sw_rw_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_iso_part_sw_rd_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_iso_part_sw_wr_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: lc_ctrl_pkg
struct: lc_tx
signame: lc_ctrl_lc_seed_hw_rd_en
width: 1
type: uni
end_idx: -1
act: req
suffix: ""
default: lc_ctrl_pkg::Off
}
{
package: ""
struct: logic
signame: pwrmgr_aon_wakeups
width: 3
type: uni
end_idx: -1
act: rcv
suffix: ""
default: ""
}
{
package: ""
struct: logic
signame: pwrmgr_aon_rstreqs
width: 1
type: uni
end_idx: -1
act: rcv
suffix: ""
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rom_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: rom_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: ram_main_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: ram_main_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: eflash_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: eflash_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: main_tl_peri_req
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: main_tl_peri_rsp
width: 1
type: req_rsp
end_idx: -1
act: req
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: flash_ctrl_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: flash_ctrl_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: hmac_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: hmac_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: kmac_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: kmac_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: aes_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: aes_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: entropy_src_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: entropy_src_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: csrng_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: csrng_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: edn0_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: edn0_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: edn1_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: edn1_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rv_plic_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: rv_plic_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: otbn_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: otbn_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: keymgr_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: keymgr_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: sram_ctrl_main_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: sram_ctrl_main_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: uart0_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: uart0_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: uart1_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: uart1_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: uart2_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: uart2_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: uart3_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: uart3_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: i2c0_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: i2c0_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: i2c1_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: i2c1_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: i2c2_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: i2c2_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: pattgen_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: pattgen_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: gpio_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: gpio_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: spi_device_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: spi_device_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: spi_host0_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: spi_host0_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: spi_host1_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: spi_host1_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rv_timer_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: rv_timer_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: usbdev_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: usbdev_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: pwrmgr_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: pwrmgr_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: rstmgr_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: rstmgr_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: clkmgr_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: clkmgr_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: pinmux_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: pinmux_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: ram_ret_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: ram_ret_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: otp_ctrl_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: otp_ctrl_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: lc_ctrl_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: lc_ctrl_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: sensor_ctrl_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: sensor_ctrl_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: alert_handler_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: alert_handler_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: sram_ctrl_ret_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: sram_ctrl_ret_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: aon_timer_aon_tl_req
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: req
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: aon_timer_aon_tl_rsp
width: 1
type: req_rsp
end_idx: -1
act: rsp
suffix: rsp
default: ""
}
{
package: rstmgr_pkg
struct: rstmgr_out
signame: rstmgr_aon_resets
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: rstmgr_pkg
struct: rstmgr_cpu
signame: rstmgr_aon_cpu
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: pwrmgr_pkg
struct: pwr_cpu
signame: pwrmgr_aon_pwr_cpu
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: clkmgr_pkg
struct: clkmgr_out
signame: clkmgr_aon_clocks
width: 1
type: uni
end_idx: -1
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: main_tl_corei_req
width: 1
type: req_rsp
end_idx: -1
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: main_tl_corei_rsp
width: 1
type: req_rsp
end_idx: -1
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: main_tl_cored_req
width: 1
type: req_rsp
end_idx: -1
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: main_tl_cored_rsp
width: 1
type: req_rsp
end_idx: -1
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: main_tl_dm_sba_req
width: 1
type: req_rsp
end_idx: -1
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: main_tl_dm_sba_rsp
width: 1
type: req_rsp
end_idx: -1
default: ""
}
{
package: tlul_pkg
struct: tl_h2d
signame: main_tl_debug_mem_req
width: 1
type: req_rsp
end_idx: -1
default: ""
}
{
package: tlul_pkg
struct: tl_d2h
signame: main_tl_debug_mem_rsp
width: 1
type: req_rsp
end_idx: -1
default: ""
}
]
}
}